Display device

Abstract

Disclosed is a display device including: a display panel including a plurality of pixels configured to receive an initialization voltage through an initialization voltage line; a controller configured to output a voltage control signal for controlling a voltage level of the initialization voltage; and a power manager configured to provide the initialization voltage to the initialization voltage line, the power manager changes the voltage level of the initialization voltage to an initialization level at or after a power-on time at which power is started to be supplied and before a display-on time at which an image is started to be displayed, based on the voltage control signal, and the power manager changes the voltage level of the initialization voltage to a target level corresponding to the brightness of the image at or after the display on time based on the voltage control signal.

Description

Technical Field

[0001] Embodiments relate to a display device and more particularly to a display device including a flexible substrate. Background Art

[0002] The display device may include a substrate and a transistor and a voltage line disposed on the substrate. The transistor may be turned on in response to a signal applied to a gate electrode, and the voltage line may transmit a voltage to a source electrode or a drain electrode of the transistor.

[0003] When voltages having mutually different polarities are respectively applied to the gate electrodes and voltage lines of transistors adjacent to each other, induced charges may be accumulated in a portion of the substrate located below the transistor, and the threshold voltage of the transistor may be shifted by the induced charges. When the threshold voltage of the transistor shifts, the leakage current of the transistor may increase, and the display quality of an image displayed by the display device may be deteriorated. Summary of the invention

[0004] The embodiment can provide a display device in which the display quality of an image is improved.

[0005] An embodiment of a display device includes: a display panel, including a plurality of pixels configured to receive an initialization voltage through an initialization voltage line; a controller, configured to output a voltage control signal for controlling a voltage level of the initialization voltage; and a power manager, configured to provide the initialization voltage to the initialization voltage line, the power manager changing the voltage level of the initialization voltage to an initialization level based on the voltage control signal at or after a power-on time when power supply starts and before a display-on time when display of an image starts, and the power manager changing the voltage level of the initialization voltage to a target level corresponding to the brightness of the image based on the voltage control signal at or after the display-on time.

[0006] In an embodiment, an absolute value of the initialization level may be smaller than an absolute value of the target level.

[0007] In an embodiment, the initialization level may be about -1V to about 1V.

[0008] In an embodiment, the polarity of the initialization level may be different from the polarity of the target level.

[0009] In an embodiment, the power manager may be configured to change the voltage level of the initialization voltage to a predetermined fixed level at or after the power-on time and before the voltage level of the initialization voltage is changed to the initialization level. The absolute value of the initialization level may be smaller than the absolute value of the fixed level.

[0010] In an embodiment, the power manager can be configured to change the voltage level of the initialization voltage from the target level to the initialization level based on the voltage control signal at or after the display off time when the display of the image starts to end and before the power off time when the supply of the power starts to be cut off.

[0011] In an embodiment, the power manager may be configured to change the voltage level of the initialization voltage to a predetermined fixed level at or after the display off time and before the voltage level of the initialization voltage is changed to the initialization level. The absolute value of the initialization level may be smaller than the absolute value of the fixed level.

[0012] In an embodiment, the power manager may be configured to change the voltage level of the initialization voltage from the target level to the initialization level during a vertical edge period in which a data voltage is not supplied to each of the plurality of pixels based on the voltage control signal.

[0013] In an embodiment, each of the plurality of pixels may include: a driving transistor configured to generate a driving current; a write transistor connected between the driving transistor and a data line configured to transmit a data voltage; a light emitting diode configured to emit light based on the driving current; and a bypass transistor connected between the initialization voltage line and the light emitting diode.

[0014] In an embodiment, the initialization voltage line may at least partially overlap with a gate electrode of the write transistor.

[0015] An embodiment of a display device includes: a display panel including a plurality of pixels configured to receive an initialization voltage through an initialization voltage line; a controller configured to output a voltage control signal for controlling a voltage level of the initialization voltage; and a power manager configured to provide the initialization voltage to the initialization voltage line, and the power manager changes the voltage level of the initialization voltage from a target level corresponding to the brightness of the image to an initialization level at or after a display off time at which a display image starts to end and before a power off time at which supply power starts to be cut off based on the voltage control signal. The absolute value of the initialization level may be smaller than the absolute value of the target level.

[0016] In an embodiment, the initialization level may be about -1V to about 1V.

[0017] In an embodiment, the polarity of the initialization level may be different from the polarity of the target level.

[0018] In an embodiment, the power manager may be configured to change the voltage level of the initialization voltage to a predetermined fixed level at or after the power-on time and before the voltage level of the initialization voltage is changed to the initialization voltage. The absolute value of the initialization level may be smaller than the absolute value of the fixed level.

[0019] In an embodiment, the power manager can be configured to change the voltage level of the initialization voltage to the target level during an effective period in which the data voltage is provided to each of the multiple pixels based on the voltage control signal, and the power manager can change the voltage level of the initialization voltage from the target level to the initialization level during a vertical edge period in which the data voltage is not provided to each of the multiple pixels based on the voltage control signal.

[0020] In an embodiment, each of the plurality of pixels may include: a driving transistor configured to generate a driving current, a write transistor connected between the driving transistor and a data line configured to transmit a data voltage, a light emitting diode configured to emit light based on the driving current, and a bypass transistor connected between the initialization voltage line and the light emitting diode.

[0021] An embodiment of a display device includes: a display panel including a plurality of pixels configured to receive an initialization voltage through an initialization voltage line; a controller configured to output a voltage control signal for controlling a voltage level of the initialization voltage; and a power manager configured to provide the initialization voltage to the initialization voltage line, the power manager changing the voltage level of the initialization voltage to a target level corresponding to brightness of an image in an effective period in which a data voltage is provided to each of the plurality of pixels based on the voltage control signal, and the power manager changing the voltage level of the initialization voltage from the target level to an initialization level in a vertical edge period in which the data voltage is not provided to each of the plurality of pixels based on the voltage control signal. The absolute value of the initialization level may be smaller than the absolute value of the target level.

[0022] In an embodiment, the initialization level may be about -1V to about 1V.

[0023] In an embodiment, the polarity of the initialization level may be different from the polarity of the target level.

[0024] In an embodiment, each of the plurality of pixels may include: a driving transistor configured to generate a driving current, a write transistor connected between the driving transistor and a data line configured to transmit a data voltage, a light emitting diode configured to emit light based on the driving current, and a bypass transistor connected between the initialization voltage line and the light emitting diode.

[0025] In the display device according to the embodiment, at or after the power-on time and before the display-on time, at or after the display-off time and before the power-off time, or in the vertical edge period within the frame period, the absolute value of the voltage level of the initialization voltage can be reduced, so that the amount of induced charge in the flexible substrate can be reduced, and the shift of the threshold voltage of the transistor can be reduced. Therefore, the display quality of the image displayed by the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 It is shown Figure 1 A circuit diagram of a pixel included in a display device.

[0029] Figure 3 It is shown Figure 2 A plan view of a portion of a pixel. Figure 4 It is along Figure 3 A cross-sectional view taken along line AA'.

[0030] Figure 5 is a diagram for describing control of an initialization voltage according to an embodiment of the present disclosure.

[0031] Figure 6 is a diagram for describing control of an initialization voltage according to an embodiment of the present disclosure.

[0032] Figure 7 is a diagram for describing control of an initialization voltage according to an embodiment of the present disclosure.

[0033] Figure 8 is a diagram for describing control of an initialization voltage according to an embodiment of the present disclosure.

[0034] Fig. 9 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0035] Fig.10is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0036] Fig.11 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0037] Fig.12 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Hereinafter, a display device according to an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals in the accompanying drawings will be used for the same or similar elements.

[0039] Figure 1 is a block diagram showing a display device 100 according to an embodiment of the present disclosure.

[0040] Reference Figure 1 , the display device 100 may include a display panel 110 , a scan driver 120 , an emission driver 130 , a data driver 140 , a power manager 150 , and a controller 160 .

[0041] The display panel 110 may include pixels PX. According to an embodiment, the pixels PX may include a first pixel configured to emit light having a first color, a second pixel configured to emit light having a second color, and a third pixel configured to emit light having a third color. For example, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0042] The scan driver 120 may provide a scan signal SS to the pixel PX. The scan driver 120 may sequentially generate first to nth scan signals SS corresponding to first to nth pixel rows, respectively, based on the first control signal CNT1 (where n is a natural number greater than or equal to 2). The first control signal CNT1 may include a scan clock signal, a scan start signal, and the like.

[0043] The emission driver 130 may provide the emission signal EM to the pixel PX. The emission driver 130 may sequentially generate first to nth emission signals EM corresponding to first to nth pixel rows, respectively, based on the second control signal CNT2. The second control signal CNT2 may include an emission clock signal, an emission start signal, and the like.

[0044] The data driver 140 may provide the data voltage VDAT to the pixel PX. The data driver 140 may generate first to m-th data voltages VDAT (where m is a natural number greater than or equal to 2) corresponding to the first to m-th pixel columns, respectively, based on the second image data IMD2 and the third control signal CNT3. According to an embodiment, the second image data IMD2 may include grayscale values ​​corresponding to the pixels PX, respectively. The third control signal CNT3 may include a data clock signal, a horizontal start signal, a load signal, and the like.

[0045] The power manager 150 may provide a first power voltage ELVDD, a second power voltage ELVSS, a first initialization voltage VINT (hereinafter referred to as "gate initialization voltage VINT"), and a second initialization voltage VAINT (hereinafter referred to as "initialization voltage VAINT") to the pixel PX. The power manager 150 may generate the first power voltage ELVDD, the second power voltage ELVSS, the gate initialization voltage VINT, and the initialization voltage VAINT based on the fourth control signal CNT4. The fourth control signal CNT4 may include a voltage control signal VCS for controlling a voltage level of the initialization voltage VAINT. The power manager 150 may change the voltage level of the initialization voltage VAINT based on the voltage control signal VCS.

[0046] The controller 160 may control the operation or driving of the scan driver 120, the operation or driving of the emission driver 130, the operation or driving of the data driver 140, and the operation or driving of the power manager 150. The controller 160 may generate a first control signal CNT1, a second control signal CNT2, a second image data IMD2, a third control signal CNT3, and a fourth control signal CNT4 based on the first image data IMD1 and the control signal CNT. According to an embodiment, the first image data IMD1 may include grayscale values ​​corresponding to the pixels PX, respectively. The controller 160 may convert the first image data IMD1 into the second image data IMD2. The control signal CNT may include a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and the like.

[0047] Figure 2 It is shown Figure 1 1 is a circuit diagram of a pixel PX included in a display device 100.

[0048] Reference Figure 1 and Figure 2, the pixel PX may include a driving transistor T1 (hereinafter referred to as "first transistor T1"), a writing transistor T2 (hereinafter referred to as "second transistor T2"), a compensation transistor T3 (hereinafter referred to as "third transistor T3"), an initialization transistor T4 (hereinafter referred to as "fourth transistor T4"), a first emission transistor T5 (hereinafter referred to as "fifth transistor T5"), a second emission transistor T6 (hereinafter referred to as "sixth transistor T6"), a bypass transistor T7 (hereinafter referred to as "seventh transistor T7"), a storage capacitor CST, and a light emitting diode EL. The scanning signal SS may include a writing gate signal GW, a compensation gate signal GC, an initialization gate signal GI, and a bypass gate signal GB.

[0049] The first transistor T1 may be connected between the first node N1 and the second node N2. The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode connected to the third node N3. The first transistor T1 may generate a driving current DC corresponding to a voltage between the first node N1 and the third node N3.

[0050] The second transistor T2 may be connected between the first node N1 and a data line DL configured to transmit a data voltage VDAT, and may be turned on in response to a write gate signal GW. The second transistor T2 may include a first electrode connected to the data line DL, a second electrode connected to the first node N1, and a gate electrode configured to receive the write gate signal GW. The second transistor T2 may transmit the data voltage VDAT to the first node N1 in response to the write gate signal GW.

[0051] The third transistor T3 may be connected between the second node N2 and the third node N3 and turned on in response to the compensation gate signal GC. The third transistor T3 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode configured to receive the compensation gate signal GC. The third transistor T3 may connect the second node N2 to the third node N3 in response to the compensation gate signal GC. According to an embodiment, the third transistor T3 may include a bottom gate electrode and a top gate electrode configured to receive the compensation gate signal GC. In other words, the third transistor T3 may be a dual-gate transistor.

[0052] The fourth transistor T4 may be connected between the third node N3 and a gate initialization voltage line configured to transmit a gate initialization voltage VINT, and is turned on in response to an initialization gate signal GI. The fourth transistor T4 may include a first electrode connected to the gate initialization voltage line, a second electrode connected to the third node N3, and a gate electrode configured to receive the initialization gate signal GI. The fourth transistor T4 may transmit the gate initialization voltage VINT to the third node N3 in response to the initialization gate signal GI. According to an embodiment, the fourth transistor T4 may include a bottom gate electrode and a top gate electrode configured to receive the initialization gate signal GI. In other words, the fourth transistor T4 may be a dual-gate transistor.

[0053] The fifth transistor T5 may be connected between the first node N1 and a first power voltage line configured to transmit the first power voltage ELVDD, and may be turned on in response to the emission signal EM. The fifth transistor T5 may include a first electrode connected to the first power voltage line, a second electrode connected to the first node N1, and a gate electrode configured to receive the emission signal EM. The fifth transistor T5 may transmit the first power voltage ELVDD to the first node N1 in response to the emission signal EM.

[0054] The sixth transistor T6 may be connected between the second node N2 and the fourth node N4 and turned on in response to the emission signal EM. The sixth transistor T6 may include a first electrode connected to the second node N2, a second electrode connected to the fourth node N4, and a gate electrode configured to receive the emission signal EM. The sixth transistor T6 may connect the second node N2 to the fourth node N4 in response to the emission signal EM.

[0055] The seventh transistor T7 may be connected between the fourth node N4 and an initialization voltage line IVL configured to transmit an initialization voltage VAINT, and may be turned on in response to a bypass gate signal GB. The seventh transistor T7 may include a first electrode connected to the initialization voltage line IVL, a second electrode connected to the fourth node N4, and a gate electrode configured to receive the bypass gate signal GB. The seventh transistor T7 may transmit the initialization voltage VAINT to the fourth node N4 in response to the bypass gate signal GB.

[0056] Despite Figure 2, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is a P-type transistor (e.g., a PMOS transistor) and the third transistor T3 and the fourth transistor T4 are N-type transistors (e.g., NMOS transistors), but the present disclosure is not limited thereto. According to another embodiment, at least one of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be an N-type transistor, and at least one of the third transistor T3 and the fourth transistor T4 may be a P-type transistor.

[0057] The storage capacitor CST may be connected between the third node N3 and the first power voltage line. The storage capacitor CST may include a first electrode connected to the third node N3 and a second electrode connected to the first power voltage line. The storage capacitor CST may maintain the voltage of the third node N3.

[0058] Despite Figure 2 , an embodiment in which the pixel PX includes seven transistors and one capacitor has been shown, but the present disclosure is not limited thereto. According to another embodiment, the pixel PX may include three to six transistors or eight or more transistors and two or more capacitors.

[0059] The light emitting diode EL may be connected between the fourth node N4 and a second power voltage line configured to transmit a second power voltage ELVSS. The light emitting diode EL may include a first electrode (e.g., an anode) connected to the fourth node N4 and a second electrode (e.g., a cathode) connected to the second power voltage line. The light emitting diode EL may emit light based on the driving current DC.

[0060] According to an embodiment, the light emitting diode EL may be an organic light emitting diode. According to another embodiment, the light emitting diode EL may be an inorganic light emitting diode, a micro light emitting diode or a quantum dot light emitting diode.

[0061] Figure 3 It is shown Figure 2 A plan view of a portion of a pixel PX. Figure 4 It is along Figure 3 A cross-sectional view taken along line AA'.

[0062] Reference Figures 1 to 4The pixel PX may include a substrate SUB, a buffer layer BUF, a first active layer ACT1, a first gate insulating layer GI1, a first gate layer GAT1, a second gate insulating layer GI2, a second gate layer GAT2, a first interlayer insulating layer ILD1, a second active layer, a third gate insulating layer GI3, a third gate layer GAT3, a second interlayer insulating layer ILD2, a first source-drain layer, a first via insulating layer VIA1, and a second source-drain layer.

[0063] The substrate SUB may be a flexible substrate including an organic material. According to an embodiment, the substrate SUB may include a first organic layer OL1, a first barrier layer BAR1 disposed on the first organic layer OL1, a second organic layer OL2 disposed on the first barrier layer BAR1, and a second barrier layer BAR2 disposed on the second organic layer OL2. According to an embodiment, each of the first organic layer OL1 and the second organic layer OL2 may include an organic insulating material. For example, each of the first organic layer OL1 and the second organic layer OL2 may include polyimide (PI). According to an embodiment, each of the first barrier layer BAR1 and the second barrier layer BAR2 may include an inorganic insulating material. For example, each of the first barrier layer BAR1 and the second barrier layer BAR2 may include a silicon compound or amorphous silicon.

[0064] The buffer layer BUF may be disposed on the substrate SUB. According to an embodiment, the buffer layer BUF may include an inorganic insulating material. For example, the buffer layer BUF may include silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0065] The first active layer ACT1 may be disposed on the buffer layer BUF. According to an embodiment, the first active layer ACT1 may include polysilicon. The first electrode, the channel, and the second electrode of the first transistor T1, the first electrode, the channel, and the second electrode of the second transistor T2, the first electrode, the channel, and the second electrode of the fifth transistor T5, the first electrode, the channel, and the second electrode of the sixth transistor T6, and the first electrode, the channel, and the second electrode of the seventh transistor T7 may be formed along the first active layer ACT1.

[0066] The first gate insulating layer GI1 may be disposed on the first active layer ACT1. According to an embodiment, the first gate insulating layer GI1 may include an inorganic insulating material. For example, the first gate insulating layer GI1 may include silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0067] The first gate layer GAT1 may be disposed on the first gate insulating layer GI1. According to an embodiment, the first gate layer GAT1 may include a conductive material. For example, the first gate layer GAT1 may include a metal and a metal compound, etc. The gate electrode of the first transistor T1, the gate electrode G2 of the second transistor T2, the gate electrode of the fifth transistor T5, the gate electrode of the sixth transistor T6, the gate electrode of the seventh transistor T7, and the first electrode of the storage capacitor CST may be formed by the first gate layer GAT1.

[0068] The second gate insulating layer GI2 may be disposed on the first gate layer GAT1. According to an embodiment, the second gate insulating layer GI2 may include an inorganic insulating material. For example, the second gate insulating layer GI2 may include silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0069] The second gate layer GAT2 may be disposed on the second gate insulating layer GI2. According to an embodiment, the second gate layer GAT2 may include a conductive material. For example, the second gate layer GAT2 may include a metal and a metal compound, etc. The bottom gate electrode of the third transistor T3, the bottom gate electrode of the fourth transistor T4, and the second electrode of the storage capacitor CST may be formed by the second gate layer GAT2.

[0070] The first interlayer insulating layer ILD1 may be disposed on the second gate layer GAT2. According to an embodiment, the first interlayer insulating layer ILD1 may include an inorganic insulating material. For example, the first interlayer insulating layer ILD1 may include silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0071] The second active layer may be disposed on the first interlayer insulating layer ILD1. According to an embodiment, the second active layer may include an oxide semiconductor. The first electrode, channel, and second electrode of the third transistor T3 and the first electrode, channel, and second electrode of the fourth transistor T4 may be formed along the second active layer.

[0072] The third gate insulating layer GI3 may be disposed on the second active layer. According to an embodiment, the third gate insulating layer GI3 may include an inorganic insulating material. For example, the third gate insulating layer GI3 may include silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0073] The third gate layer GAT3 may be disposed on the third gate insulating layer GI3. According to an embodiment, the third gate layer GAT3 may include a conductive material. For example, the third gate layer GAT3 may include a metal and a metal compound, etc. The top gate electrode of the third transistor T3 and the top gate electrode of the fourth transistor T4 may be formed by the third gate layer GAT3.

[0074] The second interlayer insulating layer ILD2 may be disposed on the third gate layer GAT3. According to an embodiment, the second interlayer insulating layer ILD2 may include an inorganic insulating material. For example, the second interlayer insulating layer ILD2 may include silicon oxide, silicon nitride, silicon oxynitride, and the like.

[0075] The first source-drain layer may be disposed on the second interlayer insulating layer ILD2. According to an embodiment, the first source-drain layer may include a conductive material. For example, the first source-drain layer may include a metal and a metal compound, etc. The first source-drain layer may include an initialization voltage line IVL and a connection pattern CP. The initialization voltage line IVL may contact a portion of the first active layer ACT1 corresponding to the first electrode of the seventh transistor T7 through a contact hole. The connection pattern CP may contact a portion of the first active layer ACT1 corresponding to the first electrode of the second transistor T2 through a contact hole.

[0076] The first via insulating layer VIA1 may be disposed on the first source-drain layer. According to an embodiment, the first via insulating layer VIA1 may include an inorganic insulating material. For example, the first via insulating layer VIA1 may include silicon oxide, silicon nitride, silicon oxynitride, etc. According to another embodiment, the first via insulating layer VIA1 may include an organic insulating material. For example, the first via insulating layer VIA1 may include polyimide (PI), etc.

[0077] The second source-drain layer may be disposed on the first via insulating layer VIA1. According to an embodiment, the second source-drain layer may include a conductive material. For example, the second source-drain layer may include a metal and a metal compound, etc. The first source-drain layer may include a data line DL. The data line DL may contact the connection pattern CP through a contact hole.

[0078] When viewed in a plan view, the initialization voltage line IVL may be adjacent to the second transistor T2. According to an embodiment, when viewed in a plan view, the initialization voltage line IVL may at least partially overlap with the gate electrode G2 of the second transistor T2. When the initialization voltage line IVL is adjacent to the second transistor T2 when viewed in a plan view, an initialization voltage VAINT less than 0V (e.g., about -7.3V) is applied to the initialization voltage line IVL, and a gate high voltage greater than 0V (about 7.4V) is applied to the gate electrode G2 of the second transistor T2, and an induced charge may be accumulated in a portion of the substrate SUB (e.g., the second organic layer OL2) located below the second transistor T2. When the induced charge accumulates in a portion of the substrate SUB located below the second transistor T2, the threshold voltage of the second transistor T2 may shift, so that the leakage current of the second transistor T2 may increase. When the leakage current of the second transistor T2 increases, flicker may be visually recognized in the image displayed by the display device 100.

[0079] Figure 5 is a diagram for describing control of an initialization voltage VAINT according to an embodiment of the present disclosure.

[0080] Reference Figures 1 to 5 According to an embodiment, the power manager 150 may change the voltage level of the initialization voltage VAINT to a predetermined fixed level L_FXD at or after the power-on time T_PON when power starts to be supplied to the display device 100. The period before the power-on time T_PON may be defined as a power-off period PWROFF. In the power-off period PWROFF, the voltage level of the initialization voltage VAINT may be about 0V. The fixed level L_FXD may be less than 0V and may be, for example, about -5V.

[0081] The power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT before the display on time T_DON at which the display device 100 starts to display an image based on the voltage control signal VCS. The power manager 150 may change the voltage level of the initialization voltage VAINT from the fixed level L_FXD to the initialization level L_INIT in response to the falling edge of the voltage control signal VCS. A period after the power on time T_PON and before the display on time T_DON may be defined as a power on period PWRON. The absolute value of the initialization level L_INIT may be less than the absolute value of the fixed level L_FXD. According to an embodiment, the initialization level L_INIT may be about -1V to about 1V.

[0082] The power manager 150 may change the voltage level of the initialization voltage VAINT to a target level L_TGT corresponding to the brightness of the image at or after the display on time T_DON based on the voltage control signal VCS. The power manager 150 may change the voltage level of the initialization voltage VAINT from the initialization level L_INIT to the target level L_TGT in response to the rising edge of the voltage control signal VCS. The period after the display on time T_DON may be defined as the display on period DISON. The absolute value of the initialization level L_INIT may be less than the absolute value of the target level L_TGT. According to an embodiment, the target level L_TGT may be about -7V to about -2V. The target level L_TGT may gradually decrease as the brightness of the image decreases, and the target level L_TGT may gradually increase as the brightness of the image increases. For example, when the brightness of the image corresponds to the lowest grayscale, the target level L_TGT may be about -7V, and when the brightness of the image corresponds to the highest grayscale, the target level L_TGT may be about -2V.

[0083] According to an embodiment, the polarity of the initialization level L_INIT may be different from the polarity of the target level L_TGT. For example, when the target level L_TGT is less than 0V, the initialization level L_INIT may be greater than 0V.

[0084] Since the voltage level of the initialization voltage VAINT is changed to the initialization level L_INIT having an absolute value less than the absolute value of the target level L_TGT at or after the power-on time T_PON and before the display-on time T_DON in the present embodiment, the amount of induced charge accumulated in the substrate SUB due to the proximity of the initialization voltage line IVL and the second transistor T2 can be reduced, and the shift of the threshold voltage of the second transistor T2 can be reduced. Therefore, the leakage current of the second transistor T2 can be reduced, and the display quality of the image displayed by the display device 100 can be improved. In addition, since the voltage level of the initialization voltage VAINT is changed to the initialization level L_INIT before the display-on time T_DON, the change in the voltage level of the initialization voltage VAINT may not affect the image display of the display device 100.

[0085] Figure 6 is a diagram for describing control of an initialization voltage VAINT according to an embodiment of the present disclosure.

[0086] Reference Figures 1 to 6 According to an embodiment, the power manager 150 may change the voltage level of the initialization voltage VAINT from the target level L_TGT to the fixed level L_FXD at or after the display off time T_DOFF at which the display device 100 starts to end the display of the image. A period after the display on time T_DON and before the display off time T_DOFF may be defined as a display on period DISON. In the display on period DISON, the voltage level of the initialization voltage VAINT may be the target level L_TGT.

[0087] The power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT before the power-off time T_POFF at which the power supplied to the display device 100 starts to be cut off based on the voltage control signal VCS. The power manager 150 may change the voltage level of the initialization voltage VAINT from the fixed level L_FXD to the initialization level L_INIT in response to the falling edge of the voltage control signal VCS. A period after the display-off time T_DOFF and before the power-off time T_POFF may be defined as a display-off period DISOFF.

[0088] The power manager 150 may change the voltage level of the initialization voltage VAINT to about 0 V at or after the power-off time T_POFF based on the voltage control signal VCS. The power manager 150 may change the voltage level of the initialization voltage VAINT from the initialization level L_INIT to about 0 V in response to a rising edge of the voltage control signal VCS. A period after the power-off time T_POFF may be defined as a power-off period PWROFF.

[0089] Since the voltage level of the initialization voltage VAINT is changed to the initialization level L_INIT having an absolute value less than the absolute value of the target level L_TGT at or after the display off time T_DOFF and before the power off time T_POFF in the present embodiment, the amount of induced charge accumulated in the substrate SUB due to the proximity of the initialization voltage line IVL and the second transistor T2 can be reduced, and the shift of the threshold voltage of the second transistor T2 can be reduced. Therefore, the leakage current of the second transistor T2 can be reduced, and the display quality of the image displayed by the display device 100 can be improved. In addition, since the voltage level of the initialization voltage VAINT is changed to the initialization level L_INIT at or after the display off time T_DOFF, the change in the voltage level of the initialization voltage VAINT may not affect the image display of the display device 100.

[0090] Figure 7 is a diagram for describing control of an initialization voltage VAINT according to an embodiment of the present disclosure.

[0091] Reference Figures 1 to 7 According to an embodiment, the power manager 150 may change the voltage level of the initialization voltage VAINT to the target level L_TGT in the active period ACT in which the data voltage VDAT is provided to the pixel PX based on the voltage control signal VCS. The power manager 150 may change the voltage level of the initialization voltage VAINT from the initialization level L_INIT to the target level L_TGT in response to a rising edge of the voltage control signal VCS.

[0092] The power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT in the vertical porch period VP in which the data voltage VDAT is not provided to the pixel PX based on the voltage control signal VCS. The power manager 150 may change the voltage level of the initialization voltage VAINT from the target level L_TGT to the initialization level L_INIT in response to the falling edge of the voltage control signal VCS. The vertical porch period VP may include a vertical front porch period VFP after the active period ACT and a vertical back porch period VBP before the active period ACT.

[0093] Since in the present embodiment, the voltage level of the initialization voltage VAINT is changed to the initialization level L_INIT having an absolute value less than the absolute value of the target level L_TGT in the vertical edge period VP, the amount of induced charge accumulated in the substrate SUB due to the proximity of the initialization voltage line IVL and the second transistor T2 can be reduced, and the shift of the threshold voltage of the second transistor T2 can be reduced. Therefore, the leakage current of the second transistor T2 can be reduced, and the display quality of the image displayed by the display device 100 can be improved. In addition, since the voltage level of the initialization voltage VAINT is changed to the initialization level L_INIT in the vertical edge period VP in which the data voltage VDAT is not supplied to the pixel PX, the influence of the change in the voltage level of the initialization voltage VAINT on the display device 100 can be minimized.

[0094] Figure 8 is a diagram for describing control of an initialization voltage VAINT according to an embodiment of the present disclosure.

[0095] Reference Figure 1 and Figure 8 , also refer to Figure 7 According to an embodiment, the power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT in each of the vertical porch periods VP. For example, as in Case 1, the power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT in each of the consecutive first to fifth vertical porch periods VP1 to VP5.

[0096] According to an embodiment, the power manager 150 may periodically change the voltage level of the initialization voltage VAINT to the initialization level L_INIT in one vertical edge period VP among a plurality of vertical edge periods VP. For example, the power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT in each of the first vertical edge period VP1, the third vertical edge period VP3, and the fifth vertical edge period VP5 as in Case 2, change the voltage level of the initialization voltage VAINT to the initialization level L_INIT in each of the first vertical edge period VP1 and the fourth vertical edge period VP4 as in Case 3, or change the voltage level of the initialization voltage VAINT to the initialization level L_INIT in each of the first vertical edge period VP1 and the fifth vertical edge period VP5 as in Case 4.

[0097] Fig. 9 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0098] Reference Figure 1 , Figure 5 and Fig. 9 According to an embodiment, the power manager 150 may change the voltage level of the initialization voltage VAINT to a fixed level L_FXD at or after the power-on time T_PON (S110). In the power-off period PWROFF, the voltage level of the initialization voltage VAINT may be about 0 V. The fixed level L_FXD may be less than 0 V and may be, for example, about -5 V.

[0099] The power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT before the display on time T_DON based on the voltage control signal VCS (S120). The power manager 150 may change the voltage level of the initialization voltage VAINT from the fixed level L_FXD to the initialization level L_INIT in response to the falling edge of the voltage control signal VCS. The absolute value of the initialization level L_INIT may be less than the absolute value of the fixed level L_FXD. According to an embodiment, the initialization level L_INIT may be about -1V to about 1V.

[0100] The power manager 150 may change the voltage level of the initialization voltage VAINT to a target level L_TGT corresponding to the brightness of the image at or after the display on time T_DON based on the voltage control signal VCS (S130). The power manager 150 may change the voltage level of the initialization voltage VAINT from the initialization level L_INIT to the target level L_TGT in response to the rising edge of the voltage control signal VCS. The absolute value of the initialization level L_INIT may be less than the absolute value of the target level L_TGT. According to an embodiment, the target level L_TGT may be about -7V to about -2V.

[0101] According to an embodiment, the polarity of the initialization level L_INIT may be different from the polarity of the target level L_TGT. For example, when the target level L_TGT is less than 0V, the initialization level L_INIT may be greater than 0V.

[0102] Fig.10 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0103] Reference Figure 1 , Figure 6 and Fig.10 According to an embodiment, the power manager 150 may change the voltage level of the initialization voltage VAINT from the target level L_TGT to the fixed level L_FXD at or after the display off time T_DOFF (S210). In the display on period DISON, the voltage level of the initialization voltage VAINT may be the target level L_TGT.

[0104] The power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT before the power off time T_POFF based on the voltage control signal VCS (S220). The power manager 150 may change the voltage level of the initialization voltage VAINT from the fixed level L_FXD to the initialization level L_INIT in response to a falling edge of the voltage control signal VCS.

[0105] The power manager 150 may change the voltage level of the initialization voltage VAINT to about 0V at or after the power off time T_POFF based on the voltage control signal VCS (S230). The power manager 150 may change the voltage level of the initialization voltage VAINT from the initialization level L_INIT to about 0V in response to a rising edge of the voltage control signal VCS.

[0106] Fig.11 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0107] Reference Figure 1 , Figure 7 and Fig.11 According to an embodiment, the power manager 150 may change the voltage level of the initialization voltage VAINT to the target level L_TGT in the active period ACT based on the voltage control signal VCS (S310). The power manager 150 may change the voltage level of the initialization voltage VAINT from the initialization level L_INIT to the target level L_TGT in response to the rising edge of the voltage control signal VCS.

[0108] The power manager 150 may change the voltage level of the initialization voltage VAINT to the initialization level L_INIT in the vertical porch period VP based on the voltage control signal VCS (S320). The power manager 150 may change the voltage level of the initialization voltage VAINT from the target level L_TGT to the initialization level L_INIT in response to a falling edge of the voltage control signal VCS.

[0109] Fig.12 is a block diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure.

[0110] Reference Fig.12 , the electronic device 1000 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The display device 1160 may be connected to Figure 1The electronic device 1000 may also include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, or other systems.

[0111] The processor 1110 may perform a specific calculation or task. According to an embodiment, the processor 1110 may be a microprocessor or a central processing unit (CPU), etc. The processor 1110 may be connected to other components through an address bus, a control bus, and a data bus, etc. According to an embodiment, the processor 1110 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. According to an embodiment, the processor 1110 may process the first image data ( Figure 1 The first image data IMD1) and the control signal ( Figure 1 The control signal CNT) is provided to the display device 1160.

[0112] The memory device 1120 may store data required for the operation of the electronic device 1000. For example, the memory device 1120 may include: a nonvolatile memory device (such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM)); or a volatile memory device (such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM).

[0113] The storage device 1130 may include a solid state drive (SSD), a hard disk drive (HDD), a compact disk read-only memory (CD-ROM), etc. The I / O device 1140 may include: an input device such as a keyboard, a keypad, a touch pad, a touch screen, or a mouse; and an output device such as a speaker or a printer. The power supply 1150 may supply the power required for the operation of the electronic device 1000. The display device 1160 may be connected to other components through a bus or other communication links.

[0114] According to the display device 1160, at or after the power-on time and before the display-on time, at or after the display-off time and before the power-off time, or in the vertical edge period within the frame period, the absolute value of the voltage level of the initialization voltage can be reduced, so that the amount of induced charge in the flexible substrate can be reduced, and the shift of the threshold voltage of the transistor can be reduced. Therefore, the display quality of the image displayed by the display device 1160 can be improved.

[0115] The display device according to the embodiment can be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a portable multimedia player (PMP), a personal digital assistant (PDA), or an MPEG audio layer 3 (MP3) player, etc.

[0116] Although the embodiments have been described with reference to the drawings, the embodiments are examples and those skilled in the art may make modifications and changes to the embodiments without departing from the scope and spirit of the appended claims.

Claims

1. A display device, wherein: The display device comprises: The display panel includes a plurality of pixels configured to receive an initialization voltage through an initialization voltage line; a controller configured to output a voltage control signal for controlling a voltage level of the initialization voltage; and A power manager is configured to provide the initialization voltage to the initialization voltage line, the power manager changes the voltage level of the initialization voltage to an initialization level at or after a power-on time when power supply starts and before a display-on time when display of an image starts based on the voltage control signal, and the power manager changes the voltage level of the initialization voltage to a target level corresponding to the brightness of the image at or after the display-on time based on the voltage control signal.

2. The display device according to claim 1, wherein: The initialization level is -1V to 1V.

3. The display device according to claim 1, wherein: A polarity of the initialization level is different from a polarity of the target level.

4. The display device according to claim 1, wherein: The power manager is configured to change the voltage level of the initialization voltage to a predetermined fixed level at or after the power-on time and before the voltage level of the initialization voltage is changed to the initialization level, and An absolute value of the initialization level is smaller than an absolute value of the fixed level.

5. The display device according to claim 1, wherein: The power manager is configured to change the voltage level of the initialization voltage from the target level to the initialization level based on the voltage control signal at or after a display off time at which displaying of the image starts to end and before a power off time at which supply of the power starts to be cut off.

6. The display device according to claim 5, wherein: the power manager is configured to change the voltage level of the initialization voltage to a predetermined fixed level at or after the display off time and before the voltage level of the initialization voltage is changed to the initialization level, and An absolute value of the initialization level is smaller than an absolute value of the fixed level.

7. A display device, wherein: The display device comprises: The display panel includes a plurality of pixels configured to receive an initialization voltage through an initialization voltage line; a controller configured to output a voltage control signal for controlling a voltage level of the initialization voltage; and a power manager configured to supply the initialization voltage to the initialization voltage line, and the power manager changes the voltage level of the initialization voltage from a target level corresponding to the brightness of the image to an initialization level at or after a display off time at which a display image starts to end and before a power off time at which supply power starts to be cut off based on the voltage control signal, The absolute value of the initialization level is smaller than the absolute value of the target level.

8. The display device according to claim 7, wherein: A polarity of the initialization level is different from a polarity of the target level.

9. A display device, wherein: The display device comprises: The display panel includes a plurality of pixels configured to receive an initialization voltage through an initialization voltage line; a controller configured to output a voltage control signal for controlling a voltage level of the initialization voltage; and a power manager configured to supply the initialization voltage to the initialization voltage line, the power manager changing the voltage level of the initialization voltage to a target level corresponding to brightness of an image in an effective period in which a data voltage is supplied to each of the plurality of pixels based on the voltage control signal, and the power manager changing the voltage level of the initialization voltage from the target level to an initialization level in a vertical edge period in which the data voltage is not supplied to each of the plurality of pixels based on the voltage control signal, The absolute value of the initialization level is smaller than the absolute value of the target level.

10. The display device according to claim 9, wherein: A polarity of the initialization level is different from a polarity of the target level.

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