Pixel driving circuit and driving method thereof, array substrate and display panel

Abstract

The embodiment of the invention provides a pixel driving circuit and a driving method thereof, an array substrate and a display panel, relates to the technical field of display, and aims to solve the problem that the threshold compensation duration of the pixel driving circuit is insufficient. The pixel driving circuit comprises a driving sub-circuit, a light-emitting control sub-circuit, a write-in sub-circuit, a compensation sub-circuit and a storage sub-circuit. The driving sub-circuit is coupled with the first node, the second node and the third node. The light-emitting control sub-circuit comprises a first branch circuit, and the first branch circuit is coupled with a first power supply signal line, a first enable signal line and a second node. The compensation sub-circuit is coupled with the first scanning signal line, the second scanning signal line, the first node, the third node, the fourth node and the second power supply signal line. The write-in sub-circuit is coupled with the third scanning signal line, the data write-in signal line and the fourth node. The storage sub-circuit is coupled with the first node and the fourth node. The display panel is used for displaying images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, an array substrate and a display panel. Background Art

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used because of their characteristics of self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each sub-pixel includes a pixel driving circuit and a light-emitting device. The light-emitting device is driven by the pixel driving circuit to emit light, thereby realizing display. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a pixel driving circuit and a driving method thereof, an array substrate and a display panel, so as to improve the problem of insufficient threshold compensation time of the pixel driving circuit.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, a pixel driving circuit is provided. The pixel driving circuit includes a driving subcircuit, a light emitting control subcircuit, a writing subcircuit, a compensation subcircuit and a storage subcircuit. The driving subcircuit is coupled to a first node, a second node and a third node, and the driving subcircuit is configured to transmit the voltage from the second node to the third node under the control of the voltage of the first node. The light emitting control subcircuit includes a first branch, and the first branch is coupled to a first power signal line, a first enable signal line and a second node. The first branch is configured to cooperate with the driving subcircuit under the control of a first enable signal from the first enable signal line in a compensation phase, and transmit the first power signal received at the first power signal line to the third node. The compensation subcircuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node and a second power signal line. The compensation subcircuit is configured to, in a compensation phase, transfer the voltage of the third node to the first node under the control of the first scan signal received at the first scan signal line, and transfer the second power signal received at the second power signal line to the fourth node under the control of the second scan signal received at the second scan signal line. The write subcircuit is coupled to the third scan signal line, the data write signal line and the fourth node. The write subcircuit is configured to, in a write phase, transfer the data write signal received at the data write signal line to the fourth node under the control of the third scan signal received at the third scan signal line. The storage subcircuit is coupled to the first node and the fourth node. In the write phase, the storage subcircuit is configured to couple the voltage of the fourth node to the first node.

[0006] The above pixel driving circuit can utilize the driving subcircuit, the light emitting control subcircuit, the writing subcircuit, the compensation subcircuit and the storage subcircuit to cooperate with each other, and the writing data voltage and the compensation threshold voltage can be realized through two separate paths respectively, so as to separate the threshold compensation stage from the writing stage, so as to prevent the duration of the writing stage from limiting the duration of the threshold compensation stage. That is, the duration of the threshold compensation stage can be made unaffected by the data writing time (row time), and it can be ensured that the threshold compensation stage has a sufficient duration to fully write the required voltage, so as to compensate for the threshold voltage fluctuation in a larger range, so that the threshold voltage is fully compensated.

[0007] Based on this, the pixel driving circuit provided in the embodiment of the present disclosure can fully compensate the threshold voltage of the driving sub-circuit (driving transistor) in the pixel driving circuit even at a high refresh rate, or in a low grayscale image or black state, which can help improve the difference in display brightness and enhance the uniformity of display image quality.

[0008] In some embodiments, the driving subcircuit includes a driving transistor, a control electrode of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node.

[0009] In some embodiments, the compensation subcircuit includes a second transistor and a ninth transistor. The control electrode of the second transistor is coupled to the first scan signal line, the first electrode of the second transistor is coupled to the third node, and the second electrode of the second transistor is coupled to the first node. The control electrode of the ninth transistor is coupled to the third scan signal line, the first electrode of the ninth transistor is coupled to the second power signal line, and the second electrode of the ninth transistor is coupled to the fourth node.

[0010] In some embodiments, the writing subcircuit includes a fourth transistor, a control electrode of the fourth transistor is coupled to the third scanning signal line, a first electrode of the fourth transistor is coupled to the data writing signal line, and a second electrode of the fourth transistor is coupled to the fourth node.

[0011] In some embodiments, the storage subcircuit includes a storage capacitor, a first plate of the storage capacitor is coupled to the fourth node, and a second plate of the storage capacitor is coupled to the first node.

[0012] In some embodiments, the light-emitting control subcircuit further includes a second branch, the second branch is coupled to the third node, the second enable signal line and the light-emitting device. In the light-emitting stage, the light-emitting control subcircuit is configured to cooperate with the driving subcircuit under the control of the first enable signal from the first enable signal line and the second enable signal from the second enable signal line to transmit the first power signal received at the first power signal line to the light-emitting device.

[0013] In some embodiments, the first branch includes a fifth transistor, the control electrode of the fifth transistor is coupled to the first enable signal line, the first electrode of the fifth transistor is coupled to the first power signal line, and the second electrode of the fifth transistor is coupled to the second node. The second branch includes a sixth transistor, the control electrode of the sixth transistor is coupled to the second enable signal line, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the light emitting device.

[0014] In some embodiments, the pixel driving circuit further includes a first reset subcircuit. The first reset subcircuit is coupled to the first node, the first reset signal line, and the first initialization signal line. The first reset subcircuit is configured to, under the control of a first reset signal received from the first reset signal line, transmit the first initialization signal received from the first initialization signal line to the first node to reset the first node.

[0015] In some embodiments, the first reset subcircuit includes a first transistor, a control electrode of the first transistor is coupled to the first reset signal line, a first electrode of the first transistor is coupled to the first initialization signal line, and a second electrode of the first transistor is coupled to the first node.

[0016] In some embodiments, the pixel driving circuit further includes a second reset subcircuit. The second reset subcircuit is coupled to the light-emitting device, the second reset signal line, and the second initialization signal line. The second reset subcircuit is configured to, under the control of the second reset signal received from the second reset signal line, transmit the second initialization signal received from the second initialization signal line to the light-emitting device to reset the light-emitting device.

[0017] In some embodiments, the second reset subcircuit includes a seventh transistor, a control electrode of the seventh transistor is coupled to the second reset signal line, a first electrode of the seventh transistor is coupled to the second initialization signal line, and a seventh electrode of the eighth transistor is coupled to the light emitting device.

[0018] In some embodiments, the pixel driving circuit further includes a third reset subcircuit. The third reset subcircuit is coupled to the second node, the third reset signal line, and the first reference voltage signal line. The third reset subcircuit is configured to, under the control of a third reset signal received from the third reset signal line, transmit the first reference voltage signal received from the first reference voltage signal line to the second node to reset the second node.

[0019] In some embodiments, the third reset subcircuit includes an eighth transistor, a control electrode of the eighth transistor is coupled to the third reset signal line, a first electrode of the eighth transistor is coupled to the first reference voltage signal line, and a second electrode of the eighth transistor is coupled to the second node.

[0020] In some embodiments, a voltage value of the first power signal is equal to a voltage value of the second power signal.

[0021] In some embodiments, the first power signal line is multiplexed as the second power signal line.

[0022] In some embodiments, when the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor: at least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is a dual-gate transistor.

[0023] In some embodiments, when the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor: at least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is an N-type transistor.

[0024] On the other hand, a driving method of a pixel driving circuit is provided. The pixel driving circuit includes: a driving subcircuit, a light-emitting control subcircuit, a writing subcircuit, a compensation subcircuit and a storage subcircuit. The driving subcircuit is coupled to a first node, a second node and a third node. The light-emitting control subcircuit includes a first branch, and the first branch is coupled to a first power signal line, a first enable signal line and a second node. The compensation subcircuit is coupled to a first scanning signal line, a second scanning signal line, the first node, the third node, a fourth node, a first power signal line and a second power signal line. The writing subcircuit is coupled to a third scanning signal line, a data writing signal line and the fourth node. The storage subcircuit is coupled to the first node and the fourth node.

[0025] The driving method includes: a compensation phase and a writing phase. In the compensation phase, the first branch, under the control of the first enable signal from the first enable signal line, cooperates with the driving sub-circuit to transmit the first power signal received at the first power signal line to the third node. The compensation sub-circuit, under the control of the first scan signal received from the first scan signal line, transmits the voltage of the third node to the first node; under the control of the second scan signal received from the second scan signal line, transmits the second power signal received at the second power signal line to the fourth node. And, the storage sub-circuit receives the voltage of the first node and the voltage of the fourth node. In the writing phase, the writing sub-circuit, under the control of the third scan signal received from the third scan signal line, transmits the data write signal received at the data write signal line to the fourth node. And, the storage sub-circuit couples the voltage of the fourth node to the first node.

[0026] In some embodiments, the pixel driving circuit further includes a third reset subcircuit, the third reset subcircuit being coupled to the second node, the third reset signal line and the first reference voltage signal line. The driving method further includes a first reset phase. In the first reset phase, the third reset subcircuit, under the control of a third reset signal received from the third reset signal line, transmits the first reference voltage signal received from the first reference voltage signal line to the second node, thereby resetting the second node.

[0027] In some embodiments, the pixel driving circuit further includes a first reset subcircuit, the first reset subcircuit being coupled to the first node, the first reset signal line and the first initialization signal line. The driving method further includes a first initialization phase. In the first initialization phase, the first reset subcircuit, under the control of a first reset signal received from the first reset signal line, transmits a first initialization signal received from the first initialization signal line to the first node to initialize the first node.

[0028] In some embodiments, the driving method further includes a second initialization stage. In the second initialization stage, the first reset subcircuit transmits the first initialization signal received from the first initialization signal line to the first node under the control of the first reset signal received from the first reset signal line. The compensation subcircuit transmits the voltage of the first node to the third node under the control of the first scan signal received from the first scan signal line. And the driving subcircuit transmits the voltage from the second node to the third node under the control of the voltage of the first node to initialize the first node, the second node and the third node.

[0029] The driving method of the above pixel driving circuit has the same structure and beneficial technical effects as the pixel driving circuits provided in some of the above embodiments, which will not be described in detail here.

[0030] In another aspect, an array substrate is provided, comprising a substrate and a plurality of pixel driving circuits as described in any of the above embodiments located on the substrate.

[0031] In some embodiments, the plurality of pixel driving circuits are arranged in multiple rows and columns. The array substrate further includes: a plurality of first scanning signal lines, a plurality of second scanning signal lines, and a plurality of first reset signal lines. The plurality of first scanning signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The second direction intersects with the first direction. The plurality of second scanning signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. The plurality of first reset signal lines are located on one side of the substrate, extend along the first direction, and are arranged along the second direction. Among them, the second scanning signal line coupled to the nth row of pixel driving circuits, the first scanning signal line coupled to the n+3th row of pixel driving circuits, and the first reset signal line coupled to the n+6th row of pixel driving circuits respond to the control of the same control signal, and n is a positive integer.

[0032] The array substrate has the same structure and beneficial technical effects as the pixel driving circuits provided in some of the above embodiments, which will not be described in detail here.

[0033] In another aspect, a display panel is provided, wherein the display panel comprises a light emitting device layer and an array substrate as described in any one of the above embodiments, wherein the light emitting device layer comprises a plurality of light emitting devices, and the pixel driving circuit is coupled to the light emitting devices.

[0034] The above-mentioned display panel has the same structure and beneficial technical effects as the array substrate provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0036] Figure 1 is a structural diagram of a display device according to some embodiments;

[0037] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0038] Figure 3 is a cross-sectional view of a display panel according to some embodiments;

[0039] Figure 4 is a structural diagram of an array substrate according to some embodiments;

[0040] Figure 5 is an equivalent circuit diagram of a pixel driving circuit according to some possible implementation schemes;

[0041] Figure 6 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0042] Figure 7 is an equivalent circuit diagram of a pixel driving circuit according to some other embodiments;

[0043] Figure 8 is an equivalent circuit diagram of a pixel driving circuit according to some further embodiments;

[0044] Fig. 9 is an equivalent circuit diagram of a pixel driving circuit according to some further embodiments;

[0045] Fig.10 is an equivalent circuit diagram of a pixel driving circuit according to some further embodiments;

[0046] Fig.11 is a timing diagram of a pixel driving circuit according to some embodiments;

[0047] Fig.12 is a timing diagram of a pixel driving circuit according to some other embodiments;

[0048] Fig.13 is a structural diagram of an array substrate according to some other embodiments;

[0049] Fig.14 is a timing diagram of a pixel driving circuit according to some further embodiments;

[0050] Fig.15 is a timing diagram of a pixel driving circuit according to some further embodiments. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0052] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0053] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0054] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0055] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0056] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0057] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0058] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0059] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0060] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0061] As used herein, "vertical" includes the conditions described and conditions similar to the conditions described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "vertical" includes absolute vertical and approximate vertical, wherein the acceptable deviation range of approximate vertical can also be, for example, a deviation within 5°.

[0062] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0063] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0064] In the circuit structure provided by the embodiments of the present disclosure, the first node, the second node and other nodes do not represent actually existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0065] In the circuit structure provided in the embodiment of the present disclosure, the first electrode of each transistor used is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure can be indistinguishable in structure.

[0066] Figure 1 is a structural diagram of a display device according to some embodiments. Figure 1 As shown, some embodiments of the present disclosure provide a display device 300 , which includes a display panel 200 .

[0067] Exemplarily, the display device 300 also includes a frame and other electronic accessories.

[0068] Exemplarily, the display device 300 may be an electroluminescent display device or a photoluminescent display device. When the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). When the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0069] Exemplarily, the display device 300 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0070] Figure 2 is a structural diagram of a display panel according to some embodiments, Figure 3 is a cross-sectional view of a display panel according to some embodiments.

[0071] Some embodiments of the present disclosure provide a display panel 200. Figure 2 and Figure 3 As shown, the display panel 200 includes a display area (full name in English: Active Area, referred to as AA area; also referred to as effective display area) AA. The display area AA includes a plurality of sub-pixel areas P, and the plurality of sub-pixel areas P can be arranged in an array. The sub-pixel area P is the smallest unit for the display panel 200 to display a picture.

[0072] In some examples, a sub-pixel region P includes a pixel driving circuit Q and a light-emitting device O electrically connected to the pixel driving circuit Q. The pixel driving circuit Q can be adjusted based on a plurality of different types of signal lines to generate a driving signal, and each light-emitting device O can emit light under the driving action of the driving signal generated by the corresponding pixel driving circuit Q. Based on this, the pixel driving circuits Q in the plurality of sub-pixel regions can drive the corresponding light-emitting devices O to emit light, so that the display panel 200 can display a predetermined image in the display area AA. Specifically, the plurality of sub-pixel regions P may include a plurality of sub-pixel regions P with different luminous colors.

[0073] Exemplarily, the plurality of sub-pixel regions P may include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first sub-pixel region, the second sub-pixel region, and the third sub-pixel region emit three primary colors of light, respectively. For example, the first sub-pixel region may emit red light, the second sub-pixel region may emit green light, and the third sub-pixel region may emit blue light. Based on this, by adjusting the brightness (grayscale) of the sub-pixel regions P of different colors, the display of multiple colors can be achieved through color combination and superposition, thereby achieving full-color display of the display panel 200.

[0074] Please continue to combine Figure 2 and Figure 3 As shown, the display panel 200 further includes an array substrate 100 and a light emitting device layer 210. The array substrate 100 may include a plurality of pixel driving circuits Q. The light emitting device layer 210 is located on one side of the array substrate 100, and the light emitting device layer 210 includes a plurality of light emitting devices O, and the light emitting devices O are electrically connected to the pixel driving circuit Q in the array substrate 100.

[0075] In some examples, the light-emitting device O includes an anode layer, a light-emitting layer, and a cathode layer stacked in sequence. In some examples, an electron transport layer is further provided between the cathode layer and the light-emitting layer, and a hole transport layer is further provided between the anode layer and the light-emitting layer. Exemplarily, the light-emitting device O may be an OLED light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device, that is, the light-emitting device O may be any other light-emitting device (e.g., a light-emitting device that emits light by discharge), as long as they can emit light so that the display panel 200 can display a picture.

[0076] In some examples, the plurality of pixel driving circuits Q and the plurality of light emitting devices O may be coupled one-to-one. In other examples, one pixel driving circuit Q may be coupled to a plurality of light emitting devices O, or a plurality of pixel driving circuits Q may be coupled to one light emitting device O.

[0077] Below, the present disclosure takes the coupling of a pixel driving circuit Q and a light-emitting device O as an example to schematically illustrate the structure of the display panel 200 .

[0078] Figure 4 is a structural diagram of an array substrate according to some embodiments.

[0079] See also Figure 4 As shown, some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a substrate 01 and a pixel circuit layer 02 located on one side of the substrate 01. The pixel circuit layer 02 includes a plurality of pixel driving circuits Q.

[0080] In some examples, the substrate 01 may be a flexible substrate. Exemplarily, the material of the substrate 01 may be an organic material. For example, the material of the substrate 01 may be any one of polyimide (full name in English: Polyimide, English abbreviation: PI), polycarbonate (full name in English: Polycarbonate, English abbreviation: PC) or polyvinyl chloride (full name in English: Polyvinyl Chloride, English abbreviation: PVC).

[0081] In some other examples, the substrate 01 may be a rigid substrate. For example, the rigid substrate may be a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0082] In some examples, the pixel circuit layer 02 includes multiple metal layers stacked on the substrate 01. The multiple metal layers are provided with pixel driving circuits Q and multiple different types of signal lines. Among them, the different types of signal lines include multiple first scanning signal lines G1, but are not limited thereto. The different types of signal lines may also include other types of signal lines, which will be described in detail below.

[0083] The plurality of pixel driving circuits Q are located on one side of the substrate 01 and are arranged in multiple rows and columns. For the convenience of description, the plurality of pixel driving circuits Q are described in the present disclosure by taking the arrangement in matrix as an example.

[0084] At this time, return Figure 2 As shown, the pixel driving circuits Q arranged in a row along the first direction X are called a row of pixel driving circuits Q, and the pixel driving circuits Q arranged in a row along the second direction Y are called a column of pixel driving circuits Q.

[0085] Figure 5 is an equivalent circuit diagram of a pixel driving circuit according to some possible implementation schemes.

[0086] See also Figure 5 As shown, the pixel driving circuit Q may be a first pixel driving circuit. The first pixel driving circuit includes: a first reset transistor M1, a compensation transistor M2, a driving transistor M3, a data writing transistor M4, a first light emission control transistor M5, a second light emission control transistor M6, a second reset transistor M7 and a capacitor Cst.

[0087] Since the first pixel driving circuit needs to be electrically connected to a variety of different types of signal lines, Figure 5, various types of signal lines are also illustrated. The various types of signal lines may include: a first scan signal line G1, a second scan signal line G2, a data write signal line Data, an enable signal line EM, a first power signal line Vdd, a first reset signal line R1, a second reset signal line R2, a first initialization signal line Vinit1, and a second initialization signal line Vinit2.

[0088] The control electrode of the first reset transistor M1 is coupled to the first reset signal line R1 , the first electrode of the first reset transistor M1 is coupled to the first initialization signal line Vinit1 , and the second electrode of the first reset transistor M1 is coupled to the first node N1 .

[0089] A control electrode of the compensation transistor M2 is coupled to the first scan signal line Gate1 , a first electrode of the compensation transistor M2 is coupled to the first node N1 , and a second electrode of the compensation transistor M2 is coupled to the third node N3 .

[0090] The control electrode of the driving transistor M3 is coupled to the first node N1 , the first electrode of the driving transistor M3 is coupled to the second node N2 , and the second electrode of the driving transistor M3 is coupled to the third node N3 .

[0091] A control electrode of the data writing transistor M4 is coupled to the second scanning signal line Gate2 , a first electrode of the data writing transistor M4 is coupled to the data writing signal line Data, and a second electrode of the data writing transistor M4 is coupled to the second node N2 .

[0092] A control electrode of the first light emission control transistor M5 is coupled to the enable signal line EM, a first electrode of the first light emission control transistor M5 is coupled to the first power signal line VDD, and a second electrode of the first light emission control transistor M5 is coupled to the second node N2.

[0093] The control electrode of the second light emitting control transistor M6 is coupled to the enable signal line EM, the first electrode of the second light emitting control transistor M6 is coupled to the third node N3, and the second electrode of the second light emitting control transistor M6 is coupled to one end of the light emitting device O. The other end of the light emitting device O is coupled to the third power signal line VSS. The voltage value of the third power signal provided by the third power signal line VSS is less than the voltage value of the first power signal provided by the first power signal line VDD.

[0094] Exemplarily, one end of the light emitting device O coupled to the first pixel driving circuit is the anode of the light emitting device O, and one end of the light emitting device O coupled to the third power signal point VSS is the cathode of the light emitting device O.

[0095] A control electrode of the second reset transistor M7 is coupled to the second reset signal line R2 , a first electrode of the second reset transistor M7 is coupled to the second initialization signal line Vinit2 , and a second electrode of the second reset transistor M7 is coupled to the light emitting device O.

[0096] It should be noted that each sub-pixel in the display panel 200 is driven by multiple thin film transistors (TFTs) to emit light. The use of TFT driving technology can improve display speed, contrast, brightness, and resolution. However, TFT has a hysteresis effect. The hysteresis effect of TFT is an uncertainty in the electrical characteristics of TFT under a certain bias voltage, that is, the current flowing through the TFT is not only related to the current bias voltage, but also to the state of the TFT at the previous moment. The hysteresis effect of TFT is related to the gate dielectric, semiconductor material, and interface state traps of the TFT. In the light-emitting stage, the hysteresis effect of TFT will cause a trend of current decrease within a frame, which is perceived by the human eye as a flickering phenomenon, thereby affecting the display quality of the display panel 200.

[0097] In order to improve the hysteresis effect of the driving transistor M3, the threshold voltage of the pixel circuit is usually compensated to improve the brightness uniformity of the entire display screen. Specifically, the threshold voltage of the pixel circuit can be compensated when data is written.

[0098] In some embodiments, Figure 5 The driving process of the first pixel driving circuit shown is: one frame period includes an initialization phase, a writing phase and a light emitting phase.

[0099] Initialization stage: the first reset signal transmitted by the first reset signal line R1 is a valid signal. At this time, the first reset transistor M1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 is transmitted to the third node N3, and the third node N3 is reset, so as to improve the stability of the driving transistor M3 included in the first pixel driving circuit.

[0100] Writing stage: The first scanning signal transmitted by the first scanning signal line G1 is a valid signal, and the compensation transistor M2 is turned on. Also, the second scanning signal transmitted by the second scanning signal line G2 is a valid signal, at which time the data writing transistor M4 is turned on, and the data writing signal transmitted by the data writing signal line Data can be transmitted to the first node N1 through the data writing transistor M4, the driving transistor M3, and the compensation transistor M2 in sequence, and the first node N1 is compensated, and the potential of the first node N1 gradually rises to Vdata+Vth.

[0101] Wherein, Vdata is the voltage value of the data write signal provided by the data write signal line Data, and Vth is the threshold voltage of the driving transistor M3 in the first pixel driving circuit. When the potential of the first node N1 is Vdata+Vth, the charging process is completed. Subsequently, the storage capacitor Cst is discharged to keep the driving transistor M3 included in the first pixel driving circuit continuously turned on to ensure that the light-emitting device O emits light.

[0102] Light-emitting stage: the enable signal transmitted by the enable signal line EM is a valid signal, at which time the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned on. At this time, the storage capacitor Cst is discharged to keep the driving transistor M3 included in the first pixel driving circuit continuously turned on.

[0103] Based on this, the constant voltage power signal provided by the first power signal line Vdd can flow through the first light emission control transistor M5, the driving transistor M3, and the second light emission control transistor M6 in sequence to the anode of the light emitting device O, and the cathode of the light emitting device O can be electrically connected to the second power signal line Vss, thereby driving the light emitting device O to emit light. Among them, the first power signal line Vdd can be a high power signal line, and the third power signal line Vss can be a low power signal line.

[0104] It should be noted that the “effective signal” refers to a signal that can turn on the transistor to which it is electrically connected. For example, if the first scanning signal line G1 is electrically connected to a P-type transistor, the effective signal is a low voltage signal, or if the first scanning signal line G1 is electrically connected to an N-type transistor, the effective signal is a high voltage signal, and the same is true for other signal lines.

[0105] The inventors have found that in the above working process of the first pixel driving circuit, since the threshold compensation and the data voltage writing are in the same phase (writing phase), the threshold compensation time and the row cycle cannot be separated.

[0106] When the display panel 200 has a high resolution or is driven at a high refresh rate, the row period of the display panel 200 becomes shorter, that is, the row period of each first pixel driving circuit becomes shorter, which shortens the writing phase of the first pixel driving circuit, resulting in a shorter threshold compensation time of the first pixel driving circuit, poor threshold compensation effect of the pixel driving circuit, and poor display uniformity of the display panel 200.

[0107] Furthermore, when the display panel 200 is in a low grayscale image or black state, the voltage value Vdata of the data write signal provided by the data write signal line Data required by the driving transistor M3 is larger, which will result in a longer time required for data writing and thus a shorter threshold compensation time of the first pixel driving circuit. The threshold compensation effect of the pixel driving circuit is poor, which will result in poor display uniformity of the display panel 200.

[0108] Figure 6 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments.

[0109] Based on the above questions, please refer to Figure 6 As shown, some embodiments of the present disclosure provide a pixel driving circuit Q. The pixel driving circuit Q may be a second type of pixel driving circuit. The pixel driving circuits Q hereinafter are all second type of pixel driving circuits.

[0110] The pixel driving circuit Q (the second pixel driving circuit) includes a driving sub-circuit 10 , a light emitting control sub-circuit 20 , a writing sub-circuit 30 , a compensation sub-circuit 40 and a storage sub-circuit 50 .

[0111] The driving subcircuit 10 is coupled to the first node N1, the second node N2 and the third node N3. The driving subcircuit 10 is configured to transmit the voltage from the second node N2 to the third node N3 under the control of the voltage of the first node N1. The driving subcircuit 10 includes a driving transistor.

[0112] The light emitting control subcircuit 20 includes a first branch 21, which is coupled to the first power signal line VDD, the first enable signal line EM1 and the second node N2. The first branch 21 is configured to cooperate with the driving subcircuit 10 under the control of the first enable signal from the first enable signal line EM1 in the compensation stage, and transmit the first power signal received at the first power signal line VDD to the third node N3.

[0113] The compensation sub-circuit 40 is coupled to the first scan signal line Gate1, the second scan signal line Gate2, the first node N1, the third node N3, the fourth node N4 and the second power signal line VGH. The compensation sub-circuit 40 is configured to, in the compensation phase, transfer the voltage of the third node N3 to the first node N1 under the control of the first scan signal received at the first scan signal line Gate1, and transfer the second power signal received at the second power signal line VGH to the fourth node N4 under the control of the second scan signal received at the second scan signal line Gate2.

[0114] The writing sub-circuit 30 is coupled to the third scanning signal line Gate3, the data writing signal line Date and the fourth node N4. The writing sub-circuit 30 is configured to, in the writing phase, under the control of the third scanning signal received at the third scanning signal line Gate3, transmit the data writing signal received at the data writing signal line Date to the fourth node N4.

[0115] The storage sub-circuit 50 is coupled to the first node N1 and the fourth node N4. In the writing phase, the storage sub-circuit 50 is configured to couple the voltage of the fourth node N4 to the first node N1.

[0116] Using the above-mentioned setting method, in the compensation stage, the first enable signal of the first enable signal line EM1 is a valid signal, which controls the first branch 21 in the light-emitting control subcircuit 20 to be turned on, the first scanning signal received at the first scanning signal line Gate1 is a valid signal, and the second scanning signal received at the second scanning signal line Gate2 is also a valid signal, which controls the compensation subcircuit 40 to be turned on.

[0117] Based on this, the compensation sub-circuit 40 is controlled to be turned on, and the second power signal received at the second power signal line VGH can be transmitted to the fourth node N4. At this time, the voltage of the fourth node N4 is the voltage V2 of the second power signal.

[0118] Furthermore, based on controlling the compensation sub-circuit 40 to be turned on, the first branch 21 is turned on, and then cooperating with the driving sub-circuit 10 (at this time, the driving sub-circuit 10 is in the on state), the first power signal received at the first power signal line VDD can be transmitted to the first node N1 via the second node N2 and the third node N3, and the first node N1 is compensated, and the potential of the first node N1 gradually rises to V1+Vth.

[0119] Wherein, V1 is the voltage value of the first power signal provided by the first power signal line VDD, and Vth is the threshold voltage of the driving sub-circuit 10 (driving transistor T3) in the second pixel driving circuit. When the potential of the first node N1 is V1+Vth, the driving sub-circuit 10 (driving transistor T3) is turned off to complete the threshold compensation.

[0120] At the same time, since the storage sub-circuit 50 is connected in series between the first node N1 and the fourth node N4, one end of the storage sub-circuit 50 receives the voltage V2 from the fourth node N4, and the other end of the storage sub-circuit 50 receives the voltage V1+Vth from the first node N1, and the storage sub-circuit 50 determines the voltage difference between its two ends.

[0121] Subsequently, the storage capacitor Cst is discharged to keep the driving subcircuit 10 (driving transistor T3) included in the second pixel driving circuit continuously turned on, so as to ensure that the light-emitting device O emits light.

[0122] After the compensation phase, when entering the writing phase, the third scanning signal received at the third scanning signal line Gate3 is a valid signal, and the control writing sub-circuit 30 is turned on, and the data writing signal received at the data writing signal line Date is transmitted to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the voltage change amount of the fourth node N4 Δ=Vdata-V2. Among them, Vdata is the voltage value of the data writing signal provided by the data writing signal line Data.

[0123] Due to the coupling effect of the storage subcircuit 50, the voltage of the first node N1 follows the change of the voltage of the fourth node N4, and the voltage change of the first node N1 is also approximately Δ=Vdata-V2. Based on this, the voltage of the first node N1 can be changed from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0124] In the light-emitting stage, the first enable signal of the first enable signal line EM1 is a valid signal, which controls the first branch 21 in the light-emitting control subcircuit 20 to be turned on, and the first power signal received at the first power signal line VDD can be transmitted to the second node N2. At this time, the voltage of the second node N2 is V1. In cooperation with the driving subcircuit 10, the voltage of the second node N2 can be transmitted to the third node N3, and finally to the light-emitting device O. In addition, the voltage of the first node N1 is maintained at Vdata+Vth.

[0125] The light emitting current of the light emitting device O electrically connected to the pixel driving circuit Q is equal to the current flowing through the driving sub-circuit 10, and its expression is as follows:

[0126]

[0127] Wherein, μ is the electron mobility of the driving subcircuit 10 (driving transistor), Cox is the insulation capacitance per unit area, is the width-to-length ratio of the driving subcircuit 10 (driving transistor), Vth is the threshold voltage of the driving subcircuit 10 (driving transistor), and Vgs is the gate-source voltage of the driving subcircuit 10 (driving transistor), that is, Vgs is the difference between the voltage of the first node N1 and the voltage of the second node N2, and its expression is as follows:

[0128] Vgs=V1+Vth+Vdata-V2-V1=Vth+Vdata-V2; (2);

[0129] Based on this, substituting expression (2) into expression (1), we get the following expression:

[0130]

[0131] It can be seen from this that the current I flowing through the driving sub-circuit 10 (driving transistor) D The current I flowing through the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V2 of the second power signal provided by the second power signal line VGH. D It has nothing to do with the threshold voltage Vth. Based on this, it is beneficial to improve the influence of the threshold voltage Vth on the luminance of the light-emitting device O, and improve the uniformity of the luminance of the light-emitting device O.

[0132] In summary, the pixel driving circuit Q provided in the embodiment of the present disclosure can utilize the driving subcircuit 10, the light emitting control subcircuit 20, the writing subcircuit 30, the compensation subcircuit 40 and the storage subcircuit 50 to cooperate with each other, and the writing data voltage Vdata and the compensation threshold voltage are respectively realized through two separate paths, and the threshold compensation stage is separated from the writing stage to prevent the duration of the writing stage from limiting the duration of the threshold compensation stage. That is, the duration of the threshold compensation stage can be made unaffected by the data writing time (row time), and it can be ensured that the threshold compensation stage has a sufficient duration to fully write the required voltage to compensate for the threshold voltage fluctuation in a larger range, so that the threshold voltage is fully compensated.

[0133] Based on this, the problem of poor display uniformity of a display panel 200 with high resolution or a display panel 200 driven with a high refresh rate due to insufficient duration of the Q threshold compensation phase of the pixel driving circuit can be effectively improved. Also, the problem of poor display uniformity of the display panel 200 in a low grayscale image or black state due to insufficient duration of the threshold compensation phase when driving the pixel driving circuit can be effectively improved.

[0134] That is, the pixel driving circuit Q provided in the embodiment of the present disclosure can fully compensate the threshold voltage of the driving sub-circuit 10 (driving transistor T3) in the pixel driving circuit Q even at a high refresh rate, or in a low grayscale image or black state, which can help improve the difference in display brightness and enhance the uniformity of display image quality.

[0135] In some embodiments, see Figure 6 As shown, the voltage value V1 of the first power supply signal is equal to the voltage value V2 of the second power supply signal, and the expression is as follows:

[0136] V2=V1;(4);

[0137] Based on this, after the compensation stage and in the light emitting stage, the voltage of the first node N1 may be V1+Vth+Vdata-V2=Vth+Vdata.

[0138] Furthermore, the gate-source voltage Vgs of the driving sub-circuit 10 (driving transistor) is Vth+Vdata-V1; (5);

[0139] Substituting expression (5) into the above expression (1), we get the following expression:

[0140]

[0141] It can be seen from this that the current I flowing through the driving sub-circuit 10 (driving transistor) D The current I of the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V1 of the first power supply signal provided by the first power supply signal line VDD. D It has nothing to do with the threshold voltage Vth. Based on this, it is beneficial to improve the influence of the threshold voltage Vth on the luminance of the light-emitting device O, and improve the uniformity of the luminance of the light-emitting device O.

[0142] In some embodiments, see Figure 6 As shown, the first power signal line VDD is multiplexed as the second power signal line VGH.

[0143] With this arrangement, on the one hand, the first power signal line VDD is multiplexed as the second power signal line VGH, that is, there is no need to set up the second power signal line VGH separately, which can help simplify the structure of the pixel driving circuit Q and reduce the layout difficulty in the display panel 200.

[0144] On the other hand, the first power signal line VDD is multiplexed as the second power signal line VGH, so that the voltage value V1 of the first power signal is equal to the voltage value V2 of the second power signal, and thus the current I flowing through the driving sub-circuit 10 (driving transistor) is D The current I of the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V1 of the first power supply signal provided by the first power supply signal line VDD. D It has nothing to do with the threshold voltage Vth. Based on this, it is beneficial to improve the influence of the threshold voltage Vth on the luminance of the light-emitting device O, and improve the uniformity of the luminance of the light-emitting device O.

[0145] Figure 7 is an equivalent circuit diagram of a pixel driving circuit according to some other embodiments.

[0146] In some embodiments, see Figure 7As shown, the driving sub-circuit 10 includes a driving transistor T3, a control electrode of the driving transistor T3 is coupled to the first node N1, a first electrode of the driving transistor T3 is coupled to the second node N2, and a second electrode of the driving transistor T3 is coupled to the third node N3.

[0147] When the voltage of the first node N1 is a valid signal, the driving transistor T3 may be turned on under the control of the voltage of the first node N1 to transmit the electrical signal (eg, data signal) from the second node N2 to the third node N3 .

[0148] It should be noted that the "effective signal" in the present disclosure refers to a signal that can turn on a transistor. When the transistor is an N-type transistor, the "effective signal" is a high voltage signal; when the transistor is a P-type transistor, the "effective signal" is a low voltage signal. The following embodiments are the same and will not be repeated.

[0149] Exemplarily, when the driving transistor T3 is a P-type transistor, the driving transistor T3 is controlled to be turned on when the voltage of the first node N1 is a low voltage signal, and the electrical signal (eg, data signal) from the second node N2 can be transmitted to the third node N3.

[0150] Exemplarily, when the driving transistor T3 is an N-type transistor, the driving transistor T3 is controlled to be turned on when the voltage of the first node N1 is a high voltage signal, and the electrical signal (eg, data signal) from the second node N2 can be transmitted to the third node N3.

[0151] It should be noted that the “high voltage signal” and “low voltage signal” mentioned above are popular terms. Generally speaking, the opening condition of an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage, and the threshold voltage of the N-type transistor is a positive value. In this case, the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The opening condition of a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage, and the threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. In this case, the gate voltage signal that turns on the P-type transistor is called a low voltage signal, wherein the voltage of the “high voltage signal” is greater than the voltage of the “low voltage signal”.

[0152] In some embodiments, see Figure 7As shown, the compensation sub-circuit 40 includes a second transistor T2 and a ninth transistor T9. The control electrode of the second transistor T2 is coupled to the first scan signal line Gate1, the first electrode of the second transistor T2 is coupled to the third node N3, and the second electrode of the second transistor T2 is coupled to the first node N1. The control electrode of the ninth transistor T9 is coupled to the third scan signal line Gate3, the first electrode of the ninth transistor T9 is coupled to the second power signal line VGH, and the second electrode of the ninth transistor T9 is coupled to the fourth node N4.

[0153] Based on this, in the compensation stage, the second scan signal received at the second scan signal line Gate2 is also a valid signal, which controls the ninth transistor T9 to be turned on, and can transmit the second power signal received at the second power signal line VGH to the fourth node N4.

[0154] Also, in the compensation stage, the first scanning signal received at the first scanning signal line Gate1 is a valid signal, which controls the second transistor T2 to turn on, and can transmit the voltage of the third node N3 to the first node N1 to compensate the first node N1. The potential of the first node N1 gradually rises to V1+Vth, and the driving sub-circuit 10 (driving transistor T3) is turned off to complete the threshold compensation, and the charging process of the storage sub-circuit 50 is completed.

[0155] In some embodiments, see Figure 7 As shown, the writing sub-circuit 30 includes a fourth transistor T4, a control electrode of the fourth transistor T4 is coupled to the third scanning signal line Gate3, a first electrode of the fourth transistor T4 is coupled to the data writing signal line Date, and a second electrode of the fourth transistor T4 is coupled to the fourth node N4.

[0156] Based on this, in the writing stage, the third scanning signal received at the third scanning signal line Gate3 is a valid signal, and the fourth transistor T4 is controlled to turn on, and the data writing signal received at the data writing signal line Date is transmitted to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the voltage change amount of the fourth node N4 Δ=Vdata-V2. Among them, Vdata is the voltage value of the data writing signal provided by the data writing signal line Data.

[0157] Due to the coupling effect of the storage subcircuit 50, the voltage of the first node N1 follows the change of the voltage of the fourth node N4, and the voltage change of the first node N1 is also approximately Δ=Vdata-V2. Based on this, the voltage of the first node N1 can be changed from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0158] Then, the current I flowing through the driving sub-circuit 10 (driving transistor) is calculated. DBased on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O can be improved, and the uniformity of the luminance of the light-emitting device O is improved.

[0159] In some embodiments, see Figure 7 As shown, the storage sub-circuit 50 includes a storage capacitor Cst, a first plate of the storage capacitor Cst is coupled to the fourth node N4, and a second plate of the storage capacitor Cst is coupled to the first node N1.

[0160] During the compensation stage, since the first plate of the storage capacitor Cst is coupled to the fourth node N4, the voltage of the first plate of the storage capacitor Cst is the voltage V2 of the second power signal received at the second power signal line VGH; and since the second plate of the storage capacitor Cst is coupled to the first node N1, the voltage of the second plate of the storage capacitor Cst is the voltage V1+Vth of the first node N.

[0161] In the writing stage, the third scanning signal received at the third scanning signal line Gate3 is a valid signal, and the fourth transistor T4 is controlled to turn on, and the data writing signal received at the data writing signal line Date is transmitted to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata, and the voltage change amount of the fourth node N4 is Δ=Vdata-V2.

[0162] Due to the coupling effect of the storage capacitor Cst, the voltage of the first node N1 can follow the change of the voltage of the fourth node N4.

[0163] Based on this, the voltage change amount of the first node N1 is also approximately Δ=Vdata-V2. Furthermore, the voltage of the first node N1 can be changed from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0164] Then, the current I flowing through the driving sub-circuit 10 (driving transistor) is calculated. D Based on this, the influence of the threshold voltage Vth on the luminance of the light-emitting device O can be improved, and the uniformity of the luminance of the light-emitting device O is improved.

[0165] Figure 8 is an equivalent circuit diagram of a pixel driving circuit according to some further embodiments.

[0166] In some embodiments, see Figure 8 As shown, the light emitting control subcircuit 20 in the pixel driving circuit Q further includes a second branch 22. The second branch 22 is coupled to the third node N3, the second enabling signal line EM2 and the light emitting device O.

[0167] In the light emitting stage, under the control of the second enable signal from the second enable signal line EM2, the second branch 22 is turned on, and the voltage of the third node N3 can be transmitted to the light emitting device O to drive the light emitting device O to emit light.

[0168] As for the light-emitting control subcircuit 20, in the light-emitting stage, the light-emitting control subcircuit 20 is configured to turn on the first branch 21 under the control of the first enable signal line EM1, and turn on the second branch 22 under the control of the second enable signal line EM2, and can also cooperate with the driving subcircuit 10 to transmit the first power signal received at the first power signal line VDD to the light-emitting device O. That is, in the light-emitting stage, the light-emitting control subcircuit 20 is configured to transmit the first power signal received at the first power signal line VDD to the anode of the light-emitting device O, and the cathode of the light-emitting device O can be electrically connected to the second power signal line Vss, so as to drive the light-emitting device O to emit light.

[0169] In some embodiments, please refer to Figure 8 As shown, the first branch 21 includes a fifth transistor T5, a control electrode of the fifth transistor T5 is coupled to the first enable signal line EM1, a first electrode of the fifth transistor T5 is coupled to the first power signal line VDD, and a second electrode of the fifth transistor T5 is coupled to the second node N2.

[0170] In the compensation stage, the first enable signal provided by the first enable signal line EM1 is a valid signal, which controls the fifth transistor T5 to turn on, and the first power signal provided by the first power signal line VDD is transmitted to the second node N2; then cooperates with the driving sub-circuit 10 to transmit the voltage of the second node N2 (the voltage V1 of the first power signal) to the third node N3; finally, cooperates with the compensation sub-circuit 40, and the voltage of the third node N3 (the voltage V1 of the first power signal) is transmitted to the first node N1 until the voltage of the first node N1 is V1+Vth, and controls the driving sub-circuit 10 (driving transistor T3) to turn off, and completes the threshold compensation.

[0171] In some embodiments, please refer to Figure 8 As shown, the second branch 22 includes a sixth transistor T6, a control electrode of the sixth transistor T6 is coupled to the second enable signal line EM2, a first electrode of the sixth transistor T6 is coupled to the third node N3, and a second electrode of the sixth transistor T6 is coupled to the light emitting device O.

[0172] In the light-emitting stage, the first enable signal provided by the first enable signal line EM1 is a valid signal, which controls the fifth transistor T5 to turn on, and the second enable signal provided by the second enable signal line EM2 is also a valid signal, which controls the sixth transistor T6 to turn on, and then cooperates with the driving sub-circuit 10 to transmit the first power signal provided by the first power signal line VDD to the light-emitting device O to drive the light-emitting device O to emit light.

[0173] In some embodiments, please refer to Figure 8 As shown, the pixel driving circuit Q further includes a first reset subcircuit 60. The first reset subcircuit 60 is coupled to the first node N1, the first reset signal line R1 and the first initialization signal line Vinit1. The first reset subcircuit 60 is configured to, under the control of the first reset signal received from the first reset signal line R1, transmit the first initialization signal received from the first initialization signal line Vinit1 to the first node N1 to initialize the first node N1.

[0174] Before the compensation stage, the first node N1 of the pixel driving circuit Q may be initialized. At this time, the first reset signal provided by the first reset signal line R1 is a valid signal, and the first reset sub-circuit 60 is controlled to be turned on, and the first initialization signal received by the first initialization signal line Vinit1 is transmitted to the first node N1, and the first node N1 is initialized. That is, the control electrode of the driving transistor T3 is initialized by the first initialization signal provided by the first initialization signal line Vinit1, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0175] In some examples, the first initialization signal provided by the first initialization signal line Vinit1 is a low voltage signal. Based on this, before the compensation phase, the low voltage signal is transmitted to the first node N1 to initialize the control electrode of the driving transistor T3, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0176] Exemplarily, the low voltage signal may be a signal having a voltage Vdata lower than that of a data write signal when the display panel 200 displays any gray scale, so as to eliminate a residual signal when displaying a previous frame of an image.

[0177] In some embodiments, please refer to Figure 8 As shown, the first reset subcircuit 60 includes a first transistor T1, a control electrode of the first transistor T1 coupled to the first reset signal line R1, a first electrode of the first transistor T1 coupled to the first initialization signal line Vinit1, and a second electrode of the first transistor T1 coupled to the first node N1.

[0178] Before the compensation stage, the first reset signal provided by the first reset signal line R1 can be controlled to be a valid signal, the first transistor T1 can be controlled to turn on, the first initialization signal received on the first initialization signal line Vinit1 can be transmitted to the first node N1, the first node N1 can be reset, and the control electrode of the driving transistor T3 can be reset, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0179] In addition, when the first node N1 is initialized by using the first initialization signal provided by the first initialization signal line Vinit1, the first initialization signal provided by the first initialization signal line Vinit1 is synchronously transmitted to the storage capacitor Cst in the storage sub-circuit 50. In the subsequent compensation stage, the storage capacitor Cst in the storage sub-circuit 50 can be discharged to keep the driving sub-circuit 10 (driving transistor T3) continuously turned on, ensuring that the first power signal provided by the first power signal terminal VDD can be transmitted to the first node N1.

[0180] In some embodiments, please refer to Figure 8 As shown, the pixel driving circuit Q further includes a second reset subcircuit 70. The second reset subcircuit 70 is coupled to the light-emitting device O, the second reset signal line R2, and the second initialization signal line Vinit2. The second reset subcircuit 70 is configured to, under the control of the second reset signal received from the second reset signal line R2, transmit the second initialization signal received from the second initialization signal line Vinit2 to the light-emitting device O to reset the light-emitting device O.

[0181] Before the light-emitting stage is performed, the light-emitting device O electrically connected to the pixel driving circuit Q may be reset. At this time, the second reset signal provided by the second reset signal line R2 is a valid signal, and the second reset subcircuit 70 is controlled to be turned on, so as to transmit the second initialization signal received on the second initialization signal line Vinit2 to the light-emitting device O, and reset the anode of the light-emitting device O, which is beneficial to improving the stability of the light-emitting device O.

[0182] In some examples, the second initialization signal provided by the second initialization signal line Vinit2 is a low voltage signal. Based on this, before the light-emitting stage, the low voltage signal is transmitted to the anode of the light-emitting device O to control the light-emitting device O not to emit light, improve the influence of the charge remaining in the anode of the light-emitting device O on the light-emitting brightness, and improve the uniformity of the brightness of the light-emitting device O.

[0183] Exemplarily, the low voltage signal may be a signal less than 0V, so as to control the light emitting device O not to emit light, thereby improving the influence of the charge remaining in the anode of the light emitting device O on the light emitting brightness.

[0184] In some embodiments, please refer to Figure 8As shown, the second reset subcircuit 70 includes a seventh transistor T7, a control electrode of the seventh transistor T7 coupled to the second reset signal line R2, a first electrode of the seventh transistor T7 coupled to the second initialization signal line Vinit2, and a seventh electrode of the eighth transistor T8 coupled to the light-emitting device O.

[0185] Before the light-emitting stage, the second reset signal provided by the second reset signal line R2 can be controlled to be a valid signal, and the seventh transistor T7 can be controlled to turn on to transmit the second initialization signal received on the second initialization signal line Vinit2 to the light-emitting device O, thereby resetting the anode of the light-emitting device O, which is beneficial to improving the stability of the light-emitting device O.

[0186] In some embodiments, please refer to Figure 8 As shown, the pixel driving circuit Q further includes a third reset subcircuit 80. The third reset subcircuit 80 is coupled to the second node N2, the third reset signal line R3 and the first reference voltage signal line Vref; the third reset subcircuit 80 is configured to, under the control of the third reset signal received from the third reset signal line R3, transmit the first reference voltage signal received from the first reference voltage signal line Vref to the second node N2, and reset the second node N2.

[0187] Before the compensation phase, the third reset signal provided by the third reset signal line R3 can be controlled to be a valid signal to control the third reset sub-circuit 80 to be turned on, and the first reference voltage signal received by the first reference voltage signal line Vref is transmitted to the second node N2 to reset the second node N2. Based on this, the initial state of the driving transistor T3 before the writing phase can be fixed, so that the driving transistor T3 is in a stable state during the writing phase, and the hysteresis effect of the driving transistor T3 is greatly improved.

[0188] In some examples, the first reference voltage signal provided by the first reference voltage signal line Vref may be a high voltage signal. The gate-source voltage Vgs of the driving transistor T3 in the pixel driving circuit Q is less than Vth, and the driving transistor T3 is in a conduction bias state. That is, before data is written, the driving transistor is in a conduction bias state, ensuring that the driving transistor in each pixel driving circuit is charged and compensated from the conduction bias state without being affected by the data voltage of the previous frame, which can eliminate the influence of the hysteresis of the driving transistor T3 and improve the residual image and response time.

[0189] In some embodiments, please refer to Figure 8 As shown, the third reset subcircuit 80 includes an eighth transistor T8, a control electrode of the eighth transistor T8 is coupled to the third reset signal line R3, a first electrode of the eighth transistor T8 is coupled to the first reference voltage signal line Vref, and a second electrode of the eighth transistor T8 is coupled to the second node N2.

[0190] Before the compensation phase, the third reset signal provided by the third reset signal line R3 can be controlled to be a valid signal to control the eighth transistor T8 to turn on, transmit the first reference voltage signal received by the first reference voltage signal line Vref to the second node N2, and reset the second node N2. Based on this, the initial state of the driving transistor T3 before the writing phase can be fixed, so that the driving transistor T3 is in a stable state during the writing phase, and the hysteresis effect of the driving transistor T3 is greatly improved.

[0191] In some embodiments, please refer to Figure 8 As shown, the third reset signal line R3 is multiplexed as the second reset signal line R2.

[0192] With such configuration, on the one hand, the third reset signal line R3 is multiplexed as the second reset signal line R2 , and there is no need to separately configure the second reset signal line R2 , which can help simplify the structure of the pixel driving circuit Q and reduce the difficulty of layout within the display panel 200 .

[0193] On the other hand, the third reset signal line R3 is multiplexed as the second reset signal line R2, and the third reset signal can be used to control the second reset sub-circuit 70 (seventh transistor T7) to be turned on multiple times (once in the reset stage, and once again after the writing stage and before the light-emitting stage), and the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O, and the anode of the light-emitting device O is reset multiple times, which can help improve the stability of the light-emitting device O.

[0194] In some embodiments, please refer to Figure 8 As shown, when the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9:

[0195] The above nine transistors may all be P-type transistors, that is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 may all be P-type transistors.

[0196] In the case where the above 9 transistors are all P-type transistors, the above “valid signal” can be understood as a low voltage signal, that is, the above 9 transistors can all be turned on under the control of the low level signal.

[0197] In some examples, the above nine transistors can be set to be low temperature polysilicon transistors (Low Temperature Poly-silicon, LTPS). That is, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 can all be low temperature polysilicon transistors. Since low temperature polysilicon transistors have higher carrier mobility, the above transistors can have a faster response speed.

[0198] Fig. 9 is an equivalent circuit diagram of a pixel driving circuit according to some further embodiments.

[0199] In some embodiments, see Fig. 9 As shown, the first transistor T1 in the first reset subcircuit 60 in the pixel driving circuit Q can be an N-type transistor. When the first transistor T1 is an N-type transistor, the above-mentioned "valid signal" can be understood as a high voltage signal. That is, the above-mentioned first transistor T1 can be turned on under the control of the high voltage signal.

[0200] Setting the first transistor T1 as an N-type transistor can help reduce the risk of leakage of the first transistor T1 and help ensure the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within a frame.

[0201] In some examples, the semiconductor material of the N-type transistor may be Indium Gallium Zinc Oxide (IGZO), and the oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the first node N1 through the first transistor T1 during the light emitting stage.

[0202] In some embodiments, see Fig. 9 As shown, the second transistor T2 in the compensation subcircuit 40 in the pixel driving circuit Q can be an N-type transistor. In the case where the second transistor T2 is an N-type transistor, the above-mentioned "effective signal" can be understood as a high voltage signal. That is, the above-mentioned second transistor T2 can be turned on under the control of the high voltage signal.

[0203] Setting the second transistor T2 as an N-type transistor can help reduce the risk of leakage of the second transistor T2 and help ensure the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within a frame.

[0204] In some examples, the semiconductor material of the N-type transistor may be Indium Gallium Zinc Oxide (IGZO), and the oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the first node N1 through the second transistor T2 during the light emitting stage.

[0205] In some embodiments, see Fig. 9 As shown, since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, in the light-emitting stage, the first node N1 and the fourth node N4 are both in a suspended state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0206] Based on this, the fourth transistor T4 in the data writing subcircuit 30 in the pixel driving circuit Q can be an N-type transistor. In the case where the fourth transistor T4 is an N-type transistor, the above-mentioned "valid signal" can be understood as a high voltage signal. That is, the above-mentioned fourth transistor T4 can be turned on under the control of the high voltage signal.

[0207] Setting the fourth transistor T4 as an N-type transistor can help reduce the risk of leakage of the fourth transistor T4 and help ensure the stability of the voltage of the fourth node N4, thereby preventing the fourth node N4 from affecting the voltage of the first node N1, so as to improve the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness retention rate of the light-emitting device O within a frame.

[0208] In some examples, the semiconductor material of the N-type transistor may be Indium Gallium Zinc Oxide (IGZO), and the oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the fourth node N4 through the fourth transistor T4 during the light emitting stage.

[0209] In some embodiments, see Fig. 9 As shown, since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, in the light-emitting stage, the first node N1 and the fourth node N4 are both in a suspended state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0210] Based on this, the ninth transistor T9 in the compensation subcircuit 40 in the pixel driving circuit Q can be an N-type transistor. In the case where the ninth transistor T9 is an N-type transistor, the above-mentioned "effective signal" can be understood as a high voltage signal. That is, the above-mentioned ninth transistor T9 can be turned on under the control of the high voltage signal.

[0211] Setting the ninth transistor T9 as an N-type transistor can help reduce the risk of leakage of the ninth transistor T9 and help ensure the stability of the voltage of the fourth node N4, thereby preventing the fourth node N4 from affecting the voltage of the first node N1, so as to improve the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness retention rate of the light-emitting device O within a frame.

[0212] In some examples, the semiconductor material of the N-type transistor may be indium gallium zinc oxide (IGZO), and the oxide transistor has a smaller off-leakage current, thereby reducing the leakage current of the fourth node N4 through the ninth transistor T9 during the light emitting stage.

[0213] In some embodiments, see Fig. 9 As shown, in the case where the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a fourth transistor T4 and a ninth transistor T9: at least one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is an N-type transistor.

[0214] Such a configuration can improve the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light emitting device O within a frame.

[0215] Among them, “at least one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is an N-type transistor” may include the following situations:

[0216] The first type: any one of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be an N-type transistor.

[0217] The second type: any two of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be N-type transistors.

[0218] The third type: any three of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be N-type transistors.

[0219] The fourth type: the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are all N-type transistors. Fig. 9 It is illustrated by taking the example that the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 are all N-type transistors. However, the present disclosure is not limited thereto.

[0220] No matter which of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is set as an N-type transistor, the stability of the driving transistor T3 and the brightness maintenance rate of the light-emitting device O in one frame can be improved.

[0221] Fig.10 is an equivalent circuit diagram of a pixel driving circuit according to some further embodiments.

[0222] In some embodiments, see Fig.10 As shown, the first transistor T1 in the first reset sub-circuit 60 in the pixel driving circuit Q can be a dual-gate transistor.

[0223] In the case where the first transistor T1 is a dual-gate transistor: the first transistor T1 may be a P-type transistor, or the first transistor T1 may be an N-type transistor.

[0224] When the first transistor T1 is a P-type dual-gate transistor, the above-mentioned “effective signal” can be understood as a low voltage signal. That is, the above-mentioned first transistor T1 can be turned on under the control of the low voltage signal.

[0225] When the first transistor T1 is an N-type dual-gate transistor, the above “effective signal” can be understood as a high voltage signal, that is, the above first transistor T1 can be turned on under the control of the high voltage signal.

[0226] Setting the first transistor T1 as a dual-gate transistor can help improve the stability of the first transistor, thereby helping to reduce the risk of leakage of the first transistor T1. Based on this, it can help to ensure the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness retention rate of the light-emitting device O within a frame.

[0227] In some embodiments, see Fig.10 As shown, the second transistor T2 in the compensation sub-circuit 40 in the pixel driving circuit Q can be a dual-gate transistor.

[0228] In the case where the second transistor T2 is a dual-gate transistor: the second transistor T2 may be a P-type transistor, or the second transistor T2 may be an N-type transistor.

[0229] When the second transistor T2 is a P-type dual-gate transistor, the above-mentioned “valid signal” can be understood as a low voltage signal. That is, the above-mentioned second transistor T2 can be turned on under the control of the low voltage signal.

[0230] When the second transistor T2 is an N-type dual-gate transistor, the above-mentioned “effective signal” can be understood as a high voltage signal. That is, the above-mentioned second transistor T2 can be turned on under the control of the high voltage signal.

[0231] Setting the second transistor T2 as a dual-gate transistor can help improve the stability of the second transistor T2, thereby helping to reduce the risk of leakage of the second transistor T2. Based on this, it can help to ensure the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness retention rate of the light-emitting device O within a frame.

[0232] In some embodiments, see Fig.10 As shown, since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, in the light-emitting stage, the first node N1 and the fourth node N4 are both in a suspended state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0233] Based on this, the fourth transistor T4 in the data writing sub-circuit 30 in the pixel driving circuit Q can be a dual-gate transistor.

[0234] In the case where the fourth transistor T4 is a dual-gate transistor: the fourth transistor T4 may be a P-type transistor, or the fourth transistor T4 may be an N-type transistor.

[0235] When the fourth transistor T4 is a P-type dual-gate transistor, the above-mentioned “valid signal” can be understood as a low voltage signal. That is, the above-mentioned fourth transistor T4 can be turned on under the control of the low voltage signal.

[0236] When the fourth transistor T4 is an N-type dual-gate transistor, the above-mentioned “valid signal” can be understood as a high voltage signal. That is, the above-mentioned fourth transistor T4 can be turned on under the control of the high voltage signal.

[0237] Setting the fourth transistor T4 as a dual-gate transistor can help improve the stability of the fourth transistor T4, thereby helping to reduce the risk of leakage of the fourth transistor T4, so as to ensure the stability of the voltage of the fourth node N4. Therefore, the fourth node N4 can be prevented from affecting the voltage of the first node N1, so as to improve the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within one frame.

[0238] In some embodiments, see Fig.10 As shown, since the two plates of the storage capacitor Cst are coupled to the first node N1 and the fourth node N4 respectively, in the light-emitting stage, the first node N1 and the fourth node N4 are both in a suspended state, and the potential of the first node N1 will fluctuate due to the potential jump of the fourth node N4.

[0239] Based on this, the ninth transistor T9 in the compensation sub-circuit 40 in the pixel driving circuit Q can be set as a dual-gate transistor.

[0240] In the case where the ninth transistor T9 is a dual-gate transistor: the ninth transistor T9 may be a P-type transistor, or the ninth transistor T9 may be an N-type transistor.

[0241] When the ninth transistor T9 is a P-type dual-gate transistor, the above-mentioned “valid signal” can be understood as a low voltage signal. That is, the above-mentioned ninth transistor T9 can be turned on under the control of the low voltage signal.

[0242] When the ninth transistor T9 is an N-type dual-gate transistor, the above-mentioned “valid signal” can be understood as a high voltage signal. That is, the above-mentioned ninth transistor T9 can be turned on under the control of the high voltage signal.

[0243] Setting the ninth transistor T9 as a dual-gate transistor can help improve the stability of the ninth transistor T9, thereby helping to reduce the risk of leakage of the ninth transistor T9, so as to ensure the stability of the voltage of the fourth node N4. Therefore, the fourth node N4 can be prevented from affecting the voltage of the first node N1, so as to improve the stability of the voltage of the first node N1, that is, to ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light-emitting device O within one frame.

[0244] In some embodiments, see Fig.10 As shown, in the case where the pixel driving circuit Q includes a first transistor T1, a second transistor T2, a fourth transistor T4 and a ninth transistor T9: at least one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is a dual-gate transistor.

[0245] Such a configuration can improve the stability of the voltage of the first node N1, that is, ensure the stability of the driving transistor T3, so as to improve the brightness maintenance rate of the light emitting device O within a frame.

[0246] Among them, “at least one of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is a dual-gate transistor” may include the following situations:

[0247] The first type: any one of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be a dual-gate transistor.

[0248] The second type: any two of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be double-gate transistors.

[0249] The third type: any three of the first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 may be dual-gate transistors.

[0250] The fourth type: the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are all dual-gate transistors. Fig.10 The first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 are all dual-gate transistors for illustration. However, the present disclosure is not limited thereto.

[0251] No matter which of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 is set as a dual-gate transistor, the stability of the driving transistor T3 and the brightness maintenance rate of the light-emitting device O in one frame can be improved.

[0252] Fig.11 is a timing diagram of a pixel driving circuit according to some embodiments.

[0253] Some embodiments of the present disclosure further provide a driving method for a pixel driving circuit, which is applied to the pixel driving circuit Q in any of the above embodiments.

[0254] Please combine Figure 8 to Figure 10 As shown, the pixel driving circuit Q includes: a driving subcircuit 10, a light-emitting control subcircuit 20, a writing subcircuit 30, a compensation subcircuit 40 and a storage subcircuit 50. The driving subcircuit 10 is coupled to the first node N1, the second node N2 and the third node N3. The light-emitting control subcircuit 20 includes a first branch 21, and the first branch 21 is coupled to the first power signal line VDD, the first enable signal line EM1 and the second node N2. The compensation subcircuit 40 is coupled to the first scanning signal line Gate1, the second scanning signal line Gate2, the first node N1, the third node N3, the fourth node N4, the first power signal line VDD and the second power signal line VGH; wherein the voltage value of the first power signal is equal to the voltage value of the second power signal. The writing subcircuit 30 is coupled to the third scanning signal line Gate3, the data writing signal line Date and the fourth node N4. The storage subcircuit 50 is coupled to the first node N1 and the fourth node N4.

[0255] First, Figure 8 The pixel driving circuit Q shown in FIG. 1 is described as an example, that is, the 9 transistors in the pixel driving circuit Q are all P-type transistors. The following method is also applicable to the pixel driving circuit Q including P-type dual-gate transistors, that is, the following method is also applicable to Fig.10 The pixel driving circuit shown.

[0256] The driving method includes: a plurality of light-emitting cycles F. One light-emitting cycle F (one frame) includes one refresh frame and at least one hold frame. One light-emitting cycle (one frame) is one display frame, that is, one display picture.

[0257] The refresh frame includes a compensation phase t2 and a writing phase t3.

[0258] In the compensation stage t2, the second scanning signal provided by the second scanning signal line Gate2 is a low level signal, the compensation sub-circuit 40 (ninth transistor T9) is controlled to be turned on, and the second power signal received at the second power signal line VGH is transmitted to the fourth node N4. At this time, the voltage value of the fourth node N4 is the voltage value V2 of the second power signal.

[0259] The first enable signal provided by the first enable signal line EM1 is a low voltage signal, which controls the first branch 21 to be turned on, and can transmit the first power signal received at the first power signal line VDD to the second node N2; and then cooperate with the driving sub-circuit to transmit the voltage of the second node N2 to the third node N3.

[0260] The first scanning signal provided by the first scanning signal line Gate1 is a low voltage signal, which controls the compensation subcircuit 40 (second transistor T2) to be turned on, transmits the voltage of the third node N3 to the first node N1, compensates the first node N1, and the potential of the first node N1 gradually rises to V1+Vth.

[0261] Wherein, V1 is the voltage value of the first power signal provided by the first power signal line VDD, and Vth is the threshold voltage of the driving sub-circuit 10 (driving transistor T3) in the second pixel driving circuit. When the potential of the first node N1 is V1+Vth, the driving sub-circuit 10 (driving transistor T3) is turned off to complete the threshold compensation.

[0262] Since the storage sub-circuit 50 is connected in series between the first node N1 and the fourth node N4, when one end of the storage sub-circuit 50 receives the voltage V2 from the fourth node N4 and the other end of the storage sub-circuit 50 receives the voltage V1+Vth from the first node N1, the charging process of the storage sub-circuit 50 is completed.

[0263] Based on this, the first power signal provided by the first power signal line VDD can be used to perform threshold compensation on the driving transistor T3 included in the driving sub-circuit 10 .

[0264] In the writing stage t3, the third scanning signal provided by the third scanning signal line Gate3 is a low voltage signal, which controls the data writing sub-circuit 30 (the fourth transistor T4) to be turned on, and the data writing signal received at the data writing signal line Date is transmitted to the fourth node N4. At this time, the voltage of the fourth node N4 changes from V2 to Vdata. That is, the voltage change amount of the fourth node N4 Δ=Vdata-V2. Among them, Vdata is the voltage value of the data writing signal provided by the data writing signal line Data.

[0265] The storage subcircuit 50 couples the voltage of the fourth node N4 to the first node N1. That is, the voltage of the first node N1 follows the change of the voltage of the fourth node N4, and the voltage change of the first node N1 is also approximately Δ=Vdata-V2. Based on this, the voltage of the first node N1 can be changed from V1+Vth to V1+Vth+Δ=V1+Vth+Vdata-V2.

[0266] In some examples, the refresh frame may further include a light emitting phase t5 after the writing phase t3.

[0267] In the light-emitting stage t5, the first enable signal of the first enable signal line EM1 is a low voltage signal, which controls the first branch 21 (fifth transistor T5) to be turned on, and the first power signal received at the first power signal line VDD can be transmitted to the second node N2. At this time, the voltage of the second node N2 is V1. In cooperation with the driving sub-circuit 10, the voltage of the second node N2 can be transmitted to the third node N3, and finally to the light-emitting device O.

[0268] The light emitting current of the light emitting device O electrically connected to the pixel driving circuit Q is equal to the current flowing through the driving sub-circuit 10, and its expression is as follows:

[0269]

[0270] Wherein, μ is the electron mobility of the driving subcircuit 10 (driving transistor), Cox is the insulation capacitance per unit area, is the width-to-length ratio of the driving subcircuit 10 (driving transistor), Vth is the threshold voltage of the driving subcircuit 10 (driving transistor), and Vgs is the gate-source voltage of the driving subcircuit 10 (driving transistor), that is, Vgs is the difference between the voltage of the first node N1 and the voltage of the second node N2, and its expression is as follows:

[0271] Vgs=V1+Vth+Vdata-V2-V1=Vth+Vdata-V2; (2);

[0272] Based on this, substituting expression (2) into expression (1), we get the following expression:

[0273]

[0274] It can be seen from this that the current I flowing through the driving sub-circuit 10 (driving transistor T3) D The current I flowing through the driving sub-circuit 10 (driving transistor) is only related to the voltage Vdata of the data writing signal provided by the data writing signal line Data and the voltage V2 of the second power signal provided by the second power signal line VGH. DIt has nothing to do with the threshold voltage Vth. Based on this, it is beneficial to improve the influence of the threshold voltage Vth on the luminance of the light-emitting device O, and improve the uniformity of the luminance of the light-emitting device O.

[0275] In summary, the pixel driving circuit Q driving method provided by the embodiment of the present disclosure is provided with a separate compensation stage t2 and a writing stage t3. That is, the writing of the data voltage Vdata and the compensation threshold voltage are respectively realized through two separate paths, and the threshold compensation stage is separated from the writing stage to prevent the duration of the writing stage from limiting the duration of the threshold compensation stage. Thus, the duration of the threshold compensation stage can be made unaffected by the data writing time (row time), and it can be ensured that the threshold compensation stage has a sufficient duration to fully write the required voltage to compensate for the threshold voltage fluctuation in a larger range, so that the threshold voltage is fully compensated.

[0276] Based on this, the problem of poor display uniformity of a display panel 200 with high resolution or a display panel 200 driven with a high refresh rate due to insufficient threshold compensation phase duration when driving the pixel driving circuit Q can be effectively improved. Also, the problem of poor display uniformity of a display panel 200 in a low grayscale image or black state due to insufficient threshold compensation phase duration when driving the pixel driving circuit can be effectively improved.

[0277] That is, the pixel driving circuit Q provided in the embodiment of the present disclosure can fully compensate the threshold voltage of the driving sub-circuit 10 (driving transistor T3) in the pixel driving circuit Q even at a high refresh rate, or in a low grayscale image or black state, which can help improve the difference in display brightness and enhance the uniformity of display image quality.

[0278] In some embodiments, please continue to combine Figure 8 and Fig.11 As shown, the pixel driving circuit Q further includes a third reset sub-circuit 80. The third reset sub-circuit 80 is coupled to the second node N2, the third reset signal line R3 and the first reference voltage signal line Vref.

[0279] The refresh frame further includes a reset phase t1 , and the reset phase t1 may include a first reset phase t11 .

[0280] In the first reset stage t11, the third reset signal provided by the third reset signal line R3 is a low voltage signal, which controls the third reset sub-circuit (eighth transistor T8) 80 to be turned on, and transmits the first reference voltage signal received on the first reference voltage signal line Vref to the second node N2, thereby resetting the second node N2.

[0281] Based on this, it is equivalent to resetting the second node N2 of the pixel driving circuit Q before the compensation stage t2. Therefore, the initial state of the driving transistor T3 before the writing stage can be fixed, so that the driving transistor T3 is in a stable state during the writing stage, and the hysteresis effect of the driving transistor T3 is greatly improved.

[0282] In some examples, the first reference voltage signal provided by the first reference voltage signal line Vref may be a high voltage signal. The gate-source voltage Vgs of the driving transistor T3 in the pixel driving circuit Q is less than Vth, and the driving transistor T3 is in a conduction bias state. That is, before data is written, the driving transistor is in a conduction bias state, ensuring that the driving transistor in each pixel driving circuit is charged and compensated from the conduction bias state without being affected by the data voltage of the previous frame, which can eliminate the influence of the hysteresis of the driving transistor T3 and improve the residual image and response time.

[0283] In some embodiments, please continue to combine Figure 8 and Fig.11 As shown, the pixel driving circuit Q further includes a second reset subcircuit 70. The second reset subcircuit 70 is coupled to the light emitting device O, the second reset signal line R2 and the second initialization signal line Vinit2.

[0284] In the first reset stage t11, the second reset signal provided by the second reset signal line R2 can be a low voltage signal, which controls the second reset sub-circuit (seventh transistor T7) 70 to be turned on, and transmits the second initialization signal received on the second initialization signal line Vinit2 to the light-emitting device O to reset the light-emitting device O.

[0285] This is equivalent to resetting the light-emitting device O electrically connected to the pixel driving circuit Q before the light-emitting stage t5 is performed, which is beneficial to improving the stability of the light-emitting device O.

[0286] In some examples, the second initialization signal provided by the second initialization signal line Vinit2 is a low voltage signal. Based on this, before the light-emitting stage, the low voltage signal is transmitted to the anode of the light-emitting device O to control the light-emitting device O not to emit light, improve the influence of the charge remaining in the anode of the light-emitting device O on the light-emitting brightness, and improve the uniformity of the brightness of the light-emitting device O.

[0287] Exemplarily, the low voltage signal may be a signal less than 0V, so as to control the light emitting device O not to emit light, thereby improving the influence of the charge remaining in the anode of the light emitting device O on the light emitting brightness.

[0288] In some embodiments, please continue to combine Figure 8 and Fig.11 As shown, the third reset signal line R3 is multiplexed as the second reset signal line R2.

[0289] As the above structure is set, in the first reset stage t11, the second reset sub-circuit 70 and the third reset sub-circuit 80 are turned on simultaneously in response to the low voltage signal provided by the third reset signal line R3, and the first reference voltage signal received on the first reference voltage signal line Vref is transmitted to the second node N2, and the second node N2 is reset, which can be beneficial to improve the influence of the hysteresis of the driving transistor T3. In addition, the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O, and the light-emitting device O is reset, which is beneficial to improve the stability of the light-emitting device O.

[0290] In some embodiments, please continue to combine Figure 8 and Fig.11 As shown, the pixel driving circuit Q further includes a first reset sub-circuit 60. The first reset sub-circuit 60 is coupled to the first node N1, the first reset signal line R1 and the first initialization signal line Vinit1.

[0291] The refresh frame further includes a reset phase t1 , and the reset phase t1 may further include a first initialization phase t12 .

[0292] In the first initialization stage t12, the first reset signal provided by the first reset signal line R1 is a low voltage signal, which controls the first reset sub-circuit (first transistor T1) 60 to be turned on, and transmits the first initialization signal received on the first initialization signal line Vinit1 to the first node N1 to initialize the first node N1.

[0293] Based on this, it is equivalent to initializing the first node N1 in the pixel driving circuit Q before the compensation stage t2, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0294] In some examples, the first initialization signal provided by the first initialization signal line Vinit1 is a low voltage signal. Based on this, before the compensation phase, the low voltage signal is transmitted to the first node N1 to initialize the control electrode of the driving transistor T3, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0295] Exemplarily, the low voltage signal may be a signal having a voltage Vdata lower than that of a data write signal when the display panel 200 displays any gray scale, so as to eliminate a residual signal when displaying a previous frame of an image.

[0296] In some embodiments, please continue to combine Figure 8 and Fig.11 As shown, the reset phase t1 further includes a second initialization phase t13.

[0297] In the second initialization stage t13, the first reset signal provided by the first reset signal line R1 remains as a low voltage signal, controls the first reset sub-circuit (first transistor T1) 60 to be turned on, and transmits the first initialization signal received at the first initialization signal line Vinit1 to the first node N1. At this time, the voltage of the first node N1 is the first initialization signal. In addition, the first scanning signal provided by the first scanning signal line Gate1 is a low voltage signal, controls the second transistor T2 in the compensation sub-circuit 40 to be turned on, and transmits the voltage of the first node N1 to the third node N3.

[0298] In addition, the driving sub-circuit (driving transistor T3 ) 10 is turned on under the control of the voltage of the first node N1 , so that the voltage of the third node N3 can be transmitted to the second node N2 .

[0299] Based on this, the first reset signal line R1, the first scan signal line Gate1 and the first initialization signal line Vinit1 can be used to synchronously initialize the first node N1, the second node N2 and the third node N3, so as to improve the stability of the driving transistor T3 included in the driving sub-circuit 10.

[0300] In some embodiments, please continue to combine Figure 8 and Fig.11 As shown, the refresh frame further includes a second reset phase t4. The second reset phase t4 is after the writing phase t3 and before the light emitting phase t5.

[0301] In the second reset stage t4, the low voltage signal provided by the second reset signal line R2 is used to control the second reset sub-circuit (seventh transistor T7) 70 to be turned on, and the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O, so that the light-emitting device O is reset again, which is beneficial to improve the stability of the light-emitting device O.

[0302] Furthermore, since the three reset signal lines R3 are multiplexed as the second reset signal line R2, in the second reset stage t4, the low voltage signal provided by the third reset signal line R3 can be used to control the third reset sub-circuit (eighth transistor T8) 80 to be turned on, and the first reference voltage signal received on the first reference voltage signal line Vref is transmitted to the second node N2, and the second node N2 is reset, which is beneficial to improve the stability of the driving transistor T3.

[0303] In addition, after the refresh frame in each frame of the light-emitting period F is completed, the frame holding stage is entered. At this time, the third reset signal line R3 can be used to provide a low voltage signal to control the second reset subcircuit 70 and the third reset subcircuit 80 to be turned on, and the first reference voltage signal received on the first reference voltage signal line Vref is transmitted to the second node N2, and the second node N2 is reset, which can be beneficial to improve the stability of the driving transistor T3. In addition, the second initialization signal received on the second initialization signal line Vinit2 is transmitted to the light-emitting device O, and the light-emitting device O is reset to ensure that the anode voltage of each light-emitting device O is consistent at the start time of the next frame refresh, thereby improving the uniformity of the brightness of the light-emitting device O.

[0304] In addition, in the holding frame, the first enable signal line EM1 and the second enable signal line EM2 can also be used to provide a low voltage signal to turn on the light emitting control subcircuit 20 and cooperate with the driving subcircuit 10 to drive the light emitting device O to emit light.

[0305] Fig.12 is a timing diagram of a pixel driving circuit according to some other embodiments.

[0306] by Fig. 9 The pixel driving circuit Q shown is described as an example, that is, the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 in the pixel driving circuit Q are all N-type transistors. The following method is also applicable to the pixel driving circuit Q including N-type dual-gate transistors.

[0307] and Fig.11 The differences between the drive methods shown are: Fig.11 The first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 in the corresponding pixel driving circuit Q are all P-type transistors.

[0308] and Fig.12 The first transistor T1 , the second transistor T2 , the fourth transistor T4 and the ninth transistor T9 in the corresponding pixel driving circuit Q are all N-type transistors.

[0309] Based on this, Fig.12 The effective signals of the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 in the pixel driving circuit Q driven by the timing diagram shown are high voltage signals. That is, the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 are all turned on under high voltage control. Fig.11 The driving method shown is consistent with that shown in FIG. 1 , and the only difference is that the “effective signal” for controlling the first transistor T1, the second transistor T2, the fourth transistor T4 and the ninth transistor T9 to turn on is different. For how to drive the pixel driving circuit in other stages, it can be combined with Fig.11 The above-mentioned driving method will not be described in detail here.

[0310] Fig.13 is a structural diagram of an array substrate according to some other embodiments. Fig.13 In order to clearly illustrate how to set each signal line to respond to the same signal terminal, Fig.13 Only the second scanning signal line Gate2 coupled to the first row of pixel driving circuits, the first scanning signal line Gate1 coupled to the fourth row of pixel driving circuits, and the first reset signal line R1 coupled to the seventh row of pixel driving circuits Q are illustrated.

[0311] See also Fig.13 As shown, some embodiments of the present disclosure provide an array substrate 100. The array substrate 100 includes a display area AA and a peripheral area SA. The peripheral area SA may be located on at least one side (e.g., one side; or all around, i.e., including upper and lower sides and left and right sides) of the display area AA.

[0312] The array substrate 100 includes a substrate 01 and a pixel circuit layer 02 located on one side of the substrate 01. The pixel circuit layer 02 includes a plurality of pixel driving circuits Q, and the plurality of pixel driving circuits Q are arranged in multiple rows and columns.

[0313] For the convenience of explanation, the above-mentioned multiple pixel driving circuits Q are described in the present disclosure by taking a matrix arrangement as an example.

[0314] At this time, the pixel driving circuits Q arranged in a row along the first direction X are called a row of pixel driving circuits Q, and the pixel driving circuits Q arranged in a row along the second direction Y are called a column of pixel driving circuits Q.

[0315] The array substrate 100 further includes a plurality of different types of signal lines to drive the pixel driving circuit Q. The plurality of different types of signal lines include a plurality of first scanning signal lines Gate1 , a plurality of second scanning signal lines Gate2 , and a plurality of first reset signal lines R1 .

[0316] The plurality of first scanning signal lines Gate1 are located on one side of the substrate and extend along a first direction X and are arranged along a second direction Y, and the second direction Y intersects the first direction X. One first scanning signal line Gate1 is coupled to a row of pixel driving circuits Q.

[0317] The plurality of second scanning signal lines Gate2 are located at one side of the substrate, and the plurality of second scanning signal lines Gate2 extend along the first direction X and are arranged along the second direction Y. One second scanning signal line Gate2 is coupled to a row of pixel driving circuits Q.

[0318] The plurality of first reset signal lines R1 are located on one side of the substrate, and the plurality of first reset signal lines R1 extend along the first direction X and are arranged along the second direction Y. One first reset signal line R1 is coupled to a row of pixel driving circuits Q.

[0319] Multiple first scan signal lines Gate1, multiple second scan signal lines Gate2, and multiple first reset signal lines R1 can be controlled by different signal terminals. However, it is found through research that since the signal terminals are located in the peripheral area SA, when multiple first scan signal lines Gate1, multiple second scan signal lines Gate2, and multiple first reset signal lines R1 can be controlled by different signal terminals, it will result in too many signal terminals being required to be arranged in the array substrate 100, which will result in too much space being occupied in the array substrate 100, that is, it will result in an increase in the area of ​​the peripheral area SA, thereby affecting the subsequent display panel 200 to achieve a narrow frame.

[0320] In some examples, the first direction X and the second direction Y may be approximately perpendicular, and the angle between the first direction X and the second direction Y is approximately equal to 90°. For example, the angle between the first direction X and the second direction Y may be 85°, 90°, or 95°.

[0321] Based on the above problems, some embodiments of the present disclosure provide an array substrate 100, see Fig.13 As shown, a second scanning signal line Gate2 coupled to the pixel driving circuit of the nth row and a first scanning signal line Gate1 coupled to the pixel driving circuit of the (n+3)th row may be set to respond to the control of the same control signal.

[0322] That is, the second scanning signal line Gate2 coupled to the nth row of pixel driving circuits and the first scanning signal line Gate1 coupled to the n+3th row of pixel driving circuits can be coupled to the same signal terminal, where n is a positive integer.

[0323] Because, the first scanning signal provided by the first scanning signal line Gate1 can be used to control the second transistor T2 in the compensation sub-circuit 40 to turn on, and cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10 to initialize the first node N1, the second node N2 and the third node N2 at the same time; then the second scanning signal provided by the second scanning signal line Gate2 can be used to control the ninth transistor T9 in the compensation sub-circuit 40 to turn on, and cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light-emitting control sub-circuit 20 and the storage sub-circuit 50 to perform threshold compensation.

[0324] Based on this, the second scanning signal line Gate2 coupled to the pixel driving circuit of the nth row can be set to be coupled to the first scanning signal line Gate1 coupled to the pixel driving circuit of the n+3th row at the same signal terminal. That is, when the gate signal is sent to the second scanning signal line Gate2 coupled to the pixel driving circuit of the nth row to control the ninth transistor T9 in the compensation subcircuit 40 in the pixel driving circuit of the nth row to turn on, the gate signal can be sent to the first scanning signal line Gata1 coupled to the pixel driving circuit of the n+3th row to control the second transistor T2 in the compensation subcircuit 40 in the pixel driving circuit of the n+3th row to turn on, so that the first node N1, the second node N2 and the third node N2 are initialized before the pixel driving circuit of the n+3th row performs threshold compensation.

[0325] Such a configuration can not only ensure the conduction of the sub-circuit electrically connected to the first scanning signal line Gate1 and the second scanning signal line Gate2 in the pixel driving circuit Q, but also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0326] In some embodiments, see Fig.13 As shown, a second scanning signal line Gate2 coupled to the n-th row of pixel driving circuits and a first reset signal line R1 coupled to the n+6-th row of pixel driving circuits may be set to respond to the control of the same control signal.

[0327] That is, the second scanning signal line Gate2 coupled to the nth row of pixel driving circuits and the first reset signal line R1 coupled to the n+6th row of pixel driving circuits may be coupled to the same signal terminal, where n is a positive integer.

[0328] When driving the pixel driving circuit Q, it is necessary to first use the first reset signal provided by the first reset signal line R1 to control the first transistor T1 in the first reset sub-circuit to turn on and initialize the first node N1; then use the second scan signal provided by the second scan signal line Gate2 to control the ninth transistor T9 in the compensation sub-circuit 40 to turn on, and cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light emitting control sub-circuit 20 and the storage sub-circuit 50 to perform threshold compensation.

[0329] Based on this, the second scanning signal line Gate2 coupled to the pixel driving circuit of the nth row and the first reset signal line R1 coupled to the pixel driving circuit of the (n+6th) row may be coupled to the same signal terminal.

[0330] That is, when the signal end is used to send a gate signal to the second scanning signal line Gate2 coupled to the n-th row pixel driving circuit to control the ninth transistor T9 in the compensation sub-circuit 40 in the n-th row pixel driving circuit to turn on, the signal end can be used to synchronously send a gate signal to the first reset signal line R1 coupled to the n+6-th row pixel driving circuit to control the first transistor T1 in the first reset sub-circuit in the n+6-th row pixel driving circuit to turn on, so that the n+6-th row pixel driving circuit can initialize the first node N1 before performing threshold compensation.

[0331] Such a configuration can not only ensure the conduction of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first reset signal line R1 and the second scanning signal line Gate2, but also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0332] In some embodiments, see Fig.13 As shown, the first scanning signal line Gate1 coupled to the pixel driving circuit of the nth row and the first reset signal line R1 coupled to the pixel driving circuit of the n+3th row can be set to respond to the control of the same control signal. Wherein, n is a positive integer. That is, the first scanning signal line Gate1 coupled to the pixel driving circuit of the nth row and the first reset signal line R1 coupled to the pixel driving circuit of the n+3th row can be set to be coupled to the same signal terminal.

[0333] When driving the pixel driving circuit Q, it is necessary to first use the first reset signal provided by the first reset signal line R1 to control the first reset sub-circuit to be turned on, and initialize the first node N1; then use the first scanning signal provided by the first scanning signal line Gate1 to control the second transistor T2 in the compensation sub-circuit 40 to be turned on, and cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10 to initialize the first node N1, the second node N2 and the third node N3 at the same time.

[0334] Based on this, the first scanning signal line Gate1 coupled to the pixel driving circuit of the nth row and the first reset signal line R1 coupled to the pixel driving circuit of the (n+3)th row may be coupled to the same signal terminal.

[0335] That is, when the signal end is used to send a gate signal to a scanning signal line Gate1 coupled to the n-th row pixel driving circuit to control the second transistor T2 in the compensation sub-circuit 40 in the n-th row pixel driving circuit to turn on, the signal end can be used to synchronously send a gate signal to the first reset signal line R1 coupled to the n+3-th row pixel driving circuit to control the first transistor T1 in the first reset sub-circuit in the n+3-th row pixel driving circuit to turn on, so that the n+3-th row pixel driving circuit can initialize the first node N1, the second node N2 and the third node N2 before performing threshold compensation.

[0336] Such a configuration can not only ensure the conduction of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first reset signal line R1 and the first scanning signal line Gate1, but also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0337] In some embodiments, see Fig.13 As shown, a second scanning signal line Gate2 coupled to the nth row of pixel driving circuits, a first scanning signal line Gate1 coupled to the n+3th row of pixel driving circuits, and a first reset signal line R1 coupled to the n+6th row of pixel driving circuits may be arranged to respond to the control of the same control signal, wherein n is a positive integer.

[0338] When driving the pixel driving circuit Q, it is necessary to first use the first reset signal provided by the first reset signal line R1 to control the first reset sub-circuit to be turned on, and initialize the first node N1; then use the first scanning signal provided by the first scanning signal line Gate1 to control the second transistor T2 in the compensation sub-circuit 40 to be turned on, and cooperate with the first reset sub-circuit 60 and the driving sub-circuit 10 to initialize the first node N1, the second node N2 and the third node N2 at the same time; finally, use the second scanning signal provided by the second scanning signal line Gate2 to control the ninth transistor T9 in the compensation sub-circuit 40 to be turned on, and cooperate with the second transistor T2 in the compensation sub-circuit 40, the driving sub-circuit 10, the first branch 21 in the light emitting control sub-circuit 20 and the storage sub-circuit 50 to perform threshold compensation.

[0339] Based on this, a second scanning signal line Gate2 coupled to the nth row of pixel driving circuits, a first scanning signal line Gate1 coupled to the n+3th row of pixel driving circuits, and a first reset signal line R1 coupled to the n+6th row of pixel driving circuits can be set to respond to the same control signal.

[0340] That is, when the signal end is used to send a gate signal to the second scanning signal line Gate2 coupled to the n-th row pixel driving circuit to control the ninth transistor T9 in the compensation sub-circuit 40 in the n-th row pixel driving circuit to turn on; the signal end can be used to send a gate signal to a scanning signal line Gate1 coupled to the n+3-th row pixel driving circuit to control the second transistor T2 in the compensation sub-circuit 40 in the n+3-th row pixel driving circuit to turn on, so that the n+3-th row pixel driving circuit can initialize the first node N1 before performing threshold compensation; and the signal end can be used to synchronously send a gate signal to the first reset signal line R1 coupled to the n+6-th row pixel driving circuit to control the first transistor T1 in the first reset sub-circuit in the n+6-th row pixel driving circuit to turn on, so that the n+6-th row pixel driving circuit can initialize each node before performing threshold compensation.

[0341] Such a configuration can not only ensure the conduction of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1; it can also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0342] For some examples, see Fig.13 As shown, the plurality of first scanning signal lines Gate1, the plurality of second scanning signal lines Gate2, and the plurality of first reset signal lines R1 can be coupled to the same signal terminal, wherein the signal terminal can be a gate driver circuit 101 (Gate Driver on Array, GOA).

[0343] The gate drive circuit 101 is used to provide gate signals for the first scan signal line Gate1, the second scan signal line Gate2 and the first reset signal line R1. The first scan signal line Gate1, the second scan signal line Gate2 and the first reset signal line R1 transmit the gate signals to the corresponding coupled sub-circuit to control the opening and closing of the transistor included in the sub-circuit.

[0344] In some examples, the gate driving circuit 101 may include a plurality of shift register units arranged in cascade. One shift register unit may be coupled to the second scanning signal line Gate2 coupled to the pixel driving circuit of the nth row, coupled to the first scanning signal line Gate1 coupled to the pixel driving circuit of the n+3th row, and coupled to the first reset signal line R1 coupled to the pixel driving circuit of the n+6th row, so as to drive the second scanning signal line Gate2 coupled to the pixel driving circuit of the nth row, the first scanning signal line Gate1 coupled to the pixel driving circuit of the n+3th row, and the first reset signal line R1 coupled to the pixel driving circuit of the n+6th row using the same shift register unit.

[0345] For example, a shift register 102 can be coupled to the second scan signal line Gate2 coupled to the 1st row of pixel driving circuits, to the first scan signal line Gate1 coupled to the 4th row of pixel driving circuits, and to the first reset signal line R1 coupled to the 7th row of pixel driving circuits.

[0346] Based on this, when the pixel driving circuit Q in the 1st row receives the second scanning signal provided by the second scanning signal line Gate2, the pixel driving circuit Q in the 4th row can simultaneously receive the first scanning signal provided by the first scanning signal line Gate1, and the pixel driving circuit Q in the 7th row receives the first reset signal provided by the first reset signal R1.

[0347] So that the pixel driving circuit Q in the 7th row and the pixel driving circuit Q in the 4th row can initialize each node before performing threshold compensation.

[0348] Such a configuration can not only ensure the conduction of the sub-circuit in the pixel driving circuit Q that is electrically connected to the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1; it can also effectively reduce the number of signal terminals in the array substrate 100, which can be beneficial to reducing the area of ​​the peripheral area SA, so as to facilitate the subsequent realization of a narrow frame of the display panel 200.

[0349] Fig.14 is a timing diagram of a pixel driving circuit according to some further embodiments, Fig.15 is a timing diagram of a pixel driving circuit according to some further embodiments.

[0350] It should be noted that when the second scanning signal line Gate2 coupled to the nth row pixel driving circuit, the first scanning signal line Gate1 coupled to the n+3th row pixel driving circuit, and the first reset signal line R1 coupled to the n+6th row pixel driving circuit are set to respond to the same control signal, when driving the corresponding pixel driving circuit, the corresponding timing diagram is combined with Fig.14 and Fig.15As shown, the pulse widths of the signals transmitted by the first scanning signal line Gate1, the second scanning signal line Gate2, and the first reset signal line R1 are equal.

[0351] in, Fig.14 The timing diagram shown is similar to Fig.11 The timing diagram shown is similar to Fig.15 The timing diagram shown is similar to Fig.12 The timing diagram is similar to that shown. That is, Fig.14 The timing diagram shown can be used to drive Figure 8 and Fig.11 The pixel driving circuit shown, Fig.15 Can be used to drive Fig. 9 The pixel driving circuit shown in FIG. Specific driving methods may refer to the above embodiments and will not be described in detail here.

[0352] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A pixel driving circuit, characterized in that: include: A driving subcircuit, a light emitting control subcircuit, a writing subcircuit, a compensation subcircuit and a storage subcircuit; The driving subcircuit is coupled to the first node, the second node and the third node, and the driving subcircuit is configured to transmit the voltage from the second node to the third node under the control of the voltage of the first node; The light-emitting control subcircuit includes a first branch, the first branch is coupled to a first power signal line, a first enable signal line, and a second node; the first branch is configured to cooperate with the driving subcircuit under the control of a first enable signal from the first enable signal line in a compensation phase to transmit a first power signal received at the first power signal line to the third node; The compensation subcircuit is coupled to the first scan signal line, the second scan signal line, the first node, the third node, the fourth node and the second power signal line; the compensation subcircuit is configured to, in a compensation phase, under the control of a first scan signal received at the first scan signal line, transmit the voltage of the third node to the first node, and under the control of a second scan signal received at the second scan signal line, transmit the second power signal received at the second power signal line to the fourth node; The write subcircuit is coupled to the third scan signal line, the data write signal line and the fourth node; the write subcircuit is configured to, in a write phase, under the control of a third scan signal received at the third scan signal line, transmit the data write signal received at the data write signal line to the fourth node; The storage sub-circuit is coupled to the first node and the fourth node; in the writing phase, the storage sub-circuit is configured to couple the voltage of the fourth node to the first node.

2. The pixel driving circuit according to claim 1, characterized in that: The driving sub-circuit includes a driving transistor, a control electrode of the driving transistor is coupled to the first node, a first electrode of the driving transistor is coupled to the second node, and a second electrode of the driving transistor is coupled to the third node.

3. The pixel driving circuit according to claim 1, characterized in that: The compensation sub-circuit includes a second transistor and a ninth transistor; The control electrode of the second transistor is coupled to the first scan signal line, the first electrode of the second transistor is coupled to the third node, and the second electrode of the second transistor is coupled to the first node; The control electrode of the ninth transistor is coupled to the third scan signal line, the first electrode of the ninth transistor is coupled to the second power signal line, and the second electrode of the ninth transistor is coupled to the fourth node.

4. The pixel driving circuit according to claim 1, characterized in that: The write subcircuit includes a fourth transistor, a control electrode of the fourth transistor is coupled to the third scan signal line, a first electrode of the fourth transistor is coupled to the data write signal line, and a second electrode of the fourth transistor is coupled to the fourth node.

5. The pixel driving circuit according to claim 1, characterized in that: The storage subcircuit includes a storage capacitor, a first plate of the storage capacitor is coupled to the fourth node, and a second plate of the storage capacitor is coupled to the first node.

6. The pixel driving circuit according to claim 1, characterized in that: The light-emitting control subcircuit also includes a second branch, which is coupled to the third node, the second enable signal line and the light-emitting device; in the light-emitting stage, the light-emitting control subcircuit is configured to cooperate with the driving subcircuit under the control of the first enable signal from the first enable signal line and the second enable signal from the second enable signal line to transmit the first power signal received at the first power signal line to the light-emitting device.

7. The pixel driving circuit according to claim 6, characterized in that: The first branch includes a fifth transistor, a control electrode of the fifth transistor is coupled to the first enable signal line, a first electrode of the fifth transistor is coupled to the first power signal line, and a second electrode of the fifth transistor is coupled to the second node; The second branch includes a sixth transistor, a control electrode of the sixth transistor is coupled to the second enable signal line, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the light emitting device.

8. The pixel driving circuit according to claim 1, characterized in that: Also includes a first reset subcircuit; The first reset sub-circuit is coupled to the first node, the first reset signal line and the first initialization signal line; the first reset sub-circuit is configured to, under the control of the first reset signal received from the first reset signal line, transmit the first initialization signal received on the first initialization signal line to the first node to reset the first node.

9. The pixel driving circuit according to claim 8, characterized in that: The first reset subcircuit includes a first transistor, a control electrode of the first transistor is coupled to the first reset signal line, a first electrode of the first transistor is coupled to the first initialization signal line, and a second electrode of the first transistor is coupled to the first node.

10. The pixel driving circuit according to claim 1, characterized in that: Also comprising a second reset subcircuit; The second reset sub-circuit is coupled to the light-emitting device, the second reset signal line and the second initialization signal line; the second reset sub-circuit is configured to, under the control of the second reset signal received from the second reset signal line, transmit the second initialization signal received on the second initialization signal line to the light-emitting device to reset the light-emitting device.

11. The pixel driving circuit according to claim 10, characterized in that: The second reset subcircuit includes a seventh transistor, a control electrode of the seventh transistor is coupled to the second reset signal line, a first electrode of the seventh transistor is coupled to the second initialization signal line, and a seventh electrode of the eighth transistor is coupled to the light emitting device.

12. The pixel driving circuit according to claim 1, characterized in that: Also includes a third reset subcircuit; The third reset sub-circuit is coupled to the second node, the third reset signal line and the first reference voltage signal line; the third reset sub-circuit is configured to, under the control of a third reset signal received from the third reset signal line, transmit the first reference voltage signal received on the first reference voltage signal line to the second node, thereby resetting the second node.

13. The pixel driving circuit according to claim 12, characterized in that: The third reset subcircuit includes an eighth transistor, a control electrode of the eighth transistor is coupled to the third reset signal line, a first electrode of the eighth transistor is coupled to the first reference voltage signal line, and a second electrode of the eighth transistor is coupled to the second node.

14. The pixel driving circuit according to claim 1, characterized in that: The voltage value of the first power signal is equal to the voltage value of the second power signal.

15. The pixel driving circuit according to claim 1, characterized in that: The first power signal line is multiplexed as the second power signal line.

16. The pixel driving circuit according to claim 1, characterized in that: In the case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor: At least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is a dual-gate transistor.

17. The pixel driving circuit according to claim 1, characterized in that: In the case where the pixel driving circuit includes a first transistor, a second transistor, a fourth transistor and a ninth transistor: At least one of the first transistor, the second transistor, the fourth transistor and the ninth transistor is an N-type transistor.

18. A driving method for a pixel driving circuit, characterized in that: The pixel driving circuit comprises: a driving subcircuit, a light emitting control subcircuit, a writing subcircuit, a compensation subcircuit and a storage subcircuit; The driving subcircuit is coupled to the first node, the second node and the third node; The light emitting control subcircuit comprises a first branch, the first branch is coupled to a first power signal line, a first enable signal line and a second node; The compensation sub-circuit is coupled to the first scan signal line, the second scan signal line, the first node, the third node, the fourth node, the first power signal line and the second power signal line; The writing sub-circuit is coupled to the third scanning signal line, the data writing signal line and the fourth node; The storage sub-circuit is coupled to the first node and the fourth node; The driving method comprises: a compensation phase and a writing phase; In the compensation stage, the first branch, under the control of the first enable signal from the first enable signal line, cooperates with the driving sub-circuit to transmit the first power signal received at the first power signal line to the third node; the compensation sub-circuit, under the control of the first scan signal received at the first scan signal line, transmits the voltage of the third node to the first node; under the control of the second scan signal received at the second scan signal line, transmits the second power signal received at the second power signal line to the fourth node; and the storage sub-circuit receives the voltage of the first node and the voltage of the fourth node; In the write phase, the write subcircuit, under the control of the third scan signal received at the third scan signal line, transmits the data write signal received at the data write signal line to the fourth node; and the storage subcircuit couples the voltage of the fourth node to the first node.

19. The driving method according to claim 18, characterized in that: The pixel driving circuit further includes a third reset subcircuit, wherein the third reset subcircuit is coupled to the second node, the third reset signal line and the first reference voltage signal line; The driving method also includes a first reset stage. In the first reset stage, the third reset sub-circuit, under the control of a third reset signal received from the third reset signal line, transmits the first reference voltage signal received on the first reference voltage signal line to the second node to reset the second node.

20. The driving method according to claim 19, characterized in that: The pixel driving circuit further includes a first reset subcircuit, wherein the first reset subcircuit is coupled to the first node, the first reset signal line and the first initialization signal line; The driving method also includes a first initialization stage. In the first initialization stage, the first reset sub-circuit, under the control of a first reset signal received from the first reset signal line, transmits a first initialization signal received from the first initialization signal line to the first node to initialize the first node.

21. The driving method according to claim 20, characterized in that: The driving method further comprises a second initialization phase; In the second initialization stage, the first reset subcircuit transmits the first initialization signal received from the first initialization signal line to the first node under the control of the first reset signal received from the first reset signal line; The compensation sub-circuit transmits the voltage of the first node to the third node under the control of the first scan signal received from the first scan signal line; The driving sub-circuit transmits the voltage from the second node to the third node under the control of the voltage of the first node, so as to initialize the first node, the second node and the third node.

22. An array substrate, characterized in that: include: A substrate, and a plurality of pixel driving circuits as claimed in any one of claims 1 to 21 located on the substrate.

23. The array substrate according to claim 22, characterized in that: The plurality of pixel driving circuits are arranged in multiple rows and columns; the array substrate further comprises: A plurality of first scanning signal lines are located on one side of the substrate, extending along a first direction and arranged along a second direction, wherein the second direction intersects the first direction; a plurality of second scanning signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; a plurality of first reset signal lines, located on one side of the substrate, extending along the first direction and arranged along the second direction; Among them, the second scanning signal line coupled to the nth row pixel driving circuit, the first scanning signal line coupled to the n+3th row pixel driving circuit, and the first reset signal line coupled to the n+6th row pixel driving circuit respond to the control of the same control signal, and n is a positive integer.

24. A display panel, characterized in that: include: a light emitting device layer, comprising a plurality of light emitting devices; as well as, An array substrate as described in claim 22 or 23 above; wherein the pixel driving circuit is coupled to the light emitting device.

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