Grid control field sequence circuit and method

Abstract

The invention discloses a grid control field sequence circuit and method, and the circuit comprises M rows of sub-circuits, each sub-circuit comprises a compensation unit, and each compensation unit comprises a first transistor, a second transistor, a fourth transistor, and a fifth transistor. The second source-drain electrode of the first transistor is further coupled to the grid electrode of a fourth transistor, the first source-drain electrode of the fourth transistor is coupled to the second source-drain electrodes of the third transistor and the fifth transistor, and the second source-drain electrode of the fourth transistor is coupled to the second source-drain electrode of the second transistor; the grid electrode of the fifth transistor is coupled to the row grid signal line of the Nth row, the first source and drain electrode of the fifth transistor is coupled to the data signal line, and the second source and drain electrode of the fifth transistor is coupled to the first source and drain electrode of the fourth transistor. The beneficial effects of the invention are that the threshold voltage is eliminated by using the conduction characteristic of the transistor, thereby avoiding the image abnormity phenomenon caused by the drift of the threshold voltage.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a field sequence circuit and method for gate control. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] Due to the influence of transistor process technology, the threshold voltage of driving transistors at different spatial locations is likely to be different. For hydrogenated amorphous silicon, low-temperature polysilicon, and oxide transistors, the threshold voltage will also change with the working state, that is, the threshold voltage drifts. Since the potential finally written to the pixel electrode under gate control is related to the threshold voltage, changes or inconsistencies in the threshold voltage of the driving transistor will cause uneven display of the liquid crystal display.

[0004] Therefore, the present invention proposes a field sequential circuit and method for gate control to eliminate the influence of threshold voltage, thereby avoiding the influence of abnormal picture display. Summary of the invention

[0005] The purpose of the present invention is to provide a field sequence circuit and method for gate control, which can eliminate the influence of threshold voltage.

[0006] The object of the present invention is to realize a gate-controlled field sequential circuit through the following technical solution, comprising M rows of sub-circuits, wherein the sub-circuits include a compensation unit and a driving unit; The compensation unit includes a first transistor, a second transistor, a fourth transistor, a fifth transistor and a pre-storage capacitor; The gate of the first transistor of the sub-circuit of the Nth row is coupled to the row gate signal line of the N-1th row, the first source and drain of the first transistor are coupled to the positive power line, the second source and drain of the first transistor are coupled to one end of the pre-storage capacitor, and the other end of the pre-storage capacitor is coupled to the common signal line; The second source and drain of the first transistor are also coupled to the gate of the fourth transistor, the first source and drain of the fourth transistor are coupled to the second source and drain of the third transistor and the fifth transistor, and the second source and drain of the fourth transistor are coupled to the second source and drain of the second transistor; The first source and drain of the second transistor of the sub-circuit of the Nth row are coupled to one end of the pre-storage capacitor, and the gate of the second transistor is coupled to the row gate signal line of the Nth row; The gate of the third transistor is coupled to the transfer signal line, and the first source and drain of the third transistor are coupled to the positive power line; The gate of the fifth transistor of the sub-circuit of the Nth row is coupled to the row gate signal line of the Nth row, the first source and drain of the fifth transistor is coupled to the data signal line, and the second source and drain of the fifth transistor is coupled to the first source and drain of the fourth transistor; The second source and drain of the fourth transistor are also coupled to the driving unit; The M and N are positive integers, 1 <N≤M。

[0007] Further, the driving unit includes a sixth transistor and a pixel electrode; the gate of the sixth transistor is coupled to the transfer signal line, the first source and drain of the sixth transistor are coupled to the second source and drain of the second transistor, the second source and drain of the sixth transistor are coupled to the pixel electrode, and the other end of the pixel electrode is coupled to the common signal line.

[0008] Furthermore, the driving unit further includes a storage capacitor, one end of the storage capacitor is coupled to the second source and drain of the sixth transistor, and the other end of the storage capacitor is coupled to the common signal line.

[0009] Furthermore, the subcircuit also includes a reset unit, which includes a seventh transistor, a first source and drain of the seventh transistor is coupled to the driving unit, a second source and drain of the seventh transistor is coupled to the ground line, and the other end of the storage capacitor is coupled to the common signal line.

[0010] Furthermore, the subcircuit also includes a selection unit, the first source and drain of the first transistor, the first source and drain of the third transistor, and the first source and drain of the fifth transistor are all coupled to the selection unit; the gate of the first transistor is coupled to a reset signal line.

[0011] Further, the selection unit includes an eighth transistor, a ninth transistor and a power signal line; The gate of the eighth transistor is coupled to the data control signal line, the first source and drain of the eighth transistor are coupled to the data signal line, and the second source and drain of the eighth transistor are coupled to the second source and drain of the ninth transistor; the gate of the ninth transistor is coupled to the power control signal line, and the first source and drain of the ninth transistor are coupled to the power signal line.

[0012] The present invention also provides a gate-controlled field sequence circuit control method, comprising: In the backlight-on phase of the sub-circuit in row N: The row gate signal line of the Nth row jumps to a high level, and the second transistor and the fifth transistor are turned on. The data signal line maintains the potential of the second node at the data signal voltage through the fifth transistor; the pre-storage capacitor maintains the first node at a high potential and simultaneously maintains the third node at a high potential; At this time, the fourth transistor is turned on until it reaches a saturation state. When the fourth transistor is in a saturation state, the first node and the second node are discharged to the sum of the data signal voltage and the threshold voltage of the fourth transistor; The row gate signal line of the Nth row jumps to a low level, and the second transistor and the fifth transistor are turned off; In the backlight off phase of the sub-circuit in row N: The reset signal line jumps to a high level, and the seventh transistor is turned on, so that the pixel electrode is reset through the seventh transistor; After the reset is completed, the reset signal line jumps to a low level, and the seventh transistor is turned off; The transfer signal line jumps to a high level, and the third transistor and the sixth transistor are turned on; The positive power line makes the potential of the second node high through the third transistor; At this time, the pre-storage capacitor maintains the potential of the first node as the sum of the data signal line and the threshold voltage; the fourth transistor is saturated and discharged, so that the potential of the third node is the data signal voltage when cut off, and the data signal voltage is written into the pixel electrode through the sixth transistor.

[0013] The present invention also provides a gate-controlled field sequence circuit control method, comprising: In the backlight-on phase of the sub-circuit in row N: The row gate signal line of the Nth row jumps to a high level, and the second transistor and the fifth transistor are turned on; the data signal control line jumps to a high level, and the eighth transistor is turned on. The data signal line maintains the potential of the second node at the data signal voltage through the fifth transistor and the eighth transistor; the second transistor connects the first node and the third node; The pre-storage capacitor maintains the first node and the third node at a high potential; At this time, the fourth transistor is turned on until it reaches a saturation state. When the fourth transistor is in a saturation state, the first node and the second node are discharged to the sum of the data signal voltage and the threshold voltage of the fourth transistor; The row gate signal line of the Nth row jumps to a low level, and the second transistor and the fifth transistor are turned off; the data signal control line jumps to a low level, and the eighth transistor is turned off: In the backlight off phase of the sub-circuit in row N: The power control signal line jumps to a high level, and the ninth transistor is turned on, so that the power signal line inputs a preset square wave to the field sequence circuit through the ninth transistor; The transfer signal line jumps to a high level, and the third transistor and the sixth transistor are turned on; The power signal line enables the pixel electrode to be reset through a preset square wave through the ninth transistor, the third transistor and the sixth transistor; After the reset is completed, the power signal line makes the potential of the second node high through the ninth transistor and the third transistor; At this time, the pre-storage capacitor maintains the potential of the first node as the sum of the data signal line and the threshold voltage; the fourth transistor is saturated and discharged, so that the potential of the third node is the data signal voltage when cut off, and the data signal voltage is written into the pixel electrode through the sixth transistor.

[0014] Furthermore, before the backlight-on phase of the sub-circuit in the Nth row, a preset high phase is also included; The preset high stage includes: The row gate signal line of the N-1th row jumps to a high level, the first transistor is turned on, and the positive power line charges the pre-storage capacitor through the first transistor, so that the potential of the first node becomes a high potential; The row gate signal line of the N-1th row jumps to a low level, and the first transistor is turned off.

[0015] The present invention has the following advantages: The present invention sets a compensation unit, stores a high potential in advance through a pre-storage capacitor, so that the gate of the fourth transistor is a high potential; turns on the second transistor, so that the gate and source-drain of the fourth transistor are connected, that is, the first node and the third node are turned on; at this time, the transistor conduction characteristic is used to make the potential difference between the first node and the second node the threshold voltage of the fourth transistor, and the potential of the first node is the sum of the data signal voltage and the threshold voltage; when writing, the data signal voltage and the threshold voltage are stored in the pre-storage capacitor, and the conduction characteristic of the transistor is used again to make the potential of the third node the data signal voltage. Since the pre-compensated threshold voltage is in the pre-storage capacitor, the influence of the threshold voltage can be eliminated after the conduction, and the influence of the data signal writing into the pixel electrode is reduced, thereby avoiding the abnormal screen display caused by uneven in-plane process and the drift of the threshold voltage of the transistor over time. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A circuit diagram of a first embodiment of the present invention; Figure 2 is a timing diagram of the first embodiment of the present invention; Figure 3 is a circuit diagram of Embodiment 2 of the present invention; Figure 4 is a circuit diagram of a selection unit according to a second embodiment of the present invention; Figure 5 This is a timing diagram of the second embodiment of the present invention. DETAILED DESCRIPTION

[0017] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0018] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0019] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other. Example

[0020] See also Figure 1 , the present invention provides a gate-controlled field sequential circuit, comprising M rows of sub-circuits, the sub-circuit comprising a compensation unit and a driving unit; The compensation unit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5 and a pre-storage capacitor Cst1; The gate of the first transistor T1 of the sub-circuit of the Nth row is coupled to the row gate signal line ScanN-1 of the N-1th row, the first source and drain of the first transistor T1 are coupled to the positive power line Vdd, the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cst1, and the other end of the pre-storage capacitor Cst1 is coupled to the common signal line Com; the second source and drain of the first transistor T1 is also coupled to the gate of the fourth transistor T4, the first source and drain of the fourth transistor T4 is coupled to the second source and drain of the third transistor T3 and the fifth transistor T5, and the second source and drain of the fourth transistor T4 is coupled to the second source and drain of the second transistor T2; The first source and drain of the second transistor T2 of the sub-circuit of the Nth row are coupled to one end of the pre-storage capacitor Cst1, and the gate of the second transistor T2 is coupled to the row gate signal line ScanN of the Nth row; the gate of the third transistor T3 is coupled to the transfer signal line Tran, and the first source and drain of the third transistor T3 are coupled to the positive power line Vdd; the gate of the fifth transistor T5 is coupled to the row gate signal line ScanN of the Nth row, the first source and drain of the fifth transistor T5 are coupled to the data signal line Data, and the second source and drain of the fifth transistor T5 are coupled to the first source and drain of the fourth transistor T4; the second source and drain of the fourth transistor T4 are also coupled to the first source and drain of the sixth transistor T6.

[0021] Further, the driving unit includes a sixth transistor T6, a pixel electrode Clc and a storage capacitor Cst2; the gate of the sixth transistor T6 is coupled to the transfer signal line Tran, the first source and drain of the sixth transistor T6 are coupled to the second source and drain of the second transistor T2, the second source and drain of the sixth transistor T6 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cst2 is coupled to the second source and drain of the sixth transistor T6, and the other end of the storage capacitor Cst2 is coupled to the common signal line Com.

[0022] Furthermore, the subcircuit also includes a reset unit, which includes a seventh transistor T7, a first source and drain of the seventh transistor T7 coupled to the driving unit, a second source and drain of the seventh transistor T7 coupled to the ground line Vss, and the other end of the storage capacitor Cst2 coupled to the common signal line Com.

[0023] like Figure 2 As shown, before the backlight-on stage of the sub-circuit in the Nth row, a preset high stage is also included; The preset high stage includes: the row gate signal line ScanN-1 of the N-1th row jumps to a high level, the first transistor T1 is turned on, and the positive power line Vdd charges the pre-storage capacitor Cst1 through the first transistor T1, so that the potential of the first node A becomes a high potential. At this time, the potential of the first node A VA=Vdd; The row gate signal line ScanN-1 of the N-1th row jumps to a low level, and the first transistor T1 is turned off; The preset high stage is used to charge the pre-storage capacitor Cst1 to maintain a high potential at the first node A, so that the fourth transistor T4 can enter a preset on-off state in a subsequent stage.

[0024] In the backlight-on phase of the sub-circuit in row N: The row gate signal line ScanN of the Nth row jumps to a high level, and the second transistor T2 and the fifth transistor T5 are turned on; the data signal line Data makes the potential of the second node B continue to be the data signal voltage through the fifth transistor T5, that is, VB=Vdata; the pre-storage capacitor Cst1 maintains the first node A at a high potential, and at the same time maintains the third node C at a high potential through the second transistor T2, that is, VA=VC=Vdd; The fourth transistor T4 is turned on until it reaches a saturation state. Since the second node B maintains the data signal voltage Vdata, when the fourth transistor T4 is in a saturation state, the first node A and the third node C are discharged to the sum of the data signal voltage Vdata and the threshold voltage Vth of the fourth transistor T4, that is, VA=VC=Vdata+Vth; the row gate signal line ScanN of the Nth row jumps to a low level, and the second transistor T2 and the fifth transistor T5 are turned off; In the backlight-on stage, the fourth transistor T4 cooperates with the pre-storage capacitor Cst1, the second transistor T2 and the fifth transistor T5 to extract the threshold voltage Vth and store it in the first node A, thereby pre-compensating the threshold voltage Vth.

[0025] In the backlight off phase of the sub-circuit in row N: The reset signal line Reset jumps to a high level, and the seventh transistor T7 is turned on, so that the pixel electrode Clc is reset through the seventh transistor T7; After the reset is completed, the reset signal line Reset jumps to a low level, and the seventh transistor T7 is turned off; The transfer signal line Tran jumps to a high level, and the third transistor T3 and the sixth transistor T6 are turned on; The positive power line Vdd makes the potential of the second node B high through the third transistor T3, at this time VB=Vdd; At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A at VA=Vdata+Vth, so that the fourth transistor T4 is in a saturated state. At this time, the potential of the third node C is the data signal voltage Vdata when it is cut off, that is, VC=Vdata; The sixth transistor T6 is turned on, and the data signal voltage Vdata of the third node C is written into the pixel electrode Clc through the sixth transistor T6.

[0026] At this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor T3, the fourth transistor T4 and the sixth transistor T6, so that the pixel voltage Vpixel=Vdata; by utilizing the saturation state characteristics of the fourth transistor T4, it can offset the pre-compensated threshold voltage Vth, thereby avoiding the impact of the threshold voltage change.

[0027] The present invention sets a compensation unit and uses the law of charge conservation to stabilize the potential of the first node A at Vdd; the sum of the potential of the second node B is maintained at Vdata through the data signal line Data, and the on-off and off voltage characteristics of the fourth transistor T4 are used to discharge the first node A and the third node C when the fourth transistor T4 reaches saturation, so that the transistor is stabilized in a saturated state. At this time, VA=VC=Vdata+Vth, and the threshold voltage of the fourth transistor T4 is pre-written into the first node A for storage, so as to offset the threshold voltage Vth when the voltage of the pixel electrode Clc is subsequently written; When writing, the saturation discharge characteristics of the transistor are used again. At this time, VB=Vdd, VA=Vdata+Vth, so VC=Vdata when stable. This eliminates the influence of the threshold voltage Vth on the writing of the data signal into the pixel electrode, thereby avoiding abnormal screen display caused by uneven in-plane process and drift of the threshold voltage Vth of the transistor over time.

[0028] Embodiment 2 like Figure 3 As shown, this embodiment is a field sequential circuit of gate control. In this embodiment 2, the sub-circuit includes a selection unit, a compensation unit and a driving unit; The compensation unit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5 and a pre-storage capacitor Cst1; The first source and drain of the first transistor T1 are coupled to the selection unit; the gate of the first transistor T1 is coupled to the row gate signal line ScanN-1 (or the reset signal line Reset) of the N-1th row, the second source and drain of the first transistor T1 is coupled to one end of the pre-storage capacitor Cst1, and the other end of the pre-storage capacitor Cst1 is coupled to the common signal line Com; the second source and drain of the first transistor T1 is also coupled to the gate of the fourth transistor T4, the first source and drain of the fourth transistor T4 is coupled to the second source and drain of the third transistor T3 and the fifth transistor T5, and the second source and drain of the fourth transistor T4 is coupled to the second source and drain of the second transistor T2. source and drain; the first source and drain of the second transistor T2 are coupled to one end of the pre-storage capacitor Cst1, and the gate of the second transistor T2 is coupled to the row gate signal line ScanN of the Nth row; the gate of the third transistor T3 is coupled to the transfer signal line Tran, and the first source and drain of the third transistor T3 are coupled to the selection unit; the gate of the fifth transistor T5 is coupled to the row gate signal line ScanN of the Nth row, the first source and drain of the fifth transistor T5 is coupled to the selection unit, and the second source and drain of the fifth transistor T5 is coupled to the first source and drain of the fourth transistor T4; the second source and drain of the fourth transistor T4 is also coupled to the first source and drain of the sixth transistor T6.

[0029] Further as Figure 4As shown, the selection unit includes an eighth transistor T8, a ninth transistor T9 and a power signal line Vdd-Vss; the gate of the eighth transistor T8 is coupled to the data control signal line Data-Ctrl, the first source and drain of the eighth transistor T8 are coupled to the data signal line Data, and the second source and drain of the eighth transistor T8 are coupled to the second source and drain of the ninth transistor T9; the gate of the ninth transistor T9 is coupled to the power control signal line V-Ctrl, and the first source and drain of the ninth transistor T9 are coupled to the power signal line Vdd-Vss; the selection unit is arranged outside the display area of ​​the field sequential circuit.

[0030] Further, the driving unit includes a sixth transistor T6, a pixel electrode Clc and a storage capacitor Cst2; the gate of the sixth transistor T6 is coupled to the transfer signal line Tran, the first source and drain of the sixth transistor T6 are coupled to the second source and drain of the second transistor T2, the second source and drain of the sixth transistor T6 are coupled to the pixel electrode Clc, and the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cst2 is coupled to the second source and drain of the sixth transistor T6, and the other end of the storage capacitor Cst2 is coupled to the common signal line Com.

[0031] like Figure 5 As shown, before the backlight-on stage of the sub-circuit in the Nth row, a preset high stage is also included; The preset high stage includes: the row gate signal line ScanN-1 of the N-1th row jumps to a high level, the first transistor T1 is turned on, and the positive power line Vdd charges the pre-storage capacitor Cst1 through the first transistor T1, so that the potential of the first node A becomes a high potential. At this time, the potential of the first node A VA=Vdd; The row gate signal line ScanN-1 of the N-1th row jumps to a low level, and the first transistor T1 is turned off; The preset high stage is used to charge the pre-storage capacitor Cst1 to maintain a high potential at the first node A, so that the fourth transistor T4 can enter a preset on-off state in a subsequent stage.

[0032] In the backlight-on phase of the sub-circuit in row N: The row gate signal line ScanN of the Nth row jumps to a high level, and the second transistor T2 and the fifth transistor T5 are turned on; the data signal control line Data-Ctrl jumps to a high level, and the eighth transistor T8 is turned on. The data signal line Data makes the potential of the second node B continue to be the data signal voltage through the eighth transistor T8 and the fifth transistor T5, that is, VB=Vdata; the second transistor T2 is turned on so that the first node A and the third node C are connected; The pre-storage capacitor Cst1 maintains the first node A and the third node C at a high potential, that is, VA=VC=Vdd; At this time, the fourth transistor T4 is turned on until it reaches a saturation state. Since the second node B maintains the data signal voltage Vdata, when the fourth transistor T4 is in a saturation state, the first node A and the third node C are discharged to the sum of the data signal voltage Vdata and the threshold voltage Vth of the fourth transistor T4, that is, VA=VC=Vdata+Vth; the row gate signal line ScanN of the Nth row jumps to a low level, and the second transistor T2 and the fifth transistor T5 are turned off; In the backlight-on stage, the fourth transistor T4 cooperates with the pre-storage capacitor Cst1, the second transistor T2 and the fifth transistor T5 to extract the threshold voltage Vth and store it in the first node A, thereby pre-compensating the threshold voltage Vth.

[0033] In the backlight off phase of the sub-circuit in row N: The power control signal line V-Ctrl jumps to a high level, and the ninth transistor T9 is turned on, so that the power signal line Vdd-Vss inputs a preset square wave to the field sequence circuit through the ninth transistor T9; The preset square wave is a square wave that goes low first and then high, Vss when low and Vdd when high; The transfer signal line Tran jumps to a high level, and the third transistor T3 and the sixth transistor T6 are turned on; The level of the preset square wave output by the power signal line Vdd-Vss at this time is low and the level of the preset square wave is high level Vdd, and the potential of the second node B is high potential through the ninth transistor T9 and the third transistor T3, that is, VB=Vdd; At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A at VA=Vdata+Vth; so that the fourth transistor T4 is saturated until it reaches the saturation state. At this time, the potential of the third node C is the data signal voltage Vdata when it is cut off, that is, VC=Vdata; The sixth transistor T6 is turned on, and the data signal voltage Vdata of the third node C is written into the pixel electrode Clc through the sixth transistor T6.

[0034] At this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor T3, the fourth transistor T4 and the sixth transistor T6, so that the pixel voltage Vpixel=Vdata; by utilizing the saturation state characteristics of the fourth transistor T4, it can offset the pre-compensated threshold voltage Vth, thereby avoiding the impact of the threshold voltage change.

[0035] The present invention sets a compensation unit and, through the law of conservation of charge, stabilizes the potential of the first node A at Vdd; the sum maintains the potential of the second node B at Vdata through the data signal line Data, and through the on-off and off-voltage characteristics of the fourth transistor T4, when the fourth transistor T4 reaches saturation, the first node A and the third node C discharge, so that the transistor is stabilized in a saturated state. At this time, VA=VC=Vdata+Vth, and the threshold voltage of the fourth transistor T4 is pre-written into the first node A for storage, so that the threshold voltage Vth is offset when the voltage of the pixel electrode Clc is subsequently written, thereby avoiding the abnormal screen display caused by uneven in-plane process and the drift of the threshold voltage Vth of the transistor over time.

[0036] This embodiment does not need to set up a reset unit, and the working process of the field sequential circuit can be completed by selecting the unit to input corresponding signals into the surface at different time periods; thereby saving a transistor, thereby improving the aperture ratio in the surface.

[0037] Embodiment 3 This embodiment is a gate-controlled field sequence circuit control method.

[0038] In the third embodiment, before the backlight-on phase of the sub-circuit in the Nth row, a preset high phase is also included; The preset high stage includes: the row gate signal line ScanN-1 of the N-1th row jumps to a high level, the first transistor T1 is turned on, and the positive power line Vdd charges the pre-storage capacitor Cst1 through the first transistor T1, so that the potential of the first node A becomes a high potential. At this time, the potential of the first node A VA=Vdd; The row gate signal line ScanN-1 of the N-1th row jumps to a low level, and the first transistor T1 is turned off; The preset high stage is used to charge the pre-storage capacitor Cst1 to maintain a high potential at the first node A, so that the fourth transistor T4 can enter a preset on-off state in a subsequent stage.

[0039] In the backlight-on phase of the sub-circuit in row N: The row gate signal line ScanN of the Nth row jumps to a high level, and the second transistor T2 and the fifth transistor T5 are turned on; the data signal line Data makes the potential of the second node B continue to be the data signal voltage through the fifth transistor T5, that is, VB=Vdata; the second transistor T2 is turned on so that the first node A and the third node C are connected; The pre-storage capacitor Cst1 maintains the first node A and the third node C at a high potential, that is, VA=VC=Vdd; At this time, the fourth transistor T4 is turned on until it reaches a saturation state. Since the second node B maintains the data signal voltage Vdata, when the fourth transistor T4 is in a saturation state, the first node A and the third node C are discharged to the sum of the data signal voltage Vdata and the threshold voltage Vth of the fourth transistor T4, that is, VA=VC=Vdata+Vth; the row gate signal line ScanN of the Nth row jumps to a low level, and the second transistor T2 and the fifth transistor T5 are turned off; In the backlight-on stage, the fourth transistor T4 cooperates with the pre-storage capacitor Cst1, the second transistor T2 and the fifth transistor T5 to extract the threshold voltage Vth and store it in the first node A, thereby pre-compensating the threshold voltage Vth.

[0040] In the backlight off phase of the sub-circuit in row N: The reset signal line Reset jumps to a high level, and the seventh transistor T7 is turned on, so that the pixel electrode Clc is reset through the seventh transistor T7; After the reset is completed, the reset signal line Reset jumps to a low level, and the seventh transistor T7 is turned off; The transfer signal line Tran jumps to a high level, and the third transistor T3 and the sixth transistor T6 are turned on; The positive power line Vdd makes the potential of the second node B high through the third transistor T3, at this time VB=Vdd; At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A at VA=Vdata+Vth, so that the fourth transistor T4 is in a saturated state, and the potential of the third node C is the data signal voltage Vdata when it is cut off, that is, VC=Vdata; The sixth transistor T6 is turned on, and the data signal voltage Vdata of the third node C is written into the pixel electrode Clc through the sixth transistor T6.

[0041] At this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor T3, the fourth transistor T4 and the sixth transistor T6, so that the pixel voltage Vpixel=Vdata; by utilizing the saturation state of the fourth transistor T4, it can offset the pre-compensated threshold voltage Vth, thereby avoiding the impact of the change in the threshold voltage Vth.

[0042] This embodiment is used for the first embodiment and the deformation circuit of the first embodiment, and its beneficial effects are the same as those of the first embodiment.

[0043] Embodiment 4 The fourth embodiment is a gate-controlled field sequence circuit control method.

[0044] Before the backlight-on phase of the sub-circuit in the Nth row, a preset high phase is also included; The preset high stage includes: the row gate signal line ScanN-1 of the N-1th row jumps to a high level, the first transistor T1 is turned on, and the positive power line Vdd charges the pre-storage capacitor Cst1 through the first transistor T1, so that the potential of the first node A becomes a high potential. At this time, the potential of the first node A VA=Vdd; The row gate signal line ScanN-1 of the N-1th row jumps to a low level, and the first transistor T1 is turned off; The preset high stage is used to charge the pre-storage capacitor Cst1 to maintain a high potential at the first node A, so that the fourth transistor T4 can enter a preset on-off state in a subsequent stage.

[0045] In the backlight-on phase of the sub-circuit in row N: The row gate signal line ScanN of the Nth row jumps to a high level, and the second transistor T2 and the fifth transistor T5 are turned on; the data signal control line Data-Ctrl jumps to a high level, and the eighth transistor T8 is turned on. The data signal line Data makes the potential of the second node B continue to be the data signal voltage through the eighth transistor T8 and the fifth transistor T5, that is, VB=Vdata; the second transistor T2 is turned on so that the first node A and the third node C are connected; The pre-storage capacitor Cst1 maintains the first node A and the third node C at a high potential, that is, VA=VC=Vdd; At this time, the fourth transistor T4 is turned on until it reaches a saturation state. Since the second node B maintains the data signal voltage Vdata, when the fourth transistor T4 is in a saturation state, the first node A and the third node C are discharged to the sum of the data signal voltage Vdata and the threshold voltage Vth of the fourth transistor T4, that is, VA=VC=Vdata+Vth; the row gate signal line ScanN of the Nth row jumps to a low level, and the second transistor T2 and the fifth transistor T5 are turned off; In the backlight-on stage, the fourth transistor T4 cooperates with the pre-storage capacitor Cst1, the second transistor T2 and the fifth transistor T5 to extract the threshold voltage Vth and store it in the first node A, thereby pre-compensating the threshold voltage Vth.

[0046] In the backlight off phase of the sub-circuit in row N: The power control signal line V-Ctrl jumps to a high level, and the ninth transistor T9 is turned on, so that the power signal line Vdd-Vss inputs a preset square wave to the field sequence circuit through the ninth transistor T9; The preset square wave is a square wave that goes low first and then high, Vss when low and Vdd when high; The transfer signal line Tran jumps to a high level, and the third transistor T3 and the sixth transistor T6 are turned on; The level of the preset square wave output by the power signal line Vdd-Vss at this time is low and the level of the preset square wave is high level Vdd, and the potential of the second node B is high potential through the ninth transistor T9 and the third transistor T3, that is, VB=Vdd; At this time, the pre-storage capacitor Cst1 maintains the potential of the first node A at VA=Vdata+Vth; so that the fourth transistor T4 is saturated until it reaches the saturation state. At this time, the potential of the third node C is the data signal voltage Vdata when it is cut off, that is, VC=Vdata; The sixth transistor T6 is turned on, and the data signal voltage Vdata of the third node C is written into the pixel electrode Clc through the sixth transistor T6.

[0047] At this stage, the accurate data signal voltage Vdata is written into the pixel electrode Clc through the third transistor T3, the fourth transistor T4 and the sixth transistor T6, so that the pixel voltage Vpixel=Vdata; by utilizing the saturation state characteristics of the fourth transistor T4, it can offset the pre-compensated threshold voltage Vth, thereby avoiding the impact of the change in the threshold voltage Vth.

[0048] This embodiment is used to provide a control method different from the third embodiment, and its beneficial effects are the same as those of the second embodiment.

[0049] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A gate-controlled field sequential circuit, characterized in that: comprising M rows of sub-circuits, wherein the sub-circuits include compensation units and driving units; The compensation unit includes a first transistor (T1), a second transistor (T2), a fourth transistor (T4), a third transistor (T3), a fifth transistor (T5) and a pre-storage capacitor (Cst1); The gate of the first transistor (T1) of the sub-circuit of the Nth row is coupled to the row gate signal line (ScanN-1) of the N-1th row, the first source and drain of the first transistor (T1) are coupled to the positive power line (Vdd), the second source and drain of the first transistor (T1) are coupled to one end of the pre-storage capacitor (Cst1), and the other end of the pre-storage capacitor (Cst1) is coupled to the common signal line (Com); The second source and drain of the first transistor (T1) is also coupled to the gate of the fourth transistor (T4), the first source and drain of the fourth transistor (T4) is coupled to the second source and drain of the third transistor (T3) and the fifth transistor (T5), and the second source and drain of the fourth transistor (T4) is coupled to the second source and drain of the second transistor (T2); The first source and drain of the second transistor (T2) of the sub-circuit of the Nth row is coupled to one end of the pre-storage capacitor (Cst1), and the gate of the second transistor (T2) is coupled to the row gate signal line (ScanN) of the Nth row; The gate of the third transistor (T3) of the sub-circuit in the Nth row is coupled to the transfer signal line (Tran), and the first source and drain of the third transistor (T3) is coupled to the positive power line (Vdd); The gate of the fifth transistor (T5) of the sub-circuit of the Nth row is coupled to the row gate signal line (ScanN) of the Nth row, the first source and drain of the fifth transistor (T5) is coupled to the data signal line (Data), and the second source and drain of the fifth transistor (T5) is coupled to the first source and drain of the fourth transistor (T4); The second source and drain of the fourth transistor (T4) of the sub-circuit in the Nth row is also coupled to the driving unit; The M and N are positive integers, 1 <N≤M。 2. A gate-controlled field sequential circuit according to claim 1, characterized in that: The driving unit includes a sixth transistor (T6) and a pixel electrode (Clc); The gate of the sixth transistor (T6) is coupled to the transfer signal line (Tran), the first source and drain of the sixth transistor (T6) are coupled to the second source and drain of the second transistor (T2), the second source and drain of the sixth transistor (T6) are coupled to the pixel electrode (Clc), and the other end of the pixel electrode (Clc) is coupled to the common signal line (Com).

3. A gate-controlled field sequential circuit according to claim 2, characterized in that: The driving unit further includes a storage capacitor (Cst2), one end of the storage capacitor (Cst2) is coupled to the second source and drain of the sixth transistor (T6), and the other end of the storage capacitor (Cst2) is coupled to the common signal line (Com).

4. The gate-controlled field sequential circuit according to claim 1, characterized in that: The sub-circuit also includes a reset unit, which includes a seventh transistor (T7), a first source and a drain of the seventh transistor (T7) coupled to the driving unit, a second source and a drain of the seventh transistor (T7) coupled to the ground line (Vss), and the other end of the storage capacitor (Cst2) coupled to the common signal line (Com).

5. The gate-controlled field sequence circuit according to claim 2, characterized in that: The sub-circuit also includes a selection unit, the first source and drain of the first transistor (T1), the first source and drain of the third transistor (T3) and the first source and drain of the fifth transistor (T5) are all coupled to the selection unit; the gate of the first transistor (T1) is coupled to a reset signal line (Reset).

6. The gate-controlled field sequential circuit according to claim 5, characterized in that: The selection unit includes an eighth transistor (T8), a ninth transistor (T9) and a power signal line (Vdd-Vss); The gate of the eighth transistor (T8) is coupled to a data control signal line (Data-Ctrl), the first source and drain of the eighth transistor (T8) are coupled to a data signal line (Data), and the second source and drain of the eighth transistor (T8) are coupled to the second source and drain of the ninth transistor (T9); the gate of the ninth transistor (T9) is coupled to a power control signal line (V-Ctrl), and the first source and drain of the ninth transistor (T9) are coupled to a power signal line (Vdd-Vss).

7. A gate-controlled field sequence circuit control method, applied to any field sequence circuit according to claim 1 to claim 4, characterized in that: include: In the backlight-on phase of the sub-circuit in row N: The row gate signal line (ScanN) of the Nth row jumps to a high level, and the second transistor (T2) and the fifth transistor (T5) are turned on. The data signal line (Data) makes the potential of the second node (B) continue to be the data signal voltage through the fifth transistor (T5); the pre-storage capacitor (Cst1) maintains the first node (A) at a high potential, and at the same time maintains the third node (C) at a high potential through the second transistor (T2); The fourth transistor (T4) is turned on until it reaches a saturation state, and the first node (A) and the third node (C) are discharged to the sum of the data signal voltage and the threshold voltage of the fourth transistor (T4); The row gate signal line (ScanN) of the Nth row jumps to a low level, and the second transistor (T2) and the fifth transistor (T5) are turned off; In the backlight off phase of the sub-circuit in row N: The reset signal line (Reset) jumps to a high level, and the seventh transistor (T7) is turned on, so that the pixel electrode (Clc) is reset through the seventh transistor (T7); After the reset is completed, the reset signal line (Reset) jumps to a low level, and the seventh transistor (T7) is turned off; The transfer signal line (Tran) jumps to a high level, and the third transistor (T3) and the sixth transistor (T6) are turned on; The positive power line (Vdd) makes the potential of the second node (B) high through the third transistor (T3); The fourth transistor (T4) is in a saturated state again, the potential of the third node (C) is the data signal voltage, and the data signal voltage is written into the pixel electrode (Clc) through the sixth transistor (T6).

8. A gate-controlled field sequence circuit control method, applied to any field sequence circuit described in claim 1, 5 or 6, characterized in that: include: In the backlight-on phase of the sub-circuit in row N: The row gate signal line (ScanN) of the Nth row jumps to a high level, and the second transistor (T2) and the fifth transistor (T5) are turned on; the pre-storage capacitor (Cst1) maintains the first node (A) at a high potential, and at the same time maintains the third node (C) at a high potential through the second transistor (T2); The data signal control line (Data-Ctrl) jumps to a high level, the eighth transistor (T8) is turned on, and the data signal line (Data) maintains the potential of the second node (B) at the data signal voltage through the fifth transistor (T5) and the eighth transistor (T8); The fourth transistor (T4) is turned on until it reaches a saturation state. When the fourth transistor (T4) is in the saturation state, the first node (A) and the second node (B) are discharged to the sum of the data signal voltage and the threshold voltage of the fourth transistor (T4); The row gate signal line (ScanN) of the Nth row jumps to a low level, and the second transistor (T2) and the fifth transistor (T5) are turned off; the data signal control line (Data-Ctrl) jumps to a low level, and the eighth transistor (T8) is turned off: In the backlight off phase of the sub-circuit in row N: The power control signal line (V-Ctrl) jumps to a high level, and the ninth transistor (T9) is turned on, so that the power signal line (Vdd-Vss) inputs a preset square wave to the field sequence circuit through the ninth transistor (T9); The transfer signal line (Tran) jumps to a high level, and the third transistor (T3) and the sixth transistor (T6) are turned on; The power signal line (Vdd-Vss) enables the pixel electrode (Clc) to be reset through a preset square wave via a ninth transistor (T9), a third transistor (T3) and a sixth transistor (T6); After the reset is completed, the power signal line (Vdd-Vss) makes the potential of the second node (B) high through the ninth transistor (T9) and the third transistor (T3); The pre-storage capacitor (Cst1) maintains the potential of the first node (A) as the sum of the data signal line and the threshold voltage, and the fourth transistor (T4) is saturated and discharged, so that the potential of the third node (C) is the data signal voltage when it is turned off, and the data signal voltage is written into the pixel electrode (Clc) through the sixth transistor (T6).

9. A gate-controlled field sequence circuit control method according to claim 7 or 8, characterized in that: include: Before the backlight-on phase of the sub-circuit in the Nth row, a preset high phase is also included; The preset high stage includes: The row gate signal line (ScanN-1) of the N-1th row jumps to a high level, the first transistor (T1) is turned on, and the positive power line (Vdd) charges the pre-storage capacitor (Cst1) through the first transistor (T1), so that the potential of the first node (A) becomes a high potential; The row gate signal line (ScanN-1) of the N-1th row jumps to a low level, and the first transistor (T1) is turned off.

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