Method and apparatus for cancellation pulse generation with reduced waveform storage to reduce crests in transmission signal

Abstract

The invention relates to a method and apparatus for cancelation pulse generation with reduced waveform storage to reduce crests in a transmission signal. An example apparatus implementing cancellation pulse generation described herein includes a first memory [924] that stores a first subset of data samples of a single pulse cancellation waveform. The example apparatus includes a second memory [926] storing a second subset of data samples of the single pulse cancellation waveform, the second subset including data samples of the single pulse cancellation waveform different from the first subset. The example apparatus includes first circuitry [940] coupled in parallel to the first memory [924] and the second memory [926]. The example apparatus includes a plurality of buffers [950]. The example apparatus includes second circuitry [945] coupled to the plurality of buffers [950].

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit and priority of Indian Provisional Patent Application No. 202341051095 filed on July 28, 2023, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to transmitters and, more particularly, to cancel pulse generation with reduced waveform storage to reduce peaks in a transmit signal. Background Art

[0004] Wireless communication technology enables various electronic devices (e.g., mobile phones, tablets, laptops, etc.) to support the execution of increasingly diverse and complex workloads. Safely, efficiently, and accurately exchanging information over wireless media involves technical challenges. One such technical challenge is the low efficiency of power amplifiers. Generally, the efficiency of a power amplifier decreases as the amplitude of its output signal increases. Summary of the invention

[0005] For implementing methods and apparatus for generating cancellation pulses, an example apparatus includes a first memory storing a first subset of data samples of a single pulse cancellation waveform. The example apparatus includes a second memory storing a second subset of data samples of the single pulse cancellation waveform, the second subset including data samples of the single pulse cancellation waveform different from the first subset. The example apparatus includes a first circuit system configured to access first data samples from the first memory and second data samples from the second memory in parallel. The example apparatus includes a plurality of buffers respectively associated with a plurality of output cancellation pulses to be generated. The example apparatus includes a second circuit system configured to provide the first data sample and the second data sample to one or more of the plurality of buffers.

[0006] For implementing the method and apparatus for generating cancellation pulses, another example apparatus includes a plurality of memories, respective ones of the memories storing respective different data sample subsets of a single pulse cancellation waveform, the total number of the memories being based on the total number of output cancellation pulses that can be generated, the respective ones of the memories having respective storage capacities based on a ratio of the total number of samples of the single pulse cancellation waveform to the total number of output cancellation pulses that can be generated. The example apparatus includes programmable circuitry configured to access respective data samples from the respective ones of the memories in parallel, generate one or more output cancellation pulses based on the accessed respective data samples, and combine an input signal with the one or more output cancellation pulses to generate an output signal to be transmitted.

[0007] For methods and apparatus implementing cancellation pulse generation, an example non-transitory computer-readable medium includes computer-readable instructions for causing at least one processor circuit to: obtain at least an index corresponding to a sample of a pulse cancellation waveform to be used to generate one or more output cancellation pulses, the index being based on one or more locations of one or more peaks of an input signal; access, in parallel, respective data samples from respective ones of a plurality of memories, the plurality of memories collectively storing a single instance of the pulse cancellation waveform, the respective ones of the memories storing respective different subsets of data samples of the pulse cancellation waveform, the respective ones of the memories having respective storage capacities less than the total number of samples of the single instance of the pulse cancellation waveform, and generate the one or more output cancellation pulses based on the accessed respective data samples. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an example communication system including a client device and a base station.

[0009] Figure 2 Shows the Figure 1 Example envelope of a time domain input signal transmitted by a transmitter circuit system in a base station.

[0010] Figure 3 is a graph of an example complementary cumulative distribution function showing the effect of crest factor reduction on Figure 2 The influence of the time domain input signal.

[0011] Figure 4 is included in Figure 1 A block diagram of an example implementation of a transmitter circuit system in a base station of FIG.

[0012] Figure 5 is included in Figure 4 00140] A block diagram of an example implementation of crest factor reduction circuitry in a transmitter circuitry of FIG.

[0013] Figure 6 Show Figure 4 and 5 Example operation of the crest factor reduction circuit system.

[0014] Figure 7 is included in Figure 5 A block diagram of an example implementation of a cancellation waveform generation circuit system in an example crest factor reduction circuit system of FIG.

[0015] Figure 8 is included in Figure 7 A block diagram of a first example implementation of a cancellation pulse generation circuit system in a cancellation waveform generation circuit system of FIG.

[0016] Fig. 9is included in Figure 7 0026] Block diagram of a second example implementation of a cancellation pulse generating circuit system in a cancellation waveform generating circuit system of.

[0017] Fig. 10A The reference pulse elimination waveform is shown across the Fig. 9 Example partitioning of an elimination pulse subset memory in an elimination pulse generating circuit system.

[0018] Fig. 10B Shown based on Fig. 10A Example segmentation of Fig. 9 Example operation of the elimination pulse generating circuit system.

[0019] Figure 11-13 is a representation that can be executed, instantiated, or performed by an exemplary programmable circuit system to implement Figure 7 and 9 A flowchart of example machine readable instructions or example operations of a cancellation waveform generating circuit system.

[0020] Fig.14 is a block diagram of an example processing platform including programmable circuitry configured to execute, instantiate, or perform example machine-readable instructions or to perform Figure 11-13 Example operations to implement Figure 7 and 9 Elimination waveform generating circuit system.

[0021] Fig.15 yes Fig.14 A block diagram of an example implementation of a programmable circuit system.

[0022] Fig.16 yes Fig.14 A block diagram of another example implementation of a programmable circuit system.

[0023] The drawings are not necessarily drawn to scale. Generally, the same reference numerals in the drawings and the specification refer to the same or similar parts. Although the drawings show regions with clean lines and borders, some or all of these lines and borders may be idealized. In reality, borders and lines may not be observable, blended, or irregular. DETAILED DESCRIPTION

[0024] One technique used to quantify the power consumption of a transmitter device is the peak-to-average power ratio (PAR). PAR is determined by (i) squaring the peak amplitude of the transmitter output signal to obtain the peak power consumed, (ii) calculating the root mean square (RMS) value of the transmitter output signal to obtain the average power consumed, and (iii) dividing the peak power consumed by the average power consumed. In general, the performance of power amplifier circuitry within a transmitter device decreases as PAR increases. Therefore, members of the industry seek to produce transmitters with low PAR.

[0025] Some transmitter devices maintain low PAR by reducing the amplitude (e.g., magnitude) of peaks within an input signal prior to transmitting the output signal over a transmission medium. Reducing the peak magnitude of the input signal reduces peak power consumption, which in turn reduces PAR and improves the performance of the transmitter. As used herein, the technique of modifying the input signal as described above may be referred to as crest factor reduction (CFR).

[0026] Industry members employ various CFR techniques to reduce PAR. One such technique is the pulse-canceled CFR (PC-CFR) technique, which may also be referred to as peak-canceled CFR (PC-CFR). PC-CFR involves calculating one or more cancellation pulses (CPs) based on the properties of one or more peaks of the input signal, and adding the one or more CPs to the input signal in a direction opposite to the peaks. Another such technique is windowed CFR, which involves multiplying the input signal with a window waveform similar to the CP.

[0027] The example PC-CFR technique presented herein generates a CP based on stored data samples of a reference pulse cancellation waveform (PCW), also referred to as a peak cancellation waveform (PCW). In the example PC-CFR technique presented herein, the data samples of the PCW are scaled based on a cancellation phasor calculated for a given peak of an input signal to generate a CP to cancel the given peak. In addition, the example PC-CFR technique presented herein accesses data samples of the PCW based on the position of the given peak in the input signal for generating a CP to cancel the given peak.

[0028] In addition, the example PC-CFR technique proposed herein can generate multiple CPs for multiple signal peaks in parallel based on a single stored PCW. This is different from other PC-CFR techniques, which utilize multiple stored PCWs to generate multiple CPs, each of which is dedicated to generating different ones in the CP. Therefore, compared to such other techniques, the example PC-CFR technique proposed herein can reduce the memory resource footprint by a factor corresponding to the total number of CPs that can be generated. As described in further detail below, such memory footprint reduction is achieved by: a subset of data samples of a single PCW is stored across multiple memories, so that data samples corresponding to multiple CPs can be accessed in parallel, or multiple data samples corresponding to a single CP can be accessed in parallel. In addition, the example technique for generating CPs described herein can also be applied to generate window waveforms, which are used to multiply with input signals in windowed CFR applications.

[0029] Turning to the schema, Figure 1 is a block diagram of an example communication system. Figure 1 An example network 100, an example network device 102, an example client device 104, and an example transmission medium 106 are included. Network device 102 includes example controller circuitry 108, example transmitter circuitry 110, and example receiver circuitry 112. Similarly, client device 104 includes example controller circuitry 118, example receiver circuitry 114, and example transmitter circuitry 116. Figure 1 is an example of a transmitter device implemented within a telecommunications use case. However, a transmitter device implemented in the teachings described herein may be implemented in any type of use case or application.

[0030] The network 100 connects various endpoint devices and facilitates communication between them to support the Internet or telephone devices. In the example shown, the network 100 is a cellular network. However, the example network 100 can be implemented using any suitable wired or wireless network, including, for example, one or more data buses, one or more local area networks (LANs), one or more wireless LANs (WLANs), one or more coaxial cable networks, one or more satellite networks, one or more private networks, one or more public networks, etc. As used above and herein, the term "communication", including its variations (e.g., secure or unsecure communication, compressed or uncompressed communication, etc.), covers direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but includes selective communication at periodic or non-periodic intervals, as well as one-time events.

[0031] Network device 102 may refer to any device that connects client device 104 to other devices within network 100. Figure 1 In the example, the network device 102 is directly connected to the client device 104 via the transmission medium 106. In other examples, the network device 102 can communicate with the client device 104 indirectly by exchanging data across one or more intermediate devices. The network device 102 can operate using various network communication protocols and perform various cellular network operations. For example, the network device 102 can be implemented as one or more of a base station, a cellular tower, a signal repeater, a macro radio remote unit (RRU), a multiple input multiple output (MIMO) antenna system, a distributed antenna system (DAS), etc. Therefore, the network device 102 provides frequency profile information in some examples and does not provide frequency profile information in other examples.

[0032] Client device 104 refers to any terminal device capable of connecting to network 100. Therefore, client device 104 can form a data request in response to input from a user and transmit the request via network 100. Example devices that can implement client device 104 may include, but are not limited to, mobile phones, smart vehicles, wearable devices, etc.

[0033] exist Figure 1 In some examples, network device 102 and client device 104 communicate with each other using a cellular network protocol (e.g., 3G, 4G LTE, 5G, etc.). In some examples, network device 102 and client device 104 may use different wireless or wired communication protocols, including but not limited to Universal Serial Bus (USB), Ethernet, Wi-Fi, or Wi-Fi. Near Field Communication (NFC), Orthogonal Frequency Division Multiplexing (OFDM), Code Division Multiple Access (CDMA), etc. In some examples, the type of communication protocol used between network device 102 and client device 104 is based in part on whether transmission medium 106 is a wired or wireless medium.

[0034] Controller circuitry 108 receives data from a source (e.g., internal memory, client device 104, etc.) and performs operations in response to the data. For example, controller circuitry 108 generates a digital input signal x(n) to be provided to client device 104. Similarly, controller circuitry 118 receives data from a source and performs operations in response to the data. Controller circuitry 108 and 118 may be implemented by any type of programmable circuitry. Examples of programmable circuitry include a programmable microprocessor, a field programmable gate array (FPGA) that can instantiate instructions, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP) or a microcontroller, and an integrated circuit (IC), such as an application specific integrated circuit (ASIC).

[0035] Transmitter circuitry 110 and transmitter circuitry 116 receive digital signals from controller circuitry 108 and controller circuitry 118, respectively. Both transmitter circuitry 110 and transmitter circuitry 116 perform signal processing operations including CFR described in the teachings herein. Thus, example transmitter circuitry 110 and transmitter circuitry 116 may be implemented within network device 102 and client device 104, respectively, at a lower cost and size than other transmitter devices. Transmitter circuitry 110 in combination with Figure 2 Further description.

[0036] Receiver circuitry 112 receives analog signals transmitted by transmitter circuitry 116, converts the analog signals into digital signals, and provides the digital signals to controller circuitry 108. Similarly, receiver circuitry 114 receives analog signals transmitted by transmitter circuitry 110, converts the analog signals into digital signals, and provides the digital signals to controller circuitry 118.

[0037] As mentioned above, the network device 102 and the client device 104 communicate with each other using a network protocol. For example, the network device 102 may be a 4G / 5G base station 102 in communication with the client device 104, such as when the client device 104 is a mobile device 104. If the signal transmitted from the 4G / 5G base station exhibits a high PAR, the transmission circuit system may implement power back-off in the power amplifier (PA), thereby reducing the output RMS power and PA efficiency. Therefore, in the illustrated example, the transmitter circuit system 110 of the network device 102 implements CFR, enabling the PA used in the network device 102 to operate at a higher RMS power and making the operation of digital pre-distortion (DPD) easier. In some examples, the transmitter circuit system 116 of the client device 104 implements CFR for similar reasons.

[0038] In the illustrated example, the transmitter circuitry 110 of the network device 102 employs CFR to reduce the PAR of the baseband signal prior to DPD. For example, the complex baseband time domain input signal is processed across multiple CFR stages to limit the peak magnitude to a target PAR, but without reducing the adjacent channel leakage ratio. As described in further detail below, a given CFR stage includes interpolating the complex baseband signal to a higher sampling rate, identifying peaks, and calculating one or more cancellation waveforms to reduce or eliminate the peaks. CFR can better utilize the PA dynamic range by enabling the PA to operate at a higher RMS power, thereby improving efficiency.

[0039] Figure 2 It is shown in Figure 1FIG. 2 is an example complex baseband envelope 200 of an example time-domain input signal transmitted by transmitter circuitry 110 of network device 102. This envelope 200 of the example signal exhibits occasional peaks, such as example peak 205 having a PAR of ˜12 dB. Peaks such as peak 205 may cause the PA of network device 102 to operate in a saturation region, which may degrade ACLR.

[0040] The CFR reduces the probability that a signal to be transmitted by the transmitter circuitry 110 of the network device 102 will exceed a PAR target. Figure 4 Example complementary cumulative distribution function (CCDF) curves 305 and 310 are shown in FIG. Figure 1 The effect of the signal transmitted by the transmitter circuit system 110 of the network device 102 on the CFR algorithm implemented by the transmitter circuit system 110 of the network device 102 in the illustrated example has an example PAR target of 8 dB. Curve 305 represents the signal transmitted by the transmitter circuit system 110 of the network device 102. Figure 2 1, which has a PAR that exceeds the PAR target by ˜12 dB. Curve 310 represents the CCDF of an example output signal produced by the CFR processing implemented by the transmitter circuitry 110. CCDF 310 shows that the output signal from the CFR processing is limited to the PAR target of 8 dB. As described in further detail below, the CFR operation is performed in the transmitter circuitry 110 before the DPD correction to limit the PAR of the output transmission signal from the transmitter circuitry 110 of the network device 102.

[0041] Figure 4 yes Figure 1 1 is a block diagram of an example implementation of transmitter circuitry 110. Transmitter circuitry 110 includes example CFR circuitry 402, example digital predistortion (DPD) corrector circuitry 404, example DPD estimator circuitry 406, example transmitter (TX) digital circuitry 410, example TX digital-to-analog converter (DAC) circuitry 412, example TX digital step attenuator (DSA) circuitry 418, example power amplifier (PA) circuitry 420, example antenna 424, example feedback (FB) analog-to-digital circuitry (ADC) 428, and example FB digital circuitry 430. Figure 4 Also included are an example input signal 401 (referred to herein as x(n) 401), as well as an example modified signal 403 (which may be referred to herein as r(n) 403), an example output signal 421 (which may be referred to herein as s(t) 421).

[0042] CFR circuitry 402 reduces or suppresses peaks within x(n) 401 to produce a modified signal r(n) 403 having a lower PAR than x(n) 401. By reducing or suppressing the peaks, the local maximum maintained in r(n) 403 may also have a smaller magnitude than the local maximum of x(n) 401. Example CFR circuitry 402 produces r(n) 403 by performing a PC-CFR operation, as described in the teachings herein.

[0043] DPD corrector circuitry 404 predistorts r(n) 403 to counteract distortion that occurs when the power of the signal is amplified by PA 420. DPD corrector circuitry 404 performs predistortion using various configuration parameters. The values ​​of the configuration parameters are updated by DPD estimator circuitry 406. DPD estimator circuitry 406 samples r(n) 403, the output of DPD corrector circuitry 404, and s(t) 421 (e.g., the output of PA circuitry 420) to assist in determining how r(n) 403 will be predistorted. One or more of DPD corrector circuitry 404 or DPD estimator circuitry 406 may be implemented by any type of programmable circuitry.

[0044] TX digital circuitry 410 interpolates the output of DPD corrector circuitry 404 to introduce additional data points. The additional data points increase the sampling rate of the modified signal relative to the sampling rate of the original input signal x(n) 401. Example TX digital circuitry 410 both i) ensures that the frequency of the information in output signal s(t) 421 is high enough to enable receiver circuitry 114 to recover the information, and ii) allows DPD corrector circuitry 404 to sample the signal for predistortion only when needed (e.g., at a relatively low frequency).

[0045] The example TX DAC circuitry 412 converts the output of the TX digital circuitry 410 from a digital signal to an analog signal. Thus, the information transmitted across the transmission medium 106 is encoded continuously across a range of voltages rather than a set of discrete voltages.

[0046] Example TX DSA circuitry 418 attenuates the above analog signal so that the amount of power consumed by PA circuitry 420 is consistent. TX DSA circuitry 418 performs the attenuation in response to the gain of PA circuitry 420, which may change in response to temperature. PA circuitry 420 then amplifies the interpolated and attenuated signal to produce a transmission s(t) 421, which is transmitted across transmission medium 106 via antenna 424. The amplification of PA circuitry 420 introduces nonlinearity, which is counteracted by the predistortion of DPD corrector circuitry 404.

[0047] FB DSA circuitry 426 receives analog signal s(t) 421 from PA circuitry 420 and attenuates the signal. In some examples, FB DSA circuitry 426 attenuates signal s(t) 421 in response to operating parameters of FB ADC circuitry 428.

[0048] FB ADC circuitry 428 converts the attenuated version of z(t) 421 from an analog signal back to a digital signal. Next, FB digital circuitry 430 decimates the digital signal (eg, removes data points therefrom). The resulting signal is obtained by DPD estimator circuitry 406 and controller circuitry 108.

[0049] Figure 5 is included in Figure 4 FIG. 4 is a block diagram of an example implementation of CFR circuitry 402 in example transmitter circuitry 110 of FIG. Figure 5 The CFR circuit system 402 may be instantiated (e.g., create an instance, generate, materialize, implement, etc. for any length of time) by a programmable circuit system (e.g., a central processing unit (CPU) executing a first instruction). In addition, Figure 5 The CFR circuit system 402 may be instantiated (e.g., created as an instance, produced for any length of time, materialized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) or (ii) a field programmable gate array (FPGA), which is constructed or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. Thus, Figure 5 Some or all of the circuitry may be instantiated at the same or different times. Figure 5 Some or all of the circuitry of can be instantiated, for example, in one or more threads that execute in parallel on hardware or in serial on hardware. In addition, in some examples, Figure 5 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions or FPGA circuitry performing operations to implement one or more virtual machines or containers.

[0050] Figure 5The example CFR circuitry 402 includes example CFR circuitry stages 505, 510, and 515. The CFR circuitry stage 505 of the illustrated example includes example delay circuitry 520, example interpolation circuitry 525, example peak detection circuitry 530, example cancellation phasor calculation circuitry 535, example cancellation waveform generation circuitry 540, and example compensation circuitry 545. In the illustrated example, CFR circuitry stages 510 and 515 also include corresponding instances of example delay circuitry 520, example interpolation circuitry 525, example peak detection circuitry 530, example cancellation phasor calculation circuitry 535, example cancellation waveform generation circuitry 540, and example compensation circuitry 545. Although in the illustrated example, the example CFR circuitry stages 510 and 515 are not limited to the example delay circuitry 520, example interpolation circuitry 525, example peak detection circuitry 530, example cancellation phasor calculation circuitry 535, example cancellation waveform generation circuitry 540, and example compensation circuitry 545. Figure 5 Three CFR circuitry stages 505 , 510 , and 515 are shown in the example of , but CFR circuitry 402 may include fewer CFR circuitry stages (eg, only CFR circuitry stage 505 , or only CFR circuitry stages 505 and 510 ) or more CFR circuitry stages.

[0051] At a high level, the CFR circuit system 402 of the illustrated example implements PC-CFR. PC-CFR involves peak detection and peak removal. For example, the input signal envelope crossing above a peak limit commensurate with the PAR target value is monitored to detect the occurrence of a peak (also referred to as a crest) in the input signal envelope. A pre-stored peak removal waveform (PCW) is scaled based on peak attributes (e.g., position, amplitude, phase, etc.) and combined with the input signal (e.g., added, subtracted, etc.) to remove or otherwise reduce the detected peak. The CFR circuit system 402 of the illustrated example includes the plurality of CFR stages 505, 510, and 515 to progressively remove additional peaks detected after earlier stages of peak detection and peak removal. In addition, the CFR circuit system 402 of the illustrated example performs peak detection and peak removal using an oversampled PCW to support precise alignment of the CP with the detected peak. For example, waveform oversampling factors M=1, 2, 4, 8, etc. may be supported.

[0052] More specifically, in Figure 5 The example CFR circuit system 402 will have an interface sampling rate f int A complex baseband input signal x(n) at a corresponding data sampling rate is provided to the input of the interpolation circuit system 525. The interpolation circuit system 525 interpolates or, in other words, oversamples the input signal x(n) by an oversampling factor M (e.g., 1, 2, 4, or 8) to generate a complex baseband input signal x(n) at the output of the interpolation circuit system 525 having an oversampling rate f OS The complex baseband interpolated samples y(n′) are obtained by: intThe signal samples are of the same type, and the index n′ refers to the sample with oversampling rate f OS signal samples.

[0053] In the example shown, the output of the interpolation circuitry 525 is coupled to the input of the peak detection circuitry 530. The interpolated samples y(n′) are provided to the input of the peak detection circuitry 530, which calculates the envelope (e.g., magnitude) |y(n′)| of the complex baseband interpolated samples y(n′). 2 The peak detection circuitry 530 compares the envelope (eg, magnitude) |y(n′)| 2 and the peak threshold λ corresponding to the PAR target of the CFR circuit system 402 2 The peak detection circuit system 530 detects whether the peak value meets or exceeds the peak threshold value λ 2 One or more peaks and identifying the one or more peaks The corresponding one or more sample positions (eg, indices) τ in the complex baseband interpolated samples y(n′) i In the example shown, the peak detection circuitry 530 is capable of detecting a maximum of P peaks, such as P=6 or some other value. The peak detection circuitry 530 has an output for providing a peak Peak position τ i and the interpolated samples y i The value at the peak.

[0054] The output of the peak detection circuitry 530 is coupled to the input of the cancellation phasor calculation circuitry 535. Peak position τ i The value of the interpolated sample y at the peak is provided to the input of the cancellation phasor calculation circuit system 535. For a given peak value i, the cancellation phasor calculation circuit system 535 calculates the value of the peak value based on the peak value. and the sample value y corresponding to the peak i To calculate the elimination phasor Elimination phasor for a given peak value i With amplitude α i and Phase The cancellation phasor calculation circuitry 535 has an output for providing a cancellation phasor for the detected peak value i and the peak position τ i .

[0055] The output of the cancellation phasor calculation circuitry 535 is coupled to the input of the cancellation waveform generation circuitry 540. The cancellation phasor for the detected peak value i and the peak position τ iis provided to the input of the cancellation waveform generation circuitry 540. For a given detected peak i, the cancellation waveform generation circuitry 540 generates a peak position τ based on the peak position τ. i The stored samples of the pulse cancellation waveform are accessed to generate a cancellation pulse corresponding to the peak value i. The cancellation waveform generation circuit system 540 also uses the cancellation phasor for the peak value i The cancellation pulse for peak i is scaled to generate a scaled cancellation pulse corresponding to the peak i. The cancellation waveform generation circuit system 540 further combines (e.g., sums, adds, etc.) the corresponding scaled cancellation pulses determined for the detected peaks (e.g., a total of up to P peaks) to generate an overall pulse cancellation signal z(n), which can cancel or otherwise reduce the detected peaks (e.g., a total of up to P peaks) in the input signal. The cancellation waveform generation circuit system 540 has an output for providing the pulse cancellation signal z(n).

[0056] The output of cancellation waveform generation circuitry 540 is coupled to an input of compensation circuitry 545. Compensation circuitry 545 also has another input coupled to the output of delay circuitry 520. Delay circuitry 520 has an input for accepting a complex baseband input signal x(n). Delay circuitry 520 is configured to delay the complex baseband input signal x(n) by an amount of time to compensate for the length of the stored pulse cancellation waveform from its start position to its peak position, as well as the processing performed by interpolation circuitry 525, peak detection circuitry 530, cancellation phasor calculation circuitry 535, and cancellation waveform generation circuitry 540.

[0057] The output of delay circuitry 520 provides the delayed complex baseband input signal x(n) to one input of compensation circuitry 545. The output of cancellation waveform generation circuitry 540 provides the pulse cancellation signal z(n) to another input of compensation circuitry 545. Compensation circuitry 545 combines the delayed complex baseband input signal x(n) with the pulse cancellation signal z(n) (e.g., adds, subtracts, etc.) to produce an initial version of the modified signal r(n). In the example shown, subsequent CFR circuitry stages 510 and 515 sequentially re-process the initial version of the modified signal r(n) to output the modified signal r(n) 403 described above.

[0058] Figure 6 Show Figure 4 5 for removing peaks in an example input signal x(n). Figure 6An example input signal envelope 605 corresponding to an input signal x(n) is depicted. The input signal envelope 605 has an example peak value 610 detected by the peak detection circuitry 530 to exceed an example peak threshold value 615, as described above. The cancellation phasor calculation circuitry 535 and the cancellation waveform generation circuitry 540 generate an example scaled cancellation pulse z(n) having an example cancellation pulse envelope 620 capable of canceling or reducing the peak value 610, as described above. The compensation circuitry 545 combines the scaled cancellation pulse z(n) with the input signal x(n) to generate an example modified signal r(n) having an example modified signal envelope 625 in which the peak value 610 has been reduced to an example peak value 630 that satisfies (e.g., is less than or equal to) the peak threshold value 615.

[0059] Figure 7 is included in Figure 5 4 is a block diagram of an example implementation of cancellation waveform generation circuitry 540 in example CFR circuitry 402 of FIG. Figure 7 The elimination waveform generation circuit system 540 can be instantiated (e.g., create an instance, generate, materialize, implement, etc. for any length of time) by a programmable circuit system (e.g., a central processing unit (CPU)) executing a first instruction. In addition, Figure 7 The elimination waveform generation circuit system 540 may be instantiated (e.g., created as an instance, produced for any length of time, materialized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) or (ii) a field programmable gate array (FPGA), which is constructed or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. Therefore, Figure 7 Some or all of the circuitry may be instantiated at the same or different times. Figure 7 Some or all of the circuitry of can be instantiated, for example, in one or more threads that execute in parallel on hardware or in serial on hardware. In addition, in some examples, Figure 7 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions or FPGA circuitry performing operations to implement one or more virtual machines or containers.

[0060] Figure 7 The elimination waveform generation circuit system 540 includes an example elimination pulse generation circuit system 705, example scaling circuit systems 710-720, and an example summing circuit system 725. The example elimination pulse generation circuit system 705 has one or more inputs for coupling to the output of the phasor calculation circuit system 535 to receive oversampled time indices {τ1, τ2, ..., τ 1, τ2, ..., τ 2 ... PThe removal pulse generation circuitry 705 is capable of generating a maximum of P removal pulses corresponding to a maximum of P peaks detected in the current peak removal window of the input signal. For example, the limit on the number P of peaks that can be removed may be P=6 or some other value.

[0061] In the example shown, the current peak cancellation window utilized by the cancellation pulse generation circuitry 705 corresponds to the current sample index n of the input signal x(n). For example, the current peak cancellation window may be centered on the current sample index n of the input signal x(n). In the example shown, the peak cancellation window extends on both sides of the current sample index n and has a span corresponding to the number of equivalent interface rate samples of the stored PCW used by the cancellation pulse generation circuitry 705 to generate its output cancellation pulses. For example, if the number of sampled samples of the PCW stored in the memory is N and the oversampling factor of the interpolation circuitry 525 is M, then the number of equivalent interface rate samples of the stored PCW is N / M.

[0062] In the example shown, the cancellation pulse generation circuit system 705 has a set of outputs for providing cancellation pulses corresponding to peaks detected in the sampled (e.g., interpolated) input signal samples y(n′). For example, the cancellation pulse generation circuit system 705 reads one or more (≤P) samples {h(m1), h(m2), ..., h(m′) from the PCW storage memory. P )}, where h(·) represents the stored PCW, and indexes m1, m2, …, m P represents a corresponding index sequence corresponding to the corresponding one or more (≤P) cancellation pulses generated by the cancellation pulse generation circuit system 705. The cancellation pulse generation circuit system 705 generates a corresponding index sequence corresponding to the corresponding one or more (≤P) cancellation pulses generated by the cancellation pulse generation circuit system 705 based on the peak position time index {τ1, τ2, ..., τ P} and the current sample index n to determine the elimination pulses h(m1), h(m2), ..., h(m P ) with indices m1, m2, ..., m P In the example shown, the elimination pulse generation circuit system 705 can read out the PCW storage memory in parallel with arbitrary indexes {m1(n), m2(n), . . . , m P In addition, the elimination pulse generation circuitry 705 may change the memory index when a previously detected peak leaves the peak elimination window, when a new peak is detected in the peak elimination window, and at other times.

[0063] The scaling circuitry 710-720 has a set of inputs for coupling to the set of outputs of the cancellation pulse generation circuitry 705 to receive the one or more (≤P) samples {h(m1), h(m2), ..., h(m P The scaling circuit system 710-720 also has another set of inputs for coupling to the output of the elimination phasor calculation circuit system 535 to receive the one or more elimination phasors calculated by the elimination phasor calculation circuit system 535 for the one or more elimination pulses. The cancellation phasor calculation circuit system 535 is used to calculate one or more cancellation phasors in response to the Scaling the one or more (≤P) samples {h(m1), h(m2), ..., h(m P )} (e.g., multiplying them) to determine the time index {τ1, τ2, …, τ P The scaling circuit system 710-720 has a set of outputs for providing the one or more (≤P) samples {h(m1), h(m2), ..., h(m) corresponding to the one or more cancellation pulses. P )}.

[0064] The summing circuit system 725 has a set of inputs for coupling to the set of outputs of the scaling circuit systems 710-720 to receive the time indexes {τ1, τ2, ..., τ P} of the one or more (≤P) samples {h(m1), h(m2), ..., h(m P )}. The summing circuit system 725 performs summing on the one or more (≤P) samples {h(m1), h(m2), ..., h(m P )} are summed or otherwise combined to generate an overall pulse-canceled signal sample z(n). The summing circuitry 725 has an output for providing an overall pulse-canceled signal sample z(n), which is added or otherwise combined with the delayed baseband input sample x(n) by the compensation circuitry 545, as described above.

[0065] Figure 8 is included in Figure 7 0066] A block diagram of a first example implementation of a cancellation pulse generation circuit system 705 in the cancellation waveform generation circuit system 540 of FIG. Figure 8The elimination pulse generation circuit system 705 can be instantiated (e.g., create an instance, generate, materialize, implement, etc. for any length of time) by a programmable circuit system (e.g., a central processing unit (CPU)) executing a first instruction. In addition, Figure 8 The elimination pulse generation circuit system 705 may be instantiated (e.g., created as an instance, generated for any length of time, materialized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) or (ii) a field programmable gate array (FPGA), which is constructed or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. Therefore, Figure 8 Some or all of the circuitry may be instantiated at the same or different times. Figure 8 Some or all of the circuitry of can be instantiated, for example, in one or more threads that execute in parallel on hardware or in serial on hardware. In addition, in some examples, Figure 8 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions or FPGA circuitry performing operations to implement one or more virtual machines or containers.

[0066] Figure 8 The erasure pulse generation circuit system 705 includes one or more instances of an example erasure pulse readout circuit system 805 and an example erasure pulse (CP) index generation circuit system 810-820. The erasure pulse readout circuit system 805 includes one or more example CP memories 824-834. Figure 8 In the example of , the number of instances of CP index generation circuit systems 810-820 and the number of CP memories 824-834 corresponds to the maximum number P of elimination pulses that can be generated by the elimination pulse generation circuit system 705 at a given time, corresponding to the maximum number P of peaks that can be eliminated simultaneously.

[0067] In order to support the parallel generation of up to P erasure pulses h(m1), h(m2), ..., h(m P), the cancellation pulse readout circuit system 805 includes P CP memories 824-834 (e.g., P=6 or some other value), each dedicated to generating a different one of the maximum P possible cancellation pulses. In addition, each of the CP memories 824-834 stores a separate complete copy of the reference PCW having N samples, as described above. Therefore, each of the CP memories 824-834 is sized to store at least N data samples, corresponding to the complete sampled size of the reference PCW. For example, assume that 24 bits are used to represent the in-phase component (I) and the orthogonal component (Q) of each complex data sample of the reference PCW, and the reference PCW includes N=4096 samples. Then, each of the CP memories 824-834 requires a storage capacity of at least 12 kilobytes (KB) (corresponding to ((4096*24) / 8) / 1024). Furthermore, if the generation of a maximum of P=6 elimination pulses is to be supported, and there are three (3) CFR circuit system levels and four (4) transmission paths to be supported, then the total PCW memory storage capacity required for the elimination pulse readout circuit system 805 is 864 kB (corresponding to 12*6*3*4).

[0068] exist Figure 8 In the example shown, each of the CP memories 824-834 is paired with a corresponding instance of the index generation circuit system 810-820 so that the CP memories 824-834 can be accessed in parallel. In addition, the i-th instance of the pair of index generation circuit systems 810-820 and its corresponding i-th memory 824-834 are responsible for generating the i-th elimination pulse h(m) of the i-th peak to be eliminated. i ). More specifically, for a current input sample index n of the input signal x(n) 401, the i-th CP index generation circuit system 810-820 calculates a corresponding memory index m corresponding to a sample of the PCW to be read out from its corresponding CP memory 824-834. i (n) to generate the i-th elimination pulse h(m i ). In the example shown, the i-th CP index generation circuit system 810-820 generates the memory index m using Equation 1 i (n) to access the elimination pulse sample h(m) from its corresponding CP memory 824-834 i ), Equation 1 is:

[0069] m i (n) = M*n-τ i Equation 1

[0070] In Equation 1, M is the oversampling factor, τ iis the time index of the detected peak (at the oversampling rate), Δ is the group delay of the PCW (at the oversampling rate), n is the current input sample time index, and i ranges from 1 to P possible pulses that can be eliminated. (In some examples, Equation 1 can be modified to take into account implementation-dependent delays.) Thus, instances of index generation circuitry 810-820 have respective inputs for accepting respective passed sample position time indices {τ1, τ2, ..., τ2} corresponding to the positions of the one or more peaks (up to P) where the elimination pulses are to be generated. P The respective instances of the index generation circuit systems 810-820 generate the respective sample indices m1, m2, ..., m of the stored PCWh(·) to be read out using Equation 1. P , based on the peak position time index {τ1,τ2,…,τ P} Generate corresponding elimination pulses h(m1), h(m2), ..., h(m P ). The respective instances of the index generation circuit systems 810-820 have outputs for using the sample indices m1, m2, ..., m generated by them. P accesses their corresponding paired CP memories 824-834 so that the memories output corresponding erasure pulses h(m1), h(m2), ..., h(m P ), as shown. Therefore, each pair of the i-th CP index generation circuit system 810-820 and the corresponding i-th CP memory 824-834 is used to generate the i-th elimination pulse to eliminate or reduce the position time index τ i The i-th peak at .

[0071] Fig. 9 is included in Figure 7 FIG. 5 is a block diagram of a second example implementation of a cancellation pulse generation circuit system 705 in the example cancellation waveform generation circuit system 540 of FIG. Fig. 9 The elimination pulse generation circuit system 705 can be instantiated (e.g., create an instance, generate, materialize, implement, etc. for any length of time) by a programmable circuit system (e.g., a central processing unit (CPU)) executing a first instruction. In addition, Fig. 9 The elimination pulse generation circuit system 705 may be instantiated (e.g., created as an instance, generated for any length of time, materialized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) or (ii) a field programmable gate array (FPGA), which is constructed or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. Therefore, Fig. 9 Some or all of the circuitry may be instantiated at the same or different times. Fig. 9Some or all of the circuitry of can be instantiated, for example, in one or more threads that execute in parallel on hardware or in serial on hardware. In addition, in some examples, Fig. 9 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions or FPGA circuitry performing operations to implement one or more virtual machines or containers.

[0072] Fig. 9 The elimination pulse generation circuit system 705 includes the above-mentioned Figure 8 The CP index generation circuit system 810-820. Therefore, as described above in conjunction with Figure 8 As described, the CP index generation circuitry 810-820 generates up to P corresponding sample indices m1, m2, ..., m P , for identifying a maximum of P PCW samples to be read from the memory to generate a maximum of P corresponding cancellation pulses h(m1), h(m2), ..., h(m P As further described above, the CP index generation circuitry 810-820 generates up to P corresponding sample indices m1, m2, ..., m based on Equation 1. P .

[0073] However, unlike the Figure 8 Compared with the erasure pulse generating circuit system 705 and the erasure pulse reading circuit system 805, Fig. 9 The elimination pulse generation circuit system 705 includes an example elimination pulse readout circuit system 905 that implements a crest factor reduction architecture that uses a portion of the memory and may have an associated reduced area and power consumption. To implement this architecture, Fig. 9 The example elimination pulse readout circuit system 905 includes example CP memories 924-934, which are also referred to as example CP subset memories 924-934, relative to Figure 8 CP memories 824-834 in the cancellation pulse readout circuitry 805 have a reduced memory footprint. In some examples, one or more of the CP subset memories 924-934 are included in the transmitter circuitry 110 but are implemented externally relative to the CFR circuitry 402 and the cancellation pulse readout circuitry 905. Fig. 9 The eliminate pulse readout circuit system 905 further includes an example CP memory access controller circuit system 940 , an example CP memory output circuit system 945 , an example buffer circuit system 950 , and an example CP generation control circuit system 955 .

[0074] At a high level, to achieve a reduced memory footprint, the elimination pulse readout circuitry 905 operates as follows. In the elimination pulse readout circuitry 905, the CP subset memories 924-934 collectively store a single instance of a reference PCW, where the N data samples of the single reference PCW are split across P CP subset memories 924-934 such that each subset memory stores N / P samples of the reference PCW. To enable the P CP subset memories 924-934 to be accessed in parallel (e.g., in input sample instance n, in the same read clock interval, etc.), the CP memory access controller circuitry 940 indexes up to P different PCW samples {m1, m2, ..., m2} corresponding to the maximum P elimination pulses to be generated. P} into a set of transformed up to P subset memory indices {k1, k2, ..., k P}, where each transformed index k1, k2, ..., k P The CP memory output circuitry 945 converts the memory index {k1, k2, ..., k P The maximum P outputs {h(k1), h(k2), ..., h(k P )} and provides the reordered CP subset memory output to the buffer circuitry 950. The buffer circuitry 950 includes P different first-in-first-out (FIFO) buffers, each corresponding to a different generated cancellation pulse, such that the FIFO buffers output (after appropriate delays, as described below) the respective cancellation pulse samples {h(m1), h(m2), ..., h(m3)} for the up to P cancellation pulses to be generated. P )}. Based on the current input sample index n, the CP generation control circuit system 955 controls the index transformation performed by the CP memory access controller circuit system 940, the output sample reordering performed by the CP memory output circuit system 945, and the delay configured for the FIFO in the buffer circuit system 950.

[0075] As mentioned above, multiple peaks may be detected within the peak cancellation window. To generate a cancellation pulse for each peak, the cancellation pulse readout circuitry 905 is capable of reading out P different arbitrary sample indices of the reference PCW in parallel. The reference PCW contains samples at the sampling rate, but the cancellation pulses are generated at the interface rate and with possibly different sampling phase offsets. In addition, the cancellation pulse readout circuitry 905 operates with deterministic delays so that when a new peak is detected within the peak cancellation window, a corresponding cancellation pulse is generated with an appropriate fixed delay.

[0076] exist Figure 8In the elimination pulse readout circuit system 805, P instances of dedicated CP memories 824-834, each having a size to store N data samples, are used to store identical copies of the reference PCW. The arrangement allows the elimination pulse readout circuit system 805 to index each memory independently. In contrast, Fig. 9 The pulse-elimination readout circuitry 905 partitions the N samples of a single reference PCW into P instances of CP subset memories 924-934, each sized to store only N / P data samples, resulting in a reduction in memory area / footprint by a factor of P. However, without proper partitioning, it may not be possible to access P different arbitrary sample indices of the reference PCW from the CP subset memories 924-934 in parallel, since some necessary samples may already be stored in the same subset memory 924-934.

[0077] Fig. 10A An example partitioning 1000 of samples of a single reference PCW across CP subset memories 924-934 is shown. The example partitioning 1000 is based on the fact that as the sample index n of the input x(n) increases, the PCW sample index m corresponding to the i-th cancellation pulse of the i-th peak increases. i The oversampling factor M is increased. Based on the fact, the partitioning 1000 causes the N words of the reference PCW to be partitioned for storage in the P subset memories 924-934 so that each subset of M rows holds consecutive samples of the reference PCW due to the oversampling rate M. In addition, the PCW sample indexes are separated by a value of M across the P subset memories 924-934. Fig. 10A The example segmentation 1000 shown in FIG. 1 is an example implementation for an oversampling factor M=4 and a maximum number of peaks P=6.

[0078] In other words, Fig. 10A In the example partitioning 1000 of FIG. 1 , respective CP subset memories 924-934 store respective example subsets 1004-1014 of data samples of a single reference PCW, wherein different CP subset memories 924-934 store different subsets of data samples. For example, the first CP subset memory 924 stores an example first subset 1004 of data samples of a single reference PCW, wherein the first subset 1004 includes an example subset 1024 and an example subset 1026. Similarly, the second CP subset memory 926 stores an example second subset 1006 of data samples of a single reference PCW, wherein the second subset 1006 includes an example subset 1034 and an example subset 1036, and the subsets 1034 and 1036 are different from the subsets 1024 and 1026.

[0079] In addition, the data sample subsets stored in a given CP subset memory 924-934 include a number of consecutive data samples corresponding to a single reference PCW with an oversampling factor of M. For example, each of the first subsets 1004 stored in the first CP subset memory 924 includes a number of consecutive data samples corresponding to a single reference PCW with an oversampling factor of M=4. For example, subset 1024 includes M=4 consecutive data samples of the reference PCW h(0), h(1), h(2), and h(3), subset 1026 includes M=4 consecutive data samples of the reference PCW h(24), h(25), h(26), and h(27), and so on. Similarly, each of the second subsets 1006 stored in the second CP subset memory 926 includes a number of consecutive data samples corresponding to a single reference PCW with an oversampling factor of M=4. For example, subset 1034 contains M=4 consecutive data samples h(4), h(5), h(6) and h(7) of the reference PCW, subset 1036 contains M=4 consecutive data samples h(28), h(29), h(30) and h(37) of the reference PCW, and so on.

[0080] In addition, adjacent data sample subsets stored in a given CP subset memory 924-934 are separated by a number of consecutive data samples of a single reference PCW corresponding to the product of the oversampling factor M and the total number of output cancellation pulses P that the cancellation pulse generation circuit system 705 is capable of generating. For example, adjacent subsets in the first subset 1004 stored in the first CP subset memory 924 are separated by a number of consecutive data samples of a single reference PCW corresponding to a function (e.g., product) of the oversampling factor M=4 and the total number of output cancellation pulses P=6 that the cancellation pulse generation circuit system 705 is capable of generating, such as 4*6=24 samples in the illustrated example. For example, data samples h(0), h(1), h(2), and h(3) of an initial subset 1024 in the first subset 1004 are separated from data samples h(24), h(25), h(26), and h(27) of the next adjacent subset 1026 of the first subset 1004 by 4*6=24 consecutive samples. Similarly, adjacent subsets in the second subset 1006 stored in the second CP subset memory 926 are separated by a number of consecutive data samples of a single reference PCW corresponding to a function (e.g., product) of the oversampling factor M=4 and the total number of output cancellation pulses P=6 that the elimination pulse generation circuit system 705 is capable of generating, such as 4*6=24 samples in the illustrated example. For example, data samples h(4), h(5), h(6), and h(7) of the initial subset 1034 in the second subset 1006 are separated from data samples h(28), h(29), h(30), and h(31) of the next adjacent subset 1036 in the second subset 1006 by 4*6=24 consecutive samples.

[0081] In addition, corresponding data sample subsets in adjacent accessors in the CP subset memories 924-934 are separated by a number of consecutive data samples of a single reference PCW corresponding to the oversampling factor M. For example, data samples h(0), h(1), h(2), and h(3) of subset 1024 in the first subset 1004 are separated by M=4 consecutive data samples from corresponding data samples h(4), h(5), h(6), and h(7) of subset 1034 in the second subset 1006. Similarly, data samples h(24), h(25), h(26), and h(27) of subset 1026 in the first subset 1004 are separated by M=4 consecutive data samples from corresponding data samples h(28), h(29), h(30), and h(31) of subset 1036 in the second subset 1006. In addition, subset 1034 in the second subset 1006 contains data samples of a single reference PCW starting from a sample index (e.g., n′=4 in the illustrated example) corresponding to an oversampling factor M (e.g., M=4). In the illustrated example, one of the CP subset memories 924-934 is considered adjacent to another of the CP subset memories 924-934 if the consecutive data sample subsets they store satisfy the aforementioned characteristics regardless of their physical circuit locations. In some examples, the CP subset memories 924-934 are labeled with memory identifiers such that adjacent subset memories have consecutive (e.g., separated by a value of one) memory identifiers. For example, in Fig. 10A , the CP subset memories 924-934 are labeled with corresponding memory identifiers 1, 2, 3, etc., such that subset memories having identifiers that differ by a value of one are adjacent.

[0082] Because the data samples of a single reference PCW stored in the CP subset memories 924-934 are oversampled by an oversampling factor M=4, for a reference PCW with a position time index τ i For a given peak value of , only one sample index of the M phases corresponding to a single reference PCW will be selected by the corresponding CP index generation circuit system 810-820 to generate a cancellation pulse for the peak value. i For a given peak output cancellation pulse, successive data samples of the PCW will be read from the successors of the CP subset memories 924-934 until the Pth CP subset memory is read, after which data samples will begin to be read from the next subset of data samples in the first CP subset memory, and so on. The CP memory access controller circuit system 940 takes advantage of this feature to index up to P different PCW samples {m1, m2, ..., m3} corresponding to the maximum P cancellation pulses to be generated. P} into a set of new P subset memory indices (also called subset memory sample indices) {k1, k2, …, k P}, so that the corresponding PCW data samples {h(k1),h(k2),…,h(k P )} is accessed from different ones of the CP subset memories 924-934 based on those subset memory indices, where k1 is the index of the first CP subset memory 924, k2 is the index of the second CP subset memory 926, and so on, where k P is the index of the Pth CP subset memory 934.

[0083] Here are two example algorithms, Fig. 9 The cancellation pulse readout circuitry 905 is implemented to read out PCW data samples from the CP subset memories 924-934 in parallel, thereby generating up to P cancellation pulses to cancel or reduce up to P peaks or crests in the input signal x(n).

[0084] The first example algorithm implemented by the elimination pulse readout circuit system 905 reads out the individual (single) PCW samples of each of the maximum P elimination pulses in parallel from the CP subset memories 924-934. The first example algorithm starts after the peak detection circuit system 530 detects a first peak in the input signal x(n). As described above, the first CP index generation circuit system 810 generates a first CP index based on equation 1 and the position time index τ of the peak. i As described above, the PCW sample index m1(n) identifies the first sample h(m1(n)) of the reference PCW to be read from the memory to generate the corresponding elimination pulse of the first peak.

[0085] The first CP index generation circuitry 810 provides the PCW sample index m1(n) to the CP memory access controller circuitry 940, as shown in FIG. Fig. 9 As shown. Because the PCW sample index m1(n) corresponds to the first detected peak, the CP subset memories 924-934 are not currently accessed. Therefore, the CP memory access controller circuit system 940 sets the first CP subset memory index k1(n) of the first CP subset memory 924 based on the access requirement of the generated sample index m1(n), which is used to access the initial data sample of the reference PCW that starts generating the elimination pulse corresponding to this first detected peak. For example, the CP memory access controller circuit system 940 uses Equation 2 to transform the generated sample index m1(n) into the first CP subset memory k1(n), which is:

[0086]

[0087] In Equation 2, f is the polyphase index of the current peak, which can have a value in the range of 0 to M-1, and is a floor operator. Thus, the first CP subset memory k1(n) corresponding to the generated sample index m1(n) will point to one of the multiple phases of the first subset 1024 of data samples stored in the first CP subset memory 924, because those data samples correspond to the beginning of the reference PCW. In addition, the CP generation control circuitry 955 will buffer the first FIFO in the buffer circuitry 950 (at Fig. 9 The readout delay δ1 of the buffer circuit system 950 (labeled as FIFO1 in the figure) is set to δ1=P to set the baseline delay of the buffer circuit system 950 equal to the maximum number P of erasure pulses that the erasure pulse readout circuit system 905 can generate.

[0088] For subsequent input sample indices (n+1), (n+2), ... and so on, the CP memory access controller circuitry 940 sets the CP subset memory index for subsequent CP subset memories 926-934 to be accessed to obtain subsequent data samples of the reference PCW to be used to generate the elimination pulse corresponding to this first detected peak. For example, the CP memory access controller circuitry 940 sets k2(n+1)=k1(n) to access the second CP subset memory 926 at the next sample index (n+1), sets k3(n+2)=k1(n) to access the third CP subset memory 928 at the subsequent sample index (n+2), and so on. Therefore, each successive data sample of the reference PCW will be due to Fig. 10A The CP memory output circuitry 945 writes the accessed data samples to the FIFO1 buffer of the buffer circuitry 950. The FIFO1 buffer of the buffer circuitry 950 will output the PCW samples {h(m1(n)), h(m1(n+1)), ...} corresponding to the first eliminated pulse of the first detected peak based on the configured delay δ1=P.

[0089] Next, assume that the peak detection circuit system 530 detects a second peak in the input signal x(n). After detecting the second peak, the CP memory access controller circuit system 940 performs a check to determine whether the current sample index m1(n) of the first peak and the new index m2(n) determined by the CP index generation circuit system 810 for the second peak will point to a data sample in the first CP subset memory 924 (because the new index m2(n) will initially point to one of the multiple phases of the first subset 1024 of data samples stored in the first CP subset memory 924). If not, then the CP memory access controller circuit system 940 sets the first CP subset memory index k1(n) of the first CP subset memory 924 based on the access requirements of the generated sample index m2(n), which is used to access the initial data sample of the reference PCW that starts generating the elimination pulse corresponding to this second detected peak. For example, the CP memory access controller circuit system 940 uses Equation 2 above to transform the generated sample index m2(n) into the first CP subset memory index k1(n). In addition, the CP generation control circuit system 955 sets the second FIFO (in Fig. 9 The readout delay δ2 of the buffer circuit system 950 (labeled as FIFO2) is set to δ2=P, corresponding to the baseline delay of the buffer circuit system 950.

[0090] Because the current sample index m1(n) of the first peak and the new index m2(n) of the second peak point to different CP subset memories 924-934 in this case, the CP memory access controller circuit system 940 can access the reference PCW samples of the first peak and the second peak in parallel from different ones of the CP subset memories 924-934. For subsequent input sample indexes (n+1), (n+2), ... and so on, the CP memory access controller circuit system 940 sets the CP subset memory index of the subsequent CP subset memory 926-934 to be accessed to obtain the subsequent data samples of the reference PCW to be used to generate the elimination pulse corresponding to this second detected peak, as described above. For example, the CP memory access controller circuit system 940 sets k2(n+1)=k1(n) to access the second CP subset memory 926 at the next sample index (n+1), sets k3(n+2)=k1(n) to access the third CP subset memory 928 at the subsequent sample index (n+2), and so on. Therefore, each successive data sample referenced to the PCW will be Fig. 10AThe storage arrangement shown is accessed by the next adjacent CP subset memory 924-934 and restored to the CP subset memory 924 after the last CP subset memory 934 is accessed. In addition, for a given next sample index, the CP subset memory 924-934 accessed to obtain the data samples of the reference PCW of the second peak will always be different from the CP subset memory 924-934 accessed to obtain the data samples of the reference PCW of the first peak, and thus the samples of these two peaks can be accessed in parallel. The CP memory output circuit system 945 writes the data samples accessed for the second peak to the FIFO2 buffer of the buffer circuit system 950. The FIFO2 buffer of the buffer circuit system 950 will output the PCW samples {h(m2(n)),h(m2(n+1)),…} of the second elimination pulse corresponding to the second detected peak based on the configured delay δ2=P.

[0091] However, if both the current sample index m1(n) and the new index m2(n) of the first peak will access the first CP subset memory 924, then the CP memory access controller circuit system 940 delays access to the first CP subset memory 924 for the second peak. The CP memory access controller circuit system 940 achieves this by setting the first CP subset memory index k1(n+1) for the next time index based on m2(n) and using Equation 2. This delays access to the PCW sample of the second peak by one input signal sample. In addition, the CP generation control circuit system 955 sets the readout delay δ2 of FIFO2 in the buffer circuit system 950 to δ2=P-1 (which is one input time index less than the baseline delay of the buffer circuit system 950) to compensate for the one sample readout delay introduced by the CP memory access controller circuit system 940.

[0092] In this case, at the next increment of the time index of the input signal, the first CP subset memory index k1(n+1) of the second peak elimination pulse will point to the data sample in the first subset 1024 of the first CP subset memory 924, while the first peak elimination pulse will point to the data sample in the second CP subset memory 926. Therefore, the CP memory access controller circuit system 940 can access the two different samples from the two different CP subset memories 924-926 in parallel. In addition, the memory access controller circuit system 940 can continue to access different samples of the first and second elimination pulses from the two different CP subset memories 924-934 in parallel for each consecutive input time index n. In addition, the CP memory output circuit system 945 writes the data sample accessed for the second elimination pulse to the FIFO2 buffer of the buffer circuit system 950, as described above. In this case, the FIFO2 buffer of the buffer circuitry 950 will output PCW samples {h(m2(n)), h(m2(n+1)), ...} corresponding to the second cancellation pulse of the second detected peak based on the configured delay δ2=P-1.

[0093] Next, assume that the elimination pulse readout circuit system 905 is generating the (i-1) active peaks in the peak elimination window, and the peak detection circuit system 530 detects the i-th peak in the input signal x(n). After detecting the i-th peak, the CP memory access controller circuit system 940 performs a check to determine whether any of the previous peaks accessed the first subset memory 924. This is because the new index m determined by the i-th instance of the CP index generation circuit system 810-820 for the i-th peak i (n) will first point to one of the multiple phases of the first subset 1024 of data samples stored in the first CP subset memory 924. If not, the CP memory access controller circuitry 940 generates a sample index m based on the generated sample index m. i The first CP subset memory index k1(n) of the first CP subset memory 924 is set according to the access request of the CP memory access controller circuit system 940, which is used to access the initial data sample of the reference PCW for starting to generate the elimination pulse corresponding to the i-th detected peak. For example, the CP memory access controller circuit system 940 uses the above equation 2 to convert the generated sample index m i (n) is transformed into the first CP subset memory index k1 (n). In addition, the CP generation control circuitry 955 sets the readout delay δi of the i-th FIFO in the buffer circuitry 950 to δi=P, corresponding to the baseline delay of the buffer circuitry 950.

[0094] In this case, the indices for accessing PCW samples for different peaks all point to different CP subset memories 924-934. Thus, the CP memory access controller circuitry 940 can access the reference PCW samples for the initial peak in parallel from different ones of the CP subset memories 924-934. For subsequent input sample indices (n+1), (n+2), ... and so on, the CP memory access controller circuitry 940 sets the CP subset memory indices of subsequent CP subset memories 926-934 as described above to access subsequent data samples of the reference PCW to be used to generate the i-th cancellation pulse corresponding to the i-th detected peak. Thus, for a new i-th peak, each successive data sample of the reference PCW will be due to Fig. 10A The CP subset memory 924-934 is accessed from the next adjacent CP subset memory 924-934 according to the storage arrangement shown, and restored to the CP subset memory 924 after the last CP subset memory 934 is accessed. In addition, for a given next sample index, the CP subset memory 924-934 accessed to obtain the data samples of the reference PCW of the i-th peak will always be different from the CP subset memory 924-934 accessed to obtain the data samples of the reference PCW of the other (i-1) peaks, and therefore the samples of all peaks can be accessed in parallel. The CP memory output circuit system 945 writes the data samples accessed for the i-th peak to the i-th FIFO buffer of the buffer circuit system 950. The i-th FIFO buffer of the buffer circuit system 950 will output the PCW sample {h(m ) of the i-th cancellation pulse corresponding to the i-th detected peak based on the configured delay δi=P. i (n)),h(m i (n+1)),…}.

[0095] However, if one of the indices of the other (i-1) existing peaks is to access the first subset memory 924, then the CP memory access controller circuitry 940 calculates the maximum number of subsequent samples, represented as a variable L, during which the first subset memory 924 will be accessed consecutively for the existing (i-1) peaks. The CP memory access controller circuitry 940 then calculates the maximum number of subsequent samples, represented as a variable L, during which the first subset memory 924 will be accessed consecutively for the existing (i-1) peaks. i (n) and sets the first CP subset memory sample index k1 after L sample indices, i.e., k1(n+L), using Equation 2. This delays the access of the new PCW sample of the i-th detected peak by L input signal samples. In addition, the CP generation control circuit system 955 sets the readout delay δi of the i-th FIFO buffer in the buffer circuit system 950 to δi=PL to compensate for the L sample readout delay introduced by the CP memory access controller circuit system 940.

[0096] In this case, at the Lth increment of the time index of the input signal, the first CP subset memory index k1(n+L) will point to the data samples in the first subset 1024 of the first CP subset memory 924, while the elimination pulses of the other peaks will point to the data samples of different ones of the CP subset memories 926-934 other than the first CP subset memory 924. Therefore, the CP memory access controller circuit system 940 can access different samples from different CP subset memories 924-934 in parallel. In addition, the memory access controller circuit system 940 can continue to access different samples of i different elimination pulses from different ones of the CP subset memories 924-934 in parallel for each consecutive input time index n. In addition, the CP memory output circuit system 945 writes the data sample accessed for the i-th elimination pulse to the i-th FIFO buffer of the buffer circuit system 950, as described above. In this case, the i-th FIFO buffer of the buffer circuitry 950 will output the PCW sample {h(m i (n)),h(m i (n+1)),…}.

[0097] It should be noted that when a new peak is detected, no more than (P-1) erasure pulses will be currently being generated by the erasure pulse readout circuitry 905. The example first algorithm described above ensures that different erasure pulses are mapped to different subset memories for all sample indices n.

[0098] In the example shown, the CP generation control circuit system 955 provides the CP memory output circuit system 945 with information describing the reordering of the output samples of the CP subset memory {h(k1), h(k2), ..., h(kP)} to be applied to the current sample index so that the output samples are provided to the correct FIFO. The CP memory output circuit system 945 writes the reference PCW data samples output from the CP subset memory to the corresponding FIFO of the buffer circuit system 950. Based on the delay configured as described above, a maximum of P sample instances can pass to generate the elimination pulse of the most recently detected peak. Therefore, the FIFO is used to generate the P sample delays so that the elimination pulse output is time-aligned even in the worst case and has a deterministic latency. The delay of the i-th FIFO is programmed by the CP generation control circuit system 955 as δ i , as described above, so that the FIFOs generate the expected set of cancellation pulses {h(m1), h(m2), ..., h(m P )}.

[0099] Fig. 10B Shown included in Fig. 9 Example operation 1050 of the erasure pulse readout circuit system 905 in the erasure pulse generation circuit system 705. In example operation 1050, the erasure pulse readout circuit system 905 implements the first example algorithm described above to access the Fig. 10A 1000 of the example partition CP subset memory 924-934. Therefore, the example operation 1050 corresponds to an oversampling factor M=4 and a maximum number of simultaneous peak elimination pulses P=6. In addition, based on Fig. 10A The PCW samples are stored in P=6 CP subset memories 924-934 in the partition 1000. In addition, k1(n), k2(n), ..k6(n) are corresponding transformed CP subset memory indexes 1052 for accessing the corresponding CP subset memories 924-934, and the memory values ​​read out from the CP subset memories 924-934 are stored in the FIFO of the buffer circuit system 950, as described above.

[0100] As described above, when the peak detection circuitry 530 detects a peak in the input signal x(n), the CP index generation circuitry 810-820 generates a PCW sample index corresponding to the peak based on the phase of the peak (e.g., 0, 1, 2, or 3 when the oversampling factor M=4 in this example). Fig. 10B In the example shown, the peak detection circuitry 530 detects a first example peak 1054 with polyphase 0. The first CP index generation circuitry 810 generates an example PCW sample index 1056 for the first peak as m1(n)=0,4,8,12,16,… According to the first example algorithm described above, because this is the first detected peak, the CP generation control circuitry 955 sets the first FIFO (in the buffer circuitry 950) to Fig. 10B The delay of FIFO1 in the figure is set to δ1=P=6 (corresponding to Fig. 10B In addition, since there are no other peaks to be serviced, there is no contention for accessing the CP subset memories 924-934 at this time.

[0101] Continuing with the first peak, at the first sample instance when m1(n)=0, the CP memory access controller circuit system 940 executes the first example algorithm described above and assigns k1=0 and accesses the 0th position of the first CP subset memory 924, causing the CP memory output circuit system 945 to read out the PCW sample h(0). In the next sample instance, the CP memory access controller circuit system 940 accesses the 0th position of the second CP subset memory 926 by setting k2=0 (which corresponds to the PCW sample index m1(n)=4). When m1(n)=24 (corresponding to the PCW sample h(24)), this operation continues after P=6 clock cycles, and the first CP subset memory 924 is accessed again.

[0102] When the peak detection circuitry 530 detects a new peak, the CP memory access controller circuitry 940 performs a check according to the first example algorithm described above to determine whether the first CP subset memory 924 is available and can read out PCW samples for this new peak without contention with the previous peak. Fig. 10B In operation 1050, the peak detection circuit system 530 detects a second example peak 1060 with a multi-phase of 1. The second CP index generation circuit system 815 generates an example PCW sample index 1062 for the second peak as m2(n)=1, 5, 9, 13, 17, ... According to the first example algorithm described above, the CP memory access controller circuit system 940 will have no contention for accessing h(1) from the first CP subset memory 924 because a different CP subset memory (e.g., the fifth memory 932) is accessed for the first peak. Therefore, the CP memory access controller circuit system 940 assigns k1=1 and accesses the first position of the first CP subset memory 924, causing the CP memory output circuit system 945 to read out the PCW sample h(1). In addition, the CP generation control circuit system 955 allocates the second FIFO (in the buffer circuit system 950) in the buffer circuit system 950. Fig. 10B The delay of FIFO2 in the figure is set to δ2=P=6 (corresponding to Fig. 10B 1064 in the figure).

[0103] However, if the first CP subset memory 924 is not available, as in Fig. 10B In the event that the third example peak 1066 is detected in the example operation 1050, the CP memory access controller circuitry 940 calculates the maximum number of subsequent samples, represented as a variable L, during which the first subset memory 924 will be accessed continuously. Fig. 10BIn the example of , the first CP subset memory 924 will access a sample index of the second peak at time index n=12. Therefore, the CP memory access controller circuit system 940 determines L=1, so that the access of the PCW sample of the third peak 1066 is delayed by one input sample time, as described above. Therefore, the CP generation control circuit system 955 will buffer the third FIFO in the circuit system 950 (at Fig. 10B The delay of FIFO3 in the figure is set to δ3=P-1=5 (corresponding to Fig. 10B 1068 in the figure).

[0104] The second example algorithm implemented by the erasure pulse readout circuit system 905 reads out multiple PCW samples of a single erasure pulse in parallel from the CP subset memories 924-934. In the second example algorithm, for a given input sample index n, the CP memory access controller circuit system 940 uses equation 2 above based on the initial sample index m generated for the i-th peak by the i-th instance of the CP index generation circuit system 810-820 i (n) and determine the CP subset memory index k corresponding to the i-th eliminated pulse of the i-th detected peak i (n), as described above. Next, the CP memory access controller circuitry 940 accesses the CP subset memories 924-934 in parallel to obtain P consecutive PCW samples {h(k i ),h(k i +M),…,h(k i +PM-M)}. Then, the CP memory output circuitry 945 stores the accessed reference PCW sample {h(k i ),h(k i +M),…,h(k i +PM-M)} is written from the CP subset memory 924-934 to the i-th FIFO of the buffer circuit system 950.

[0105] At the next sample index n+1, the CP memory access controller circuitry 940 uses the same process to access P consecutive PCW samples corresponding to the (i+1)th eliminated pulse of the (i+1)th detected peak from the CP subset memories 924-934 in parallel. The CP memory output circuitry 945 then stores the accessed reference PCW samples {h(k i+1 ),h(k i+1 +M),…,h(k i+1The vector of (i+1)} is written from the CP subset memories 924-934 to the (i+1)th FIFO of the buffer circuitry 950. The CP memory access controller circuitry 940 and the CP memory output circuitry 945 repeat the aforementioned operations in a cyclic manner so as to sequentially obtain P consecutive PCW samples from the CP subset memories 924-934 in parallel for a maximum of P cancellation pulses corresponding to a maximum of P detected peaks. If fewer than P peaks in the peak cancellation window are generated at any point in time, the CP subset memories 924-934 are not accessed for a minority of sample indices in each group of P sample indices.

[0106] Furthermore, assume that the erasure pulse readout circuitry 905 is currently generating erasure pulses for the (i-1) active peaks in the peak erasure window, and the i-th peak is detected. In this second example algorithm, the memory access controller circuitry 940 checks to determine whether the CP subset memory 924-934 has been accessed for one of the existing (i-1) erasure pulses for the current sample time instant n. If not, then the memory access controller circuitry 940 accesses the P-continuous PCW samples {h(k i ),h(k i +M),…,h(k i In addition, the CP generation control circuit system 955 sets the delay parameter δ of the i-th elimination pulse i Set to 0, where δ i represents the initial offset between the write and read pointers of the i-th FIFO in the buffer circuit system 950 for outputting the i-th erasure pulse. In addition, the CP generation control circuit system 955 sets the delay of the i-th FIFO in the buffer circuit system 950 accordingly.

[0107] In other cases, the memory access controller circuitry 940 calculates the maximum number of subsequent samples, represented as a variable L, during which the CP subset memories 924-934 will be accessed consecutively. In this example, P consecutive PCW samples corresponding to the i-th cancellation pulse of the i-th peak will be accessed by the memory access controller circuitry 940 from the CP subset memories 924-934 at sample instance (n+L). Therefore, the CP generation control circuitry 955 sets the delay parameter δ of the i-th cancellation pulse to i is set to L. In addition, the CP generation control circuitry 955 sets the delay of the i-th FIFO in the buffer circuitry 950 accordingly.

[0108] In some examples, the effective length of the reference pulse cancellation waveform can be doubled by designing it to have a conjugate symmetry property such that h(k)=h*(2N-k-2). In such examples, the N samples {h(0), h(1), ..., h(N-1)} stored in the CP subset memories 924-934 correspond to one-half of the total PCW. However, to exploit this conjugate symmetry, during the generation of a given cancellation pulse, the sample index of the PCW is decremented each time the center sample of the reference PCW is reached.

[0109] Such operations may be implemented as follows using the second example algorithm described above. The PCWs are stored in the CP subset memories 924-934 such that the center data sample is stored in the last or Pth subset memory 934. In some examples, a maximum of (P-1) zeros are appended to the beginning of the reference PCW to accomplish this. Then, during operation, after the memory access controller circuitry 940 accesses the center PCW sample from the Pth subset memory 934, the memory access controller circuitry 940 decrements the index of the data sample read from the CP subset memories 924-934. In addition, the CP memory output circuitry 945 flips the order in which the vectors of P samples are read out of the CP subset memories 924-934 at each sample instant so that the data sample vector {h(k i +PM-M),h(k i +PM-2M),…,h(k i )} instead of the vector {h(k i ),h(k i +M),…,h(k i +PM-M)} is written to the i-th FIFO in the buffer circuitry 950. In addition, in some examples, if the sample phase offset of the i-th peak causes the center data sample of the PCW to be read, the CP generation control circuitry 955 performs a dynamic offset adjustment (e.g., adjustment 1) to the write pointer or the read pointer so that the center data sample of the PCW is not repeated at the output of the i-th FIFO.

[0110] In some examples, the pulse elimination readout circuit system 905 includes means for accessing the CP subset memory. For example, the means for accessing the CP subset memory can be implemented by the CP memory access controller circuit system 940. In some examples, the CP memory access controller circuit system 940 can be instantiated by programmable circuit system, such as Fig.14 Example programmable circuit system 1412. For example, CP memory access controller circuit system 940 can be Fig.15 The example microprocessor 1500 executes machine executable instructions instantiated, for example, by at least Fig.11 Frame 1110, Fig.12 Frame 1205-1210, Fig.13 In some examples, the CP memory access controller circuit system 940 may be instantiated by a hardware logic circuit system, which may be an ASIC, XPU, or other processor configured or constructed to perform operations corresponding to machine-readable instructions. Fig.16 1600. In addition, the CP memory access controller circuit system 940 can be instantiated by any other combination of hardware, software, or firmware. For example, the CP memory access controller circuit system 940 can be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete or integrated analog or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured or constructed to execute some or all of the machine-readable instructions or to execute some or all of the operations corresponding to the machine-readable instructions, without executing software or firmware, but other structures are equally suitable.

[0111] In some examples, the elimination pulse readout circuit system 905 includes means for outputting data from the CP subset memory. For example, the means for outputting data from the CP subset memory can be implemented by the CP memory output circuit system 945. In some examples, the CP memory output circuit system 945 can be instantiated by programmable circuit system, such as Fig.14 Example programmable circuit system 1412. For example, CP memory output circuit system 945 can be Fig.15 The example microprocessor 1500 executes machine executable instructions instantiated, for example, by at least Fig.11 Frame 1110, Fig.12 Frame 1220, Fig.13 In some examples, the CP memory output circuit system 945 may be instantiated by a hardware logic circuit system, which may be an ASIC, XPU, or other processor configured or constructed to perform operations corresponding to the machine-readable instructions. Fig.16 1600. In addition, the CP memory output circuit system 945 can be instantiated by any other combination of hardware, software, or firmware. For example, the CP memory output circuit system 945 can be implemented by at least one or more hardware circuits (e.g., processor circuit systems, discrete or integrated analog or digital circuit systems, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured or constructed to execute some or all of the machine-readable instructions or to perform some or all operations corresponding to the machine-readable instructions, without executing software or firmware, but other structures are equally suitable.

[0112] In some examples, the elimination pulse readout circuit system 905 includes means for buffering the elimination pulse data. For example, the means for buffering the elimination pulse data can be implemented by the buffer circuit system 950. In some examples, the buffer circuit system 950 can be instantiated by the programmable circuit system, such as Fig.14 Example programmable circuit system 1412. For example, buffer circuit system 950 can be Fig.15 The example microprocessor 1500 executes machine executable instructions instantiated, for example, by at least Fig.11 In some examples, buffer circuit system 950 may be instantiated by hardware logic circuit system, which may be configured or constructed to perform operations corresponding to machine-readable instructions by an ASIC, XPU, or Fig.16 1600. In addition, buffer circuit system 950 may be instantiated by any other combination of hardware, software, or firmware. For example, buffer circuit system 950 may be implemented by at least one or more hardware circuits (e.g., processor circuit system, discrete or integrated analog or digital circuit system, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured or constructed to execute some or all of the machine-readable instructions or to perform some or all operations corresponding to the machine-readable instructions, without executing software or firmware, but other structures are equally suitable.

[0113] In some examples, the elimination pulse readout circuit system 905 includes means for controlling the generation of the elimination pulse. For example, the means for controlling the generation of the elimination pulse can be implemented by the CP generation control circuit system 955. In some examples, the CP generation control circuit system 955 can be instantiated by a programmable circuit system, such as Fig.14 Example programmable circuit system 1412. For example, CP generation control circuit system 955 can be Fig.15 The example microprocessor 1500 executes machine executable instructions instantiated, for example, by at least Fig.12 Frame 1225, Fig.13 In some examples, the CP generation control circuit system 955 may be instantiated by a hardware logic circuit system, which may be an ASIC, XPU, or other processor configured or constructed to perform operations corresponding to machine-readable instructions. Fig.16FPGA circuit system 1600. In addition, CP generation control circuit system 955 can be instantiated by any other combination of hardware, software or firmware. For example, CP generation control circuit system 955 can be implemented by at least one or more hardware circuits (e.g., processor circuit system, discrete or integrated analog or digital circuit system, FPGA, ASIC, XPU, comparator, operational amplifier (op-amp), logic circuit, etc.) configured or constructed to execute some or all of the machine-readable instructions or to perform some or all operations corresponding to the machine-readable instructions, without executing software or firmware, but other structures are equally suitable.

[0114] Despite Figure 7 and 9 An example manner of implementing the cancellation waveform generation circuit system 540 is shown in FIG. Figure 7 and 9 One or more elements, processes or devices shown in the can be combined, divided, rearranged, omitted, eliminated or implemented in any other way. In addition, Figure 7 and 9 The elimination pulse generation circuit system 705, scaling circuit system 710-720, summing circuit system 725, CP index generation circuit system 810-820, elimination pulse readout circuit system 905, CP subset memory 924-934, CP memory access controller circuit system 940, CP memory output circuit system 945, buffer circuit system 950, CP generation control circuit system 955 or more generally the example elimination waveform generation circuit system 540 can be implemented solely by hardware or by a combination of hardware and software or firmware. Thus, for example, any of the cancellation pulse generation circuitry 705, the scaling circuitry 710-720, the summing circuitry 725, the CP index generation circuitry 810-820, the cancellation pulse readout circuitry 905, the CP subset memories 924-934, the CP memory access controller circuitry 940, the CP memory output circuitry 945, the buffer circuitry 950, the CP generation control circuitry 955, or more generally the example cancellation waveform generation circuitry 540 may be implemented by programmable circuitry in conjunction with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an ASIC, a programmable logic device (PLD), or a field programmable logic device (FPLD) such as an FPGA. Still further, the example cancellation waveform generation circuitry 540 may include one or more elements, processes, or devices as Figure 7 and 9The present invention may be in addition to or instead of those shown in, or may include more than one of any or all of the shown elements, processes, and devices.

[0115] Figure 11-13 The diagram shows a representation that can be executed by a programmable circuit system to implement or instantiate Figure 7 and 9 Example machine readable instructions or representations of the cancellation waveform generation circuitry 540 may be executed by the programmable circuitry to implement or instantiate Figure 7 and 9 Flowchart of an example operation of the elimination waveform generation circuit system 540. The machine-readable instructions may be one or more executable programs or part of one or more executable programs for use by, for example, the following in conjunction with Fig.14 The programmable circuitry 1412 shown in the example processor platform 1400 described herein may perform, or may be part of, one or more functions or functions that will be described below in conjunction with the programmable circuitry 1412. Fig.15 In some examples, machine-readable instructions enable operations, tasks, etc. to be performed or executed in an automatic manner in the real world. As used herein, "automatically" means without human intervention.

[0116] The program may be embodied as instructions (e.g., software or firmware) stored on one or more non-transitory computer-readable or machine-readable storage media, such as cache memory, magnetic storage devices or disks (e.g., floppy disks, hard disk drives (HDDs), etc.), optical storage devices or disks (e.g., Blu-ray discs, compact disks (CDs), digital versatile disks (DVDs), etc.), redundant arrays of independent disks (RAIDs), registers, ROMs, solid-state drives (SSDs), SSD memories, non-volatile memories (e.g., electrically erasable programmable read-only memories (EEPROMs), flash memories, etc.), volatile memories (e.g., any type of random access memory (RAM), etc.), or any other storage devices or storage disks. The instructions of the non-transitory computer-readable or machine-readable media may be programmed or executed by programmable circuit systems located in one or more hardware devices, but the entire program or a portion thereof may also be executed or instantiated or embodied as dedicated hardware by one or more hardware devices other than programmable circuit systems. The machine-readable instructions may be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., server and client hardware devices). For example, the client hardware device may be implemented by an end-client hardware device (e.g., a hardware device associated with a human or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that can facilitate communication between a server and an end-client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. In addition, although the example programs are referenced Figure 11-13 The flowchart shown in the figure is described, but many other implementation examples can also be used to eliminate the method of waveform generation circuit system 540. For example, the execution order of the blocks of the flowchart can be changed, or some of the blocks described can be changed, eliminated or combined. In addition, any or all of the blocks in the flowchart can be implemented by one or more hardware circuits (e.g., processor circuit system, discrete or integrated analog or digital circuit system, FPGA, ASIC, comparator, operational amplifier (op-amp), logic circuit, etc.) configured to perform the corresponding operation without executing software or firmware. The programmable circuit system can be distributed in different network locations or one or more hardware devices (e.g., single-core processor (e.g., single-core CPU), multi-core processor (e.g., multi-core CPU, XPU, etc.) local. For example, the programmable circuit system can be a CPU or FPGA located in the same package (e.g., the same integrated circuit package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks, etc., or any combination thereof.

[0117] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bit stream (e.g., a computer-readable bit stream, a machine-readable bit stream, etc.), etc.) or a data structure (e.g., as part of an instruction, a code, a representation of a code, etc.), which may be used to create, manufacture, or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located in the same or different locations (e.g., a cloud, an edge device, etc.) of a network or collection of networks. The machine-readable instructions may need to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, redistributed, compiled, etc., so that they can be directly read, interpreted, or executed by a computing device or other machine. For example, machine-readable instructions may be stored in multiple portions that are separately compressed, encrypted, or stored on separate computing devices such that when decrypted, decompressed, or combined, the portions form a set of computer-executable or machine-executable instructions that implement one or more functions or operations that may together form a program, such as described herein.

[0118] In another example, the machine-readable instructions may be stored in a state where they can be read by the programmable circuit system, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or another device. In another example, the machine-readable instructions may require configuration (e.g., storing settings, inputting data, recording network addresses, etc.) before the machine-readable instructions or corresponding programs can be executed in whole or in part. Thus, as used herein, a machine-readable, computer-readable, or machine-readable medium may contain instructions or programs regardless of the specific format or state of the machine-readable instructions or programs.

[0119] The machine-readable instructions described herein may be represented by any past, present or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, Csharp, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0120] As mentioned above, Figure 11-13The example operations of may be implemented using executable instructions (e.g., computer-readable or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device or storage disk, and exclude propagating signals, and exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, temporarily, for temporary buffering, or for caching of information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, or electrical) hardware that retains information for a period of time, but excludes propagating signals and excludes transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical or electrical device, hardware, or circuit system, that may or may not be configured or manufactured to execute computer-readable instructions, machine-readable instructions, etc., with computer-readable instructions, machine-readable instructions, etc.

[0121] Fig.11 It means that it can be executed, instantiated or performed by a programmable circuit system to implement Figure 7 and 9 A flow chart of example machine readable instructions or example operations 1100 of the cancellation waveform generation circuit system 540. Fig.11 The example machine readable instructions or example operations 1100 of begin at block 1105: the CP memory access controller circuitry 940 obtains a sample index from the CP index generation circuitry 810-820. As described above, the sample index corresponds to a data sample of a PCW to be used to generate one or more output cancellation pulses corresponding to one or more peaks detected in the input signal x(n).

[0122] At block 1110, the CP memory access controller circuitry 940 accesses individual samples of the reference PCW in parallel from the group of CP subset memories 924-934. As described above, the group of CP subset memories 924-934 collectively stores a single instance of a PCW, and different ones of the CP subset memories 924-934 store different subsets of data samples of the reference PCW. At block 1110, the CP memory output circuitry 945 also provides the accessed samples of the reference PCW to the FIFO buffer of the buffer circuitry 950, as described above.

[0123] At block 1115, the FIFO buffers of the buffer circuitry 950 output their respective PCW samples to generate the one or more cancellation pulses, as described above.

[0124] At block 1120, the scaling circuitry 710-720 and the summing circuitry 725 combine the one or more cancellation pulses generated at block 1115 to generate an overall pulse cancellation signal sample z(n), as described above. In addition, the overall pulse cancellation signal sample z(n) is combined with the input sample x(n) (e.g., by the compensation circuitry 545) to generate a modified signal r(n) for transmission, as described above. If the cancellation pulse generation is complete (block 1125), then the machine-readable instructions or example operations 1100 end. Otherwise, processing returns to block 1105 and subsequent blocks thereof so that the cancellation pulse generation continues.

[0125] Fig.12 It means that the programmable circuit system can be executed, instantiated or performed to implement the first example algorithm described above. Fig.11 Example machine readable instructions for processing at block 1110 or a flowchart of example operations 1110A. Fig.12 Example machine readable instructions or example operations 1100A begin at block 1205: The CP memory access controller circuitry 940 accesses the original sample index {m1, m2, ..., m} corresponding to one or more elimination pulses (eg, up to P) to be generated. P}, as described above.

[0126] At block 1210, the CP memory access controller circuitry 940 indexes the raw samples {m1, m2, . . . , m P} into transformed indices, also called transformed CP subset memory indices {k1, k2, …, k P}, as described above. The transformed index {k1, k2, ..., k P} Allows individual data samples to be accessed in parallel from respective ones of the CP subset memories 924-934, with each individual data sample corresponding to a different one of the cancellation pulses to be generated, as further described above.

[0127] At block 1215, the CP memory access controller circuitry 940 uses the transformed index {k1, k2, . . . , k P} Access individual data samples in parallel from corresponding ones of the CP subset memories 924-934, as described above.

[0128] At block 1220, the CP memory output circuitry 945 outputs the respective individual data samples accessed at block 1215 to respective FIFO buffers (of the buffer circuitry 950) corresponding to the respective erasure pulses to be generated, as described above.

[0129] At block 1225, the CP generation control circuitry 955 configures the FIFO buffers of the buffer circuitry 950 with corresponding delays so that the FIFO buffers output their corresponding data samples (which correspond to corresponding cancellation pulses) to align with the corresponding peaks to be cancelled in the input signal, as described above. The example machine readable instructions or example operations 1110A then end.

[0130] Fig.13 It means that the programmable circuit system can be executed, instantiated or performed to implement the second example algorithm described above. Fig.11 Example machine readable instructions for processing at block 1110 or a flowchart of example operations 1110B. Fig.13The example machine readable instructions or example operations 1100B of begin at block 1305: the CP memory access controller circuitry 940 begins generating data samples for one or more erasure pulses in a cyclic manner. At block 1310, the CP memory access controller circuitry 940 accesses a sample index identifying a PCW sample to be accessed for a first erasure pulse generated, as described above. At block 1315, the CP memory access controller circuitry 940 uses the sample index to access P consecutive PCW samples of the given erasure pulse in parallel from the CP subset memories 924-934, as described above. At block 1320, the CP memory output circuitry 945 provides the P consecutive PCW samples accessed at block 1315 to a given FIFO buffer of the buffer circuitry 950 corresponding to the given erasure pulse generated, as described above. At block 1325, the CP generation control circuitry 955 configures the FIFO buffer to output the data samples stored therein based on a delay that aligns the data samples with a given peak of the input signal to be eliminated using the elimination pulse. At block 1330, the CP memory access controller circuitry 940 continues to process the elimination pulse in a loop. The example machine readable instructions or example operations 1100B then end.

[0131] Fig.14 Is constructed to execute or instantiate Figure 11-13 Example machine readable instructions or example operations to implement Figure 7 and 9 14 is a block diagram of an example programmable circuit system platform 1400 of the elimination waveform generation circuit system 540. For example, the programmable circuit system platform 1400 can be a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, a tablet computer, such as an iPad TM ), personal digital assistants (PDAs), internet appliances, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (e.g., augmented reality (AR) head-mounted devices, virtual reality (VR) head-mounted devices, etc.) or other wearable devices, or any other type of computing or electronic device.

[0132] The programmable circuit system platform 1400 of the illustrated example includes a programmable circuit system 1412. The programmable circuit system 1412 of the illustrated example is hardware. For example, the programmable circuit system 1412 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers of any desired family or manufacturer. The programmable circuit system 1412 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 1412 implements Figure 7 and 9 The elimination pulse generating circuit system 705, the scaling circuit system 710-720, the summing circuit system 725, the CP index generating circuit system 810-820, the elimination pulse reading circuit system 905, the CP subset memory 924-934, the CP memory access controller circuit system 940, the CP memory output circuit system 945, the buffer circuit system 950, the CP generation control circuit system 955 or more generally the elimination waveform generating circuit system 540.

[0133] The programmable circuit system 1412 of the illustrated example includes a local memory 1413 (e.g., cache, registers, etc.). The programmable circuit system 1412 of the illustrated example communicates with a main memory 1414, 1416 including a volatile memory 1414 and a non-volatile memory 1416 via a bus 1418. The volatile memory 1414 may be a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 1416 may be implemented by flash memory or any other desired type of memory device. Access to the main memory 1414, 1416 of the illustrated example is controlled by a memory controller 1417. In some examples, the memory controller 1417 may be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry for managing data flow to and from the main memory 1414, 1416 of any desired family or manufacturer.

[0134] The programmable circuit system platform 1400 of the illustrated example also includes an interface circuit system 1420. The interface circuit system 1420 can be implemented by hardware using any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, or a peripheral component interconnect express (PCIe) interface.

[0135] In the example shown, one or more input devices 1422 are connected to the interface circuitry 1420. The input devices 1422 allow a user (e.g., a human user, a machine user, etc.) to enter data or commands into the programmable circuitry 1412. The input devices 1422 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a track pad, a trackball, an isochronous device, or a voice recognition system.

[0136] One or more output devices 1424 are also connected to the interface circuit system 1420 of the illustrated example. The output device 1424 may be implemented by, for example, a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, or a speaker. Thus, the interface circuit system 1420 of the illustrated example may include a graphics driver card, a graphics driver chip, or a graphics processor circuit system, such as a GPU.

[0137] The interface circuitry 1420 of the illustrated example also includes a communication device, such as a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface to facilitate the exchange of data with an external machine (e.g., any kind of computing device) over the network 1426. Communications may occur over, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, or the like.

[0138] The programmable circuit system platform 1400 of the illustrated example also includes one or more mass storage disks or devices 1428 for storing firmware, software or data. Examples of such mass storage disks or devices 1428 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices or SSDs.

[0139] can be Figure 11-13 The machine-readable instructions 1432 implemented by the machine-readable instructions may be stored in the mass storage device 1428, in the volatile memory 1414, in the non-volatile memory 1416, or on at least one removable non-transitory computer-readable storage medium (eg, a CD or DVD).

[0140] Fig.15 yes Fig.14 1412 of the programmable circuit system 1412. In this example, Fig.14 The programmable circuit system 1412 is implemented by the microprocessor 1500. For example, the microprocessor 1500 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit system). The microprocessor 1500 executes Figure 11-13 Some or all of the machine-readable instructions in the flowchart of Figure 2 The circuit system of the machine readable instructions is instantiated as a logic circuit to perform operations corresponding to those machine readable instructions. In some such examples, Figure 7 and 9The circuit system is instantiated by the hardware circuit of the microprocessor 1500 in combination with machine-readable instructions. For example, the microprocessor 1500 may be implemented by a multi-core hardware circuit system such as a CPU, DSP, GPU, XPU, etc. The microprocessor 1500 of this example is a multi-core semiconductor device including N cores, but it may include any number of example cores 1502 (for example, 1 core). The cores 1502 of the microprocessor 1500 may operate independently or collaborate to execute machine-readable instructions. For example, the machine code corresponding to a firmware program, a built-in software program, or a software program may be executed by one of the cores 1502, or by multiple cores 1502 at the same or different times. In some examples, the machine code corresponding to the firmware program, the built-in software program, or the software program is split into threads and executed in parallel by two or more of the cores 1502. The software program may correspond to a program represented as Figure 11-13 A flowchart may contain part or all of the machine-readable instructions or operations.

[0141] The cores 1502 can communicate via a first example bus 1504. In some examples, the first bus 1504 can be implemented by a communication bus to enable communications associated with one or more of the cores 1502. For example, the first bus 1504 can be implemented by at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. In addition, the first bus 1504 can be implemented by any other type of computing or electrical bus. The cores 1502 can obtain data, instructions, or signals from one or more external devices via an example interface circuit system 1506. The cores 1502 can output data, instructions, or signals to the one or more external devices via the interface circuit system 1506. Although the core 1502 of this example includes an example local memory 1520 (e.g., a level 1 (L1) cache that can be split into an L1 data cache and an L1 instruction cache), the microprocessor 1500 also includes an example shared memory 1510 (e.g., a level 2 (L2 cache)) that can be shared by the cores for high-speed access to data or instructions. Data or instructions can be transferred (e.g., shared) by writing to or reading from the shared memory 1510. The local memory 1520 and shared memory 1510 of each core 1502 can be a cache memory and a main memory (e.g., a cache memory including multiple levels) . Fig.14 The cache memory may be part of a storage device hierarchy of main memory 1414, 1416 of the main memory 1414, 1416. For example, memories at higher levels in the hierarchy may exhibit lower access times and have smaller storage capacities than memories at lower levels. Changes to the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0142] Each core 1502 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit system. Each core 1502 includes a control unit circuit system 1514, an arithmetic and logic (AL) circuit system (sometimes referred to as an ALU) 1516, a plurality of registers 1518, a local memory 1520, and a second example bus 1522. Other structures may exist. For example, each core 1502 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating point unit (FPU) circuit system, etc. The control unit circuit system 1514 includes a semiconductor-based circuit configured to control (e.g., coordinate) data movement within the corresponding core 1502. The AL circuit system 1516 includes a semiconductor-based circuit configured to perform one or more mathematical or logical operations on data within the corresponding core 1502. The AL circuit system 1516 of some examples performs integer-based operations. In other examples, the AL circuit system 1516 also performs floating-point operations. In still other examples, AL circuitry 1516 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, AL circuitry 1516 may be referred to as an arithmetic logic unit (ALU).

[0143] Registers 1518 are semiconductor-based structures for storing data or instructions, such as the results of one or more operations performed by the AL circuit system 1516 of the corresponding core 1502. For example, registers 1518 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Registers 1518 may be arranged in memory banks, such as Fig.15 In addition, registers 1518 may be organized into any other arrangement, format, or structure, such as being distributed throughout core 1502 to reduce access time. Second bus 1522 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0144] Each core 1502, or more generally the microprocessor 1500, may include other structures in addition to those shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid sites (CMSs), one or more shifters (e.g., barrel shifters), or other circuitry. The microprocessor 1500 is a semiconductor device fabricated to include many transistors that are interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.

[0145] The microprocessor 1500 may include or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, the accelerator is implemented by logic circuitry to perform certain tasks faster or more efficiently than a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those described herein. A GPU, DSP, or other programmable device may also be an accelerator. The accelerator may be onboard the microprocessor 1500, in the same chip package as the microprocessor 1500, or in one or more packages separate from the microprocessor 1500.

[0146] Fig.16 yes Fig.14 1412 is a block diagram of another example embodiment of programmable circuit system 1412. In this example, programmable circuit system 1412 is implemented by FPGA circuit system 1600. For example, FPGA circuit system 1600 can be implemented by an FPGA. For example, FPGA circuit system 1600 can be used to perform operations that can be performed by other situations. Fig.15 However, once configured, FPGA circuit system 1600 instantiates the operations or functions corresponding to the machine-readable instructions in hardware, and thus can often perform the operations / functions faster than if a general-purpose microprocessor executed corresponding software.

[0147] More specifically, compared to the above Fig.15 The microprocessor 1500 (which is programmable to execute Figure 11-13 a general purpose device that contains some or all of the machine-readable instructions of a flowchart, but whose interconnections and logic circuitry are fixed after manufacture), Fig.16 The example FPGA circuit system 1600 includes interconnects and logic circuit systems, which can be configured, constructed, programmed or interconnected in different ways after manufacturing to, for example, instantiate corresponding to the logic circuits represented as Figure 11-13 In particular, FPGA circuit system 1600 can be viewed as an array of logic gates, interconnects, and switches. The switches can be programmed to change the way the logic gates are interconnected through the interconnects, effectively forming one or more dedicated logic circuits (unless and until FPGA circuit system 1600 is reprogrammed). The logic circuits are configured so that the logic gates cooperate in different ways to perform different operations on the data received by the input circuit system. Those operations can correspond to the operations represented as Figure 11-13 Thus, FPGA circuit system 1600 may be configured or constructed to correspond to some or all of the instructions (e.g., software or firmware) of the flowchart of FIG. Figure 11-13Some or all of the operations / functions of the machine-readable instructions of the flowchart are effectively instantiated into dedicated logic circuits, thereby performing the operations / functions corresponding to those software instructions in a dedicated manner, similar to an ASIC. Therefore, FPGA circuit system 1600 can execute the operations corresponding to those software instructions faster than a general-purpose microprocessor can execute. Figure 11-13 Some or all of the operations / functions of the machine-readable instructions.

[0148] exist Fig.16 In an example, the FPGA circuit system 1600 is configured or constructed in response to being programmed (or reprogrammed one or more times) based on a binary file. In some examples, the binary file can be compiled or generated based on instructions in a hardware description language (HDL), such as Lucid, Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or a program corresponding to one or more operations / functions in HDL; the code / program can be converted into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) can be converted (e.g., by a compiler, a software application, etc.) into a binary file. In some examples, Fig.16 The FPGA circuit system 1600 can access or load binary files so that Fig.16 The FPGA circuit system 1600 is configured or constructed to perform the one or more operations / functions. For example, a binary file can be composed of a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or Fig.16 The FPGA circuit system 1600 can be implemented by accessing machine-readable instructions, thereby causing Fig.16 Configuration or construction of FPGA circuit system 1600 or part thereof.

[0149] In some examples, the binary file is compiled, generated, transformed, or otherwise output from a unified software platform for programming the FPGA. For example, the unified software platform can convert a first instruction (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into a second instruction in HDL corresponding to the one or more operations / functions. In some such examples, the binary file is compiled, generated, or otherwise output from the unified software platform based on the second instruction. In some examples, Fig.16 The FPGA circuit system 1600 can access or load binary files so that Fig.16The FPGA circuit system 1600 is configured or constructed to perform the one or more operations / functions. For example, a binary file may consist of a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), Fig.16 The FPGA circuit system 1600 can access the machine-readable instructions implemented to cause Fig.16 Configuration or construction of FPGA circuit system 1600 or part thereof.

[0150] Fig.16 FPGA circuit system 1600 includes an example input / output (I / O) circuit system 1602 for obtaining data from or outputting data to an example configuration circuit system 1604 or external hardware 1606. For example, configuration circuit system 1604 may be implemented by an interface circuit system that can obtain a binary file to configure FPGA circuit system 1600 or a portion thereof, and the binary file may be implemented by a bitstream, data, or machine-readable instructions. In some such examples, configuration circuit system 1604 may obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement an artificial intelligence / machine learning (AI / ML) model to generate a binary file), etc., or any combination thereof. In some examples, external hardware 1606 may be implemented by an external hardware circuit system. For example, external hardware 1606 may be implemented by Fig.15 The microprocessor 1500 is implemented as described above.

[0151] FPGA circuitry 1600 also includes an array of example logic gate circuitry 1608, a plurality of example configurable interconnects 1610, and example storage circuitry 1612. Logic gate circuitry 1608 and configurable interconnects 1610 may be configured to instantiate a Figure 11-13 One or more operations / functions or other desired operations of at least some of the machine-readable instructions. Fig.16 The logic gate circuitry 1608 shown is manufactured in blocks or groups. Each block contains a semiconductor-based electrical structure that can be configured into a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., an AND gate, an OR gate, a NOR gate, etc.) that provides a basic building block for the logic circuit. There are electrically controlled switches (e.g., transistors) within each logic gate circuitry 1608 so that the configuration of the electrical structure or logic gate can form a circuit that performs the desired operation / function. The logic gate circuitry 1608 may include other electrical structures, such as a lookup table (LUT), a register (e.g., a flip-flop or latch), a multiplexer, etc.

[0152] The configurable interconnect 1610 of the illustrated example is a conductive path, trace, via, etc. that may include electrically controlled switches (e.g., transistors), the state of which may be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit systems 1608 to program the desired logic circuit.

[0153] The storage circuit system 1612 of the illustrated example is configured to store the results of one or more operations performed by corresponding logic gates. The storage circuit system 1612 may be implemented by registers, etc. In the illustrated example, the storage circuit system 1612 is distributed among the logic gate circuit system 1608 to facilitate access and increase execution speed.

[0154] Fig.16 The example FPGA circuit system 1600 also includes an example special operation circuit system 1614. In this example, the special operation circuit system 1614 includes a special circuit system 1616 that can be called to implement common functions so that those functions no longer need to be programmed on site. Examples of such special circuit systems 1616 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory, and multiplier-accumulator circuit systems. Other types of special circuit systems may exist. In some examples, the FPGA circuit system 1600 may also include an example general programmable circuit system 1618, such as an example CPU 1620 or an example DSP 1622. There may also be other general programmable circuit systems 1618 that can be programmed to perform other operations, such as GPUs, XPUs, etc.

[0155] although Fig.15 and 16 Shows Fig.14 Two example implementations of programmable circuitry 1412 are shown, but many other approaches are contemplated. For example, the FPGA circuitry may include an onboard CPU, such as Fig.15 One or more of the example CPUs 1620. Thus, Fig.14 The programmable circuit system 1412 can also be configured by combining at least Fig.15 An example microprocessor 1500 and Fig.16 In some such hybrid examples, Fig.15 One or more cores 1502 may execute Figure 11-13 a first portion of a flowchart of machine-readable instructions to perform a first operation / function, Fig.16 The FPGA circuit system 1600 may be configured or constructed to perform the corresponding Figure 11-13The second operation / function of the second portion of the machine readable instructions of the flowchart, or the ASIC may be configured or constructed to perform the operation corresponding to the second portion of the machine readable instructions represented as Figure 11-13 A third operation / function of a third portion of the machine readable instructions of the flowchart.

[0156] therefore, Figure 7 and 9 Some or all of the circuit systems in may be instantiated at the same or different times. Fig.15 The same or different portions of microprocessor 1500 may be programmed to execute portions of machine-readable instructions at the same or different times. In some examples, Fig.16 The same or different portions of FPGA circuit system 1600 may be configured or constructed to perform operations / functions corresponding to portions of the machine-readable instructions at the same or different times.

[0157] In some examples, for example, Figure 7 and 9 Some or all of the circuitry in may be instantiated in one or more threads that execute in parallel or serially. Fig.15 The microprocessor 1500 can execute machine-readable instructions in one or more threads of execution in parallel or serially. In some examples, Fig.16 The FPGA circuit system 1600 can be configured or constructed to perform operations / functions in parallel or serially. In addition, in some examples, Figure 7 and 9 Some or all of the circuitry in may be implemented in Fig.15 In one or more virtual machines or containers executed on the microprocessor 1500.

[0158] In some examples, Fig.14 The programmable circuit system 1412 can be in one or more packages. For example, Fig.15 Microprocessor 1500 or Fig.16 The FPGA circuit system 1600 can be in one or more packages. In some examples, the XPU can be composed of a FPGA circuit system 1600 that can be in one or more packages. Fig.14 The XPU may be implemented by programmable circuit system 1412. For example, the XPU may include a CPU in a package (e.g., Fig.15 Microprocessor 1500, Fig.16 CPU 1620, etc.), a DSP in another package (e.g., Fig.16 DSP1622 of another package), a GPU in another package, and an FPGA in yet another package (e.g., Fig.16 FPGA circuit system 1600).

[0159] "Include" and "comprising" (and all their forms and tenses) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or in any kind of claim statement, additional elements, terms, etc. may be present without falling outside the scope of the corresponding claim or statement. As used herein, for example, when the phrase "at least" is used as a transitional term in a claim preamble, it is open-ended, just as the terms "comprising" and "including" are open-ended. The term "or" when used in the form of, for example, A, B, or C, refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, articles, objects, and / or things, the phrase "at least one of A and B" is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, articles, objects, and / or things, the phrase "at least one of A or B" is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of a process, instruction, act, activity, etc., the phrase "at least one of A and B" is intended to refer to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of a process, instruction, action, activity, etc., the phrase "at least one of A or B" is intended to refer to an embodiment that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0160] As used herein, singular references (e.g., "a / an", "first", "second", etc.) do not exclude the plural. As used herein, the term "a / an" object refers to one or more of said objects. The terms "a / an", "one or more" and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not mean that a combination of features is not feasible and / or disadvantageous.

[0161] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the earth. A first part is above a second part if the second part has at least one portion between the earth and the first part. Likewise, as used herein, a first part is "below" a second part when the first part is closer to the earth than the second part. As mentioned above, a first part can be above or below a second part with one or more of the following: there are other parts in between, there are no other parts in between, the first and second parts are in contact, or the first and second parts are not in direct contact with each other.

[0162] As used herein, unless otherwise indicated, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements to which the connection reference refers or relative movement between those elements. Thus, connection references do not necessarily infer that two elements are directly connected or in a fixed relationship to each other. As used herein, stating that any part is "in contact with" another part is defined to mean that there is no intermediate part between the two parts.

[0163] Unless specifically stated otherwise, descriptors such as "first," "second," "third," and the like are used herein without any meaning of importing or otherwise indicating priority, physical order, arrangement in a list, or ordering, but are used merely as labels or arbitrary names to distinguish elements to facilitate understanding of the described examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to by a different descriptor (such as "second" or "third") in the claims. In such cases, such descriptors are used only to clearly identify these elements in the context of the discussion (such as in the claims), for example where these elements might otherwise share the same name.

[0164] As used herein, "substantially" and "approximately" modify their subject matter / values ​​to recognize that there may be variations in real-world applications. For example, "substantially" and "approximately" may modify dimensions that may not be exact due to manufacturing tolerances or other real-world imperfections. For example, unless otherwise specified herein, "substantially" and "approximately" may indicate that such dimensions may be within a tolerance range of + / - 10%.

[0165] As used herein, "substantially real time" means occurring in a near-instantaneous manner, recognizing that there may be delays in real-world computation time, transmission, etc. Therefore, unless otherwise specified, "substantially real time" means real time + 1 second.

[0166] As used herein, the phrase "communication," including variations thereof, encompasses direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, or one-time events.

[0167] As used herein, "programmable circuitry" is defined to include: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are configured to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that are programmable with instructions to perform specific functions or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include a programmable microprocessor, such as a central processing unit (CPU) that can execute a first instruction to perform one or more operations or functions, a field programmable gate array (FPGA) that can be programmed with a second instruction that enables the FPGA to be configured or configured to instantiate one or more operations or functions corresponding to the first instruction, a graphics processing unit (GPU) that can execute a first instruction to perform one or more operations or functions, a digital signal processor (DSP) that can execute a first instruction to perform one or more operations or functions, an XPU, a network processing unit (NPU), one or more microcontrollers that can execute a first instruction to perform one or more operations or functions, or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, the XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc. or any combination thereof) and orchestration technology (e.g., an application programming interface (API)), which can allocate computing tasks to programmable circuit systems that are suitable and available to perform computing tasks among the multiple types of programmable circuit systems.

[0168] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), and the like.

[0169] Based on the above, it should be appreciated that example systems, devices, articles, and methods have been described that implement cancellation pulse generation with reduced waveform storage to reduce peaks in a transmission signal. The described systems, devices, articles, and methods improve the efficiency of using a computing device by generating multiple cancellation pulses for multiple signal peaks in parallel based on a single reference pulse cancellation waveform stored in memory, thereby having a smaller memory footprint than other cancellation pulse generation techniques. Therefore, the described systems, devices, articles, and methods are directed to one or more improvements in the operation of a machine, such as a computer or other electronic or mechanical device.

[0170] Other examples and combinations thereof include the following. Example 1 includes an apparatus comprising: a first memory storing a first subset of data samples of a single pulse-canceled waveform; a second memory storing a second subset of data samples of the single pulse-canceled waveform, the second subset including data samples of the single pulse-canceled waveform different from the first subset; a first circuit system coupled to the first memory and the second memory in parallel; a plurality of buffers; and a second circuit system coupled to the plurality of buffers.

[0171] Example 2 includes an apparatus according to Example 1, wherein the first subset includes a first number of consecutive data samples of the single pulse cancellation waveform, the first number being based on an oversampling factor associated with the single pulse cancellation waveform, and an initial subset and a next subset in the first subset are separated by a second number of consecutive data samples of the single pulse cancellation waveform, the second number being based on a function of the oversampling factor and a total number of output cancellation pulses that can be generated.

[0172] Example 3 includes an apparatus according to Example 2, wherein the second subset includes the first number of consecutive data samples of the single pulse cancellation waveform, an initial subset and a next subset in the second subset are separated by the second number of consecutive data samples of the single pulse cancellation waveform, the second subset includes data samples of the single pulse cancellation waveform that are different from the first subset, and the initial subset of the second subset includes data samples of the single pulse cancellation waveform starting from a sample index corresponding to the oversampling factor.

[0173] Example 4 includes an apparatus according to Example 1, wherein the first circuit system is configured to: obtain a first index corresponding to a data sample of the single pulse cancellation waveform to be used to generate a first output cancellation pulse, the first index being based on the position of a first peak of an input signal; based on the first index, access a first data sample from the first memory and a second data sample from the second memory in parallel, the first data sample and the second data sample being associated with the first output cancellation pulse; obtain a second index corresponding to the data sample of the single pulse cancellation waveform to be used to generate a second output cancellation pulse, the second index being based on the position of a second peak of the input signal; and based on the second index, access a third data sample from the first memory and a fourth data sample from the second memory in parallel, the third data sample and the fourth data sample being associated with the second output cancellation pulse.

[0174] Example 5 includes an apparatus according to Example 4, wherein the second circuit system is configured to: provide the first data sample and the second data sample to a first buffer, the first buffer is associated with the first output cancellation pulse, and provide the third data sample and the fourth data sample to a second buffer, the second buffer is associated with the second output cancellation pulse, and the apparatus further includes a third circuit system, the third circuit system is configured to configure the first buffer based on a first delay to sequentially output the first data sample and the second data sample, and configure the second buffer based on a second delay to sequentially output the third data sample and the fourth data sample.

[0175] Example 6 includes an apparatus according to Example 1, wherein the first circuit system is used to obtain a first index of a data sample corresponding to the single pulse cancellation waveform to be used to generate one or more output cancellation pulses, transform the first index into a second index, and based on the second index, access the first data sample from the first memory and the second data sample from the second memory in parallel.

[0176] Example 7 includes an apparatus according to Example 5, wherein the first data sample corresponds to a first output elimination pulse, the second data sample corresponds to a second output elimination pulse, the second circuit system is configured to: provide the first data sample to a first buffer, the first buffer is associated with the first output elimination pulse; and provide the second data sample to a second buffer, the second buffer is associated with the second output elimination pulse, the apparatus further includes a third circuit system, the third circuit system is configured to configure the first buffer to output the first data sample based on a first delay, and configure the second buffer to output the second data sample based on a second delay.

[0177] Example 8 includes the apparatus of Example 1, further comprising third circuitry that configures the plurality of buffers with respective output delays.

[0178] Example 9 includes a transmitter device comprising: a plurality of memories, respective ones of the memories storing respective different subsets of data samples of a single pulse cancellation waveform; a crest factor reduction circuit system coupled to the plurality of memories and having an input and an output; and a digital pre-distortion corrector circuit system having an input and an output, the input of the digital pre-distortion corrector circuit system being coupled to the output of the crest factor reduction circuit system.

[0179] Example 10 includes the transmitter apparatus of Example 9, wherein the crest factor reduction circuitry is configured to access individual data samples from the respective ones of the memories in parallel and scale the accessed individual data samples based on corresponding cancellation phasors to generate one or more output cancellation pulses.

[0180] Example 11 includes the transmitter apparatus of Example 10, wherein the crest factor reduction circuitry is configured to combine the one or more output cancellation pulses to generate an output signal.

[0181] Example 12 includes the transmitter apparatus of Example 9, wherein the crest factor reduction circuitry is configured to: determine an index corresponding to a sample of the single pulse cancellation waveform to be used to generate one or more output cancellation pulses, the index being based on one or more locations of one or more peaks of an input signal; and access individual data samples in parallel from the corresponding ones of the memories based on the index.

[0182] Example 13 includes a transmitter apparatus according to Example 9, wherein the plurality of memories includes a first memory storing a first subset of data samples of the single pulse cancellation waveform, the first subset including a first number of consecutive data samples of the single pulse cancellation waveform, the first number being based on an oversampling factor associated with the single pulse cancellation waveform, and an initial subset and a next subset in the first subset are separated by a second number of consecutive data samples of the single pulse cancellation waveform, the second number being based on a function of the oversampling factor and a total number of output cancellation pulses that can be generated.

[0183] Example 14 includes the transmitter apparatus of Example 13, wherein the plurality of memories includes a second memory storing a second subset of data samples of the single pulse cancellation waveform, the second subset including the first number of consecutive data samples of the single pulse cancellation waveform, an initial subset and a next subset of the second subsets being separated by the second number of consecutive data samples of the single pulse cancellation waveform, the second subset including data samples of the single pulse cancellation waveform that are different from the first subset, and the initial subset of the second subsets including data samples of the single pulse cancellation waveform starting from a sample index corresponding to the oversampling factor.

[0184] Example 15 includes the transmitter apparatus of Example 9, wherein the transmitter apparatus is included in a base station.

[0185] Example 16 includes at least one non-transitory computer-readable medium comprising computer-readable instructions for causing at least one processor circuit to at least: obtain an index corresponding to a sample of a pulse cancellation waveform to be used to generate one or more output cancellation pulses, the index being based on one or more locations of one or more peaks of an input signal; based on the index, accessing in parallel respective data samples from respective ones of a plurality of memories that collectively store a single instance of the pulse cancellation waveform, the respective ones of the memories storing respective different subsets of data samples of the pulse cancellation waveform, the respective ones of the memories having respective storage capacities that are less than a total number of samples of the single instance of the pulse cancellation waveform; and generating the one or more output cancellation pulses based on the accessed respective data samples.

[0186] Example 17 includes at least one non-transitory computer-readable medium according to Example 16, wherein the computer-readable instructions are used to cause one or more of the at least one processor circuits to access the individual data samples from a number of memories based on a total number of output cancellation pulses that can be generated, and the corresponding storage capacity of the memories is based on a ratio of the total number of samples of the single instance of the pulse cancellation waveform to the total number of output cancellation pulses that can be generated.

[0187] Example 18 includes at least one non-transitory computer-readable medium according to Example 16, wherein the computer-readable instructions are used to cause one or more of the at least one processor circuits to access the individual data samples from a first memory storing a first subset of data samples of the single instance of the pulse-cancelled waveform, the first subset including a first number of consecutive data samples of the single instance of the pulse-cancelled waveform, the first number being based on an oversampling factor associated with the single instance of the pulse-cancelled waveform, and an initial subset and a next subset in the first subset being separated by a second number of consecutive data samples of the single instance of the pulse-cancelled waveform, the second number being based on the product of the oversampling factor and a total number of output-cancelled pulses that can be generated.

[0188] Example 19 includes at least one non-transitory computer-readable medium according to Example 18, wherein the computer-readable instructions are used to cause one or more of the at least one processor circuits to access the individual data samples from a second memory storing a second subset of data samples of the single instance of the pulse-cancelled waveform, the second subset including the first number of consecutive data samples of the single instance of the pulse-cancelled waveform, an initial subset and a next subset in the second subset being separated by the second number of consecutive data samples of the single instance of the pulse-cancelled waveform, the second subset including data samples of the single pulse-cancelled waveform that are different from the first subset, and the initial subset of the second subset including data samples of the single pulse-cancelled waveform starting from a sample index corresponding to the oversampling factor.

[0189] Example 20 includes at least one non-transitory computer-readable medium according to Example 16, wherein, to generate one or more output cancellation pulses, the computer-readable instructions are used to cause one or more of the at least one processor circuits to provide each accessed data sample to one or more buffers corresponding to the one or more output cancellation pulses, respectively, and configure the one or more buffers based on one or more delays so that the one or more buffers output the one or more output cancellation pulses to suppress the one or more peaks of the input signal.

[0190] The attached claims are incorporated into this detailed description by reference. Although certain example systems, devices, articles, and methods have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that fully fall within the scope of the claims of this patent.

Claims

1. A device comprising: a first memory storing a first subset of data samples of a single pulse cancellation waveform; a second memory storing a second subset of data samples of the single pulse cancellation waveform, the second subset comprising different data samples of the single pulse cancellation waveform than the first subset; a first circuit system coupled in parallel to the first memory and the second memory; Multiple buffers; as well as A second circuit system is coupled to the plurality of buffers.

2. The apparatus of claim 1 , wherein the first subset comprises a first number of consecutive data samples of the single pulse cancellation waveform, the first number being based on an oversampling factor associated with the single pulse cancellation waveform, and an initial subset and a next subset in the first subset are separated by a second number of consecutive data samples of the single pulse cancellation waveform, the second number being based on a function of the oversampling factor and a total number of output cancellation pulses that can be generated.

3. The apparatus of claim 2 , wherein the second subset comprises the first number of consecutive data samples of the single pulse cancellation waveform, an initial subset and a next subset in the second subset are separated by the second number of consecutive data samples of the single pulse cancellation waveform, the second subset comprises data samples of the single pulse cancellation waveform that are different from the first subset, and the initial subset of the second subset comprises data samples of the single pulse cancellation waveform starting from a sample index corresponding to the oversampling factor.

4. The apparatus of claim 1 , wherein the first circuit system is configured to: obtaining a first index of data samples corresponding to the single pulse cancellation waveform to be used to generate a first output cancellation pulse, the first index being based on a location of a first peak of the input signal; accessing in parallel a first data sample from the first memory and a second data sample from the second memory based on the first index, the first data sample and the second data sample being associated with the first output cancellation pulse; obtaining a second index corresponding to a data sample of the single pulse cancellation waveform to be used to generate a second output cancellation pulse, the second index being based on a location of a second peak of the input signal; and Based on the second index, a third data sample is accessed from the first memory and a fourth data sample is accessed from the second memory in parallel, the third data sample and the fourth data sample being associated with the second output elimination pulse.

5. The apparatus of claim 4, wherein the second circuit system is configured to: providing the first data sample and the second data sample to a first buffer, the first buffer being associated with the first output cancel pulse; and providing the third data sample and the fourth data sample to a second buffer, the second buffer being associated with the second output cancel pulse; and The apparatus further comprises a third circuit system configured to: configuring the first buffer to sequentially output the first data sample and the second data sample based on a first delay; and The second buffer is configured based on a second delay to sequentially output the third data sample and the fourth data sample.

6. The apparatus of claim 1, wherein the first circuit system is configured to: obtaining a first index of a data sample corresponding to the single pulse cancellation waveform to be used to generate one or more output cancellation pulses; transforming the first index into a second index; and Based on the second index, first data samples are accessed from the first memory and second data samples are accessed from the second memory in parallel.

7. The apparatus of claim 5, wherein the first data sample corresponds to a first output cancellation pulse, the second data sample corresponds to a second output cancellation pulse, and the second circuit system is configured to: providing the first data sample to a first buffer, the first buffer being associated with the first output cancel pulse; and providing the second data sample to a second buffer, the second buffer being associated with the second output cancel pulse; and The apparatus further comprises a third circuit system configured to: configuring the first buffer to output the first data sample based on a first delay; and The second buffer is configured based on a second delay to output the second data samples.

8. The apparatus of claim 1, further comprising third circuitry for configuring the plurality of buffers with respective output delays.

9. A transmitter device comprising: a plurality of memories, respective ones of the memories storing respective different subsets of data samples of a single pulse-canceled waveform; crest factor reduction circuitry coupled to the plurality of memories and having an input and an output; and A digital predistortion corrector circuitry has an input and an output, the input of the digital predistortion corrector circuitry being coupled to the output of the crest factor reduction circuitry.

10. The transmitter device of claim 9, wherein the crest factor reduction circuitry is configured to: accessing, in parallel, respective data samples from the respective ones of the memories; and Each accessed data sample is scaled to generate one or more output cancellation pulses based on a corresponding cancellation phasor.

11. The transmitter apparatus of claim 10, wherein the crest factor reduction circuitry is configured to combine the one or more output cancellation pulses to generate an output signal.

12. The transmitter device of claim 9, wherein the crest factor reduction circuitry is configured to: determining an index corresponding to a sample of the single pulse cancellation waveform to be used to generate one or more output cancellation pulses, the index being based on one or more locations of one or more peaks of the input signal; and Based on the index, individual data samples are accessed in parallel from the corresponding ones of the memories.

13. The transmitter apparatus of claim 9 , wherein the plurality of memories comprises a first memory storing a first subset of data samples of the single pulse cancellation waveform, the first subset comprising a first number of consecutive data samples of the single pulse cancellation waveform, the first number being based on an oversampling factor associated with the single pulse cancellation waveform, and an initial subset and a next subset of the first subset being separated by a second number of consecutive data samples of the single pulse cancellation waveform, the second number being based on a function of the oversampling factor and a total number of output cancellation pulses that can be generated.

14. The transmitter apparatus of claim 13 , wherein the plurality of memories comprises a second memory storing a second subset of data samples of the single pulse cancellation waveform, the second subset comprising the first number of consecutive data samples of the single pulse cancellation waveform, an initial subset and a next subset of the second subsets being separated by the second number of consecutive data samples of the single pulse cancellation waveform, the second subset comprising data samples of the single pulse cancellation waveform different from the first subset, and the initial subset of the second subsets comprising data samples of the single pulse cancellation waveform starting from a sample index corresponding to the oversampling factor.

15. The transmitter device according to claim 9, wherein the transmitter device is included in a base station.

16. A non-transitory computer-readable medium comprising computer-readable instructions for causing at least one processor circuit to at least: obtaining indices corresponding to samples of a pulse cancellation waveform to be used to generate one or more output cancellation pulses, the indices being based on one or more locations of one or more peaks of the input signal; accessing, in parallel, respective data samples from respective ones of a plurality of memories collectively storing a single instance of the pulse-canceled waveform, the respective ones of the memories storing respective different subsets of data samples of the pulse-canceled waveform, the respective ones of the memories having respective storage capacities less than a total number of samples of the single instance of the pulse-canceled waveform, based on the index; and The one or more output cancel pulses are generated based on the respective data samples accessed.

17. The non-transitory computer-readable medium of claim 16, wherein the computer-readable instructions are for causing one or more of the at least one processor circuits to access the individual data samples from a number of memories based on a total number of output cancellation pulses that can be generated, and the respective storage capacity of the memories is based on a ratio of the total number of samples of the single instance of the pulse cancellation waveform to the total number of output cancellation pulses that can be generated.

18. The non-transitory computer-readable medium of claim 16, wherein the computer-readable instructions are for causing one or more of the at least one processor circuits to access the individual data samples from a first memory storing a first subset of data samples of the single instance of the pulse-canceled waveform, the first subset comprising a first number of consecutive data samples of the single instance of the pulse-canceled waveform, the first number being based on an oversampling factor associated with the single instance of the pulse-canceled waveform, and an initial subset and a next subset in the first subset being separated by a second number of consecutive data samples of the single instance of the pulse-canceled waveform, the second number being based on a product of the oversampling factor and a total number of output-canceled pulses that can be generated.

19. The non-transitory computer-readable medium of claim 18, wherein the computer-readable instructions are for causing one or more of the at least one processor circuits to access the individual data samples from a second memory storing a second subset of data samples of the single instance of the pulse-canceled waveform, the second subset comprising the first number of consecutive data samples of the single instance of the pulse-canceled waveform, an initial subset and a next subset of the second subsets being separated by the second number of consecutive data samples of the single instance of the pulse-canceled waveform, the second subset comprising data samples of the single pulse-canceled waveform that are different from the first subset, and the initial subset of the second subset comprising data samples of the single pulse-canceled waveform starting from a sample index corresponding to the oversampling factor.

20. The non-transitory computer-readable medium of claim 16, wherein to generate one or more output cancel pulses, the computer-readable instructions are for causing one or more of the at least one processor circuits to: providing each accessed data sample to one or more buffers corresponding to the one or more output cancel pulses, respectively; and The one or more buffers are configured based on one or more delays so that the one or more buffers output the one or more output cancellation pulses to suppress the one or more peaks of the input signal.

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