Pulse generator and memory device including the same

Abstract

A pulse generator and a memory device including the same are disclosed. The memory device includes: a cell array including a plurality of static random access memory (SRAM) cells; a row decoder configured to drive a plurality of word lines of the plurality of SRAM cells based on a row address; a data input / output circuit connected to a plurality of bit lines of the cell array and connected to a sub power supply line configured to supply a cell voltage to the plurality of SRAM cells; and a word line pulse generator configured to generate a word line pulse having a first pulse width that varies based on the row address, and supply the word line pulse to the row decoder.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0100451 filed on August 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present application relates to a semiconductor memory device, and more particularly, to a pulse generator using a row address tracking function and a memory device including the pulse generator. Background Art

[0003] The semiconductor memory device may include a static random access memory (SRAM) that stores data using a latch or a dynamic random access memory (DRAM) that stores data using a capacitor. Compared to DRAM, SRAM is difficult to integrate and thus provides a small capacity in the same area, but SRAM has advantages such as high-speed operation, low power consumption, and easy control, so SRAM is used in memories that require high-speed access, such as caches.

[0004] SRAM includes a plurality of bit cells arranged in rows and columns. Each bit cell includes a latch connected to a corresponding word line and a corresponding bit line. During a write operation or a read operation, a word line pulse is applied to the word line to select the bit cell. And during a write operation, a cell voltage or a write assist voltage VDDA is applied from a write assist circuit to adjust the power supply voltage of the bit cell.

[0005] Advances in microprocessing have made it possible to integrate more components per unit area of ​​semiconductor devices. Specifically, as miniaturization increases, the resistance of metal wires connecting the components of semiconductor devices increases. As the resistance value of the metal wire increases, the signal transmission characteristics change according to the distance. In order to compensate for these transmission characteristics and ensure reliability, methods of increasing the read margin or the write margin are used. However, increasing the read margin or the write margin ultimately reduces the power efficiency of the memory device. Summary of the invention

[0006] One or more embodiments of the present disclosure provide a pulse generator for a memory device whose pulse width varies according to the position of a selected row. In addition, one or more embodiments provide a memory device that can provide high power efficiency by using a pulse generator whose pulse width varies according to the position of a selected row.

[0007] According to aspects of an embodiment, a memory device includes: a cell array including a plurality of static random access memory (SRAM) cells; a row decoder configured to drive a plurality of word lines of the plurality of SRAM cells based on a row address; a data input / output circuit connected to a plurality of bit lines of the cell array and to a sub power line configured to supply a cell voltage to the plurality of SRAM cells; and a word line pulse generator configured to generate a word line pulse having a first pulse width that varies based on a row address, and provide the word line pulse to the row decoder.

[0008] According to aspects of an embodiment, a pulse generator of a static random access memory (SRAM) device includes: a pulse generating circuit configured to generate a first pulse signal based on a write enable signal or a read enable signal; a row address tracking circuit configured to generate a second pulse signal by delaying the first pulse signal based on a row address; and a logic gate unit configured to generate a word line pulse or a write assist pulse of the SRAM device by performing a logical multiplication operation of the first pulse signal and the second pulse signal.

[0009] According to aspects of an embodiment, a memory device includes: a cell array including a plurality of static random access memory (SRAM) cells; a row decoder configured to drive a plurality of word lines of the plurality of SRAM cells based on a row address; a data input / output circuit connected to a plurality of bit lines of the cell array; a write assist circuit configured to supply a cell voltage or a write assist voltage to the plurality of SRAM cells through a sub-power line; a word line pulse generator configured to generate a word line pulse having a first pulse width that varies based on a row address to provide the word line pulse to the row decoder; and a write assist pulse generator configured to generate a write assist pulse having a second pulse width that varies based on the row address. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing a memory device according to an embodiment; Figure 2 It is shown Figure 1 A diagram showing a detailed configuration of a cell array; Figure 3 is a circuit diagram showing the structure of a word line pulse generator according to an embodiment; Figure 4 It is shown Figure 3 A circuit diagram of the structure of a word line pulse generator shown in; Figure 5 It is shown Figure 4A waveform diagram of the operating characteristics of a word line pulse generator; Figure 6 is a table showing the power reduction effect of the word line pulse RowCK according to the embodiment; Figure 7 is a circuit diagram showing the structure of a word line pulse generator according to another embodiment; Figure 8 It is shown Figure 7 A circuit diagram of the structure of a word line pulse generator shown in; Fig. 9 is a circuit diagram showing the structure of a write assist pulse generator according to an embodiment; Fig.10 It is shown Fig. 9 A circuit diagram of the structure of a write assist pulse generator shown in FIG. Fig.11 It is shown Fig.10 A waveform diagram of the operating characteristics of a write assist pulse generator; Fig.12 is a table showing the power reduction effect of the write assist pulse WAST_EN according to the embodiment; Fig.13 is a circuit diagram showing another implementation method of a word line pulse generator or a write assist pulse generator with a row address tracking function according to an embodiment; Fig.14A and Fig. 14B They are shown respectively Fig.13 A circuit diagram of an embodiment of a digitally controlled delay line; and Fig.15 is a block diagram exemplarily showing a structure of a mobile device including a memory device of an embodiment. DETAILED DESCRIPTION

[0011] It should be understood that both the foregoing general description and the following detailed description are exemplary. Reference numerals are indicated in detail in the embodiments, and examples of reference numerals are indicated in the reference drawings. Wherever possible, the same reference numerals are used in the specification and drawings to refer to the same or similar parts.

[0012] Below, the aspects and advantages of the present disclosure will be explained using SRAM as an example. However, those skilled in the art will easily understand other advantages and capabilities of the present disclosure based on the content described herein. The present disclosure can be implemented or applied through other embodiments. In addition, the detailed description can be modified or changed according to the perspective and application without significantly departing from the scope of the present disclosure, the technical spirit and other purposes.

[0013] Figure 1 is a block diagram showing a memory device according to an embodiment. Figure 1, the memory device 1000 may include a cell array 1100 , a row decoder 1200 , a data input / output (I / O) circuit 1300 , a column decoder 1400 , and a control logic circuit 1500 .

[0014] The cell array 1100 may include a plurality of SRAM cells or bit cells storing data. Each of the plurality of bit cells included in the cell array 1100 may be arranged at a point where a plurality of word lines WL intersects a plurality of bit lines BL. For example, each bit cell may be connected to a corresponding word line among a plurality of word lines WL. Each bit cell may be connected to a corresponding bit line among a plurality of bit lines BL. The bit cell may be selected by providing a word line voltage VWL to the selected word line. The bit cell may use a cell voltage VDDA to store or output data. Specifically, during a write operation, the bit cell is driven by receiving a cell voltage VDDA provided from a write assist circuit to improve write performance.

[0015] The row decoder 1200 decodes the row address R_ADDR and selects one of the multiple word lines WL according to the decoding result. During the write operation, the row decoder 1200 transmits the word line voltage VWL to a word line selected by the row address R_ADDR in the form of a pulse. And, the row decoder 1200 supplies the word line voltage VWL of the low level "L" to the word line not selected by the row address R_ADDR. Specifically, the row decoder 1200 uses the word line pulse RowCK generated by the word line pulse generator 1520 of the control logic circuit 1500 to provide the word line voltage VWL to the selected word line.

[0016] The data input / output circuit 1300 is connected to the cell array 1100 through a plurality of bit lines BL. The data input / output circuit 1300 writes data to the selected bit cell through the bit line during a write operation. During a read operation, the data input / output circuit 1300 may output the sensed data to the outside through the bit line. For example, the data input / output circuit 1300 may include a write driver and a sense amplifier. Specifically, the data input / output circuit 1300 may include a write assist circuit that adjusts the cell voltage VDDA during a write operation to improve write performance. The write assist circuit may adjust the falling time of the cell voltage VDDA according to the row address in response to a write assist enable signal WAST_EN.

[0017] The column decoder 1400 receives a column address C_ADDR from the control logic circuit 1500. The column decoder 1400 decodes the column address C_ADDR. The column decoder 1400 selects a bit line corresponding to the column address C_ADDR from among a plurality of bit lines BL connected to the cell array 1100 according to the decoding result. For example, the column decoder 1400 connects the bit line BL corresponding to the column address C_ADDR to a write driver or a sense amplifier.

[0018] The control logic circuit 1500 receives a command CMD, an address ADDR, and a clock signal CLK from an external device (e.g., a host or a central processing unit (CPU)) of the memory device 1000. The control logic circuit 1500 may control the operation of the memory device 1000 based on the clock signal CLK received from the external device. The control logic circuit 1500 may extract a row address R_ADDR and a column address C_ADDR from the received address ADDR, and transmit the row address R_ADDR to the row decoder 1200 and the column address C_ADDR to the column decoder 1400.

[0019] Specifically, the control logic circuit 1500 includes a word line pulse generator 1520 and a write assist (WAST) pulse generator 1540. The control logic circuit 1500 may also include a command decoder for decoding a received command CMD. The control logic circuit 1500 decodes the command CMD and activates the word line pulse generator 1520 or the write assist pulse generator 1540 during a write operation or a read operation.

[0020] The word line pulse generator 1520 may generate a word line pulse RowCK whose pulse width varies according to the row address R_ADDR during a write operation or a read operation. When a bit cell (hereinafter referred to as a near cell) close to the data input / output circuit 1300 is selected, the word line pulse generator 1520 generates a word line pulse RowCK having a relatively narrow pulse width. On the other hand, when a bit cell (hereinafter referred to as a far cell) located at a long distance from the data input / output circuit 1300 is selected, the word line pulse generator 1520 generates a word line pulse RowCK having a relatively wide pulse width. In other words, the word line pulse generator 1520 generates a word line pulse RowCK whose pulse width varies according to the row address R_ADDR. Then, the row decoder 1200 will use the word line pulse RowCK provided by the word line pulse generator 1520 to generate a word line voltage VWL.

[0021] The write assist pulse generator 1540 generates the defined write assist circuit 1360 (see Fig. 9, described later). The write assist pulse generator 1540 generates a write assist pulse WAST_EN whose pulse width varies according to the row address R_ADDR. When the near cell is selected, the write assist pulse generator 1540 generates a write assist pulse WAST_EN with a relatively narrow pulse width. On the other hand, when the far cell is selected, the write assist pulse generator 1540 generates a write assist pulse WAST_EN with a relatively wide pulse width. That is, the write assist pulse generator 1540 can generate a write assist pulse WAST_EN whose pulse width varies according to the row address R_ADDR. Then, the write assist circuit will cause the cell voltage VDDA to drop during the period corresponding to the write assist pulse WAST_EN.

[0022] In the above, the configuration of the memory device 1000 that generates the word line pulse RowCK or the write auxiliary pulse WAST_EN whose pulse width is adjusted according to the row address R_ADDR is briefly described. When the memory cell is selected based on the word line pulse RowCK, the bit line development size of the near cell and the far cell can be kept constant. Therefore, the power consumption caused by the excessive development of the bit line occurring in the near cell can be reduced. In addition, by changing the falling section of the cell voltage VDDA based on the write auxiliary pulse WAST_EN according to the row address R_ADDR, the power consumption caused by the excessive drop of the cell voltage VDDA occurring in the near cell can be reduced.

[0023] The memory device 1000 may be implemented with SRAM, but is not limited thereto. For example, in some embodiments, the memory device 1000 may include one of a dynamic random access memory (DRAM), a NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a ferroelectric random access memory (FRAM), a phase change random access memory (PRAM), and a magnetic random access memory (MRAM).

[0024] Figure 2 It is shown Figure 1 A diagram showing the detailed structure of a cell array. Figure 2 , a bit cell corresponding to one column is shown. Each of the bit cells BC1 to BCn may be formed at a point where the word lines WL1 to WLn intersect the bit line pairs (BLT, BLC). Hereinafter, the characteristics of each of the bit cells BC1 to BCn-1 will be described by taking the configuration of the bit cell BCn as an example.

[0025] The bit cell BCn may include a plurality of transistors PG1, PG2, PU1, PU2, PD1, and PD2 connected to a bit line pair (BLT, BLC) or a word line WLn. The plurality of transistors may include a pair of pass transistors (PG1, PG2), a pair of pull-up transistors (PU1, PU2), and a pair of pull-down transistors (PD1, PD2). The pull-up transistors PU1 and PU2 may be P-type metal oxide semiconductor (PMOS) transistors, and the pull-down transistors PD1 and PD2 and the pass transistors PG1 and PG2 may be N-type metal oxide semiconductor (NMOS) transistors.

[0026] The gates of the pass transistors PG1 and PG2 may be connected to the word line WLn, and the drains may be connected to the bit line pair BLT and BLC. The sources of the pull-up transistors PU1 and PU2 are connected to the sub power line SPL supplying the cell voltage VDDA. The sources of the pull-down transistors PD1 and PD2 are connected to the ground (VDD). The first pull-up transistor PU1 and the first pull-down transistor PD1 form an inverter, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter. The input terminal and the output terminal of each inverter are interconnected to form a latch that can store data.

[0027] The pass transistors PG1 and PG2 are turned on by the word line voltage VWL supplied to the word line WLn, thereby enabling reading or writing of the bit cell BCn. During the read operation, the data stored in the bit cell BCn can be output by a sense amplifier that senses the voltage level developed in the bit line pair (BLT, BLC). During the write operation, the latch of the bit cell BCn is set to "0" or "1" by a data signal sent from the write driver to the bit line pair (BLT, BLC). At this time, the write assist circuit that reduces the cell voltage VDDA is activated to improve the write performance of the latch. Then, the level of the cell voltage VDDA can be reduced, and the write performance of the latch can be improved.

[0028] Typically, each bit line pair (BLT, BLC) is formed using a metal pattern of a bit line formed on the same semiconductor layer. The bit line voltage provided by the write driver will be sent to the latch of the bit cell that intersects any one selected from the word lines WL1 to WLn. For example, if the word line WLn is selected, the data will be written to the bit cell BCn through the node (Nn, / Nn) where the bit line pair (BLT, BLC) intersects the bit cell BCn. Similarly, when the word line WL1 is selected, the data will be written to the bit cell BC1 through the node (N1, / N1) where the bit line pair (BLT, BLC) intersects the bit cell BC1. During the read operation, the level of the bit line pair (BLT, BLC) developed by the stored data of the selected bit cell is sensed by the sense amplifier.

[0029] In addition, a cell voltage VDDA to be used as a driving power source for each of the bit cells BC1 to BCn is transmitted to each of the bit cells BC1 to BCn through the sub power source line SPL The cell voltage VDDA is generated in a write assist circuit.

[0030] The bit line pair (BLT, BLC) or the sub power line SPL is formed as a conductive wire. For example, the bit line pair (BLT, BLC) or the sub power line SPL may be formed using a metal wire. However, as the process becomes finer, the resistance of the bit line pair (BLT, BLC) or the sub power line SPL increases. Each bit line pair (BLT, BLC) will have a greater resistance R as it moves away from the data input / output circuit 1300. BL The resistance R of the sub-power line SPL VDDA The resistance value will also be larger as it is farther away from the data input / output circuit 1300. Also, the bit line pair (BLT, BLC) or the sub power line SPL includes a parasitic capacitance Cb. Therefore, the magnitude of the voltage drop or time constant that occurs varies depending on the length of the bit line pair (BLT, BLC) or the sub power line SPL.

[0031] By applying a word line pulse RowCK or a write auxiliary pulse WAST_EN whose pulse width is adjusted according to the row address R_ADDR, the bit line voltage change in the near cell and the far cell can be controlled to be constant or controlled to a level that minimizes power consumption. In other words, during a read operation by a word line pulse RowCK adjusted according to the row address R_ADDR, in the case of a near cell, the development time of the bit line can be provided shorter than the development time of the bit line of the far cell. Therefore, the power consumed by the bit line recovery can be reduced. In addition, during a write operation, the falling section of the cell voltage VDDA based on the write auxiliary pulse WAST_EN can vary according to the row address R_ADDR. Then, the power consumption caused by the excessive drop of the cell voltage VDDA occurring in the near cell can be reduced.

[0032] Figure 3 is a circuit diagram showing the structure of a word line pulse generator according to an embodiment. Figure 3 , the word line pulse generator 1520 generates a word line pulse RowCK having a pulse width that varies according to the row address R_ADDR. The word line voltage VWL is provided to the bit cells of the selected row based on the word line pulse RowCK. Here, since the cell array 1100 is connected to the Figure 2 The cell arrays are substantially the same, so their description will be omitted. The word line pulse generator 1520 may be set to Figure 1 Part of the control logic circuit 1500.

[0033] The row address decoder 1220 and the pulse transfer circuit 1240 may be included as part of the row decoder 1200. The row address decoder 1220 decodes the input row address R_ADDR and activates the selected word line. For example, when the row address R_ADDR corresponds to the word line WL2, the row address decoder 1220 sets the word line WL2 to a high level "H" and sets the remaining word lines WL1, WL3 to WLn to a low level "L".

[0034] The pulse transmission circuit 1240 transmits the word line pulse RowCK generated by the word line pulse generator 1520 to the selected row. If the row address decoder 1220 selects the word line WLn, the word line pulse RowCK provided from the word line pulse generator 1520 will be sent to the selected word line WLn. The pulse transmission circuit 1240 may include a NAND gate and an inverter corresponding to each row.

[0035] The sense amplifier (SA) 1320 and the write driver (WD) 1340 are provided as part of the data input / output circuit 1300. The sense amplifier 1320 can sense the data of the selected bit cell in response to the sense enable signal SA_EN. The output of SA1320 is the output data Dout. That is, the sense amplifier 1320 detects the level change of the bit line pair (BLT, BLC) developed from the bit cell of the selected row during the read operation. During the write operation, the write driver 1340 transmits the input data Din to the selected bit cell via the bit line pair (BLT, BLC). The multiplexer (MUX) 1420 responds to the data from the column decoder 1400 (see Figure 1 ) to select one of the plurality of bit line pairs. Dout and Din are the signals flowing out and into the data input / output circuit 1300, respectively. Figure 1 Example of the signal DATA.

[0036] The word line pulse generator 1520 may include a pulse generating circuit 1522 , an inverter 1524 , a row address tracking circuit 1526 , a dummy line 1527 , a NAND gate 1528 , an inverter INV, and a column tracking circuit CT.

[0037] The pulse generation circuit 1522 is activated according to the access mode. For example, when the write enable signal / WEN or the read enable signal / REN is activated, the pulse generation circuit 1522 generates a first pulse signal ICK based on the clock signal CK. The first pulse signal ICK is sent to the column tracking circuit CT and the NAND gate 1528, respectively.

[0038] Inverter 1524 includes a pull-up transistor M1 and a pull-down transistor M2. The pull-up transistor M1 may be formed as a PMOS transistor, and the pull-down transistor M2 may be formed as an NMOS transistor. Specifically, the pull-down transistor M2 of inverter 1524 is connected to a row address tracking circuit 1526. Therefore, the characteristics of the pull-down operation of inverter 1524 may vary according to the row address R_ADDR. For example, if a far cell is selected and a large resistance is tracked by the row address tracking circuit 1526, the pull-down speed of inverter 1524 is reduced. As a result, the level drop speed of the output node DBL of inverter 1524 will also decrease. When the level drop rate of the output node DBL slows down, the pulse width of the word line pulse RowCK output by NAND gate 1528 and inverter INV increases.

[0039] On the other hand, if a near cell is selected and a relatively small resistance is tracked by the row address tracking circuit 1526, the pull-down speed of the inverter 1524 increases. Therefore, the level falling rate of the output node DBL of the inverter 1524 will also increase. When the level falling rate of the output node DBL increases, the pulse width of the word line pulse RowCK output through the NAND gate 1528 and the inverter INV decreases.

[0040] The row address tracking circuit 1526 includes a plurality of select transistors DT1 to DTn sharing a drain. The drain of each of the plurality of select transistors DT1 to DTn sharing a drain is connected to the source of the pull-down transistor M2. A metal line may be formed to connect the source of the pull-down transistor M2 to each of the plurality of select transistors DT1 to DTn. When the row address R_ADDR activates the word line WL1 to select a near cell, the select transistor DT1 is turned on. The row address tracking circuit 1526 may then provide a relatively small pull-down resistor to the inverter 1524. On the other hand, when the row address R_ADDR activates the word line WLn to select a far cell, the select transistor DTn is turned on. The row address tracking circuit 1526 may then provide a relatively large pull-down resistor to the inverter 1524.

[0041] The dummy line 1527 may be implemented as a dummy wire having a length corresponding to a wire (e.g., a metal wire) for supplying a cell voltage or a bit line voltage to a bit cell of the cell array 1100. The capacitors c1 to cn may be provided to the output node DBL of the inverter 1524 through the dummy line 1527. In one example, the dummy line 1527 may extend in a bit line direction.

[0042] The column tracking circuit CT delays the first pulse signal ICK by a time corresponding to the number of columns of the cell array 1100. The column tracking circuit CT may be formed using, for example, wiring such as a word line or a dummy word line. The first pulse signal ICK may be delayed by a time corresponding to the number of columns through the column tracking circuit CT and sent to the inverter 1524.

[0043] In the above, the row address tracking function of the word line pulse generator 1520 and the change of the pulse width of the word line pulse RowCK are briefly explained. The word line pulse generator 1520 is activated during a write operation or a read operation, and generates a word line pulse RowCK having a pulse width corresponding to the input row address R_ADDR. And, a word line voltage VWL corresponding to the width of the generated word line pulse RowCK will be supplied to the selected word line.

[0044] Figure 4 It is shown Figure 3 The circuit diagram of the structure of the word line pulse generator is shown in FIG. Figure 4 The word line pulse generator 1520 includes a pulse generating circuit 1522, a column tracking circuit CT, an inverter 1524, a row address tracking circuit 1526, a NAND gate 1528 and an inverter INV.

[0045] The pulse generating circuit 1522 can be activated in any operation mode using the word line pulse RowCK. That is, in response to the write enable signal / WEN or the read enable signal / REN in the write operation mode or the read operation mode, the pulse generating circuit 1522 generates the first pulse signal ICK based on the clock signal CK.

[0046] The column tracking circuit CT may delay the first pulse signal ICK based on the number of columns of the cell array 1100. For example, the column tracking circuit CT delays the first pulse signal ICK by a time corresponding to the number of columns of the cell array 1100. And the delayed first pulse signal ICK is provided to the inverter 1524.

[0047] The inverter 1524 inverts the first pulse signal ICK delayed by the column tracking circuit CT and sends it to the output node DBL. The inverter 1524 includes a pull-up transistor M1 and a pull-down transistor M2 that receive the first pulse signal ICK at the gate. The pull-down transistor M2 of the inverter 1524 is connected to the row address tracking circuit 1526. The amount of charge discharged by the pull-down transistor M2 of the inverter 1524 depends on the size of the tracking resistor Rxadd formed in the row address tracking circuit 1526. That is, the pull-down speed of the inverter 1524 can be changed according to the row address R_ADDR, and the row address R_ADDR determines the resistance of the row address tracking circuit 1526.

[0048] The row address tracking circuit 1526 can adjust the pull-down speed of the inverter 1524 based on the row address R_ADDR. For example, the row address tracking circuit 1526 provides a tracking resistor Rxadd of a size corresponding to the row selected by the row address R_ADDR. When the tracking resistor Rxadd is large, the pull-down speed of the inverter 1524 is reduced. On the other hand, when the size of the tracking resistor Rxadd is small, the pull-down speed of the inverter 1524 is increased.

[0049] The level switching speed of the output node DBL of the inverter 1524 is determined according to the tracking resistor Rxadd, which varies according to the row address R_ADDR. If the far cell is selected and a relatively large tracking resistor Rxadd is set, the falling time of the level of the output node DBL increases. Therefore, the pulse width of the word line pulse RowCK corresponding to the logical product (or, AND operation) of the output node DBL and the first pulse signal ICK increases. On the other hand, if the near cell is selected and a relatively small tracking resistor Rxadd is set, the falling time of the level of the output node DBL is reduced. Therefore, the pulse width of the word line pulse RowCK corresponding to the logical product (or, AND operation) of the output node DBL and the first pulse signal ICK decreases.

[0050] In the above, an exemplary structure of the word line pulse generator 1520 that generates the word line pulse RowCK whose pulse width varies according to the row address R_ADDR has been described. It will be understood that the structure of the word line pulse generator 1520 or the structure of the row address tracking circuit 1526 is not limited to the method shown, and various changes are possible. Figure 4 In, C DBL π may represent the parasitic capacitance of the output node DBL of the inverter 1524 .

[0051] Figure 5 It is shown Figure 4 The waveform diagram of the operating characteristics of the word line pulse generator. Figure 5 , the pulse width of the word line pulse RowCK output from the word line pulse generator 1520 may be adjusted according to the input row address R_ADDR.

[0052] At time T0, it is assumed that the read enable signal / REN or the write enable signal / WEN is in an inactive state. Then, the level of the first pulse signal ICK is generated at a low level "L". And the output node DBL of the inverter 1524 will maintain a high level "H".

[0053] At time T1, when the read enable signal / REN or the write enable signal / WEN is activated, the pulse generating circuit 1522 (see Figure 4) sets the first pulse signal ICK to a high level “H”. The word line pulse RowCK corresponding to the logical product (or, AND operation) between the high level first pulse signal ICK and the output node DBL turns to a high level “H”.

[0054] At time T2, the word line is activated by the row address R_ADDR, and the pull-down of the inverter 1524 by the row address tracking circuit 1526 begins. If the row address R_ADDR is set to "000...0" to select the word line WL1 of the near cell, the tracking resistance Rxadd provided by the row address tracking circuit 1526 is relatively small. Therefore, the pull-down speed of the inverter 1524 is set to high. Finally, the voltage drop at the output node DBL of the inverter 1524 will appear in the form of curve C1. The word line pulse RowCK can be generated by the output node DBL in the form of a narrowest pulse width PW1 corresponding to the curve C1.

[0055] On the other hand, the row address R_ADDR is set to "111 ... 1" to select the word line WLn of the far cell, and the tracking resistor Rxadd provided by the row address tracking circuit 1526 will be set to the maximum value. In this case, the pull-down speed of the inverter 1524 is set to the lowest. Finally, the voltage drop at the output node DBL of the inverter 1524 will appear in the form of a curve Cn. The word line pulse RowCK can be generated by the output node DBL in the form of a widest pulse width PWn corresponding to the curve Cn. In this way, the pulse width of the word line pulse RowCK can be adjusted to various sizes according to the row address R_ADDR.

[0056] At time T3, the pulse section of the first pulse signal ICK ends. That is, the first pulse signal ICK is restored from the high level to the low level "L".

[0057] At time T4, after the recovery of the first pulse signal ICK, the output node DBL of the inverter 1524 also turns to the high level “H”.

[0058] As described above, the word line pulse generator 1520 can generate a word line pulse RowCK whose pulse width is adjusted using the tracking function of the row address R_ADDR. By using the word line pulse RowCK whose pulse width is adjusted according to the row address R_ADDR, the bit line development section of the near cell can be reduced during the read operation. Therefore, the power consumption caused by the excessive drop in the development level of the bit line when selecting the near cell can be reduced. In addition, when using the word line pulse RowCK whose pulse width is adjusted according to the row address R_ADDR, the distribution of the effective window width of the word line voltage provided to the near cell and the far cell can be reduced during the write operation.

[0059] In the above, the operation characteristics of the word line pulse generator 1520 that generates the word line pulse RowCK whose pulse width varies according to the row address R_ADDR have been described.

[0060] Reference Figure 3 and Figure 5 In general, the rising edge of the clock pulse (or, pulse or first pulse signal) ICK flows through the NAND gate 1528 and provides a high input RowCK to the NAND gate in the pulse transmission circuit 1240. The inverter 1524 or ICK will act at a certain time to cause the falling edge of RowCK. For the near word line (e.g., the word line connected to the near cell), this time is shorter. For the waveform on the output node DBL, see Figure 5 This shorter time provides charge in a shorter time and acts on the near word line with the appropriate amount of energy. Figure 2 For a far word line (e.g., a word line connected to a far cell), the time is longer before inverter 1524 takes effect. See Figure 5 However, the falling edge of pulse ICK may cause the output of NAND gate 1528 to change before Cn has been pulled down. A longer time provides more charge to ensure Figure 2 The bit cell latch changes state as needed. Inverter 1544 receives an asserted signal (low) from the drain of the select transistor of the row address tracking circuit 1526 connected to the word line being driven high by the row address decoder 1220. There is a delay in this asserted signal depending on the distance to the word line being driven. A delayed version of ICK is fed to the gate line of inverter 1524. When the asserted signal from the drain of the select transistor pulls the input of inverter 1524 down, DBL is driven low until the end of the clock pulse that has traveled through the column tracking circuit CT.

[0061] Figure 6 TABLE 1 is a table showing the effect of reducing power consumption by the word line pulse RowCK. Figure 6 , the changes of the word line voltage VWL and the bit line voltage VBL in each far cell and near cell during the read operation and the write operation are shown. Here, the far cell will be a bit cell connected to the word line WLn, and the near cell will be a bit cell connected to the word line WL1. However, the near cell and the far cell are not limited to the examples of the present disclosure.

[0062] During a read operation, when a word line WLn for selecting a far cell is selected, a word line voltage VWL having a pulse width PW_WL_f corresponding to the word line pulse RowCK will be provided to the selected bit cell. Then, the bit line pair (BLT, BLC) is developed according to the data state of the bit cell. For example, the voltage of the bit line BLT indicated by the dotted line may be maintained, and the voltage of the complementary bit line BLC may be developed by the first voltage difference ΔVBL_f. Since the distribution resistance of the complementary bit line BLC is relatively large according to the selection of the word line WLn, the development speed of the complementary bit line BLC is relatively slow. According to an embodiment, a word line voltage VWL having a relatively wide pulse width PW_WL_f may be provided, and as a result, a read margin may be ensured.

[0063] On the other hand, when the word line WL1 for selecting the near cell is selected during the read operation, the word line pulse RowCK reflecting the row address tracking function will be generated. And the word line voltage VWL having a pulse width PW_WL_n corresponding to the word line pulse RowCK will be provided to the selected bit cell. Then, the bit line pair (BLT, BLC) is developed according to the data state of the bit cell. For example, the voltage of the bit line BLT indicated by the dotted line can be maintained, and the voltage of the complementary bit line BLC can be developed by the second voltage difference ΔVBL_n. Since the distributed resistance of the complementary bit line BLC is relatively small according to the selection of the word line WL1 corresponding to the near cell, the development speed of the complementary bit line BLC is relatively fast compared to the far cell. Therefore, when the word line voltage VWL having a relatively narrow pulse width PW_WL_n is provided, power consumption caused by excessive reduction of the bit line development level can be prevented. Even if the development speed of the bit line is fast according to the word line voltage VWL of the pulse width PW_WL_n, the time for developing the bit line can be reduced. Therefore, the second voltage difference ΔVBL_n, which is a development level of the bit line in the near cell, may be set to be the same as or similar to the first voltage difference ΔVBL_f, which is a development level of the bit line in the far cell.

[0064] During the write operation, the word line voltage VWL reflecting the row address tracking function is used. When the word line (eg, WLn) for selecting a far cell is selected, the word line voltage VWL having a pulse width PW_WL_f corresponding to the word line pulse RowCK will be provided to the selected bit cell. Then, the write driver 1340 (see Figure 3) transmits the write data to the selected bit cell through the bit line pair (BLT, BLC). At this time, the voltage of the bit line to which the write data corresponding to the low level "L" is transferred drops to a low level. Because the distributed resistance of the bit line is large, the voltage drop rate of the far cell is lower than the voltage drop rate of the near cell. In other words, the slope of the bit line voltage (solid line) is relatively gentle. Therefore, the time when the write data is written into the latch of the bit cell will correspond to the effective write window EWW_f shown.

[0065] On the other hand, when the word line (e.g., WL1) for selecting a near cell is selected during a write operation, a word line voltage VWL having a pulse width PW_WL_n corresponding to the word line pulse RowCK is applied to the selected bit cell. Then, the write driver 1340 transmits the write data to the selected bit cell through the bit line pair (BLT, BLC). At this time, the bit line voltage (solid line) to which the write data corresponding to the low level "L" is transferred drops to a low level. Because the distributed resistance of the bit line is small, the voltage drop rate of the near cell is higher than the voltage drop rate of the far cell. That is, the slope of the bit line voltage is relatively steep. Therefore, as shown, the time when the write data is written to the latch of the bit cell will correspond to the effective write window EWW_n.

[0066] As described above, the memory device 1000 according to the present disclosure can generate a word line voltage VWL whose pulse width is adjusted using the tracking function of the row address R_ADDR. By using the word line voltage VWL whose pulse width is adjusted according to the row address R_ADDR, the excessive development of the bit line occurring in the near cell can be reduced. Therefore, the power consumption caused by the excessive bit line development occurring in the near cell can be reduced. In addition, when using the word line voltage VWL whose pulse width is adjusted according to the row address R_ADDR, the distribution of the effective window width of the word line voltage VWL provided to the near cell and the far cell can be reduced during the write operation.

[0067] Figure 7 is a circuit diagram showing the structure of a word line pulse generator according to another embodiment. Figure 7 , the word line pulse generator 1520' can generate a word line pulse RowCK having a pulse width that varies according to the row address R_ADDR without using the column tracking circuit CT. The word line voltage VWL is provided to the bit cell of the selected row based on the word line pulse RowCK. Here, the cell array 1100, the row address decoder 1220, the pulse transmission circuit 1240, the multiplexer 1420, the sense amplifier 1320, and the write driver 1340 are connected with Figure 3 The cell array 1100, the row address decoder 1220, the pulse transfer circuit 1240, the multiplexer 1420, the sense amplifier 1320, and the write driver 1340 in FIG. 1 are substantially the same. Therefore, their description will be omitted.

[0068] The word line pulse generator 1520′ according to another embodiment is similar to the word line pulse generator 1520′ according to another embodiment, except that the word line pulse generator 1520′ according to another embodiment does not include the column tracking circuit CT. Figure 3 The word line pulse generator 1520 has the same configuration. For example, in the case of applying a memory device 1000 with a fixed number of columns, a separate column tracking function may not be necessary. In this case, the first pulse signal ICK output from the pulse generating circuit 1522 may be immediately provided to the inverter 1524 without a delay according to the number of columns.

[0069] In the above, the row address tracking function of the word line pulse generator 1520' and the change of the generation of the pulse width of the word line pulse RowCK are briefly explained. The word line pulse generator 1520' is activated during a write operation or a read operation without a separate column tracking function, and can generate a word line pulse RowCK having a pulse width corresponding to the input row address R_ADDR. The word line voltage VWL corresponding to the width of the generated word line pulse RowCK can be supplied to the selected word line.

[0070] Figure 8 It is shown Figure 7 The circuit diagram of the structure of the word line pulse generator is shown in FIG. Figure 8 According to another embodiment, a word line pulse generator 1520' includes a pulse generating circuit 1522, an inverter 1524, a row address tracking circuit 1526, a NAND gate 1528, and an inverter INV.

[0071] The pulse generating circuit 1522 can be activated in any operation mode using the word line pulse RowCK. That is, in the write operation mode and the read operation mode of the cell array 1100, the pulse generating circuit 1522 generates the first pulse signal ICK based on the clock signal CK in response to the write enable signal / WEN or the read enable signal / REN, respectively.

[0072] The inverter 1524 inverts the first pulse signal ICK and sends it to the output node DBL. The inverter 1524 includes a pull-up transistor M1 and a pull-down transistor M2 that receive the first pulse signal ICK at the gate. The pull-down transistor M2 of the inverter 1524 is connected to the row address tracking circuit 1526. The amount of charge discharged by the pull-down transistor M2 of the inverter 1524 depends on the size of the tracking resistor Rxadd formed in the row address tracking circuit 1526. That is, the pull-down speed of the inverter 1524 can be changed according to the row address R_ADDR, and the row address R_ADDR determines the resistance of the row address tracking circuit 1526.

[0073] The row address tracking circuit 1526 provides a tracking resistor Rxadd of a size corresponding to the row selected by the row address R_ADDR. When the tracking resistor Rxadd is large, the pull-down speed of the inverter 1524 is reduced. On the other hand, when the size of the tracking resistor Rxadd is small, the pull-down speed of the inverter 1524 is increased.

[0074] The level switching speed of the output node DBL of the inverter 1524 is determined according to the tracking resistor Rxadd, which varies according to the row address R_ADDR. In one example, the NAND gate 1526 and the inverter INV may perform a logical multiplication operation (e.g., a logical product operation (or, AND operation)) on the output of the inverter 1524 and the first pulse signal ICK to output the word line pulse RowCK. If the far cell is selected and a relatively large tracking resistor Rxadd is set, the falling time of the level of the output node DBL increases. Therefore, the pulse width of the word line pulse RowCK corresponding to the logical product (or, AND operation) of the output node DBL and the first pulse signal ICK increases. On the other hand, if the near cell is selected and a relatively small tracking resistor Rxadd is set, the falling time of the level of the output node DBL decreases. Therefore, the pulse width of the word line pulse RowCK corresponding to the logical product (or, AND operation) of the output node DBL and the first pulse signal (ICK) decreases.

[0075] Above, an exemplary structure of the word line pulse generator 1520' that generates the word line pulse RowCK whose pulse width varies according to the row address R_ADDR has been described. It will be well understood that the structure of the word line pulse generator 1520' or the structure of the row address tracking circuit 1526 is not limited to the illustrated method, and various changes are possible.

[0076] Fig. 9 is a circuit diagram showing the structure of a write assist pulse generator according to an embodiment. Fig. 9 , the write assist pulse generator 1540 may generate a write assist pulse WAST_EN having a pulse width that varies according to the row address R_ADDR. Using the write assist pulse WAST_EN, the write assist circuit 1360 may supply a cell voltage VDDA having a write assist function to the bit cell of the selected row. The write assist pulse generator 1540 may be set to Figure 1 Part of the control logic circuit 1500.

[0077] The cell array 1100 includes a plurality of bit cells arranged in rows and columns. The sub power line SPL may be formed in a direction parallel to the bit line to transmit a cell voltage VDDA having a write assist function to the bit cell. When the cell voltage VDDA is supplied from the write assist circuit 1360, the write performance is affected by the resistance R caused by the sub power line SPL. VDDA Influence.

[0078] By applying a write assist pulse WAST_EN whose pulse width is adjusted according to the row address R_ADDR, the change of the write assist voltage of the near cell and the far cell can be controlled to be constant. In other words, by the write assist pulse WAST_EN whose pulse width is adjusted according to the row address R_ADDR, during the write operation, the drop of the cell voltage VDDA of the near cell can be set to be equal to or less than the drop of the cell voltage VDDA of the far cell. Therefore, the power consumption caused by the drop of the cell voltage VDDA of the near cell can be reduced.

[0079] The row address decoder 1220 and the pulse transfer circuit 124 are included in the row decoder 1200. The row address decoder 1220 decodes the input row address R_ADDR and activates the selected word line. For example, when the row address R_ADDR corresponds to the word line WL2, the row address decoder 1220 may set the word line WL2 to a high level "H" and set the remaining word lines WL1, WL3 to WLn to a low level "L". In addition, when the selected word line is activated, one of the plurality of selection transistors DT1 to DTn of the row address tracking circuit 1546 connected to the selected word line may be turned on.

[0080] The pulse transmission circuit 1240 transmits the word line pulse generator 1520 (see Figure 3 ) is transmitted to the bit cells of the selected row. If the row address decoder 1220 activates the word line WLn, the word line pulse RowCK provided from the word line pulse generator 1520 will be sent to the selected bit cell. The pulse transmission circuit 1240 may include a NAND gate and an inverter corresponding to each row.

[0081] The write assist pulse generator 1540 may include a pulse generating circuit 1542 , an inverter 1544 , a row address tracking circuit 1546 , a dummy line 1547 , a NAND gate 1548 , and an inverter INV.

[0082] The pulse generation circuit 1542 is activated according to the access mode. For example, when the write enable signal / WEN is activated, the pulse generation circuit 1542 generates a second pulse signal WAST based on the clock signal CK. The second pulse signal WAST is sent to the inverter 1544 and the NAND gate 1548, respectively.

[0083] Inverter 1544 includes a pull-up transistor M3 and a pull-down transistor M4. The pull-up transistor M3 may be formed as a PMOS transistor, and the pull-down transistor M4 may be formed as an NMOS transistor. Specifically, the pull-down transistor M4 of inverter 1544 is connected to a row address tracking circuit 1546, and the row address tracking circuit 1546 may adjust the pull-down speed of inverter 1544 based on the row address R_ADDR. Therefore, the pull-down operation of inverter 1544 may vary according to the row address R_ADDR. For example, if a far cell is selected and a large resistance is tracked by the row address tracking circuit 1546, the pull-down speed of inverter 1544 is reduced. Therefore, the level drop rate of output node DWAST of inverter 1544 will also decrease. When the level drop speed of output node DWAST slows down, the pulse width of the write auxiliary pulse WAST_EN output by NAND gate 1548 and inverter INV increases.

[0084] On the other hand, if the near cell is selected and a relatively small resistance is tracked by the row address tracking circuit 1546, the pull-down speed of the inverter 1544 increases. Therefore, the level falling speed of the output node DWAST of the inverter 1544 will also increase. As the level falling speed of the output node DBL increases, the pulse width of the write assist pulse WAST_EN output through the NAND gate 1548 and the inverter INV decreases.

[0085] The row address tracking circuit 1546 includes a plurality of select transistors DT1 to DTn sharing a drain. The drain of each of the plurality of select transistors DT1 to DTn sharing a drain is connected to the source of the pull-down transistor M4. When the row address R_ADDR activates the word line WL1 to select a near cell, the select transistor DT1 is turned on. Then, the row address tracking circuit 1546 may provide a relatively small pull-down resistor to the inverter 1544. On the other hand, when the row address R_ADDR activates the word line WLn to select a far cell, the select transistor DTn is turned on. Then, the row address tracking circuit 1546 may provide a relatively large pull-down resistor to the inverter 1544.

[0086] The dummy line 1547 is implemented as a dummy wire corresponding to a wire (e.g., a metal wire) for supplying a cell voltage VDDA having a write assist function to a bit cell of the cell array 1100. Capacitances c1 to cn corresponding to a bit line or a sub power line SPL may be reflected in an output node DWAST of the inverter 1544 through the dummy line 1547. In one example, the dummy line 1547 may extend in a bit line direction.

[0087] The write assist circuit 1360 provides a cell voltage VDDA to the bit cell of the selected row in response to the write assist pulse WAST_EN. When the write assist pulse WAST_EN and the column select signal / YSEL are activated, the AND gate 1362 sends a pulse signal corresponding to the write assist pulse WAST_EN to the inverter 1364. The inverter 1364 transmits the cell voltage VDDA of the write assist pulse WAST_EN as an inverted phase to the selected bit cell. At this time, during the write assist pulse WAST_EN period, a drop in the cell voltage VDDA of the selected bit cell occurs, and the write performance can be improved. The inverter 1364 may include a pull-up transistor M5, a pull-down transistor M7, and a normally-on transistor M6. It will be understood that the shape or circuit structure of the inverter 1364 constituting the write assist circuit 1360 is not limited to the shape or circuit structure shown, and can be changed in various ways.

[0088] The memory device 1000 may further include a word line pulse generator 1520 (see Figure 3 ), sense amplifier 1320 or write driver 1340.

[0089] In the above, the row address tracking function of the write assist pulse generator 1540 and the characteristics of the write assist pulse WAST_EN whose pulse width is adjusted accordingly have been described. The write assist pulse generator 1540 is activated during a write operation and generates a write assist pulse WAST_EN having a pulse width corresponding to the input row address R_ADDR. Additionally, the write assist circuit 1360 may supply a cell voltage VDDA that is dropped to a selected bit cell in response to the pulse width of the write assist pulse WAST_EN.

[0090] Fig.10 It is shown Fig. 9 A circuit diagram showing the structure of a write assist pulse generator is shown in FIG. Fig.10 , the write assist pulse generator 1540 may include a pulse generating circuit 1542, an inverter 1544, a row address tracking circuit 1546, a NAND gate 1528, and an inverter INV.

[0091] The pulse generating circuit 1542 may be activated in a write operation mode. That is, the pulse generating circuit 1542 generates the second pulse signal WAST based on the clock signal CK in response to the write enable signal / WEN activated during a write operation to the cell array 1100.

[0092] The inverter 1544 inverts the second pulse signal WAST and sends it to the output node DWAST. The inverter 1544 includes a pull-up transistor M3 and a pull-down transistor M4 that receive the second pulse signal WAST at the gate. The pull-down transistor M4 of the inverter 1544 is connected to the row address tracking circuit 1546. The amount of charge discharged by the pull-down transistor M4 of the inverter 1544 depends on the size of the tracking resistor Rxadd formed in the row address tracking circuit 1546. That is, the pull-down speed of the inverter 1544 can be changed according to the row address R_ADDR, and the row address R_ADDR determines the resistance of the row address tracking circuit 1546.

[0093] The row address tracking circuit 1546 provides a tracking resistor Rxadd of a size corresponding to the row selected by the row address R_ADDR. When the tracking resistor Rxadd is large, the pull-down speed of the inverter 1544 is reduced. On the other hand, when the size of the tracking resistor Rxadd is small, the pull-down speed of the inverter 1544 is increased.

[0094] The level switching speed of the output node DWAST of the inverter 1544 is determined according to the tracking resistance Rxadd that varies based on the row address R_ADDR. In one example, the NAND gate 1528 and the inverter INV can perform a logical product operation on the output of the inverter 1544 and the second pulse signal WAST. If the far cell is selected and the relatively large tracking resistance Rxadd is set, the voltage drop time of the output node DWAST increases. Therefore, the pulse width of the write auxiliary pulse WAST_EN corresponding to the logical product (or AND operation) of the output node DWAST and the second pulse signal WAST increases. On the other hand, when the near cell is selected and the relatively small tracking resistance Rxadd is set, the voltage drop time of the output node DWAST is reduced. Therefore, the pulse width of the write auxiliary pulse WAST_EN corresponding to the logical product (or AND operation) of the output node DWAST and the second pulse signal WAST is reduced.

[0095] In the above, an exemplary structure of the write assist pulse generator 1540 that generates the write assist pulse WAST_EN whose pulse width varies according to the row address R_ADDR has been described. It will be well understood that the structure of the write assist pulse generator 1540 or the structure of the row address tracking circuit 1546 is not limited to the method shown, and various changes are possible. Fig.10 In, C DWAST ∝ ∝ ∝ 1544 may represent the parasitic capacitance of the output node DWAST of the inverter 1544 .

[0096] Fig.11 It is shown Fig.10 The waveform diagram of the operating characteristics of the write assist pulse generator. Fig.11 , the pulse width of the write assist pulse WAST_EN output from the write assist pulse generator 1540 can be freely adjusted according to the input row address R_ADDR.

[0097] At time T0, it is assumed that the write enable signal / WEN is in a deactivated state. Then, the level of the second pulse signal WAST is generated at a low level "L". And the output node DWAST of the inverter 1544 will maintain a high level "H".

[0098] At time T1, when the write enable signal / WEN is activated, the pulse generating circuit 1542 (see Fig.10 ) turns the second pulse signal WAST into a high level “H”. The write assist pulse WAST_EN corresponding to the logical product (or AND operation) of the high level second pulse signal WAST and the output node DWAST turns into a high level “H”.

[0099] At time T2, the word line is activated by the row address R_ADDR, and the pull-down operation of the inverter 1544 by the row address tracking circuit 1546 begins. If the row address R_ADDR is set to "000...0" to select the word line WL1 of the near cell, the tracking resistance Rxadd provided by the row address tracking circuit 1546 is relatively small. Therefore, the pull-down speed of the inverter 1544 is set to high. Finally, the voltage drop at the output node DWAST of the inverter 1544 will appear in the form of curve C1. The write auxiliary pulse WAST_EN can be generated by the output node DWAST voltage in the form of a narrowest pulse width PW1 corresponding to the curve C1.

[0100] On the other hand, the row address R_ADDR is set to "111 ... 1" to select the word line WLn of the far cell, and the tracking resistor Rxadd provided by the row address tracking circuit 1546 will be set to a relative maximum value. In this case, the pull-down speed of the inverter 1544 is set to the lowest. Finally, the voltage drop at the output node DWAST of the inverter 1544 will appear in the form of a curve Cn. The write auxiliary pulse WAST_EN can be generated by the output node DWAST in the form of a widest pulse width PWn corresponding to the curve Cn. In this way, the pulse width of the write auxiliary pulse WAST_EN can be adjusted to various sizes according to the row address R_ADDR.

[0101] At time T3, the pulse section of the second pulse signal WAST ends. That is, the second pulse signal (WAST) is restored from the high level "H" to the low level "L".

[0102] At time T4, after the recovery of the second pulse signal WAST, the level of the output node DWAST of the inverter 1544 also turns to the high level “H”.

[0103] As described above, the write assist pulse generator 1540 may generate a write assist pulse WAST_EN whose pulse width is adjusted using a tracking function of the row address R_ADDR. By using the write assist pulse WAST_EN whose pulse width is adjusted according to the row address R_ADDR, the magnitude of the drop in the cell voltage VDDA occurring in the near cell during the write operation may be reduced. Therefore, power consumption due to an excessively low cell voltage VDDA may be reduced.

[0104] In the above, an exemplary structure of the write assist pulse generator 1540 that generates the write assist pulse WAST_EN whose pulse width varies according to the row address R_ADDR has been described. It will be well understood that the structure of the write assist pulse generator 1540 or the structure of the row address tracking circuit 1546 is not limited to the method shown, and various changes are possible.

[0105] Fig.12 TABLE 1 is a table showing the power reduction effect of the write assist pulse WAST_EN. Fig.12 , changes of a write assist pulse WAST_EN, a word line voltage VWL, and a cell voltage VDDA in each of the far cell and the near cell during a write operation are shown.

[0106] When the write enable signal / WEN is activated and the word line WLn for selecting a remote cell is selected, the write assist pulse generator 1540 generates a write assist pulse (WAST_EN, 1561). In addition, as shown in waveform 1563, the word line voltage VWL will be applied to the word line WLn. Then, the write assist circuit 1360 (see Fig. 9 ) causes the cell voltage VDDA to drop for a time corresponding to the pulse width PW_f of the write assist pulse (WAST_EN, 1561). At this time, the magnitude of the cell voltage VDDA dropped during the time corresponding to the pulse width PW_f can be represented as a first voltage difference ΔVDDA_f.

[0107] On the other hand, when the write enable signal / WEN is activated during a write operation to a near cell connected to the word line WL1, the write assist pulse generator 1540 generates a write assist pulse WAST_EN of a pulse width (PW_n, 1565). In addition, as shown in the waveform 1567, the word line voltage VWL will be applied to the word line WL1. Then, the write assist circuit 1360 will cause the cell voltage VDDA to drop for a time corresponding to the pulse width (or pulse duration) PW_n of the write assist pulse WAST_EN 1565. At this time, the magnitude of the cell voltage VDDA dropped during the time corresponding to the pulse width PW_n can be represented as a second voltage difference ΔVDDA_n.

[0108] Here, the cell voltage drop size ΔVDDA_f of the far cell may be greater than or equal to the cell voltage drop size ΔVDDA_n of the near cell. The reason why this is possible is because a write assist pulse WAST_EN whose pulse width varies according to the row address R_ADDR is generated. Ultimately, power consumption caused by an excessive cell voltage VDDA drop of the near cell during a write operation can be prevented by the write assist pulse generator 1540.

[0109] Now consider Figure 2 The bit unit and remote unit ( Fig.12 An example or write assist is provided by a reduction in VDDA of the top of the latch. In this example, PU1 is initially turned on and needs to be turned off to flip the bit in the latch. In this example, the bit line signal / Nn goes high and this reduces the gate voltage at PMOS PU1. VDDA has been reduced by ΔVDDA_f. The bit line signal Nn has a low value and because VDDA is less than ΔVDDA_f, the current through PU1 is now small. Therefore, PU1 is assisted to turn off by the voltage ΔVDDA_f. At the same time, PD2 (NMOS transistor) is turned on and needs to be turned off. The bit line signal Nn has a low value and PD2 has few electrons in its channel (NMOS majority carriers). PU2 tends to turn on due to the low value of Nn, thereby conducting VDDA to the drain of PD2. As expected by writing a lower VDDA value with a low gate voltage of PD2 to the latch, the lower VDDA value with a low gate voltage of PD2 tends to turn PD2 off more quickly. Thus, this feature provides write assist.

[0110] Fig.13 is a circuit diagram showing another implementation method of a word line pulse generator or a write assist pulse generator having a row address tracking function. Fig.13 , the row address tracking pulse generator 1560 includes a pulse generating circuit 1562, a digitally controlled delay line 1564, a first inverter INV1, a NAND gate 1566 and a second inverter INV2.

[0111] The pulse generating circuit 1562 can be activated in the write operation mode or the read operation mode. That is, in the write operation mode or the read operation mode of the cell array 1100, the pulse generating circuit 1562 generates a pulse signal CPS based on the clock signal CK in response to the write enable signal / WEN or the read enable signal / REN.

[0112] The digitally controlled delay line (DCDL) 1564 reflects the delay corresponding to the row address R_ADDR in the input pulse signal CPS. That is, the digitally controlled delay line 1564 can be switched by the row address R_ADDR, or the pulse signal CPS can be switched to pass through a resistor or impedance corresponding to the row address R_ADDR. In this way, the row address R_ADDR tracking function can be implemented without using a separate dummy metal line. In one example, the inverter 1524 can delay the first pulse signal ICK based on the row address R_ADDR, the inverter 1544 can delay the second pulse signal WAST based on the row address R_ADDR, and the digitally controlled delay line 1564 can delay the pulse signal CPS based on the row address R_ADDR.

[0113] The first inverter INV1 inverts the output of the digitally controlled delay line 1564 and transmits it to the NAND gate 1566. The NAND gate 1566 and the second inverter INV2 perform a logic multiplication operation on the pulse signal CPS directly transmitted from the pulse generating circuit 1562 and the output of the delayed pulse signal CPS' via the digitally controlled delay line 1564 and the first inverter INV1. As a result of the logic multiplication operation, the NAND gate 1566 and the second inverter INV2 may output a word line pulse RowCK or a write assist pulse WAST_EN.

[0114] The row address tracking pulse generator 1560 is described above, and the row address tracking pulse generator 1560 generates a word line pulse RowCK or a write auxiliary pulse WAST_EN whose pulse width varies according to the row address R_ADDR using the digital control delay line 1564. When the row address tracking pulse generator 1560 is applied, the word line pulse RowCK or the write auxiliary pulse WAST_EN can be easily generated without using a separate dummy metal line.

[0115] Fig.14A and Fig. 14B They are shown respectively Fig.13 Circuit diagram of an embodiment of a digitally controlled delay line. Fig.14A A digitally controlled delay line 1564a is shown using a switch configuration, and Fig. 14B A digitally controlled delay line 1564b is shown using a tri-state inverter configuration.

[0116] Reference Fig.14A , the digitally controlled delay line 1564a includes switches SW1 to SWn corresponding to each of the plurality of rows Xsel[i]. The switch of one row selected by the row address R_ADDR among the plurality of rows Xsel[i] is turned on. Then, the input signal (IN) will be sent to the output side (OUT) through the resistance path with the selected row. Fig.14A In the example, Rd may represent the resistance of the resistive path.

[0117] Reference Fig. 14B , the digitally controlled delay line 1564b includes tri-state inverters TSI_1 to TSI_n corresponding to each of the plurality of rows Xsel[i]. The digitally controlled delay line 1564b may be implemented by replacing the switches SW1 to SWn of the digitally controlled delay line 1564a with the tri-state inverters TSI_1 to TSI_n and adding an inverter to the output side.

[0118] Fig.15 is a block diagram showing a hardware structure of a mobile device including a memory device. Fig.15 , the mobile device 2000 may include a CPU 2100, a RAM 2200, an input / output interface 2300, a storage device 2400, and a system bus 2500. Here, the mobile device 2000 may be a computer system or a workstation.

[0119] The CPU 2100 executes software (applications, operating system, device drivers) to be executed on the mobile device 2000. The CPU 2100 will execute the operating system (OS) loaded into the RAM 2200. The CPU 2100 will execute various application programs to be run based on the operating system OS. The CPU 2100 may include an SRAM 2150 used as a cache. The SRAM 2150 may be Figure 1 A memory device including a word line pulse generator or a write assist pulse generator having a row address tracking function. Therefore, when the SRAM 2150 is used as a cache, high power efficiency can be achieved in a mobile environment.

[0120] The operating system OS or the application program will be loaded into the RAM 2200. When the mobile device 2000 is booted, the OS image stored in the storage device 2400 will be loaded into the RAM 2200 based on the boot sequence. All input / output operations of the mobile device 2000 can be supported by the operating system OS. Similarly, an application program selected by the user or selected to provide a basic service can be loaded into the RAM 2200. The RAM 2200 can be a volatile memory (such as a static random access memory (SRAM) or a dynamic random access memory (DRAM)) or a non-volatile memory (such as a PRAM, MRAM, ReRAM, FRAM, or NOR flash memory).

[0121] The input / output interface 2300 controls user input and output from a user interface device. For example, the input / output interface 2300 may include a keyboard, a touch pad, and a monitor for receiving commands or data from a user.

[0122] The storage device 2400 is provided as a storage medium of the mobile device 2000. The storage device 2400 may be provided as a memory card (Multimedia Card (MMC), Embedded MMC (eMMC), Secure Digital (SD), Micro SD, etc.) or a hard disk drive (HDD). The storage device 2400 may include a NAND flash memory having a large storage capacity. Alternatively, the storage device 2400 may include a next-generation non-volatile memory (such as PRAM, MRAM, ReRAM, and FRAM).

[0123] The system bus 2500 is a bus for providing a network inside the mobile device 2000. The CPU 2100, the RAM 2200, the input / output interface 2300, and the storage device 2400 are connected through the system bus 2500 and can exchange data with each other. However, the configuration of the system bus 2500 is not limited to the above description, and may further include a mediation means for efficient management.

[0124] The above mobile device 2000 may include the SRAM 2150 including the word line pulse generator or the write assist pulse generator having a row address tracking function according to the present disclosure. Therefore, the mobile device 2000 may provide high low power performance in a mobile environment.

[0125] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory device, comprising: a cell array including a plurality of static random access memory cells; a row decoder configured to drive a plurality of word lines of the plurality of static random access memory cells based on a row address; a data input / output circuit connected to a plurality of bit lines of the cell array and to a sub power supply line configured to supply a cell voltage to the plurality of SRAM cells; as well as The word line pulse generator is configured to generate a word line pulse having a first pulse width that varies based on a row address and provide the word line pulse to the row decoder.

2. The memory device according to claim 1, wherein: The word line pulse generator includes: A first pulse generating circuit is configured to generate a first pulse signal based on a write enable signal or a read enable signal; A first inverter configured to invert the first pulse signal; A first row address tracking circuit configured to adjust a pull-down speed of the first inverter based on a row address; and The first logic gate unit is configured to perform a logic multiplication operation on the output of the first inverter and the first pulse signal to output a word line pulse.

3. The memory device according to claim 2, wherein: The first row address tracking circuit includes a plurality of first selection transistors, each of the plurality of first selection transistors having a drain connected to the pull-down transistor of the first inverter, a gate connected to a corresponding word line of the plurality of word lines, and a source connected to ground.

4. The memory device according to claim 3, further comprising: A metal line connects the drain of each of the plurality of first selection transistors to the source of the pull-down transistor.

5. The memory device according to claim 2, wherein: The word line pulse generator further includes a dummy line extending in a bit line direction at an output terminal of the first inverter.

6. The memory device according to claim 2, wherein: The word line pulse generator further includes a column tracking circuit configured to delay the first pulse signal based on the number of columns of the cell array to send the delayed first pulse signal to the first inverter.

7. The memory device of claim 1 , further comprising: a write assist pulse generator configured to: generate a write assist pulse having a second pulse width that varies based on a row address; as well as The write assist circuit is configured to provide a cell voltage to a selected SRAM cell through a sub power line based on a write assist pulse during a write operation.

8. The memory device according to claim 7, wherein: The write assist pulse generator includes: a second pulse generating circuit configured to generate a second pulse signal in response to a write enable signal; a second inverter configured to invert the second pulse signal; A second row address tracking circuit configured to adjust a pull-down speed of the second inverter based on the row address; and The second logic gate unit is configured to perform a logical product operation on the output of the second inverter and the second pulse signal to output a write assist pulse.

9. The memory device according to claim 8, wherein: The write assist circuit is further configured to reduce a cell voltage of the selected SRAM cell during a pulse duration of the write assist pulse.

10. The memory device according to claim 9, wherein: The second row address tracking circuit includes a plurality of second selection transistors, each of the plurality of second selection transistors having a drain connected to the pull-down transistor of the second inverter, a gate connected to a corresponding word line of the plurality of word lines, and a source connected to ground.

11. The memory device of claim 10, further comprising: A metal line connects the drain of each of the plurality of second selection transistors to the source of the pull-down transistor of the second inverter.

12. A pulse generator for a static random access memory device, the pulse generator comprising: A pulse generating circuit configured to generate a first pulse signal based on a write enable signal or a read enable signal; a row address tracking circuit configured to generate a second pulse signal by delaying the first pulse signal based on the row address; as well as The logic gate unit is configured to generate a word line pulse or a write assist pulse of the static random access memory device by performing a logic multiplication operation of a first pulse signal and a second pulse signal.

13. The pulse generator according to claim 12, wherein: The row address tracking circuit includes: an inverter including a pull-up transistor and a pull-down transistor; and A plurality of selection transistors each having a drain connected to the source of the pull-down transistor, a gate connected to a corresponding word line of the plurality of word lines, and a source connected to ground.

14. The pulse generator according to claim 13, wherein: A drain of each of the plurality of selection transistors and a source of the pull-down transistor are connected through a metal line.

15. The pulse generator of claim 12, further comprising: The column tracking circuit is configured to delay the first pulse signal according to the number of columns of the static random access memory device so as to send the first pulse signal to the row address tracking circuit.

16. The pulse generator according to claim 12, wherein: The row address tracking circuit includes a digitally controlled delay line configured to be switched by a row address.

17. The pulse generator according to claim 16, wherein: The digitally controlled delay line includes a switch or a tri-state inverter configured to be turned on or off by a row address.

18. A memory device comprising: a cell array including a plurality of static random access memory cells; a row decoder configured to drive a plurality of word lines of the plurality of static random access memory cells based on a row address; a data input / output circuit connected to a plurality of bit lines of the cell array; a write assist circuit configured to supply a cell voltage or a write assist voltage to the plurality of SRAM cells through a sub power line; a word line pulse generator configured to generate a word line pulse having a first pulse width varying based on a row address to provide the word line pulse to a row decoder; as well as The write assist pulse generator is configured to generate a write assist pulse having a second pulse width that varies based on a row address.

19. The memory device of claim 18, wherein: The word line pulse generator includes: A first pulse generating circuit is configured to generate a first pulse signal based on a write enable signal or a read enable signal; A first inverter configured to invert the first pulse signal; A first row address tracking circuit configured to adjust a pull-down speed of the first inverter according to a row address; and The first logic gate unit is configured to perform a logic multiplication operation on the output of the first inverter and the first pulse signal to generate a word line pulse.

20. The memory device of claim 18, wherein: The write assist pulse generator includes: a second pulse generating circuit configured to generate a second pulse signal in response to a write enable signal; a second inverter configured to invert the second pulse signal; A second row address tracking circuit configured to adjust a pull-down speed of the second inverter based on the row address; and The second logic gate unit is configured to perform a logical product operation on the output of the second inverter and the second pulse signal to output a write assist pulse.

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