Resistive random access memory and mini array thereof
By designing a memory structure containing four switching transistors and two resistance memory components, the problem of insufficient reliability after multiple use of existing resistive memory is solved, and the memory area is reduced by simplifying the circuit design, achieving high efficiency data read and store.
Patent Information
- Application Number
- CN202311058233.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-02
- Filing Date
- 2023-08-22
- Publication Date
- 2025-02-14
AI Technical Summary
After multiple writes and reads, it is difficult to correctly identify the stored data, resulting in insufficient reliability. At the same time, due to the opposite direction of the electrodes, more wires are required, which makes it difficult to reduce the memory area.
A memory structure consisting of four switching transistors and two resistive memory elements is designed, and the reliability of the memory is enhanced by simplifying the electrode direction to the same direction and using differential mode operation.
The correctness of effectively interpreting stored data after high-frequency use is achieved, improving the reliability of the memory, and reducing the memory area by simplifying the circuit design.
Smart Images
Figure CN119446224A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a resistance random access memory and a mini array thereof, and more particularly to a resistance random access memory and a mini array thereof having a resistance memory element and capable of increasing reliability. Background Art
[0002] With the development of memory technology, resistive random access memory (RRAM) is now available. Resistive random access memory may include a resistive memory element, and the resistance state of the resistive memory element may be changed by applying a voltage to write and erase data to the resistive memory element.
[0003] However, current resistive memory elements have many shortcomings. For example, after being written and read multiple times (for example, 100,000 times), it is difficult to distinguish the resistance value of the commonly known resistive memory, which makes it difficult to correctly identify the data stored in the memory after multiple accesses, resulting in insufficient reliability. In addition, in current resistive memories, the electrodes of the two resistive memory elements are often in opposite directions, so more wires must be used, which makes it difficult to reduce the area of the memory. Summary of the invention
[0004] An embodiment may provide a memory, comprising a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a first resistance memory element and a second resistance memory element. The first switch transistor comprises a drain, a source, and a gate. The second switch transistor comprises a drain, a source, and a gate. The third switch transistor comprises a drain, a drain, and a gate, wherein the drain of the third switch transistor is coupled to the source of the first switch transistor. The fourth switch transistor comprises a drain, a drain, and a gate, wherein the drain of the fourth switch transistor is coupled to the source of the second switch transistor. The first resistance memory element comprises a first end coupled to the source of the fourth switch transistor, and a second end coupled to the source of the first switch transistor. The second resistance memory element comprises a first end coupled to the source of the third switch transistor, and a second end coupled to the source of the second switch transistor.
[0005] Another embodiment may provide a memory device, comprising a first diffusion layer, a second diffusion layer, a first polysilicon layer, a second polysilicon layer, a first resistance memory element, and a second resistance memory element. The first diffusion layer may be formed along a first direction, the second diffusion layer may be formed along the first direction, and the first polysilicon layer may be formed along a second direction. The first direction is substantially perpendicular to the second direction, and the first polysilicon layer at least partially overlaps the first diffusion layer and the second diffusion layer. The second polysilicon layer may be formed along the second direction and at least partially overlaps the first diffusion layer and the second diffusion layer. The first resistance memory element may at least partially overlap the first diffusion layer and be between the first polysilicon layer and the second polysilicon layer. The second resistance memory element may at least partially overlap the second diffusion layer and be between the first polysilicon layer and the second polysilicon layer.
[0006] Another embodiment provides a mini-array of a memory device, comprising a first diffusion layer, a second diffusion layer, a first polysilicon layer, a second polysilicon layer, a third polysilicon layer, a fourth polysilicon layer, a first resistance memory element, a second resistance memory element, a third resistance memory element, and a fourth resistance memory element. The first diffusion layer can be formed along a first direction. The second diffusion layer can be formed along the first direction. The first polysilicon layer can be formed along a second direction, wherein the first direction is substantially perpendicular to the second direction, and the first polysilicon layer at least partially overlaps the first diffusion layer and the second diffusion layer. The second polysilicon layer can be formed along the second direction, at least partially overlaps the first diffusion layer and the second diffusion layer. The third polysilicon layer can be formed along the second direction, at least partially overlaps the first diffusion layer and the second diffusion layer. The fourth polysilicon layer can be formed along the second direction, at least partially overlaps the first diffusion layer and the second diffusion layer, wherein the third polysilicon layer is between the second polysilicon layer and the fourth polysilicon layer. The first resistance memory element at least partially overlaps the first diffusion layer and is between the first polysilicon layer and the second polysilicon layer. The second resistance memory element at least partially overlaps the second diffusion layer and is between the first polysilicon layer and the second polysilicon layer. The third resistance memory element at least partially overlaps the first diffusion layer and is between the third polysilicon layer and the fourth polysilicon layer. The fourth resistance memory element at least partially overlaps the second diffusion layer and is between the third polysilicon layer and the fourth polysilicon layer. The first polysilicon layer, the second polysilicon layer, the first resistance memory element and the second resistance memory element correspond to a first memory. The third polysilicon layer, the fourth polysilicon layer, the third resistance memory element and the fourth resistance memory element correspond to a second memory. The mini array includes at least the first memory and the second memory.
[0007] Another embodiment may provide a memory device, comprising a first diffusion layer, a second diffusion layer, a first conductive layer, a second conductive layer, a first resistance memory element, and a second resistance memory element. The first conductive layer may be formed on the first diffusion layer, the second conductive layer may be formed on the second diffusion layer, the first resistance memory element may be formed on the first conductive layer, the second resistance memory element may be formed on the second conductive layer, and the first conductive layer and the second conductive layer are formed from the same conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 A circuit diagram of a memory device according to an embodiment performing a write operation.
[0009] Figure 2 for Figure 1 Schematic diagram of a circuit for performing a read operation on a memory.
[0010] Figure 3 FIG. 4 is a circuit diagram of two memories in an embodiment.
[0011] Figures 4 to 8 FIG. 1 is a schematic diagram of a layout of a process for manufacturing a memory in an embodiment.
[0012] Fig. 9 Can Figure 8 , a schematic cross-sectional view of the memory along the tangent line AA'.
[0013] Fig.10 FIG. 4 is a schematic diagram of a read window when reading data from a plurality of memories in an embodiment.
[0014]
Explanation of symbols
[0015] 100, 200: Memory
[0016] 110, 120, 130, 140, 210, 220, 230, 240: switching transistors
[0017] 151, 152, 251, 252, RSE1, RSE2, RSE3, RSE4: Resistive memory element
[0018] 800:Mini Array
[0019] BE: Bottom Electrode
[0020] BL1, BL2: bit lines
[0021] CT, CT1, CT2: Contact elements
[0022] D1, D2: Direction
[0023] DF1, DF2: Diffusion layer
[0024] M1, M2, M3, M4, M11, M12, M21, M31, M32, M41, M42, M43, M44: Conductive layer
[0025] P11, P12, P21, P22: Path
[0026] PLY1, PLY2, PLY3, PLY4: polysilicon layer
[0027] RWL: Read Word Line
[0028] SL1, SL2: Source lines
[0029] T1: Groove
[0030] TE: Upper electrode
[0031] TMO: Transition Metal Oxide
[0032] VA, V1, V2, V3, VA1, VA2, V21, V22, V23, V31: Conductive perforation
[0033] WWL: Write Word Line DETAILED DESCRIPTION
[0034] In order to increase the number of times the memory is used and reduce the area of the memory, the embodiments may provide the following memory and mini array of memory. Herein, when it is mentioned that object A at least partially overlaps object B, it means that in a top view, at least a portion of object A may overlap at least a portion of object B, or object A and object B may completely overlap. The conductive through via (VIA) described herein may be a conductive connection path formed by drilling and plating a conductive material. Each of the memory 100 and the memory 200 mentioned herein may be a bit-cell of a resistive random-access memory (RRAM).
[0035] Figure 1 and Figure 2 FIG. 1 is a circuit diagram of the memory 100 in an embodiment. Figure 1 A circuit diagram of the memory 100 performing a write operation. Figure 2 A circuit diagram of the memory 100 performing a read operation.
[0036] like Figure 1 and Figure 2As shown, the memory 100 may include a first switch transistor 110, a second switch transistor 120, a third switch transistor 130, a fourth switch transistor 140, a first resistance memory element 151, and a second resistance memory element 152. The first switch transistor 110 may include a drain, a source, and a gate. The second switch transistor 120 may include a drain, a source, and a gate. The third switch transistor 130 may include a drain, a source, and a gate, wherein the drain of the third switch transistor 130 may be coupled to the source of the first switch transistor 110. The fourth switch transistor 140 may include a drain, a source, and a gate, wherein the drain of the fourth switch transistor 140 may be coupled to the source of the second switch transistor 120.
[0037] The first resistance memory element 151 may include a first end and a second end, wherein the first end of the first resistance memory element 151 may be coupled to the source of the fourth switch transistor 140, and the second end of the first resistance memory element 151 may be coupled to the source of the first switch transistor 110. The second resistance memory element 152 may include a first end and a second end, wherein the first end of the second resistance memory element 152 may be coupled to the source of the third switch transistor 130, and the second end of the second resistance memory element 152 may be coupled to the source of the second switch transistor 120.
[0038] like Figure 1 and Figure 2 As shown, each of the first resistance memory element 151 and the second resistance memory element 152 may include a top electrode TE, a bottom electrode BE, and a transition metal oxide TMO. The top electrode TE of the first resistance memory element 151 may be coupled to the first end of the first resistance memory element 151, the bottom electrode BE of the first resistance memory element 151 may be coupled to the second end of the first resistance memory element 151, and the transition metal oxide TMO of the first resistance memory element 151 may be formed between the top electrode TE and the bottom electrode BE of the first resistance memory element 151. Similarly, the top electrode TE of the second resistance memory element 152 may be coupled to the first end of the second resistance memory element 152, the bottom electrode BE of the second resistance memory element 152 may be coupled to the second end of the second resistance memory element 152, and the transition metal oxide TMO of the second resistance memory element 152 may be formed between the top electrode TE and the bottom electrode BE of the second resistance memory element 152.
[0039] like Figure 1 and Figure 2As shown, the drain of the first switch transistor 110 may be coupled to the first bit line BL1, and the gate of the first switch transistor 110 may be coupled to the read word line RWL. The drain of the second switch transistor 120 may be coupled to the second bit line BL2, and the gate of the second switch transistor 120 may be coupled to the read word line RWL. The gate of the third switch transistor 130 may be coupled to the write word line WWL, and the source of the third switch transistor 130 may be coupled to the second source line SL2. The gate of the fourth switch transistor 140 may be coupled to the write word line WWL, and the source of the fourth switch transistor 140 may be coupled to the first source line SL1.
[0040] like Figure 1 As shown, when data is written into the memory 100 through the first source line SL1 and the second source line SL2, the first switch transistor 110 and the second switch transistor 120 may be turned off, and the third switch transistor 130 and the fourth switch transistor 140 may be turned on. Figure 1 As shown, data can be written into the first resistance memory element 151 and the second resistance memory element 152 along paths P11 and P12.
[0041] Figure 1 In the example, when a logic 0 value is written into the memory 100, the first source line SL1 may have a high potential (represented herein as VH), and the second source line SL2 may have a low potential (represented herein as VL) lower than the high potential VH. In addition, when a logic 0 value is written into the memory 100, the first resistance memory element 151 may be set to a high resistance value (represented herein as RH), and the second resistance memory element 152 may be set to a low resistance value (represented herein as RL) lower than the high resistance value RH.
[0042] Figure 1 When writing a logic 1 value (logic 1) into the memory 100, the first source line SL1 may have a low potential VL, and the second source line SL2 may have a high potential VH. In addition, when writing a logic 1 value into the memory 100, the first resistance memory element 151 may be set to a low resistance value RL, and the second resistance memory element 152 may be set to a high resistance value RH.
[0043] like Figure 2 As shown, when data is read from the memory 100, the first switch transistor 110 and the second switch transistor 120 may be turned on, and the third switch transistor 130 and the fourth switch transistor 140 may be turned off. Figure 2 As shown, data can be read from the first resistive memory element 151 and the second resistive memory element 152 along paths P21 and P22 .
[0044] Figure 2In the embodiment, when a logic 0 value is read from the memory 100, the first source line SL1 may have a high potential VH, and the second source line SL2 may have a high potential VH. Figure 2 In the embodiment, when a logic 1 value is read from the memory 100, the first source line SL1 may have a high potential VH, and the second source line SL2 may have a high potential.
[0045] The above-mentioned write operation and read operation of the memory 100 can be shown in Table 1:
[0046]
[0047] (Table 1)
[0048] Figure 3 FIG. 1 is a circuit diagram of the memory 100 and the memory 200 in an embodiment. Figure 3 In the embodiment, the memory 100 and the memory 200 can be coupled to each other, and the memory 200 can be coupled to the first bit line BL1, the second bit line BL2, the first source line SL1, and the second source line SL2. By coupling the memory 100 and the memory 200, the circuit area can be saved. Figure 3 In the memory 100, the first switch transistor 110 to the fourth switch transistor 140, the first resistance memory element 151 and the second resistance memory element 152 are as described above, so they are not repeated. Similar to the first switch transistor 110, the second switch transistor 120, the third switch transistor 130, the fourth switch transistor 140, the first resistance memory element 151 and the second resistance memory element 152 of the memory 100, Figure 3 The memory 200 may include a fifth switch transistor 210, a sixth switch transistor 220, a seventh switch transistor 230, an eighth switch transistor 240, a third resistance memory element 251 and a fourth resistance memory element 252, and their coupling and operation may be similar to the memory 100, so they are not repeated.
[0049] Depend on Figures 1 to 3 It can be seen that the first resistive memory element 151 and the second resistive memory element 152 of the memory 100 can be arranged in the same direction instead of in opposite directions, so that the associated lines of the memory 100 can be simplified.
[0050] like Figure 3 As shown, the memory 100 and the memory 200 may share the first bit line BL1, the second bit line BL2, the first source line SL1 and the second source line SL2. Regarding the layout of the semiconductor, Figure 3 The memory 100 and the memory 200 may be integrated into the same mini-array 800 in the layout, such as Figure 8 shown.
[0051] Figures 4 to 8 FIG. 1 is a schematic diagram of a layout of a manufacturing process for manufacturing the memory 100 in an embodiment. In the manufacturing process of the memory 100, the layout can be sequentially arranged in a time sequence as follows: Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 shown.
[0052] Figure 4 In the present invention, the memory 100 may include a diffusion layer DF1, a diffusion layer DF2, a polysilicon layer PLY1, a polysilicon layer PLY2, a polysilicon layer PLY3, and a polysilicon layer PLY4. The polysilicon layer PLY1, the polysilicon layer PLY2, the polysilicon layer PLY3, and the polysilicon layer PLY4 may correspond to the gate of a transistor, such as a gate terminal of a field effect transistor. The diffusion layer DF1 and the diffusion layer DF2 may be formed along a direction D1. The polysilicon layers PLY1 to PL4 may be formed along a direction D2. The direction D1 may be substantially perpendicular to the direction D2. Each of the polysilicon layers PLY1 to PLY4 may at least partially overlap the diffusion layer DF1 and the diffusion layer DF2. Figure 4 In the embodiment, the diffusion layer DF1 and the diffusion layer DF2 may be formed from the same diffusion layer. For example, a trench may be formed to separate the diffusion layer DF1 and the diffusion layer DF2. Figure 4 In the embodiment of the present invention, a plurality of contact elements (contact) CT may be formed on the diffusion layer. In a top view, each contact element CT may be located between polysilicon layers.
[0053] If you will Figure 4 The polysilicon layers PLY1 and PLY2 correspond to Figure 1 The gate of the first switch transistor 110 and the gate of the second switch transistor 120 are Figure 4 The polysilicon layer PLY1 can be coupled to the read word line RWL, and Figure 4 The polysilicon layer PLY2 may be coupled to the write word line WWL.
[0054] Figure 5 In the embodiment, a conductive layer M1, a plurality of conductive vias VA, and a plurality of resistive memory elements RSE1, RSE2, RSE3, and RSE4 may be further formed above the diffusion layer DF1 and the diffusion layer DF2. One of the resistive memory elements RSE1 to RSE4 may correspond to Figures 1 to 3 One of the first resistance memory element 151, the second resistance memory element 152, the third resistance memory element 251 and the fourth resistance memory element 252. Figure 5As shown, in the top view, the resistance memory element RSE1 may at least partially overlap the diffusion layer DF1 and between the polysilicon layer PLY1 and the polysilicon layer PLY2, and the resistance memory element RSE2 may at least partially overlap the diffusion layer DF2 and between the polysilicon layer PLY1 and the polysilicon layer PLY2.
[0055] like Figure 6 As shown, a conductive layer M2 may be further formed on the diffusion layer DF1 and the diffusion layer DF2. In the top view, the conductive layer M2 may not overlap the resistive memory elements RSE1 to RSE4.
[0056] like Figure 7 As shown, a conductive layer M3 and a plurality of conductive through holes V2 may be further formed above the conductive layer M2 and the resistive memory elements RSE1 to RSE4 .
[0057] like Figure 8 As shown, a conductive layer M4 and a plurality of conductive through holes V3 may be further formed above the conductive layer M3.
[0058] Figure 8 In the embodiment, the first switch transistor 110, the second switch transistor 120, the third switch transistor 130, the fourth switch transistor 140, the first resistance memory element RSE1 and the second resistance memory element RSE2 can form a memory having four switch transistors and two resistance memory elements (which can be called 4T2R), such as the above-mentioned memory 100; and the fifth switch transistor 210, the sixth switch transistor 220, the seventh switch transistor 230, the eighth switch transistor 240, the third resistance memory element RSE3 and the fourth resistance memory element RSE4 can form another memory having four switch transistors and two resistance memory elements (4T2R), such as the above-mentioned memory 200. In the layout, the memory 100 and the memory 200 can be combined to form a mini-array 800, wherein the memory 100 and the memory 200 can share source lines and bit lines, such as Figure 3 described.
[0059] Fig. 9 Can Figure 8 , a schematic cross-sectional view of the memory along the tangent line A-A'. Fig. 9 As shown, the memory may include a diffusion layer DF1, a diffusion layer DF2, a conductive layer M11, a conductive layer M12, a contact element CT1, a contact element CT2, a conductive via VA1, a conductive via VA2, a first resistance memory element RSE1, a resistance memory element RSE2, a conductive layer M21, a conductive via V21, a conductive via V22, a conductive via V23, a conductive layer M31, a conductive layer M32, a conductive layer M41, a conductive layer M42, a conductive layer M43, a conductive layer M44, and a conductive via V31.
[0060] Fig. 9 In the embodiment, the trench T1 can be used to separate the diffusion layer DF1 and the diffusion layer DF2. The conductive layer M11 can at least partially overlap the diffusion layer DF1, and in a top view, the conductive layer M11 can be between the polysilicon layer PLY1 and the polysilicon layer PLY2. The conductive layer M12 can at least partially overlap the diffusion layer DF2, and in a top view, the conductive layer M12 can be between the polysilicon layer PLY1 and the polysilicon layer PLY2. Fig. 9 The conductive layer M11 and the conductive layer M12 may be formed from the same conductive layer, for example Figure 5 The conductive layer M1. Fig. 9 As shown, the conductive layer M11 may be formed on the diffusion layer DF1 , the conductive layer M12 may be formed on the diffusion layer DF2 , the first resistance memory element RSE1 may be formed on the conductive layer M11 , and the resistance memory element RSE2 may be formed on the conductive layer M12 .
[0061] The contact element CT1 may be formed between the diffusion layer DF1 and the conductive layer M11, the contact element CT1 may be coupled to the diffusion layer DF1 and the conductive layer M11, the contact element CT1 may at least partially overlap the diffusion layer DF1, and in a top view, the contact element CT1 may be between the polysilicon layer PLY1 and the polysilicon layer PLY2. The contact element CT2 may be formed between the diffusion layer DF2 and the conductive layer M12, the contact element CT2 may be coupled to the diffusion layer DF2 and the conductive layer M12, the contact element CT2 may at least partially overlap the diffusion layer DF2, and in a top view, the contact element CT2 may be between the polysilicon layer PLY1 and the polysilicon layer PLY2. The contact elements CT1 and CT2 may correspond to Figure 4 Contact element CT.
[0062] The conductive via VA1 may be formed between the conductive layer M11 and the first resistive memory element RSE1 . The conductive via VA1 may be coupled to the conductive layer M11 and the first resistive memory element RSE1 , and may at least partially overlap the first resistive memory element RSE1 .
[0063] The conductive via VA2 may be formed between the conductive layer M12 and the resistive memory element RSE2, the conductive via VA2 may be coupled to the conductive layer M12 and the resistive memory element RSE2, and the conductive via VA2 may at least partially overlap the resistive memory element RSE2. The conductive via VA1 and the conductive via VA2 may correspond to Figure 5 Conductive perforated VA.
[0064] Fig. 9 The first resistance memory element RSE1 and the second resistance memory element RSE2 may correspond to Figures 1 to 3 The first resistance memory element 151 and the second resistance memory element 152 are configured as follows.
[0065] like Fig. 9 As shown, the conductive layer M21 may be formed between the first resistive memory element RSE1 and the second resistive memory element RSE2. The conductive layer M31 may be formed above the first resistive memory element RSE1, and the conductive layer M31 may at least partially overlap the first resistive memory element RSE1.
[0066] The conductive layer M32 may be formed on the second resistive memory element RSE2 and the conductive layer M21. The conductive layer M32 may at least partially overlap the second resistive memory element RSE2 and the conductive layer M21. The conductive layer M21 may be formed on Figure 6 The conductive layer M31 and the conductive layer M32 may be formed from the same conductive layer, for example Figure 7 The conductive layer M3.
[0067] Fig. 9 In the embodiment, the conductive through-via V21 may be formed between the first resistive memory element RSE1 and the conductive layer M31 , the conductive through-via V21 may be coupled to the first resistive memory element RSE1 and the conductive layer M31 , and the conductive through-via V21 may at least partially overlap the first resistive memory element RSE1 .
[0068] The conductive through-via V22 may be formed between the conductive layer M21 and the conductive layer M32 , the conductive through-via V22 may be coupled to the conductive layer M21 and the conductive layer M32 , and the conductive through-via V22 may at least partially overlap the conductive layer M21 .
[0069] The conductive through-via V23 may be formed between the second resistive memory element RSE2 and the conductive layer M32 , the conductive through-via V23 may be coupled to the second resistive memory element RSE2 and the conductive layer M32 , and the conductive through-via V23 may at least partially overlap the second resistive memory element RSE2 . Fig. 9 The conductive through hole V21, the conductive through hole V22 and the conductive through hole V23 may correspond to Figure 7 The conductive through hole V2.
[0070] like Fig. 9 As shown, conductive layer M41 , conductive layer M42 , conductive layer M43 and conductive layer M44 may be formed above conductive layer M31 and conductive layer M32 , and conductive layer M41 may at least partially overlap conductive layer M32 .
[0071] The conductive through-via V31 may be formed between the conductive layer M32 and the conductive layer M41 , the conductive through-via V31 may be coupled to the conductive layer V32 and the conductive layer M41 , and the conductive through-via V31 may at least partially overlap the conductive layer M32 . Fig. 9 The conductive through hole V31 may correspond to Figure 8 Conductive vias V3. Fig. 9The conductive layer M41, the conductive layer M42, the conductive layer M43 and the conductive layer M44 may be formed from the same conductive layer, for example Figure 8 The conductive layer M4.
[0072] If you will Fig. 9 The first resistance memory element RSE1 and the second resistance memory element RSE2 correspond to Figure 1 and Figure 2 The first resistance memory element 151 and the second resistance memory element 152, then Fig. 9 The conductive layer M31 can be coupled to Figure 1 The first source line SL1, Fig. 9 The conductive layer M41 can be coupled to Figure 1 The second source line SL2, Fig. 9 The conductive layer M11 can be coupled to Figure 1 The source of the first switch transistor 110, and Fig. 9 The conductive layer M12 may be coupled to Figure 1 The source of the second switching transistor 120.
[0073] Fig.10 FIG. 4 is a schematic diagram of a read window when reading data from a plurality of memories in an embodiment. Fig.10 In the figure, the horizontal axis may correspond to the current of the memory cell, and the vertical axis may correspond to the statistical number of memories after normalization. Fig.10 In the horizontal axis, level HR may be the current level when the resistance memory element of the memory is a high resistance value (written as 0), level LR may be the current level when the resistance memory element of the memory is a low resistance value (written as 1), and level NR may be the current level used as a reference when the machine is measured.
[0074] If the memory 100 provided in the embodiment is not used, when reading the memory, the reading is performed based on the current of a single resistance memory element, which is a single mode operation. Therefore, the window pane corresponding to the high resistance value is WH, and the window pane corresponding to the low resistance value is WL, which can be expressed as WH=|NR-HR|, and WL=|LR-NR|.
[0075] If the memory 100 provided in the embodiment is used, when reading the memory, it can be judged according to the difference in current between the two resistance memory elements, which is a differential mode operation, so the window panes corresponding to the high resistance value and the low resistance value can be expressed as W=|LR-HR|. Since |LR-HR| is greater than |NR-HR|, and |LR-HR| is greater than |LR-NR|, W>WH and W>WL. It can be seen that by using the provided memory 100, the reading window pane can be enlarged. After the reading window pane is enlarged, its effect is that after the memory 100 is written and read multiple times (for example, but not limited to, 100,000 times), the data stored in the memory 100 can still be effectively judged as 0 or 1, which can improve the accuracy of reading the memory and improve the reliability of the memory.
[0076] In summary, the memory 100 of the embodiment can simplify the wiring because the two resistance memory elements are arranged in the same direction, and can improve the read window through differential operation, so as to improve the accuracy of reading and the reliability after a high number of uses. In addition, through appropriate circuit design, layout design and semiconductor structure, two memory cells (for example, Figure 3 The memories 100 and 200 are connected to each other to further reduce the circuit area. Therefore, the memory provided by the embodiment is helpful to solve the problem in the art.
[0077] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A memory comprising: A first switch transistor comprising a drain, a source, and a gate; A second switch transistor comprising a drain, a source, and a gate; a third switch transistor including a drain coupled to the source, a source, and a gate of the first switch transistor; a fourth switch transistor including a drain coupled to the source, a source, and a gate of the second switch transistor; A first resistance memory element comprises a first terminal coupled to the source of the fourth switch transistor, and a second terminal coupled to the source of the first switch transistor; and The second resistance memory element includes a first end coupled to the source of the third switch transistor and a second end coupled to the source of the second switch transistor. 2 . The memory as claimed in claim 1 , wherein when writing data into the memory, the first switch transistor and the second switch transistor are turned off, and the third switch transistor and the fourth switch transistor are turned on. 3 . The memory as claimed in claim 1 , wherein when data is read from the memory, the first switch transistor and the second switch transistor are turned on, and the third switch transistor and the fourth switch transistor are turned off.
4. The memory of claim 1, wherein: The drain of the first switch transistor is coupled to a first bit line, and the gate of the first switch transistor is coupled to a read word line; The drain of the second switch transistor is coupled to the second bit line, and the gate of the second switch transistor is coupled to the read word line; The gate of the third switch transistor is coupled to a write word line, and the source of the third switch transistor is coupled to a second source line; and The gate of the fourth switch transistor is coupled to the write word line, and the source of the fourth switch transistor is coupled to the first source line.
5. The memory as claimed in claim 4, wherein when a logic 0 value is written into the memory, the first switch transistor and the second switch transistor are turned off, the third switch transistor and the fourth switch transistor are turned on, the first source line has a high potential, and the second source line has a low potential lower than the high potential. 6 . The memory of claim 5 , wherein when writing the logic 0 value into the memory, the first resistance memory element is set to a high resistance value, and the second resistance memory element is set to a low resistance value lower than the high resistance value.
7. The memory as claimed in claim 4, wherein when a logic 0 value is read from the memory, the first switch transistor and the second switch transistor are turned on, the third switch transistor and the fourth switch transistor are turned off, the first source line has a high potential, and the second source line has the high potential.
8. The memory as claimed in claim 4, wherein when a logic 1 value is written into the memory, the first switch transistor and the second switch transistor are turned off, the third switch transistor and the fourth switch transistor are turned on, the first source line has a low potential, and the second source line has a high potential higher than the low potential. 9 . The memory of claim 8 , wherein when writing the logic 1 value into the memory, the first resistance memory element is set to a low resistance value, and the second resistance memory element is set to a high resistance value higher than the low resistance value.
10. The memory as claimed in claim 4, wherein when a logic 1 value is read from the memory, the first switch transistor and the second switch transistor are turned on, the third switch transistor and the fourth switch transistor are turned off, the first source line has a high potential, and the second source line has the high potential.
11. The memory of claim 4, wherein: The first resistance memory element comprises an upper electrode coupled to the first end of the first resistance memory element, a lower electrode coupled to the second end of the first resistance memory element, and a transition metal oxide layer formed between the upper electrode of the first resistance memory element and the lower electrode of the first resistance memory element; and The second resistance memory element includes an upper electrode coupled to the first end of the second resistance memory element, a lower electrode coupled to the second end of the second resistance memory element, and a transition metal oxide layer formed between the upper electrode of the second resistance memory element and the lower electrode of the second resistance memory element.
12. A memory comprising: A first diffusion layer formed along a first direction; a second diffusion layer formed along the first direction; A first polysilicon layer is formed along a second direction, wherein the first direction is substantially perpendicular to the second direction, and the first polysilicon layer at least partially overlaps the first diffusion layer and the second diffusion layer; A second polysilicon layer is formed along the second direction and at least partially overlaps the first diffusion layer and the second diffusion layer; A first resistance memory element at least partially overlaps the first diffusion layer and is located between the first polysilicon layer and the second polysilicon layer; and The second resistance memory element at least partially overlaps the second diffusion layer and is located between the first polysilicon layer and the second polysilicon layer. 13 . The memory as claimed in claim 12 , wherein the first diffusion layer and the second diffusion layer are formed from the same diffusion layer.
14. The memory of claim 12, further comprising: A first conductive layer at least partially overlaps the first diffusion layer and is between the first polysilicon layer and the second polysilicon layer; A second conductive layer at least partially overlaps the second diffusion layer and is between the first polysilicon layer and the second polysilicon layer, and the first conductive layer and the second conductive layer are formed from the same conductive layer; A first contact element is coupled to the first diffusion layer and the first conductive layer, at least partially overlaps the first diffusion layer, and is between the first polysilicon layer and the second polysilicon layer; A second contact element coupled to the second diffusion layer and the second conductive layer, at least partially overlapping the second diffusion layer, and between the first polysilicon layer and the second polysilicon layer; A first conductive through-hole is coupled to the first conductive layer and the first resistive memory element, and at least partially overlaps the first resistive memory element; and The second conductive through hole is coupled to the second conductive layer and the second resistance memory element, and at least partially overlaps the second resistance memory element.
15. The memory of claim 14, further comprising: A third conductive layer formed between the first resistance memory element and the second resistance memory element; a fourth conductive layer at least partially overlapping the first resistance memory element; a fifth conductive layer at least partially overlapping the second resistive memory element and the third conductive layer, and the fourth conductive layer and the fifth conductive layer are formed from the same conductive layer; A third conductive through-hole is coupled to the first resistive memory element and the fourth conductive layer, wherein the third conductive through-hole at least partially overlaps the first resistive memory element; a fourth conductive through-hole coupled to the third conductive layer and the fifth conductive layer, wherein the fourth conductive through-hole at least partially overlaps the third conductive layer; and The fifth conductive through-via is coupled to the second resistive memory element and the fifth conductive layer, wherein the fifth conductive through-via at least partially overlaps the second resistive memory element.
16. A mini-array of memory, comprising: A first diffusion layer formed along a first direction; a second diffusion layer formed along the first direction; A first polysilicon layer is formed along a second direction, wherein the first direction is substantially perpendicular to the second direction, and the first polysilicon layer at least partially overlaps the first diffusion layer and the second diffusion layer; A second polysilicon layer is formed along the second direction and at least partially overlaps the first diffusion layer and the second diffusion layer; A third polysilicon layer is formed along the second direction and at least partially overlaps the first diffusion layer and the second diffusion layer; a fourth polysilicon layer formed along the second direction and at least partially overlapping the first diffusion layer and the second diffusion layer, wherein the third polysilicon layer is between the second polysilicon layer and the fourth polysilicon layer; A first resistance memory element at least partially overlaps the first diffusion layer and is located between the first polysilicon layer and the second polysilicon layer; A second resistance memory element at least partially overlaps the second diffusion layer and is located between the first polysilicon layer and the second polysilicon layer; A third resistance memory element at least partially overlaps the first diffusion layer and is located between the third polysilicon layer and the fourth polysilicon layer; and a fourth resistance memory element at least partially overlapping the second diffusion layer and between the third polysilicon layer and the fourth polysilicon layer; wherein the first polysilicon layer, the second polysilicon layer, the first resistance memory element and the second resistance memory element correspond to a first memory; The third polysilicon layer, the fourth polysilicon layer, the third resistance memory element and the fourth resistance memory element correspond to a second memory; and The mini array at least includes the first memory and the second memory.
17. A memory comprising: a first diffusion layer; A second diffusion layer; A first conductive layer formed above the first diffusion layer; a second conductive layer formed on the second diffusion layer; A first resistance memory element is formed above the first conductive layer; and A second resistance memory element is formed above the second conductive layer; The first conductive layer and the second conductive layer are formed from the same conductive layer.
18. The memory of claim 17, further comprising: A first contact element is coupled to the first diffusion layer and the first conductive layer and is formed between the first diffusion layer and the first conductive layer; A second contact element is coupled to the second diffusion layer and the second conductive layer and is formed between the second diffusion layer and the second conductive layer; A first conductive through hole is coupled to the first conductive layer and the first resistive memory element and is formed between the first conductive layer and the first resistive memory element; and The second conductive through hole is coupled to the second conductive layer and the second resistive memory element, and is formed between the second conductive layer and the second resistive memory element.
19. The memory of claim 18, further comprising: a third conductive layer; A fourth conductive layer formed above the first resistance memory element; A fifth conductive layer formed on the second resistive memory element and the third conductive layer; A third conductive through hole is coupled to the first resistive memory element and the fourth conductive layer, and is formed between the first resistive memory element and the fourth conductive layer; a fourth conductive through hole, coupled to the third conductive layer and the fifth conductive layer, and formed between the third conductive layer and the fifth conductive layer; and a fifth conductive through hole, coupled to the second resistive memory element and the fifth conductive layer, and formed between the second resistive memory element and the fifth conductive layer; The fourth conductive layer and the fifth conductive layer are formed from the same conductive layer.
20. The memory of claim 19, further comprising: a sixth conductive layer formed on the fifth conductive layer; and The sixth conductive via is coupled to the fifth conductive layer and the sixth conductive layer and is formed between the fifth conductive layer and the sixth conductive layer.