Hybrid substrate and method for manufacturing same

Abstract

The present technology is directed to hybrid substrates and methods of making the same. In various embodiments, the present technology provides a method for fabricating a semiconductor device, the method including forming a substrate and coupling a first circuit to the substrate. The first circuit is characterized by a first coefficient of thermal expansion (CTE) and the substrate is characterized by a second CTE. The ratio of the first CTE to the second CTE is greater than or equal to 3: 5, which ensures harmonious thermal behavior, thereby improving throughput and reducing warpage. In some embodiments, one or more circuit elements may be embedded in the substrate. Other embodiments are also present.

Description

[0001] Related Applications Cross Reference

[0002] This application claims priority to U.S. Provisional Application No. 63 / 517,747, filed on August 4, 2023, which is commonly owned and incorporated herein by reference for all purposes. Technical Field

[0003] The present technology is directed to semiconductor devices and methods of manufacturing. Background Art

[0004] Over the past few decades, semiconductor packaging materials and processes have continued to develop. With the advancement of high-performance computing and related applications, there is an urgent need for substrates that can meet the needs of high integration. Various approaches involve heterogeneous integration, which allows different types of devices (e.g., silicon and / or memory components) to be integrated on a single package. However, ensuring seamless communication, efficient and high-density wiring, and effectively integrating both active and passive components onto the substrate remains a challenging task.

[0005] Various methods for enhancing substrates have been explored, but have proven to be inadequate.It is important to recognize the need for new and improved substrates and processes for their manufacture. Summary of the invention

[0006] In one aspect, the present disclosure is directed to a method for manufacturing a semiconductor device, the method comprising: forming a substrate; and coupling a first circuit to the substrate, the first circuit being characterized by a first coefficient of thermal expansion, the substrate being characterized by a second coefficient of thermal expansion, the ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion being greater than or equal to 3:5; wherein forming the substrate comprises: providing a base layer, the base layer comprising a first side and a second side; coupling a first wafer to the second side; forming a first through hole in the base layer; depositing a first layer on the first side, the first layer comprising a first dielectric material; forming a first wiring in the first layer; depositing a second layer on the first layer; and forming a first connector in the second layer, the first circuit being coupled to the substrate via the first connector.

[0007] In another aspect, the present disclosure is directed to a method for manufacturing a semiconductor device, the method comprising: forming a substrate; and coupling a first circuit to the substrate, the first circuit being characterized by a first coefficient of thermal expansion, the substrate being characterized by a second coefficient of thermal expansion, the ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion being greater than or equal to 3:5; wherein forming the substrate comprises: providing a base layer, the base layer comprising a first side and a second side; coupling a first wafer to the second side; forming a first through hole in the base layer; forming a cavity in the base layer, the cavity being positioned on the first side; embedding a second circuit in the cavity; depositing a first layer on the first side, the first layer comprising a first dielectric material; forming a first wiring in the first layer; depositing a second layer on the first layer; and forming a first connector in the second layer, the first circuit being coupled to the substrate via the first connector.

[0008] In another aspect, the present disclosure is directed to a method for manufacturing a semiconductor device, the method comprising: providing a base layer, the base layer comprising a first side and a second side; coupling a first chip to the second side; forming a first through hole in the base layer; depositing a first layer on the first side, the first layer comprising a first dielectric material; forming a first wiring in the first layer; and depositing a second layer on the first layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and to the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of a plurality of similar components. When a reference numeral is cited without specifying an existing sub-label, the reference numeral is intended to refer to all such plurality of similar components.

[0010] Figure 1 is a simplified diagram illustrating a semiconductor device having a substrate according to an embodiment of the present technology.

[0011] Figure 2 is a simplified diagram illustrating a substrate of a semiconductor device according to an embodiment of the present technology.

[0012] Figures 3A to 3B is a simplified diagram illustrating a base layer of a semiconductor substrate in accordance with an embodiment of the present technology.

[0013] Figures 4A to 4B is a simplified diagram illustrating a process of depositing one or more layers on a base layer of a semiconductor substrate according to an embodiment of the present technology.

[0014] Figure 5is a simplified diagram illustrating a planarization process for fabricating a semiconductor substrate in accordance with an embodiment of the present technology.

[0015] Figures 6A to 6B is a simplified diagram illustrating a photolithography process for fabricating a semiconductor substrate in accordance with an embodiment of the present technology.

[0016] Figures 7A to 7C is a simplified diagram illustrating one or more dielectric layers of a semiconductor substrate in accordance with an embodiment of the present technology.

[0017] Figure 8 is a simplified diagram illustrating a passivation layer of a semiconductor substrate in accordance with an embodiment of the present technology.

[0018] Fig. 9 is a simplified diagram illustrating a passivation layer of a semiconductor substrate in accordance with an embodiment of the present technology.

[0019] Fig.10 is a simplified diagram illustrating one or more wafers of coupled semiconductor substrates in accordance with an embodiment of the present technology.

[0020] Fig.11 is a simplified diagram illustrating a process of detaching a wafer from a semiconductor substrate according to an embodiment of the present technology.

[0021] Fig.12 is a simplified diagram illustrating one or more dielectric layers of a semiconductor substrate in accordance with an embodiment of the present technology.

[0022] Fig.13 is a simplified diagram illustrating a process of detaching a wafer from a semiconductor substrate according to an embodiment of the present technology.

[0023] Figures 14A to 14B is a simplified diagram illustrating a base layer of a semiconductor substrate in accordance with an embodiment of the present technology.

[0024] Figures 15A to 15B is a simplified diagram illustrating a process of depositing one or more layers on a base layer of a semiconductor substrate according to an embodiment of the present technology. DETAILED DESCRIPTION

[0025] The present technology is directed to semiconductor devices and manufacturing methods. In various embodiments, the present technology provides a method for manufacturing a semiconductor device, the method comprising forming a substrate and coupling a first circuit to the substrate. The first circuit is characterized by a first coefficient of thermal expansion (CTE) and the substrate is characterized by a second CTE. The ratio of the first CTE to the second CTE is greater than or equal to 3:5, which ensures harmonious thermal behavior, thereby improving the yield and reducing warpage. In some embodiments, one or more circuit elements may be embedded in the substrate. Other embodiments also exist.

[0026] As previously mentioned, various methods for semiconductor fabrication have proven insufficient to meet the needs of high computing applications. For example, some methods involve using silicon interposers as substrates, which are constrained by the size of the photomask in lithography, thereby facing limitations in size and complexity. In addition, the interposer is typically passive and tends to add a layer or complexity and CTE mismatch between the IC chip and the substrate. In addition, the interposer adds an additional layer of thermal resistance, which is detrimental to device performance. Co-packaging requires low warpage because optical devices are very sensitive to dimensional tolerances. Hybrid substrates not only eliminate the interposer, but also provide the low warpage packaging solution required to achieve co-packaging. Co-packaging includes the integration of photonic devices with electronic integrated circuits (ICs) to convert signals from electrons to photons and vice versa, and uses optical fibers to run traffic from and to the package. Co-packaging may also include the use of passive copper cables instead of photonic devices.

[0027] On the other hand, various technologies involve using organic substrates to provide support and electrical connections to IC chips. However, the significant difference in the coefficient of thermal expansion (CTE) between the IC chip and the organic substrate poses a challenge. The term "coefficient of thermal expansion" may refer to a measurement of the extent to which a material expands or contracts when subjected to a change in temperature. For example, an IC chip typically made of silicon may have a CTE of less than 3ppm / °C, while an organic substrate may have a higher CTE value ranging from 10ppm / °C to 16ppm / °C. This CTE mismatch may lead to potential warping and subsequent structural reliability challenges such as cracks, delamination, or solder joint failures.

[0028] In various embodiments, the present technology introduces systems and methods for producing hybrid substrates. For example, the hybrid substrate may be characterized by an asymmetric configuration that combines an interposer-like structure on one side with an organic-like substrate structure on the other side. Among other things, the hybrid substrate addresses the challenges of the current state of the art mask-limited interposer, allowing high-density wiring to meet the needs of high-performance applications. The manufacturing methods of the present technology streamline the manufacturing process by integrating different structures in a single process flow, which allows for a reduction in manufacturing steps and a reduction in production duration. The present technology solves the CTE mismatch problem at the manufacturing stage, thereby substantially reducing defects such as warpage, delamination, and solder joint failures. This results in higher yields, minimized waste, and better resource utilization. In addition, embodiments of the present technology are suitable for packaging active and passive components together with computing and memory devices to enhance performance.

[0029] The following description is presented to enable one skilled in the art to make and use the invention and to incorporate the invention into the context of a particular application. Various modifications and various uses in different applications will be readily apparent to one skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Therefore, it is not intended that the present technology be limited to the embodiments presented, but rather that the present technology be given the widest scope consistent with the principles and novel features disclosed herein.

[0030] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present technology. However, it will be apparent to those skilled in the art that the present technology can be practiced without being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form (rather than in detail) in order to avoid obscuring the present technology.

[0031] The reader is advised to pay attention to all papers and documents filed concurrently with this specification and available for public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any accompanying claims, abstracts and drawings) may be replaced by alternative features serving the same, equivalent or similar purposes. Therefore, unless otherwise expressly stated, each disclosed feature is only an example of a series of generic equivalent or similar features.

[0032] In addition, any element in the technical solution that does not explicitly state a "means" for performing a specified function or a "step" for performing a specified function should not be interpreted as a "means" or "step" clause as provided in 35 U.S.C. Section 112, paragraph 6. Specifically, the use of "step" or "action" in the claims herein is not intended to refer to the provisions of 35 U.S.C. Section 112, paragraph 6.

[0033] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0034] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed near, or disposed in some other relative manner), it is understood that the element may be directly disposed relative to the other element (e.g., disposed directly on the other element) or there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct disposition does not exclude other instances in which there may be intervening elements.

[0035] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be directly joined to the other element (without any intervening elements) or have intervening elements between the joined elements. In contrast, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining in which there may be intervening elements.

[0036] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intervening elements present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of directly coupled or connected layers does not exclude other connections in which there may be intervening elements.

[0037] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, the terms are only used to indicate the relative position and / or direction between various parts of an object and / or component.

[0038] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intervening processes may occur before and / or after any portion of the described process, and that various other procedures may be reordered, added, and / or omitted according to various embodiments.

[0039] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, the use of the singular includes the plural (unless otherwise specifically stated), and the use of the terms "and" and "or" means "and / or" (unless otherwise indicated). In addition, the use of the terms "including" and "having" and other forms (such as "includes, included", "has, have and had") should be considered non-exclusive. Moreover, unless otherwise specifically stated, terms such as "element" or "component" encompass both elements and components that include one unit and elements and components that include more than one unit.

[0040] As used herein, the phrase "at least one of..." preceding a list of items (with the terms "and" or "or" separating any of the items) modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of the items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where selection of "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is intended, it is expressly described as such.

[0041] One general aspect includes a method for manufacturing a semiconductor device, the method comprising forming a substrate, and coupling a first circuit to the substrate. The first circuit is characterized by a first coefficient of thermal expansion, the substrate is characterized by a second coefficient of thermal expansion, and the ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than or equal to 3:5. A method for forming a substrate comprises providing a base layer, the base layer comprising a first side and a second side. The method further comprises coupling a first wafer to the second side. The method further comprises forming a first via in the base layer. The method further comprises depositing a first layer on the first side, the first layer comprising a first dielectric material. The method further comprises forming a first wiring in the first layer. The method further comprises depositing a second layer on the first layer. The method further comprises forming a first connector in the second layer, the first circuit being coupled to the substrate via the first connector.

[0042] The embodiment may include one or more of the following features. The first connector includes a conductive pad. The first connector includes a metal bump. The substrate is characterized by a first thickness, the base layer is characterized by a second thickness, and the second thickness is greater than 60% of the first thickness. The base layer includes a glass material, a ceramic material, a diamond material, or a silicon material. The method further includes depositing a third layer on the substrate, the third layer coupled to the first through hole. The third layer includes a titanium nitride material, a tungsten material, a silicon oxide material, or a copper material. The first dielectric material includes a polyimide material or a silicon nitride material. The second layer includes a passivation material. The method further includes coupling a second wafer to the second layer, and detaching the first wafer from the base layer. The method further includes depositing a fourth layer on the second side, the fourth layer including a second dielectric material. The second dielectric material is different from the first dielectric material. The method further includes forming a second wiring in the fourth layer, the second wiring including a metal material.

[0043] According to another embodiment, the present technology provides a method for manufacturing a semiconductor device. The method includes forming a substrate, and coupling a first circuit to the substrate. The first circuit is characterized by a first coefficient of thermal expansion, the substrate is characterized by a second coefficient of thermal expansion, and the ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than or equal to 3:5. A method for forming a substrate includes providing a base layer, the base layer including a first side and a second side. The method further includes coupling a first wafer to the second side. The method further includes forming a first through hole in the base layer. The method further includes forming a cavity in the base layer, the cavity being positioned on the first side. The method further includes embedding a second circuit in the cavity. The method further includes depositing a first layer on the first side, the first layer including a first dielectric material. The method further includes forming a first wiring in the first layer. The method further includes depositing a second layer on the first layer. The method further includes forming a first connector in the second layer, the first circuit being coupled to the substrate via the first connector.

[0044] Embodiments may include one or more of the following features. The second circuit includes a memory, a thermal component, a mechanical component, an optical component, or an electrical component. The substrate is characterized by a first thickness, the base layer is characterized by a second thickness, and the second thickness is greater than 60% of the first thickness. The first layer is characterized by a third thickness, and the third thickness is less than or equal to 30 um. The base layer includes a glass material, a ceramic material, a diamond material, or a silicon material.

[0045] According to another embodiment, the present technology provides a method for manufacturing a semiconductor device, the method comprising providing a base layer, the base layer comprising a first side and a second side. The method further comprises coupling a first wafer to the second side. The method further comprises forming a first through hole in the base layer. The method further comprises depositing a first layer on the first side, the first layer comprising a first dielectric material. The method further comprises forming a first wiring in the first layer. The method further comprises depositing a second layer on the first layer. In some embodiments, the method further comprises embedding a circuit in the base layer.

[0046] Figure 1 1 is a simplified diagram illustrating a semiconductor device 100 having a substrate according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. As shown, semiconductor device 100 includes circuit 102. For example, circuit 102 may include an integrated circuit such as a microprocessor, a memory chip, a digital signal processor, a system-on-chip (SoC), and the like.

[0047] Depending on the implementation, the circuit 102 may include, but is not limited to, memory, thermal components, mechanical components, optical components, or electrical components, active and passive devices, die stacks, and the like. For example, the term "memory" may refer to a device capable of storing data for immediate or future use. The memory may include, but is not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), or hybrid bandwidth memory (HBM), voltage regulators, capacitors, inductors, and the like, and they should not limit the scope of the claims. The term "thermal component" may refer to a device that generates, transmits, or dissipates heat. The thermal component may include, but is not limited to, a heater, a heat sink, a thermoelectric generator, a heat pad, and the like, and they should not limit the scope of the claims. The term "mechanical component" may refer to a device that contributes to physical and structural integrity or mobile functionality within a semiconductor device, and they should not limit the scope of the claims. Mechanical components may include, but are not limited to, microelectromechanical systems (MEMS) devices, actuators, sensors, oscillators, and the like. The term "optical component" may refer to a device that manages, generates, or detects light, including but not limited to a device that converts electrons into photons or vice versa, or a device that generates or transmits laser light. Optical components may include but are not limited to lenses, waveguides, photon modulators, photonic integrated circuits, II-V semiconductors, light sources, photodetectors, integrated lasers, and the like. The term "electrical component" may refer to a device that conducts, isolates, or switches electricity, and it should not limit the scope of the claims. Electrical components may be active or passive. Active electrical components may include but are not limited to transistors, diodes, integrated circuits, and the like. Passive electrical components may include but are not limited to resistors, capacitors, inductors, and the like.

[0048] In various examples, the circuit 102 may be characterized by a first coefficient of thermal expansion (CTE). The term "coefficient of thermal expansion" may refer to a measurement of the extent to which a material expands or contracts when subjected to a change in temperature. CTE may be expressed in parts per million per degree Celsius (ppm / °C). It may be measured using various methods, such as dilatometry, interferometry, thermomechanical analysis, strain gauges, direct image correlation (DIC), and the like. It should be appreciated that CTE is an important factor affecting the reliability and performance of semiconductor packages because differences in CTE values ​​between adjacent materials may introduce thermal stresses and deformations, leading to potential reliability issues. The CTE value of a material may be associated with various factors, such as material composition, microstructure, impurities, temperature range, and the like. In various embodiments, the circuit 102 includes a silicon material and the first CTE may be modulated and may be less than 3ppm / °C in some cases.

[0049] According to some embodiments, semiconductor device 100 further includes a substrate 106 coupled to circuit 102. For example, substrate 106 is coupled to circuit 102 through joint 104. The term "substrate" may refer to a material that provides support and electrical connection to electronic components. The substrate may also provide a means for connecting an IC chip (e.g., circuit 102) to an external circuit system (e.g., a PCB board). Substrate 106 may include, but is not limited to, one or more materials such as silicon, organic materials, ceramics, diamond, or any combination thereof. The term "joint" may refer to an electrical or mechanical connection between an IC chip and a substrate. Joint 104 may include a solder-based joint (e.g., a microbump) or a solderless joint (e.g., a hybrid or direct copper bond).

[0050] Depending on the implementation, the substrate 106 may be a hybrid substrate. The term "hybrid" indicates that the substrate combines the features and properties of multiple different types of materials and / or structures. In some examples, the substrate 106 includes a first structure (e.g., an interposer-like structure) on a first side (e.g., a front side) and a second structure (e.g., an organic substrate-like structure) on a second side (e.g., a back side), or vice versa. The first side may be opposite to the second side, or vice versa. The first structure may provide a dense conductive network that allows high-density wiring, thereby ensuring efficient communication across the semiconductor device 100. In some cases, the first structure may include the electrical and thermal properties of silicon, which ensures efficient signal transmission and heat dissipation. The second structure may be suitable for integration and co-packaging of both active and passive components, thereby providing flexibility and adaptability for enhancing overall system performance. The hybrid substrate may be symmetrical or asymmetrical. For example, the two sides may be interposer-like and substrate-like, or one side may be interposer-like and the other side may be substrate-like.

[0051] In various implementations, substrate 106 can be characterized by a second CTE. For example, the ratio of the first CTE to the second CTE is greater than or equal to 3:5. By closely matching the CTEs of substrate 106 and circuit 102, the risks associated with thermal stresses, such as warping or delamination, are significantly mitigated, thereby improving the reliability and life of semiconductor device 100. In some cases, substrate 106 can be coupled to other components (e.g., a printed circuit board) via mechanisms such as solder balls, bumps, and the like.

[0052] Figure 2 2 is a simplified diagram illustrating a substrate 200 of a semiconductor device according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications.

[0053] As shown, substrate 200 includes layer 202. For example, layer 202 may be used as a passivation layer. The term "passivation layer" may refer to a material layer deposited on the surface of a semiconductor device to protect it from environmental factors (e.g., moisture, oxygen, pollutants, etc.). Layer 202 may include a passivation material, which may include but is not limited to one or more materials such as organic materials (e.g., polyimide, parylene, benzocyclobutene, etc.), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), and the like.

[0054] Depending on the implementation, layer 202 may be configured to couple to external circuitry (e.g., Figure 1 For example, layer 202 may be connected via a first connector (e.g., Figure 1 The layer 202 may include a connector 204. The term "connector" may refer to a mechanism or structure that realizes an electrical or physical connection between different components (e.g., between an external circuit and layer 202). The connector may include, but is not limited to, an ultra-fine pitch bump (uBump), a hybrid copper bond (HCB), a wire bond, a flip chip bond, and the like. For example, the term "uBump" or "ultra-fine pitch bump" may refer to a type of solder bump having a very small diameter (e.g., less than 25um) and a pitch (e.g., less than 40um) and can be used to connect an IC chip in a semiconductor package to a substrate. The hybrid copper bond may include a bond between copper or other metals (e.g., gold, etc.) and a dielectric material, which may be organic (e.g., small molecules or monomers, etc.) or inorganic (e.g., silicon oxide, other metal oxides, etc.).

[0055] In some embodiments, layer 210 may be coupled to layer 202. For example, layer 210 may include a dielectric layer. The term "dielectric layer" may refer to a non-conductive material layer used to isolate different electrical components and pathways to ensure that current is directed as intended. Layer 210 may include a first dielectric material, which includes but is not limited to one or more materials such as organic materials (e.g., built-up films, polyimide or other polymer-based dielectrics), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), etc. The composition, thickness, and number of dielectric layers may be tailored to meet specific requirements and may vary depending on the application.

[0056] In various implementations, layer 210 may include a first wiring. The first wiring may be coupled to layer 212. The term "wiring" may refer to a conductive path configured to facilitate electrical connection between components or regions in a semiconductor device. Wiring may be made using a variety of materials such as copper, aluminum, gold, etc. For example, the first wiring may include a through hole 206, which may be filled with various materials, including but not limited to copper, aluminum, gold, etc. In some cases, copper electroplating may be used to make through hole 206. Depending on the implementation, the taper ratio of through hole 206 may vary between 80% and 100%. For example, a taper ratio of 80% may indicate that the diameter of the through hole at the top is 80% of the diameter of the through hole at the bottom. In some examples, the first wiring includes a conductive trace 208. The term "conductive trace" may refer to a strip of conductive material used to connect electrical components. The conductive trace may include but is not limited to one or more materials, such as copper, aluminum, gold, etc. The size and configuration (eg, width, length, or thickness) of conductive traces 208 may vary depending on the application.

[0057] According to some embodiments, layer 212 may be coupled to layer 210. Layer 212 may include, but is not limited to, one or more materials such as glass, ceramic, diamond, silicon, and the like. For example, layer 212 may include vias 214. The term "via" may refer to an opening or hole in a substrate that allows electrical connection between different layers of the substrate. The vias may include, but are not limited to, through-silicon vias (TSVs), through-glass vias (TGVs), through-ceramic vias (TCVs), through-diamond vias (TDVs), and the like. Various techniques including, but not limited to, laser drilling, mechanical drilling, chemical etching, and the like may be used to form vias 214. For example, depending on the drilling method, the diameters of vias 214 at opposite sides may be the same or different. In some cases, vias 214 may be drilled from opposite sides (e.g., top and bottom sides) of layer 212, which may produce tapered vias. Depending on the particular application, the taper ratio of the via 214, which may be defined as the difference between the top region and the middle or bottom region of the via, may be adjusted. For example, the taper ratio of the via 214 may range from 80% to 100%. In various examples, the via 214 may be filled with a conductive material (e.g., copper, tungsten, titanium, aluminum, gold, silver, tin, nickel, lead, etc.) to ensure conductivity and structural integrity.

[0058] In some embodiments, layer 212 further includes layer 216 coupled to via 214 and layer 218 coupled to layer 216. For example, layer 218 may include a seed layer configured to promote copper deposition to ensure optimal connectivity and conductivity within substrate 200. Layer 218 may include, but is not limited to, one or more materials such as titanium nitride, tungsten, silicon oxide, copper, and the like. Layer 216 may include a via plating layer that may be deposited on the wall of a via (e.g., via 214) using an electrochemical process. Layer 216 may be configured to create a conductive path between different layers and fill via 214 with a metallic material. This may improve the electrical performance, reliability, and thermal management of semiconductor devices. Layer 216 may include, but is not limited to, one or more materials such as copper, an organic resin, and the like. In some cases, layer 212 further includes circuitry 226. Circuit 226 may include active and / or passive components that may be embedded within the substrate (e.g., layer 212) to enhance the signal integrity and overall performance of the semiconductor device. For example, circuit 226 may include, but is not limited to, memory, thermal components, mechanical components, optical components, electrical components, and the like.

[0059] In various examples, layer 226 may be coupled to layer 212. For example, layer 226 may include a dielectric layer. Layer 210 may include a second dielectric material including, but not limited to, one or more materials such as organic materials (e.g., built-up films, polyimide or other polymer-based dielectrics), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), etc. The composition, thickness, and number of dielectric layers may be tailored to meet specific requirements and may vary depending on the application.

[0060] In various embodiments, layer 226 may include a second wiring. The second wiring may be coupled to layer 212. For example, the second wiring may include a through hole 220, which may be filled with various materials, including but not limited to copper, aluminum, gold, etc. Copper plating may be used to make through hole 220. Depending on the implementation, the taper ratio of through hole 220 may vary between 80% and 100%. In some examples, the second wiring includes a conductive trace 222. The conductive trace may include but is not limited to one or more materials, such as copper, aluminum, gold, etc. The size and configuration (e.g., width, length, or thickness) of conductive trace 222 may vary depending on the application. In some embodiments, layer 226 may be coupled to layer 224, and layer 224 may include a solder resist material. The term "solder resist material" may refer to a material layer applied to the surface of a printed circuit board (PCB) and a semiconductor package to protect a circuit pattern from solder and other contaminants. The solder resist material may include but is not limited to one or more materials, such as epoxy resin, acrylic resin, polyimide resin, etc.

[0061] As previously described, the substrate 200 and external circuits (eg, Figure 2 Closely matching the CTE values ​​of the circuit 102 of the substrate 200 helps to mitigate the risks associated with thermal expansion mismatch, which can cause thermal stress and structural challenges such as delamination and warping. In various embodiments, layer 212 plays an important role in configuring the thermal expansion characteristics (e.g., CTE) of the substrate 200. For example, due to the thickness and material composition of layer 212, layer 212 has a major impact on the thermal expansion behavior of the substrate. In some instances, layer 212 accounts for more than 60% of the total thickness of substrate 200, making it a major determinant of the CTE (e.g., second CTE) of the substrate. For example, substrate 200 may be characterized by a first thickness, layer 210 may be characterized by a second thickness, and layer 212 may be characterized by a third thickness. The third thickness may be greater than 60% of the first thickness. Therefore, the CTE value of layer 212 may be associated with the second CTE. In some cases, the third thickness is greater than 100um and less than 2000um. The second thickness may be less than or equal to 30um. Layer 226 is characterized by a fourth thickness, which may be less than or equal to 30 um.

[0062] In various embodiments, the substrate 200 is characterized by an asymmetric configuration. The term "asymmetric" indicates that different sections or regions of the substrate 200 have different properties or configurations. In various examples, the first region 228 and the second region 230 are located at opposite sides of the substrate 200. The first region 228 may be characterized by features associated with a silicon interposer. For example, the first region 228 provides fine-pitch electrical interconnects, which enables high-density wiring and efficient connections across semiconductor devices. The second region 230 may be characterized by features associated with an organic substrate. For example, the second region 230 provides flexibility and enhanced thermal management capabilities, thereby allowing seamless integration of both passive and active components. This configuration improves CTE matching by strategically combining the rigidity of silicon-rich regions with the flexibility of organic-rich regions, which together minimize thermal stress and mitigate risks such as delamination and warping. The asymmetric configuration ensures high-density electrical interconnects and optimal thermal management while seamlessly aligning with existing assembly processes. For example, the fabrication of the substrate 200 can be achieved by masking one side, processing the other side, and then repeating a similar process on the other side.

[0063] Figures 3A to 3B 300 according to an embodiment of the present technology. These drawings are merely examples, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications.

[0064] like Figure 3A As shown in , the base layer 302 is coupled to the wafer 304 (e.g., the first wafer stated in technical solution 1). For example, the wafer 304 can be coupled to the base layer 302 by an adhesive and / or other mechanism. As an example, the term "base layer" may refer to a base material on which further processing can be performed. The base layer can be configured to provide support and facilitate the integration of various components and structures. Depending on the implementation, the base layer 302 may include one or more layers of materials that contribute to specific electrical, thermal and mechanical properties that are necessary for optimal performance and functionality of the integrated device. For example, the base layer 302 may be characterized by a high modulus (e.g., greater than 100 GPa) and / or a low CTE (e.g., less than 10 ppm / °C) to ensure stability and reliability during the manufacturing process and operational life cycle of the semiconductor device. In various examples, the base layer 302 may include, but is not limited to, at least one or more materials, such as glass, glass composites, ceramics, diamond, diamond composites, silicon, and the like. In some cases, the base layer 302 includes a first side (e.g., a front side or top side) and a second side (e.g., a back side or bottom side). The thickness of the base layer 302 can be adjusted according to the design and function of the semiconductor device. In various examples, the base layer 302 is characterized by a thickness greater than 100um and less than 2000um.

[0065] In some embodiments, wafer 304 may include a carrier wafer. The term "wafer" or "carrier wafer" may refer to a material or device that holds and protects a semiconductor die during processing, storage, or transportation. For example, wafer 304 may be coupled to one side (e.g., the second side) of base layer 302 to shield or mask the side during subsequent processing steps. This enables the unmasked side of base layer 302 to be selectively processed, thereby producing a desired asymmetric structure. Depending on the packaging technology and application, there are different types of wafers. For example, wafer 304 may include one or more materials, such as organic materials, core materials, glass materials, etc. Depending on the specific application, wafer 304 may have properties such as heat dissipation capabilities, identification codes, alignment marks, or other features.

[0066] Depending on the implementation, e.g. Figure 3B , a through hole 306 may be formed in the base layer 302. The through hole 306 may be configured to provide various functions, including but not limited to vertical interconnection, signal transmission, power distribution, heat dissipation, mechanical support, and the like. The through hole 306 may include but not limited to through silicon vias (TSVs), through glass vias (TGVs), through ceramic vias (TCVs), through diamond vias (TDVs), and the like. Depending on the material of the base layer and the desired properties of the through hole, the through hole 306 may be formed using various techniques, including but not limited to laser drilling, mechanical drilling, chemical etching, mold sintering, 3D printing, and the like. In various examples, the through hole 306 may be filled with a conductive material (e.g., copper, tungsten, titanium, aluminum, gold, silver, tin, nickel, lead, and the like) to ensure conductivity and structural integrity. In certain cases, the through hole 306 is initially formed as a through hole and may then be exposed during a later stage of the manufacturing process. The number and configuration of the through holes may depend on the specific implementation. For example, the vias 306 may include straight, sloped, angled, curved, or stepped sidewalls.

[0067] Figures 4A to 4B 400 is a simplified diagram illustrating a process of depositing one or more layers on a base layer of a semiconductor substrate 400 according to an embodiment of the present technology. These diagrams are merely examples, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications.

[0068] like Figure 4A, after forming the via 306, a layer 308 may be deposited on the base layer 302. For example, the layer 308 may be coupled to the via 306. For example, the layer 308 may include a seed layer configured to promote copper deposition to ensure optimal connectivity and conductivity within the substrate 400. The layer 308 may serve as a template for subsequent electroplating or electroless plating of a metal to fill the via 306. Depending on the implementation, the layer 308 may be one or more layers, which may include one or more materials, such as titanium nitride, tungsten, silicon oxide, copper, gold, nickel, and the like. Depending on the desired thickness and uniformity, the layer 308 may be deposited using various techniques, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. For example, PVD involves depositing a thin film of a material onto a substrate by evaporating a source material and then depositing the material onto the substrate. CVD involves depositing a thin film of material onto a substrate by reacting a gas containing the desired material on the substrate. ALD involves depositing a thin film of material onto a substrate by alternating pulses of a precursor gas and a reactant gas. In some cases, layer 308 includes a barrier layer configured to prevent diffusion of metal atoms into the base layer, which can cause electrical shorts or reliability issues. For example, the barrier layer may include, but is not limited to, tantalum, tantalum nitride, titanium, titanium nitride, and the like.

[0069] In various embodiments, such as Figure 4B , layer 310 may be deposited on layer 308. For example, layer 310 may include a through-hole plating layer that may be deposited on the wall of a through-hole (e.g., through-hole 306) by using an electrochemical process. For example, layer 310 may be deposited via an electroplating process, in which a conductive metal film is deposited by reducing metal ions in a solution onto a conductive surface (e.g., layer 308). Layer 310 may be configured to create a conductive path between different layers and fill through-hole 306 with a metallic material. This may improve the electrical performance, reliability, and thermal management of semiconductor devices. Layer 310 may include, but is not limited to, one or more materials such as copper, an organic resin, and the like.

[0070] Figure 5 5 is a simplified diagram illustrating a planarization process for manufacturing a semiconductor substrate 500 according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. Figure 5, through hole 306 may be filled with various materials, including but not limited to copper, aluminum, gold, resin, etc. For example, through hole 306 may be filled by electroplating or electroless plating process to establish electrical connection between different layers of semiconductor device. Once through hole 306 is filled, a planarization process may be performed to remove any excess material from the surface of substrate 500. For example, planarization may be performed using a mechanical or chemical process. Mechanical planarization involves using a rotating polishing wheel to remove excess material. Chemical planarization involves using a chemical solution to etch away excess metal. Planarization reduces parasitic capacitance and resistance, thereby improving the electrical performance and reliability of semiconductor devices. The planarization process also improves alignment and accuracy during subsequent photolithography steps by ensuring a uniform and level surface.

[0071] Figures 6A to 6B is a simplified diagram illustrating a photolithography process for manufacturing a semiconductor substrate 600 according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. As an example, the term "photolithography" refers to a process of using light to transfer a pattern from a photomask to a photosensitive material (e.g., photoresist) coated on a wafer surface. Alternatively, nanoimprint lithography can be used to imprint features directly on a wafer using specialized organic materials that are capable of maintaining the imprinted dimensions and tolerances immediately after curing.

[0072] like Fig. 6A As shown in , substrate 600 may be coated with a photoresist, which may refer to a photosensitive material that changes its properties when exposed to light. Photoresists may include, but are not limited to, phenolic resins, diazo resins, polyimide resins, metal oxides, and the like. In various examples, a photomask 312 may be coupled and aligned to substrate 600 (e.g., a first side). The term "photomask" may refer to a transparent plate with a pattern of opaque areas that block light. Photomask 312 helps create precise patterns for upcoming layers, such as vias and conductive traces. Maintaining proper alignment between photomask 312 and substrate 600 is important for accurate pattern transfer, which ensures functionality and connectivity of semiconductor devices in later stages. Substrate 600 may later be exposed to a light source (e.g., ultraviolet light) through photomask 312 to create the desired pattern for the next layer. As Figure 6B As shown in , pattern 314 can be created to serve as a template for subsequent fabrication steps. For example, in order to establish reliable connections and seamless integration among different components, pattern 314 can be used to form various structures, including but not limited to interconnects, wires, electrical contacts, conductive traces, vertical connections, vias, conductive pads, etc.

[0073] Figures 7A to 7C700 are simplified diagrams illustrating one or more dielectric layers of a semiconductor substrate 700 according to an embodiment of the present technology. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art will recognize many variations, alternatives, and modifications. Fig. 7A , layer 316 may be deposited on base layer 302 (e.g., a first side of base layer 302). Layer 316 may be configured to provide electrical insulation between different components. For example, layer 316 may include a dielectric layer. Layer 316 may include a first dielectric material, which includes but is not limited to one or more materials such as organic materials (e.g., built-up films, polyimide or other polymer-based dielectrics), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), etc. Depending on the implementation, layer 316 may be formed using various techniques, including but not limited to CVD, PVD, ALD, etc.

[0074] In various implementations, first wiring may be formed in layer 316 to provide various functions and capabilities, such as signal transmission, power distribution, heat dissipation, etc. The first wiring may be made of various materials including, but not limited to, one or more materials such as copper, aluminum, gold, etc. For example, Figure 7B , the first wiring may include a through hole 318, which may be filled with various materials, including but not limited to copper, aluminum, gold, etc. The through hole 318 may be configured to establish a vertical connection among different components, thereby allowing seamless electrical communication within the semiconductor device. Various techniques such as photolithography and etching, laser drilling, inlay, etc. may be used to form the through hole 318. The number and configuration of the through holes may depend on the specific implementation. For example, the through hole 318 may include straight, inclined, angled, curved, or stepped sidewalls. In some cases, the taper ratio of the through hole 318 may vary between 80% and 100%.

[0075] It will be appreciated that the composition, thickness and number of dielectric layers may be tailored to meet specific requirements and may vary depending on the application. Figure 7C, one or more layers 316 may be formed. Multiple layers may be stacked on top of each other. In some embodiments, the first wiring may include a conductive trace 320. For example, the conductive trace 320 may be configured to establish a horizontal electrical connection along the layer 316. The conductive trace 320 may include, but is not limited to, one or more materials, such as copper, aluminum, gold, and the like. The size and configuration (e.g., width, length, or thickness) of the conductive trace 320 may vary depending on the application. The conductive trace 320 may be formed using various techniques such as photolithography and etching, laser drilling, inlaying, and the like. In various implementations, the via 318 and the conductive trace 320 may be strategically coordinated to ensure consistent signal transmission and efficient power delivery within the semiconductor device. For example, the via 318 may connect the conductive traces 320 in different layers. This configuration permits electrical signals to seamlessly transition between layers, thereby facilitating advanced multi-layer circuit design and 3D integration. In some cases, the endpoints of conductive trace 320 may overlap or be in close proximity to via 318 , which improves connection reliability and minimizes risks such as short circuits or signal interference.

[0076] Figure 8 800 is a simplified diagram illustrating a passivation layer of a semiconductor substrate 800 according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications.

[0077] In various embodiments, layer 322 may be deposited on layer 316. For example, layer 322 may be configured to protect the internal semiconductor device from environmental factors such as moisture, impurities, mechanical damage, etc. In some embodiments, layer 322 may include a passivation material, which may include but is not limited to one or more materials such as organic materials (e.g., polyimide, parylene, benzocyclobutene, etc.), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), etc. Depending on the implementation, layer 322 may be configured to couple to the first circuit (e.g., Figure 1 Circuit 102). The first circuit may include an integrated circuit, such as a microprocessor, a memory chip, a digital signal processor, a system-on-chip (SoC), etc. In some examples, the first circuit may be characterized by a first CTE. For example, the first circuit includes a silicon material and the first CTE may be less than 3ppm / °C. In various embodiments, the substrate 800 may be characterized by a second CTE. For example, the ratio of the first CTE to the second CTE is greater than or equal to 3:5. By closely matching the CTE of the substrate 800 and the first circuit, the risks associated with thermal stress, such as warping or delamination, can be significantly reduced, thereby improving the reliability and life of the semiconductor device.

[0078] Depending on the implementation, a first connector may be formed in layer 322. The first connector may be configured to facilitate electrical, thermal, or mechanical connection between substrate 800 and other components. Figure 8 As shown in , the first connector includes a metal bump 324, which can be used to establish a connection between 800 and the first circuit. For example, the metal bump 324 can be made of various materials including but not limited to copper, tin, lead, aluminum, gold, etc. In some cases, the metal bump 324 includes one or more uBumps. By integrating the metal bump 324 in the layer 322, the substrate 800 can provide fine pitch, high density and low parasitic interconnection for high-performance electronic packaging.

[0079] Fig. 9 9 is a simplified diagram illustrating a passivation layer of a semiconductor substrate 900 according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. Fig. 9 , layer 326 may be deposited on layer 316. For example, layer 326 may be configured to provide protection to the underlying substrate and improve the electrical performance of the semiconductor device. In some embodiments, layer 326 may include a passivation material, which may include but is not limited to one or more materials such as organic materials (e.g., polyimide, parylene, benzocyclobutene, etc.), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), and the like.

[0080] Depending on the implementation, a first connector may be formed in layer 326. The first connector may be configured to facilitate electrical, thermal, or mechanical connection between substrate 900 and other components. Fig. 9 , the first connector includes a conductive pad 328, which may include various materials such as copper, gold, silver, aluminum, tin, etc. In some examples, the conductive pad 328 may include a hybrid copper bonding pad that combines dielectric bonding with metal bonding to form an interconnect between the substrate 900 and the first circuit. The hybrid copper bonding may include bonding between copper or other metals (e.g., gold, etc.) and a dielectric material, which may be organic (e.g., small molecules or monomers, etc.) or inorganic (e.g., silicon oxide, other metal oxides, etc.). For example, the conductive pad 328 may be embedded in the layer 326 to provide an electrical, thermal, or mechanical connection between the substrate 900 and the first circuit, thereby providing a high connection density with a narrow pitch (e.g., less than 10um) for high performance applications.

[0081] Fig.101 is a simplified diagram illustrating one or more wafers of coupled semiconductor substrate 1000 according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications.

[0082] As previously described, the substrate 1000 may include two or more regions (eg, Figure 2 The first region 1000 is characterized by an asymmetric configuration of a first region 228 and a second region 230 of the substrate 1000. For example, the first region may be fabricated based on one or more processes shown in FIGS. 3 to 9. The first region is characterized by features associated with a silicon interposer that provide fine-pitch electrical interconnects, thereby enabling high-density wiring and efficient connections across semiconductor devices. To facilitate the fabrication of an asymmetric structure, the fabrication of substrate 1000 may be achieved by masking one side, processing the other side, and then repeating a similar process on the other side. For example, after the first region has been processed, a second wafer (e.g., wafer 330) may be used to form the second region. The second region of substrate 1000 may have different properties or configurations than the first region. In some examples, the second region may be characterized by features associated with an organic substrate that provide flexibility and enhanced thermal management capabilities, thereby allowing seamless integration of both passive and active components.

[0083] In various implementations, wafer 330 may be coupled to substrate 1000 (e.g., a first side of substrate 1000). For example, wafer 330 may be coupled to layer 322. In certain cases, one or more components (e.g., electronic or semiconductor elements) may be mounted to substrate 1000 prior to coupling wafer 330. Integration of these components may be achieved using various techniques, including but not limited to thermocompression bonding (TCB), hybrid copper bonding (HCB), fusion bonding, and the like. Depending on the implementation, subsequent molding and / or planarization processes may be performed to encapsulate and smooth the surfaces of the bonded components.

[0084] According to some embodiments, wafer 330 may be coupled to a side different from the side of wafer 304. For example, wafer 330 is coupled to a first side and wafer 304 is coupled to a second side, or vice versa. In some cases, the first side and the second side are opposite to each other. As an example, wafer 330 includes a carrier wafer that can be configured to provide structural rigidity and support for the formation and processing of semiconductor substrate 1000. Wafer 330 can be coupled to substrate 1000 by adhesive and / or other mechanisms. In various examples, wafer 330 can include one or more materials, such as organic materials, core materials, glass materials, etc. Depending on the specific application, wafer 330 can have properties such as heat dissipation capabilities, identification codes, alignment marks, or other features.

[0085] Fig.11 1 is a simplified diagram illustrating a process of detaching a wafer from a semiconductor substrate 1100 according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. As illustrated, the wafer 304 can be detached from the substrate 1100. Depending on the implementation, various methods can be used to detach the wafer 304 from the substrate 1100, which may involve weakening the bonding between the wafer 304 and the substrate 1100 by applying a solvent, a laser beam, heat, an electric field, etc. In a specific embodiment, the wafer 304 can be coupled to the substrate 1100 using an adhesive and can be detached by a mechanical and / or chemical process. After detaching the wafer 304, the second side of the substrate 1100 can be exposed for subsequent processing and integration.

[0086] Fig.12 316. It is a simplified diagram illustrating one or more dielectric layers of a semiconductor substrate 1200 according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. As shown, after removing the wafer 304, layer 322 may be deposited on the base layer 302 (e.g., the second side of the base layer 302). Layer 332 may be configured to provide electrical insulation between different components. For example, layer 332 may include a dielectric layer. Layer 332 may include a second dielectric material, which includes but is not limited to one or more materials, such as organic materials (e.g., stacked films, polyimides or other polymer-based dielectrics), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), and the like. In some cases, the second dielectric material may be different from the first dielectric material of layer 316. Depending on the implementation, various techniques may be used to form layer 332, including but not limited to CVD, PVD, ALD, and the like.

[0087] In various embodiments, a second wiring may be formed in layer 332 to provide various functions and capabilities, such as signal transmission, power distribution, heat dissipation, and the like. The second wiring may be made of various materials including, but not limited to, one or more materials such as copper, aluminum, gold, and the like. For example, the second wiring may include a through hole 334, which may be filled with various materials, including, but not limited to, copper, aluminum, gold, and the like. The through hole 334 may be configured to establish a vertical connection among different components, thereby allowing seamless electrical communication within the semiconductor device. Various techniques such as photolithography and etching, laser drilling, inlay, and the like may be used to form the through hole 334. The number and configuration of the through holes may depend on the specific embodiment. For example, the through hole 334 may include a straight, inclined, angled, curved, or stepped sidewall. In some cases, the taper ratio of the through hole 334 may vary between 80% and 100%.

[0088] It should be understood that the composition, thickness and number of dielectric layers can be tailored to meet specific requirements and can vary depending on the application. For example, one or more layers 332 can be formed. Multiple layers can be stacked on top of each other. In some embodiments, the second wiring may include a conductive trace 336. For example, the conductive trace 336 can be configured to establish a horizontal electrical connection along the layer 332. The conductive trace 336 may include, but is not limited to, one or more materials, such as copper, aluminum, gold, etc. The size and configuration (e.g., width, length, or thickness) of the conductive trace 336 may vary depending on the application. The conductive trace 336 can be formed using various techniques such as photolithography and etching, laser drilling, inlaying, etc. In various implementations, the through hole 334 and the conductive trace 336 can be strategically coordinated to ensure consistent signal transmission and efficient power delivery within the semiconductor device. For example, the through hole 334 can connect the conductive trace 336 among different layers. This configuration allows electrical signals to seamlessly transition between layers, thereby facilitating advanced multi-layer circuit design and 3D integration. In some cases, the endpoints of conductive trace 336 may overlap or be in close proximity to via 334 , which improves connection reliability and minimizes risks such as short circuits or signal interference.

[0089] In some embodiments, layer 338 may be deposited on layer 332. For example, layer 338 may include a solder resist material that may be configured to protect the semiconductor device from solder and other contaminants. The solder resist material may include, but is not limited to, one or more materials such as epoxy resins, acrylic resins, polyimide resins, and the like. In some cases, layer 338 may be patterned to expose areas where soldering is required, thereby allowing substrate 1300 to be coupled to other components (e.g., a printed circuit board). Depending on the implementation, layer 338 may be deposited using various techniques including, but not limited to, screen printing, spraying, and the like.

[0090] Fig.13 1 is a simplified diagram illustrating a process of detaching a wafer from a semiconductor substrate 1300 according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. As previously described, the substrate 1300 may include two or more regions (e.g., Figure 2 For example, based on Figures 10 to 13 The second region is fabricated using one or more processes illustrated in . The second region of substrate 1300 may have different properties or configurations than the first region. In some examples, the second region may be characterized by features associated with an organic substrate that provide flexibility and enhanced thermal management capabilities, thereby allowing seamless integration of both passive and active components.

[0091] like Fig.13 , after the second region has been processed, the wafer 330 may be detached from the substrate 1300. Depending on the implementation, the wafer 330 may be detached from the substrate 1300 using various methods, which may involve weakening the bond between the wafer 330 and the substrate 1300 by applying a solvent, a laser beam, heat, an electric field, etc. In a particular embodiment, the wafer 330 may be coupled to the substrate 1300 using an adhesive and may be detached by mechanical and / or chemical processes.

[0092] Figures 14A to 14B 1400 according to an embodiment of the present technology. These drawings are merely examples, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. Fig.14A , the base layer 302 is coupled to the wafer 304. For example, the wafer 304 can be coupled to the base layer 302 by an adhesive and / or other mechanism. The base layer 302 may include, but is not limited to, at least one or more materials, such as glass, glass composites, ceramics, diamond, diamond composites, silicon, etc. As an example, the base layer 302 includes a first side (e.g., a front side or top side) and a second side (e.g., a back side or bottom side). Depending on the implementation, the wafer 304 can be coupled to the first side or the second side. The thickness of the base layer 302 can be adjusted according to the design and function of the semiconductor device. In various examples, the base layer 302 is characterized by a thickness greater than 100um and less than 2000um.

[0093] like Fig. 14B , a through hole 306 may be formed in the base layer 302. The through hole 306 may be configured to provide various functions, including but not limited to vertical interconnection, signal transmission, power distribution, heat dissipation, mechanical support, etc. The number and configuration of the through holes may depend on the specific implementation. For example, the through hole 306 may include straight, inclined, angled, curved or stepped sidewalls. In a particular embodiment, a cavity 340 may be formed in the base layer 302. Depending on the implementation, various techniques including but not limited to laser drilling, punching, etching, molding, 3D printing, etc. may be used to form the cavity 340. The cavity 340 may be used to integrate one or more components to enhance overall performance, as will be described later. The configuration of the cavity 340 (e.g., shape, size, depth, etc.) may vary depending on the material, component type and / or manufacturing method of the base layer 302.

[0094] Figures 15A to 15B1 is a simplified diagram illustrating a process of depositing one or more layers on a base layer of a semiconductor substrate 1500 according to an embodiment of the present technology. These diagrams are merely examples, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. Fig.15A , circuit 342 may be embedded in cavity 340. Depending on the implementation, circuit 342 may be embedded in cavity 340 using various techniques including, but not limited to, adhesives, soldering, hybrid copper bonding, and the like. Circuit 342 may include, but is not limited to, memory, thermal components, mechanical components, optical components, electrical components, and the like. For example, circuit 342 may include one or more passive or active components such as waveguides, lenses, voltage regulators, and the like. This may save space on the outer layers, allowing for more efficient wiring and reducing the need for additional layers.

[0095] In various embodiments, after the circuit 342 is embedded in the base layer 302, one or more layers may be deposited on the base layer 302 to provide protection and facilitate subsequent processing. Fig.15A , layer 344 may be deposited on base layer 302. Layer 344 may include a seed layer configured to promote copper deposition to ensure optimal connectivity and conductivity within substrate 1500. Layer 344 may serve as a template for subsequent electroplating or electroless plating of metal to fill through-hole 306. Depending on the implementation, layer 344 may be one or more layers, which may include one or more materials, such as titanium nitride, tungsten, silicon oxide, copper, gold, nickel, and the like. Depending on the desired thickness and uniformity, layer 344 may be deposited using various techniques, including but not limited to PVD, CVD, ALD, and the like. In some cases, layer 344 includes a barrier layer configured to prevent metal atoms from diffusing into the base layer, which may cause electrical shorts or reliability issues. For example, the barrier layer may include but is not limited to tantalum, tantalum nitride, titanium, titanium nitride, and the like.

[0096] In some embodiments, layer 346 may be deposited on layer 344. For example, layer 346 may include a via plating layer that may be deposited on the vias (e.g., Fig. 14B 306). For example, layer 346 may be deposited via an electroplating process, in which a conductive metal film is deposited by reducing metal ions in a solution onto a conductive surface (e.g., layer 344). Layer 346 may be configured to create a conductive path between different layers and fill via 306 with a metallic material. This may improve the electrical performance, reliability, and thermal management of the semiconductor device. Layer 346 may include, but is not limited to, one or more materials such as copper, an organic resin, and the like.

[0097] Although the above is a comprehensive description of specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the present technology as defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a substrate; as well as coupling a first circuit to the substrate, the first circuit being characterized by a first coefficient of thermal expansion, the substrate being characterized by a second coefficient of thermal expansion, a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion being greater than or equal to 3:5; The forming of the substrate comprises: providing a substrate layer, the substrate layer comprising a first side and a second side; coupling a first wafer to the second side; forming a first through hole in the base layer; depositing a first layer on the first side, the first layer comprising a first dielectric material; forming a first wiring in the first layer; depositing a second layer on the first layer; and A first connection is formed in the second layer, and the first circuit is coupled to the substrate via the first connection. The method of claim 1 , wherein the first connector comprises a conductive pad. The method according to claim 1 , wherein the first connector comprises a metal bump.

4. The method according to claim 1, wherein: The substrate is characterized by a first thickness; The base layer is characterized by a second thickness; and The second thickness is greater than 60% of the first thickness. The method according to claim 1 , wherein the base layer comprises a glass material, a ceramic material, a diamond material or a silicon material.

6. The method according to claim 1, further comprising: A third layer is deposited on the substrate, the third layer coupled to the first via. 7 . The method according to claim 6 , wherein the third layer comprises a titanium nitride material, a tungsten material, a silicon oxide material or a copper material. The method according to claim 1 , wherein the first dielectric material comprises a polyimide material or a silicon nitride material.

9. The method of claim 1, wherein the second layer comprises a passivation material.

10. The method according to claim 1, further comprising: coupling a second wafer to the second layer; and The first wafer is detached from the base layer. The method of claim 10 , further comprising depositing a fourth layer on the second side, the fourth layer comprising a second dielectric material.

12. The method of claim 11, wherein the second dielectric material is different from the first dielectric material. 13 . The method of claim 11 , further comprising forming a second wiring in the fourth layer, the second wiring comprising a metal material.

14. A method for manufacturing a semiconductor device, the method comprising: forming a substrate; as well as coupling a first circuit to the substrate, the first circuit being characterized by a first coefficient of thermal expansion, the substrate being characterized by a second coefficient of thermal expansion, a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion being greater than or equal to 3:5; The forming of the substrate comprises: providing a substrate layer, the substrate layer comprising a first side and a second side; coupling a first wafer to the second side; forming a first through hole in the base layer; forming a cavity in the base layer, the cavity being positioned on the first side; embedding a second circuit in the cavity; depositing a first layer on the first side, the first layer comprising a first dielectric material; forming a first wiring in the first layer; depositing a second layer on the first layer; and A first connection is formed in the second layer, and the first circuit is coupled to the substrate via the first connection.

15. The method of claim 14, wherein the second circuit comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component.

16. The method of claim 14, wherein: The substrate is characterized by a first thickness; The base layer is characterized by a second thickness; and The second thickness is greater than 60% of the first thickness.

17. The method of claim 14, wherein the first layer is characterized by a third thickness, the third thickness being less than or equal to 30 um.

18. The method of claim 14, wherein the base layer comprises a glass material, a ceramic material, a diamond material, or a silicon material.

19. A method for manufacturing a semiconductor device, the method comprising: providing a substrate layer, the substrate layer comprising a first side and a second side; coupling a first wafer to the second side; forming a first through hole in the base layer; depositing a first layer on the first side, the first layer comprising a first dielectric material; forming a first wiring in the first layer; and A second layer is deposited on the first layer.

20. The method of claim 19, further comprising embedding circuitry in the base layer.

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