Integrated circuit package, semiconductor device and method of manufacturing same

Abstract

A method of manufacturing a semiconductor device includes bonding a first die and a second die to a first side of a wafer, where after bonding the first die and the second die to the first side of the wafer, a gap is provided between the first die and the second die, wherein the first portion of the gap has a first width greater than a second width of the second portion of the gap, depositing a third dielectric layer on top surfaces and sidewalls of the first and second dies and on a bottom surface within the gap, forming a molding material over the third dielectric layer to fill the gap, and performing a planarization process to expose top surfaces of the first die and the second die.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit package, a semiconductor device and a manufacturing method thereof. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and layers of semiconductor material on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and assemblies thereon. Tens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are separated by sawing the integrated circuits along scribe lines. The individual dies are then individually packaged, for example, in a multi-chip module or other type of package.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0004] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising dividing a first wafer to separate a first die of the first wafer from a second die of the first wafer; and bonding the first die and the second die to a first side of a second wafer, wherein after bonding the first die and the second die to the first side of the second wafer, a gap is set between the first die and the second die, wherein a first dielectric layer of each of the first die and the second die is directly bonded to a second dielectric layer of the second wafer, and wherein a first portion of the gap has a first width greater than a second width of a second portion of the gap; depositing a third dielectric layer on top surfaces and side walls of the first die and the second die and on a bottom surface within the gap; forming a molding material over the third dielectric layer to fill the gap; performing a planarization process to expose top surfaces of the first die and the second die; and coupling a packaging substrate to a second side of the second wafer using a conductive connector, the second side of the second wafer being a side opposite to the first side of the second wafer.

[0005] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising bonding a plurality of crystal grains to a wafer, wherein after bonding the plurality of crystal grains to the wafer, setting a gap between adjacent crystal grains among the plurality of crystal grains, wherein the width of a top portion of the gap is greater than the width of a bottom portion of the gap; depositing a first dielectric layer on side walls of adjacent crystal grains within the gap and on a bottom surface of the gap, wherein the first dielectric layer fills the bottom portion of the gap; forming a molding material to fill the top portion of the gap; and flattening the molding material so that a top surface of the molding material is flush with a top surface of an adjacent crystal grain among the plurality of crystal grains.

[0006] An embodiment of the present invention provides a package, comprising a first die and a second die located on a first side of a third die and bonded to the first side of the third die, wherein the first die and the second die include a top portion; and a bottom portion, wherein each top portion has a first width, and each bottom portion has a second width greater than the first width; a first dielectric layer is disposed on adjacent side walls of the top portion and on adjacent side walls of the bottom portion; a molding material is located above the first dielectric layer, wherein the molding material is disposed above the bottom portions of the first die and the second die, and wherein a top surface of the molding material is flush with a top surface of the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 3 Cross-sectional views of intermediate steps during a process for forming a semiconductor die are shown in accordance with some embodiments.

[0009] Figures 4 to 12 Cross-sectional views are shown of intermediate steps during a process for forming an integrated chip package in accordance with some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than representing the relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one device or feature shown in a figure to another (other) device or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0012] Various embodiments provide methods for forming 3D integrated chip (3DIC) packages (e.g., integrated chip system (system on integrated chip, SoIC) packages). Forming an integrated chip package includes bonding two or more semiconductor grains (e.g., top grains) to a semiconductor wafer (e.g., bottom grains). A dielectric layer (e.g., oxide) is formed on the top surface and sidewalls of the semiconductor grains and on the bottom surface of the gaps between the semiconductor grains. A molding material is then formed to fill the remaining gaps. Advantageous features of one or more embodiments disclosed herein may include better bonding strength of the dielectric layer compared to the molding material, thereby allowing improved bonding of the semiconductor grains to the semiconductor wafer. In addition, during the thermal treatment process for curing the molding material, the dielectric layer has a lower thermal expansion than the molding material. As a result, each semiconductor grain has better bending resistance at each grain corner, and reduces the risk of semiconductor grain delamination. This further results in a more robust integrated chip package with better electrical connection to any external device (e.g., a packaging substrate), which allows enhanced device reliability.

[0013] Figures 1 to 12 1 shows a cross-sectional view of an intermediate step during a process for forming an integrated chip package 100 according to some embodiments. Figure 1, a wafer 10 is shown. The wafer 10 includes semiconductor dies 150. Each semiconductor die 150 may be a logic die (e.g., an application processor (AP), a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wideIO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), ... The wafer 10 may include a substrate 117 (e.g., a semiconductor substrate), an interconnect structure 119 disposed on the substrate 117, a bonding layer 121 disposed on the interconnect structure 119, and a bonding pad 123 disposed in the bonding layer 121 and exposed to the front surface of the wafer 10. The face of the wafer 10 including the exposed bonding pad 123 and the bonding layer 121 may also be subsequently referred to as the front face of the wafer 10.

[0014] The substrate 117 of the wafer 10 may include a crystalline silicon wafer. Depending on the design requirements, the substrate 117 may include various doped regions (e.g., a p-type substrate or an n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured for n-type fin field effect transistors (Fin-type Field Effect Transistors, FinFETs) and / or p-type FinFETs. In some alternative embodiments, the substrate 117 may include an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 117 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0015] Active and / or passive devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on the substrate 117. The devices may be interconnected through the interconnect structure 119. The interconnect structure 119 electrically connects the devices on the substrate 117 to form one or more integrated circuits. The interconnect structure 119 may include one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, etc.) and interconnect wiring or metallization patterns embedded in the one or more dielectric layers. The material of the one or more dielectric layers may include silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0), or other suitable dielectric materials. The interconnect wiring may include metal wiring. For example, the interconnect wiring includes copper wiring, copper pads, aluminum pads, or a combination thereof formed by one or more single damascene processes, dual damascene processes, etc. The side of wafer 10 including the exposed backside of substrate 117 may subsequently also be referred to as the backside of wafer 10 .

[0016] The bonding layer 121 may include a dielectric layer. The bonding pad 123 is embedded in the bonding layer 121, and the bonding pad 123 allows connection with the interconnect structure 119 and the device on the substrate 117. The material of the bonding layer 121 may be silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0), tetraethyl orthosilicate (TEOS) or other suitable dielectric materials, and the bonding pad 123 may include a conductive pad (e.g., a copper pad), a conductive via (e.g., a copper via), or a combination thereof. The bonding layer 121 can be formed by depositing a dielectric material over the interconnect structure 119 using a chemical vapor deposition (CVD) process (e.g., a plasma enhanced CVD process or other suitable process); patterning the dielectric material to form the bonding layer 121 including openings or through holes; and filling the openings or through holes defined in the bonding layer 121 with a conductive material to form a bonding pad 123 embedded in the bonding layer 121.

[0017] exist Figure 2 In the process, a mask layer 124 (e.g., a photoresist) is formed over the wafer 10, such as over the bonding layer 121 and the bonding pad 123. The mask layer 124 is patterned using suitable development and exposure techniques to form an opening in the mask layer 124 that exposes the top surface of the wafer 10. A plasma cutting process 126 is then performed to form a groove 125 that partially extends through the exposed portion of the wafer 10. In an embodiment, the plasma cutting process 126 is a dry etching process that includes a fluorine plasma that can be used to etch narrow, deep vertical grooves. In an embodiment, the plasma cutting process 126 can be a dry plasma process, such as a deep reactive ion etching (DRIE) process using a plasma gas including sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8), etc. As a result of the plasma cutting process 126, the first groove 125 and the second groove 125 are disposed between adjacent sidewalls of the paired semiconductor grains 150. Each groove 125 may have a depth D1 in a range from 10 μm to 700 μm. In some embodiments, each groove 125 may extend through the bonding layer 121 , the interconnect structure 119 , and partially through the substrate 117 .

[0018] exist Figure 3In the process, the mask layer 124 is removed using an acceptable ashing or stripping process. A temporary tape (e.g., back grinding tape) may then be applied to the front side of the wafer 10, for example, over the bonding layer 121, the bonding pad 123, and the interconnect structure 119. The wafer 10 is then flipped over, and a thinning process may then be performed on the back side of the wafer 10. The thinning process may be performed, for example, using a mechanical grinding or chemical mechanical polishing (CMP) process, in which chemical etchants and abrasives are used to react and grind away portions of the substrate 117. The back grinding tape is used to provide mechanical support during this thinning process. After the thinning process, the back grinding tape may be removed using a suitable process. In one embodiment, after the thinning process, the height H1 of the wafer 10 may be in the range of 100 μm to 700 μm. In another embodiment, the height H1 of the wafer 10 may be greater than 350 μm.

[0019] After the above-mentioned thinning process, the wafer 10 is then mounted on a frame ( Figure 3 The adhesive tape (not shown) supporting Figure 3 For example, the front side of the wafer 10 (eg, the bonding layer 121 and the bonding pad 123) is attached to a frame ( Figure 3 The adhesive tape (not shown) supporting Figure 3 The tape may be a dicing tape used to secure the wafer 10 in place during subsequent processing.

[0020] Then, along the cutting path 129 (by Figure 3 The blade cutting process 128 is performed (indicated by the dotted lines in FIG. 1 ). Each cutting path 129 is set between adjacent semiconductor grains 150. In addition, each cutting path 129 also overlaps with two adjacent grooves 125 between adjacent semiconductor grains 150. In addition, the cutting path 129 can also surround the edge portion of each adjacent semiconductor. The blade cutting process 128 forms grooves along the cutting path 129, and the grooves partially extend through the substrate 117 and connect to the grooves 125, which causes the semiconductor grains 150 to be separated from each other along the cutting path 129. The cutting process 128 includes using a high-speed rotating grinding disk or blade saw to cut along the cutting path 129. The tip of the blade may include abrasive grit or a thin diamond layer.

[0021] Each singulated semiconductor grain 150 includes a top portion 150A of the semiconductor grain and a bottom portion 150B of the semiconductor grain. The bottom portion 150B of the semiconductor grain may have a width W1 greater than the width W2 of the top portion 150A of the semiconductor grain. In this way, each sidewall of the bottom portion 150B of the semiconductor grain is offset from the corresponding sidewall of the top portion 150A of the semiconductor grain by a width W3. Each semiconductor grain 150 may have a stepped surface 117A, which also defines the top surface of the bottom portion 150B of the semiconductor grain. Each stepped surface 117A may have a width W3. In an embodiment, the stepped surface 117A may be a circular or curved surface. A cleaning process or rinsing may then be performed to clean the surface of the semiconductor grain 150. In an embodiment, the cleaning process may include exposing the surface of the semiconductor grain 150 to a cleaning solution, deionized water, or the like.

[0022] exist Figure 4 , a semiconductor wafer 20 is bonded to a semiconductor die 150. Wafer 20 may also be referred to as a bottom die subsequently. Wafer 20 includes a first packaging area 200A and a second packaging area 200B, and one or more integrated chip packages 100 are packaged in each packaging area 200A and 200B to form an integrated circuit package. The materials and formation processes of the features in wafer 20 can be found by referring to similar features in wafer 10, where similar features in wafer 10 start with the number "1", and these features correspond to features in wafer 20 with reference numerals starting with the number "2". For example, wafer 20 may include a substrate 217 on which devices (e.g., transistors, capacitors, diodes, resistors, etc.) are formed and an interconnect structure 219. The interconnect structure 219 is electrically connected to the devices on the substrate 217 to form one or more integrated circuits. The interconnect structure 219 includes one or more dielectric layers (eg, one or more interlayer dielectric (ILD) layers, intermetal dielectric (IMD) layers, etc.) and interconnect wiring or metallization patterns embedded in the one or more dielectric layers.

[0023] A bonding layer 221 is disposed on the interconnect structure 219, and a bonding pad 223 is disposed in the bonding layer 221. The bonding pad 223 allows the interconnect structure 219 to be connected to a device on the substrate 217. The wafer 20 also includes a through substrate via (TSV) 211 that can be electrically connected to a metallization pattern in the interconnect structure 219. The TSV 211 can be formed by forming a groove in the substrate 217 by, for example, etching, milling, laser technology, and / or a combination thereof. A thin barrier layer can be conformally deposited over the front side of the substrate 217 and in the opening, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, and / or a combination thereof. The barrier layer can include a nitride or an oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tungsten nitride, a combination thereof, and the like. A conductive material is deposited over the thin barrier layer and in the opening. The conductive material may be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, etc. Examples of the conductive material include copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and barrier layers may be removed from the front side of the substrate 217 by, for example, chemical mechanical polishing. Thus, in some embodiments, the TSV 211 may include a conductive material and a thin barrier layer between the conductive material and the substrate 217. In subsequent processing steps, the substrate 217 may be thinned to expose the TSV 211 (see FIG. 2 ). Figure 7 ). After thinning, TSV 211 provides electrical connection from the back side of substrate 217 to the front side of substrate 217. In various embodiments, the back side of substrate 217 may refer to the side of substrate 217 opposite to the device and interconnect structures 219, and the front side of substrate 217 may refer to the side of substrate 217 on which the device and interconnect structures 219 are disposed.

[0024] Still reference Figure 4, the semiconductor die 150 is bonded to the wafer 20, for example, in a hybrid bonding configuration. The semiconductor die 150 is disposed face-down so that the front side of the semiconductor die 150 faces the wafer 20 and the back side of the semiconductor die 150 is away from the wafer 20. The semiconductor die 150 is bonded to the bonding layer 221 and the bonding pad 223 in the bonding layer 221 on the front side. For example, the bonding layer 121 of the semiconductor die 150 can be directly bonded to the bonding layer 221 of the wafer 20, and the bonding pad 123 of the semiconductor die 150 can be directly bonded to the bonding pad 223 of the wafer 20. In an embodiment, the bonding between the bonding layer 121 and the bonding layer 221 can be oxide-to-oxide bonding, etc. The hybrid bonding process also directly bonds the bonding pad 123 of the semiconductor die 150 to the bonding pad 223 of the wafer 20 through direct metal-to-metal bonding. Therefore, the electrical connection between the semiconductor die 150 and the wafer 20 is provided by the physical connection of the bonding pad 123 to the bonding pad 223.

[0025] One or more of the bonding layer 121 or the bonding layer 221 is subjected to surface treatment. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to one or more of the bonding layer 121 or the bonding layer 221. Then the bonding pad 123 may continue to be aligned with the bonding pad 223. Next, the hybrid bonding includes a pre-bonding step during which the semiconductor grain 150 is contacted with the wafer 20. The pre-bonding may be performed at the following position: room temperature (e.g., between about 21°C and about 25°C). The hybrid bonding process continues to perform annealing, for example, at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g., copper) in the bonding pad 123 and the metal (e.g., copper) of the bonding pad 223 diffuse into each other, thereby forming a direct metal-to-metal bond. Although four semiconductor grains 150 are shown as being bonded to the wafer 20, other embodiments may include any number of semiconductor grains 150 bonded to the wafer 20. After the semiconductor dies 150 are bonded to the wafer 20, the gaps 127 may be disposed between the sidewalls of adjacent semiconductor dies 150. For example, the lower portion 127B of each gap may be disposed between the sidewalls of the bottom portions 150B of adjacent semiconductor dies, and the upper portion 127A of each gap may be disposed between the sidewalls of the top portions 150A of adjacent semiconductor dies. The upper portion 127A of the gap may have a greater width than the lower portion 127B of the gap.

[0026] exist Figure 5 In the embodiment, the dielectric layer 130 is formed on Figure 4127. For example, dielectric layer 130 is formed on the top surface and sidewalls of semiconductor grains 150. Semiconductor grains 130 are formed on the top surface and sidewalls of the top portion 150A of each semiconductor grain. Dielectric layer 130 is also formed on the top surface (e.g., step surface 117A) and sidewalls of the bottom portion 150B of each semiconductor grain. In addition, dielectric layer 130 is formed on the bottom surface within gap 127 so that dielectric layer 130 is in physical contact with the top surface of wafer 20. Dielectric layer 130 may be conformally deposited using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In an embodiment, the dielectric layer may include silicon oxide (SiOx, where x>0), silicon nitride (SiNx, where x>0), silicon oxynitride (SiOxNy, where x>0 and y>0), or the like. In other embodiments, the dielectric layer 130 may include silicon carbon nitride (SiCN), tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), etc. In other embodiments, the dielectric layer 130 may be a conformal and dense dielectric film formed using a high-density plasma (HDP) deposition method such as plasma enhanced chemical vapor deposition (PECVD). In an embodiment, the thickness T1 of the dielectric layer 130 may be in the range of 0.1 μm to 2 μm. Because the lower portion 127B of the gap has a smaller width than the upper portion 127A of the gap, the dielectric layer 130 may completely fill the lower portion 127B of each gap and only partially fill the upper portion 127A of each gap. In an embodiment, the dielectric layer 130 may have a thermal expansion coefficient in the range of 0.1 μm / m·℃ to 5 μm / m·℃.

[0027] Advantages may be achieved by forming a dielectric layer 130 on the top surface and sidewalls of the semiconductor grains 150 and within the gaps 127, wherein the dielectric layer 130 has a thickness T1 in the range from 0.1 μm to 2 μm. These advantages include that the dielectric layer 130 has a high bonding strength, which results in improved bonding of the semiconductor grains 150 to the semiconductor wafer 20. Therefore, each semiconductor grain 150 has better resistance to bending at each grain corner, and the risk of the semiconductor grains 150 having delamination is reduced. For example, a dielectric layer 130 having a thickness below 0.1 μm will result in insufficient bonding strength between the semiconductor grains 150 and the semiconductor wafer 20, resulting in an increased risk of delamination of the semiconductor grains 150. Additional advantages may be that this may be achieved by forming the dielectric layer 130 above the stepped surfaces 117A of the semiconductor grains 150, which includes an increase in available surface area due to the stepped structure of the semiconductor grains 150, so more dielectric material is allowed to be deposited on each semiconductor grain 150. This allows for better bonding strength and improves the bond between the semiconductor die 150 and the semiconductor wafer 20 .

[0028] exist Figure 6 In the embodiment, the molding material (or molding compound) 132 is formed on Figure 5 12A and 12B are formed on the structure shown in the figure so as to fill the gaps 127. For example, the molding material 132 can be formed on the surface of the dielectric layer 130 and inside the gaps 127 to fill the upper portion 127A of each gap. The molding material 132 is isolated from the top surface of the wafer 20 and the sidewalls and top surfaces of the semiconductor grains 150 by the dielectric layer 130. The molding material 132 may include a dielectric material, such as a silicon-based material, an epoxy resin, a molding material including silicon dioxide, etc. The molding material 132 may be formed using any suitable process, such as spin coating, a deposition process, an injection process, etc. After the molding material 132 is formed, a curing process may be performed at a temperature in the range of 100° C. to 250° C. to harden the molding material 132. In an embodiment, the molding material 132 is disposed above the bottom portion 150B of the semiconductor grains. In an embodiment, the molding material 132 may have a thermal expansion coefficient in the range of 5 μm / m·° C. to 50 μm / m·° C. In an embodiment, the thermal expansion coefficient of the dielectric layer 130 may be lower than the thermal expansion coefficient of the molding material 132 .

[0029] Advantages may be achieved by forming the dielectric layer 130 and the molding material 132 within the gap 127 such that the dielectric layer 130 is disposed between the sidewalls of the semiconductor die 150 and the molding material 132 and between the wafer 20 and the molding material 132, wherein the thickness T1 of the dielectric layer 130 ranges from 0.1 μm to 2 μm. These advantages include the dielectric layer 130 having a lower coefficient of thermal expansion than the molding material 132, the thermal expansion coefficient of the dielectric layer 130 being in the range of 0.1 μm / m·°C to 5 μm / °C, such that the dielectric layer 130 undergoes a smaller amount of thermal expansion during the above-described curing process for curing the molding material 132. As a result, each semiconductor die 150 has better resistance to bending at each die corner, and the risk of semiconductor die 150 delamination is reduced. For example, a dielectric layer 130 having a thickness below 0.1 μm will cause the molding material to be too close to the die corner of the semiconductor die 150, and the thermal expansion of the molding material 132 will result in an increased risk of delamination of the semiconductor die 150. Therefore, as described above, the dielectric layer 130 and the molding material 132 are formed within the gap 127, wherein the dielectric layer 130 has a thickness T1 in the range of 0.1 μm to 2 μm, resulting in a more robust integrated chip package 100 with better electrical connection to any external device (e.g., a package substrate), which allows for enhanced device reliability.

[0030] After forming the molding material 132, a planarization process is performed to remove excess portions of the molding material 132. In addition, during the planarization process, a portion of the dielectric layer 130 is also removed to expose the top surface of the semiconductor grain 150. The planarization process may include a grinding process, a CMP process, etc. Figure 6 As shown, the planarization process may cause the top surfaces of the semiconductor die 150 and the dielectric layer 130 to be flush with the top surface of the molding material 132 .

[0031] After the planarization process, a carrier substrate 136 is attached to the planarized surfaces of the semiconductor die 150, the dielectric layer 130, and the molding material 132. In an embodiment, the carrier substrate 136 includes, for example, a silicon-based material, such as glass or silicon oxide, or other materials, such as aluminum oxide, or any combination of these materials, etc. The carrier substrate 136 is planar so that a release layer 134 can be used to attach to the semiconductor die 150, the dielectric layer 130, and the molding material 132. The release layer 134 can be formed of a polymer-based material, which can be removed from the underlying structure together with the carrier substrate 136 in a subsequent step. In some embodiments, the release layer 134 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 134 can be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 134 may be dispensed as a liquid and cured, may be a laminated film laminated onto the carrier substrate 136, etc. The top surface of the release layer 134 may be flat and may have a high degree of flatness.

[0032] exist Figure 7 In the embodiment, a thinning process of the back side of the substrate 217 is performed to expose the TSV 211. The thinning process of the back side of the substrate 217 may be performed by a planarization process such as CMP, grinding, or etching. The thinning process may cause the surface of the TSV 211 to be flush with the surface of the back side of the substrate 217.

[0033] exist Figure 8 In the embodiment, polymer layer 234 is formed over exposed surfaces of substrate 217 and TSV 211. In an embodiment, polymer layer 234 may include polybenzoxazole (PBO), polyimide (PI), a polyimide derivative, or the like. Polymer layer 234 may be formed using a spin coating process or the like. Figure 8 Also shown is the patterning of the polymer layer 234 to form openings that expose the TSVs 211. In an embodiment, the polymer layer 234 may be patterned using, for example, a laser drilling method. In this method, a light-to-heat conversion (LTHC) layer ( Figure 8 Once protected, the laser is directed to those portions of the polymer layer 234 that need to be removed in order to expose the underlying TSV 211.

[0034] In another embodiment, by first applying a photoresist ( Figure 8A photoresist (not shown separately) is applied to the polymer layer 234, and then the photoresist is exposed to a patterned energy source (e.g., a patterned light source) to initiate a chemical reaction, thereby inducing a physical change in the portion of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to utilize the physical change and selectively remove the exposed portion of the photoresist or the unexposed portion of the photoresist according to the desired pattern and the exposed portion of the polymer layer 234 thereunder, for example, by a dry etching process. However, any other suitable method may be used to pattern the polymer layer 234 to form an opening.

[0035] Then, a conductive connector 238 is formed over the polymer layer 234 and in the opening of the polymer layer 234. The conductive connector 238 is electrically coupled to the semiconductor die 150 through the TSV 211. The conductive connector 238 may include a controlled collapse chip connection (C4) bump, a ball grid array (BGA) connector, a solder ball, etc. The conductive connector 238 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 238 is formed by forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into a desired bump shape.

[0036] exist Fig. 9 In the embodiment of the present invention, separation of the carrier substrate 136 is then performed to separate (or "de-attach") the carrier substrate 136 from the semiconductor die 150, the dielectric layer 130, and the molding material 132. In some embodiments, separation includes projecting light such as laser or UV light onto the release layer 134 so that the release layer 134 decomposes under the heat of the light. The carrier substrate 136 can then be mechanically removed from the integrated chip package 100.

[0037] exist Fig.10 middle, Fig. 9 The structure is flipped over and attached to a tape 148 supported by a frame 146. The tape 148 may be a dicing tape for holding the integrated chip package 100 in place during subsequent processing.

[0038] exist Fig.11 In the process, a singulation process is performed to cut along the cutting path 202 (previously Fig.10The first package area 200A and the second package area 200B are singulated along the cutting path 202 (shown in FIG. 2 ) or the scribe line area. The singulation process may include a laser slotting process during which a laser beam is used to ablate portions of the polymer layer 234, substrate 217, interconnect structure 219, and bonding layer 221 disposed along the cutting path 202 to form grooves extending through the polymer layer 234, substrate 217, interconnect structure 219, and bonding layer 221. After the laser slotting process, a sawing process is then performed along the remaining portion of the cutting path 202 to complete the first package area 200A and the second package area 200B. Each resulting singulated device stack is from one of the first package area 200A or the second package area 200B.

[0039] exist Fig.12 In the embodiment, the package substrate 240 is coupled to the Fig.11 200A or one of the first packaging areas 200A or the second packaging area 200B of the monolithic device stack shown in FIG. The packaging substrate 240 may include an interposer, a package, a core substrate, a coreless substrate, a printed circuit board (PCB), etc. In an embodiment, the packaging substrate 240 includes a substrate core 260 and a bonding pad 246 above the substrate core 260. The substrate core 260 may be made of semiconductor materials such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, etc. may also be used. In addition, the substrate core 260 may be an SOI substrate. In general, an SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an alternative embodiment, the substrate core 260 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternative core materials include bismaleimide-triazine BT resin, or other PCB materials or films.Build-up films such as ABF or other laminate materials can be used for substrate core 260.

[0040] The substrate core 260 may include active and passive devices (not shown). Various devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to provide the structural and functional requirements of the design of the device stack. The devices may be formed using any suitable method.

[0041] The substrate core 260 may also include metallization layers and vias (not shown), wherein the bonding pads 246 are physically and / or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), with vias interconnecting the conductive material layers, and may be by any suitable process (e.g., deposition, inlay, dual inlay, etc.). In some embodiments, the substrate core 260 is substantially free of active and passive devices.

[0042] In some embodiments, the conductive connectors 238 are reflowed to attach the singulated device stack from one of the first packaging region 200A or the second packaging region 200B to the bonding pads 246. The conductive connectors 238 electrically and / or physically couple the package substrate 240 to the singulated device stack, including the metallization layers in the substrate core 260. In some embodiments, a solder resist 248 is formed on the substrate core 260. The conductive connectors 238 can be disposed in openings in the solder resist 248 to electrically and mechanically couple to the bonding pads 246. The solder resist 248 can be used to protect areas of the substrate core 260 from external damage.

[0043] The conductive connectors 238 may have an epoxy flux (not shown) formed thereon before reflow thereof, wherein at least some epoxy portion of the epoxy flux remains after attaching the singulated device stack to the packaging substrate 240. This remaining epoxy portion may serve as an underfill to reduce stress and protect the joints created by the reflowed conductive connectors 238. In some embodiments, an underfill 250 may be formed between the singulated device stack and the packaging substrate 240 and around the conductive connectors 238. The underfill 250 may be formed by a capillary flow process after coupling the singulated device stack to the packaging substrate 240, or may be formed by a suitable deposition method before coupling the packaging substrate 240 to the singulated device stack.

[0044] In an embodiment, the package substrate 240 may include a bonding pad 252 above the substrate core 260. A conductive connector 254 may be coupled to the bonding pad 252 to allow the package substrate 240 to be electrically coupled to an external circuit or device. The conductive connector 254 may be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 254 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, a solder resist 248 is formed on the substrate core 260, and the conductive connector 254 may be disposed in an opening in the solder resist 248 to electrically and mechanically couple to the bonding pad 252. The solder resist 248 may be used to protect an area of ​​the substrate core 260 from external damage.

[0045] In some embodiments, a passive device (e.g., a surface mount device (SMD), not shown) may also be attached to package substrate 240 (e.g., to bonding pads 246). For example, the passive device may be bonded to the same surface of package substrate 240 as conductive connector 238.

[0046] Embodiments of the present disclosure have some advantageous features. These embodiments include a method for forming an integrated chip package. Forming an integrated chip package includes bonding two or more semiconductor grains (e.g., top grains) to a semiconductor wafer (e.g., bottom grains). A dielectric layer (e.g., oxide) is formed on the top surface and sidewalls of the semiconductor grains and on the bottom surface of the gaps between the semiconductor grains. A molding material is then formed to fill the remaining gaps. Therefore, compared with the molding material, the better bonding strength of the dielectric layer allows for improved bonding of the semiconductor grains to the semiconductor wafer. In addition, during the thermal treatment process for curing the molding material, the dielectric layer has a lower thermal expansion than the molding material. Therefore, each semiconductor grain has better bending resistance at each grain corner, and reduces the risk of semiconductor grain delamination. This further leads to a more robust integrated chip package with better electrical connection to any external device (e.g., packaging substrate), which allows enhanced device reliability.

[0047] According to one embodiment, a method for manufacturing a semiconductor device includes dicing a first wafer to separate a first die of the first wafer from a second die of the first wafer; and bonding the first die and the second die to a first side of a second wafer, wherein after bonding the first die and the second die to the first side of the second wafer, a gap is set between the first die and the second die, wherein a first dielectric layer of each of the first die and the second die is directly bonded to a second dielectric layer of the second wafer, and wherein a first portion of the gap has a first width greater than a second width of a second portion of the gap; depositing a third dielectric layer on a top surface and sidewalls of the first die and the second die and on a bottom surface within the gap; forming a molding material over the third dielectric layer to fill the gap; performing a planarization process to expose the top surfaces of the first die and the second die; coupling a package substrate to a second side of the second wafer using a conductive connector, the second side of the second wafer being a side opposite to the first side of the second wafer. In one embodiment, the third dielectric layer includes silicon oxide, silicon oxynitride, silicon carbonitride, or tetraethyl orthosilicate. In one embodiment, the thickness of the third dielectric layer is 0.1 μm to 2 μm. In one embodiment, the material of the third dielectric layer is different from the material of the first dielectric layer and the second dielectric layer. In one embodiment, performing a planarization process further includes removing a portion of the third dielectric layer and the molding material, wherein after performing the planarization process, the top surfaces of the first die and the second die are flush with the top surfaces of the third dielectric layer and the molding material. In one embodiment, the method further includes attaching a carrier substrate to the top surfaces of the first die and the second die and the planarized surfaces of the third dielectric layer and the molding material after performing the planarization process; and thinning the back side of the substrate of the second wafer to expose a through substrate via (TSV) in the second wafer. In one embodiment, segmenting the first wafer to separate the first die of the first wafer from the second die of the first wafer includes performing a plasma cutting process on a first side of the first wafer to form a first groove and a second groove, which are disposed between adjacent sidewalls of the first die and the second die; performing a blade cutting process on the second side of the first wafer to form a groove, which overlaps and communicates with the first groove and the second groove.

[0048] According to one embodiment, a method for manufacturing a semiconductor device includes bonding a plurality of dies to a wafer, wherein after bonding the plurality of dies to the wafer, a gap is provided between adjacent dies among the plurality of dies, wherein a width of a top portion of the gap is greater than a width of a bottom portion of the gap; depositing a first dielectric layer on a sidewall of an adjacent dies within the gap and on a bottom surface of the gap, wherein the first dielectric layer fills the bottom portion of the gap; forming a molding material to fill the top portion of the gap; and planarizing the molding material so that a top surface of the molding material is flush with a top surface of an adjacent dies among the plurality of dies. In one embodiment, the first dielectric layer isolates the molding material from the sidewall of the adjacent dies and the top surface of the wafer within the gap. In one embodiment, the first dielectric layer has a thickness of 0.1 μm to 2 μm. In one embodiment, the method further includes planarizing the first dielectric layer so that a top surface of the first dielectric layer is flush with a top surface of the molding material and a top surface of an adjacent dies among the plurality of dies. In one embodiment, each of the plurality of dies includes a top portion having a first width; and a bottom portion having a second width, the second width being greater than the first width. In one embodiment, after planarizing the molding material, the first dielectric layer is in physical contact with a top surface of a bottom portion of each of the plurality of dies. In one embodiment, the first dielectric layer comprises an oxide.

[0049] According to one embodiment, a package includes a first die and a second die located above and bonded to a first side of a third die, wherein the first die and the second die include a top portion; and a bottom portion, wherein each top portion has a first width and each bottom portion has a second width greater than the first width; a first dielectric layer is disposed on adjacent sidewalls of the top portion and adjacent sidewalls of the bottom portion; a molding material is located above the first dielectric layer, wherein the molding material is disposed above the bottom portions of the first die and the second die, and wherein a top surface of the molding material is flush with a top surface of the first dielectric layer. In one embodiment, the first dielectric layer has a thickness of 0.1 μm to 2 μm. In one embodiment, the first dielectric layer isolates the molding material from the first die and the second die. In one embodiment, the first dielectric layer has a lower thermal expansion coefficient than the thermal expansion coefficient of the molding material. In one embodiment, the first dielectric layer is in physical contact with the top surfaces of the bottom portions of the first die and the second die. In one embodiment, the package further includes a packaging substrate coupled to a second side of the third die using a conductive connector.

[0050] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent configurations do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: dividing the first wafer to separate a first die of the first wafer from a second die of the first wafer; bonding the first die and the second die to a first side of a second wafer, wherein a gap is provided between the first die and the second die after bonding the first die and the second die to the first side of the second wafer, wherein a first dielectric layer of each of the first die and the second die is directly bonded to a second dielectric layer of the second wafer, and wherein a first portion of the gap has a first width, the first width being greater than a second width of a second portion of the gap; Depositing a third dielectric layer on the top surface and sidewalls of the first grain and the second grain and on the bottom surface within the gap; forming a molding material over the third dielectric layer to fill the gap; performing a planarization process to expose top surfaces of the first die and the second die; as well as A package substrate is coupled to a second side of the second wafer using conductive connections, the second side of the second wafer being an opposite side from the first side of the second wafer.

2. The method according to claim 1, characterized in that The third dielectric layer includes silicon oxide, silicon oxynitride, silicon carbonitride or tetraethyl orthosilicate.

3. The method according to claim 2, characterized in that The thickness of the third dielectric layer is in the range of 0.1 μm to 2 μm.

4. The method according to claim 1, characterized in that Performing the planarization process further includes removing a portion of the third dielectric layer and a portion of the molding material, wherein after performing the planarization process, top surfaces of the first die and the second die are flush with top surfaces of the third dielectric layer and the molding material.

5. The method according to claim 1, characterized in that Slicing the first wafer to separate the first die of the first wafer from the second die of the first wafer includes: performing a plasma dicing process on a first side of the first wafer to form a first groove and a second groove disposed between adjacent sidewalls of the first die and the second die; and A blade cutting process is performed on the second side of the first wafer to form a groove, wherein the groove overlaps and connects the first groove and the second groove.

6. A method for manufacturing a semiconductor device, characterized in that: include: bonding a plurality of dies to a wafer, wherein after bonding the plurality of dies to the wafer, a gap is provided between adjacent dies among the plurality of dies, wherein a top portion of the gap has a greater width than a width of a bottom portion of the gap; depositing a first dielectric layer on the sidewalls of the adjacent grains within the gap and on the bottom surface of the gap, wherein the first dielectric layer fills a bottom portion of the gap; forming a molding material to fill a top portion of the gap; as well as The molding material is planarized so that a top surface of the molding material is flush with a top surface of the adjacent die among the plurality of dies.

7. The method according to claim 6, characterized in that The first dielectric layer isolates the molding material from the sidewalls of the adjacent die and a top surface of the wafer within the gap.

8. The method according to claim 6, characterized in that Each of the plurality of dies comprises: a top portion having a first width; and The bottom portion has a second width, wherein the second width is greater than the first width.

9. A package, characterized in that: include: A first die and a second die are located on a first side of a third die and bonded to the first side of the third die, wherein the first die and the second die include: The top portion; and bottom portions, wherein each of the top portions has a first width and each of the bottom portions has a second width greater than the first width; a first dielectric layer disposed on adjacent sidewalls of the top portion and on adjacent sidewalls of the bottom portion; and A molding material is located over the first dielectric layer, wherein the molding material is disposed over the bottom portions of the first die and the second die, and wherein a top surface of the molding material is flush with a top surface of the first dielectric layer.

10. The package according to claim 9, characterized in that The first dielectric layer has a lower thermal expansion coefficient than the molding material.

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