Semiconductor device and process for reducing cracks

Abstract

The invention relates to a semiconductor device and process for reducing cracks. An example device includes a semiconductor die (6052 of Fig. 6G) formed on a semiconductor substrate and having a device-side surface (620), a back-side surface (621) opposite the device-side surface, and a side surface (629) at an edge of the semiconductor die between the device-side surface and the back-side surface; the semiconductor die has a device region (632) including an electrical device formed on the semiconductor die, and has a dicing spacer region (630) between the device region and an edge of the semiconductor die; the semiconductor die has a polymer anchor (645) in the dicing spacer region, the polymer anchor being a recess extending through a protective overcoat dielectric layer (625) over the device-side surface of the semiconductor die and extending into the semiconductor substrate of the semiconductor die; and a polymer material (623) covering at least a portion of the semiconductor die, the polymer material filling the recess of the polymer anchor.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices produced in a wafer fabrication process and packaged in a semiconductor device package. Background Art

[0002] When semiconductor devices are manufactured using wafer fabrication processes, the semiconductor devices are coated with various materials to protect transistors, components, and routing layers formed in or above the semiconductor substrate in the device area of ​​the semiconductor die. In wafer processing, multiple replicated semiconductor dies are arranged in an array above the device side surface of the semiconductor wafer. Semiconductor dies are formed simultaneously to increase yield and reduce device cost. Wafer processing includes various processes to form transistors and other components, connect elements to form circuit systems, and metal layers formed above the semiconductor substrate to couple the circuit systems together to perform the desired functions. Wafer manufacturing processes may include various processes such as ion implantation, doping, thermal annealing, photolithography, etching, dielectric deposition, metal deposition, planarization, and passivation.

[0003] Once the semiconductor device is completed, the wafer is singulated into individual semiconductor dies. Cutting lanes extending between rows and columns of semiconductor dies are formed, the cutting lanes are parallel to each other in one direction, and perpendicular to the cutting lanes in another direction and form a grid. In the mechanical dicing method, a rotating blade of a dicing saw is used, and the rotating blade cuts through the passivation layer or protective layer above the device side surface of the semiconductor wafer, and cuts through the semiconductor wafer in the cutting lane. A dicing tape or carrier can support the wafer during and after mechanical dicing. The saw individually crosses each of the cutting lanes to cut through the semiconductor wafer. In operation, the debris and residues generated by the cutting operation may cause defects in the semiconductor die. Cracks may start in the cutting area of ​​the cutting lane and extend laterally into the device area of ​​the semiconductor die, thereby generating a discarded unit. The residues generated by the mechanical sawing operation may fall on the semiconductor die and must be removed, and if unsuccessfully removed, may also result in defective units. Additionally, mechanical dicing saws require a minimum scribe street area of ​​approximately 60-80 microns for sawing, ie, an area where other structures cannot be formed, thereby reducing the wafer area available for forming semiconductor devices.

[0004] An alternative approach uses lasers. Laser slicing tools are expensive compared to mechanical saws, and like mechanical sawing, the laser slicing process requires at least one pass of the laser over each scribe line in a raster or other pattern. The process is time consuming. The laser may cause damage to the edges of the semiconductor die and create a heat affected zone in the semiconductor substrate that may cause additional defects or thermal stresses on the semiconductor device.

[0005] An alternative laser method to laser dicing is stealth laser dicing, in which the laser is focused at a predetermined depth in the semiconductor wafer in the scribe line, but this method also forms a heat affected zone and requires a mechanical breaking step once the laser forms stress cracks in the semiconductor substrate, which may also result in cracks along the edges of the semiconductor device.

[0006] Plasma dicing offers an attractive alternative. In plasma dicing, a dry etching process, such as a deep reactive ion etch (DRIE) process, is performed in a plasma chamber. The semiconductor wafer is exposed to active ions in a plasma environment, and the bombarding ions can both remove protective materials such as passivation layers and etch into the semiconductor substrate using different process gases. By making repeated passes in the processing chamber, the semiconductor substrate can be diced. Advantages of the plasma dicing process include: the dicing streets are all cut through in parallel, thereby increasing the processing volume and reducing the cost per device. In addition, the dicing streets required are only 10 microns wide, thereby increasing the number of semiconductor dies manufactured per wafer, reducing the cost per unit and increasing the yield.

[0007] Regardless of which method is used to singulate the wafer, cracking and delamination defects continue to reduce semiconductor die yield. When forming a semiconductor device package, a polymer material such as a molding compound, an underfill, or another insulating encapsulant is typically applied to the individual semiconductor die after the device is singulated and mounted to the package substrate. The encapsulant covers at least the device side surface of the semiconductor die, where it is in contact with the polyimide (stress buffer passivation layer) and in contact with the protective overcoat (PO) material in the periphery of the semiconductor die in the dicing spacer area between the die edge and the device area formed by the dicing tool. These PO materials may include dielectric films such as silicon nitride and silicon oxynitride. The encapsulant, which may be an electronic molding compound (EMC), a thermosetting epoxy material with a filler, or an underfill such as an epoxy with a filler, does not adhere well to the protective overcoat material. Delamination and cracking may occur at the interface between the polymer material and the PO layer. Cracks that initiate in this area may propagate through the protective overcoat and into the device area in the central portion of the semiconductor die, causing the device under test to be rejected or causing a failure in the field.

[0008] It is desirable to form semiconductor devices that reduce delamination and cracking defects. Summary of the invention

[0009] A described method includes depositing a photoresist layer over a protective overcoat layer over a semiconductor wafer having semiconductor dies formed on a device-side surface, the semiconductor dies being spaced apart from each other by scribe lanes. The method proceeds to patterning the photoresist layer to form openings corresponding to polymer anchor locations in scribe spacing regions between a device region on the device-side surface of the semiconductor die and the scribe lanes. The method uses the patterned photoresist layer and etches through the protective overcoat layer in the openings to expose the device-side surface of the semiconductor wafer at the polymer anchor locations; and using the openings in the patterned photoresist layer, etches into the semiconductor wafer at the polymer anchor locations to form polymer anchors, the polymer anchors being recesses extending into the semiconductor wafer. The method proceeds to dicing the semiconductor wafer to separate the semiconductor dies, thereby forming individual semiconductor dies having the polymer anchors in the scribe spacing regions at the peripheries of the individual semiconductor dies.

[0010] In an example method described further, the method includes: depositing a photoresist layer over a protective overcoat layer over a semiconductor wafer having semiconductor dies formed on a device-side surface, the semiconductor dies being spaced apart from each other by scribe streets defined between the semiconductor dies. The method continues by patterning the photoresist layer to form openings corresponding to polymer anchor locations in scribe spacing regions between device regions on the device-side surface of the semiconductor die and the scribe streets, and forming openings in the scribe streets. The method continues by using the openings in the patterned photoresist layer, etching through the protective overcoat layer in the openings using a plasma etching process to expose the device-side surface of the semiconductor wafer at the polymer anchor locations and in the scribe streets; and using the openings in the patterned photoresist layer. The method: uses the plasma etching process to etch into the semiconductor wafer at the polymer anchor location to form a polymer anchor, wherein the polymer anchor is a recess extending into the semiconductor wafer; and simultaneously etches through the semiconductor wafer in the scribe lane, dicing the semiconductor wafer to form individual semiconductor dies, wherein the individual semiconductor dies have the polymer anchor in the scribe spacer region at the periphery of the individual semiconductor dies.

[0011] In the described examples, a device includes: a semiconductor die formed on a semiconductor substrate and having a device side surface, a backside surface opposite the device side surface, and a side surface between the device side surface and the backside surface at an edge of the semiconductor die. The semiconductor die has a device region including an electrical device formed on the semiconductor die, and a scribe spacer region between the device region and the edge of the semiconductor die. The semiconductor die has a polymer anchor in the scribe spacer region, the polymer anchor being a recess extending through a protective overcoat dielectric layer over the device side surface of the semiconductor die and extending into the semiconductor substrate of the semiconductor die. A polymer material covers at least a portion of the semiconductor die, and the polymer material fills the recess of the polymer anchor.

[0012] In another described example, a device includes: a semiconductor die having a device side surface, a backside surface opposite the device side surface, and a side extending between the device side surface and the backside surface at an edge of the semiconductor die. The semiconductor die has a device region including an electrical device formed on the semiconductor die, and a scribe spacer region between the device region and the edge of the semiconductor die. The semiconductor die has a polymer anchor in the scribe spacer region, the polymer anchor being a recess extending through a protective overcoat dielectric layer over the device side surface of the semiconductor die and extending into the semiconductor substrate of the semiconductor die. The semiconductor die is mounted to a device surface of a packaging substrate, the packaging substrate having the device surface and a board side surface opposite the device surface, and having a conductive terminal on the board side surface. A polymer material covers at least a portion of the semiconductor die and at least a portion of the packaging substrate, the polymer material fills the recess of the polymer anchor, and the terminal is exposed from the polymer material. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A-1B Semiconductor dies on a semiconductor wafer and individual semiconductor dies from a semiconductor wafer that may be used with the arrangement are illustrated in projection view and close-up projection view, respectively.

[0014] Figure 2 A top side surface of a quad flat no-lead (QFN) semiconductor device package that may be used with the arrangement is illustrated in a projection view.

[0015] Figure 3A illustrating in projection view a board side surface of an alternative quad flat no-lead package that may be used with the described arrangement; Figure 3Billustrating in cross-sectional view a flip chip ball grid array (FCBGA) package that may be used with the arrangement; and Figure 3C A flip chip chip scale package (FCCSP) that may be used with the arrangement is illustrated in another cross-sectional view as a partial view.

[0016] Figure 4A A semiconductor device package is illustrated in cross-sectional view, the semiconductor device package being a flip chip on leads (FCOL) leadless package that may be used with the arrangement. Figure 4B A semiconductor die having solder bumps extending from a device side surface is illustrated in another cross-sectional view. Figure 4C Illustration in cross-section view Figure 4B The present invention further comprises a step of mounting a semiconductor die on a package substrate. Figure 4D Another cross-sectional view showing the Figure 4C semiconductor die and package substrates. Figure 4E Another cross-sectional view shows the Figure 4D semiconductor die and package substrates, and Figure 4F Illustration in cross-section view Figure 4E A close-up view of one side of a semiconductor die in FIG. 5 , illustrating a crack propagation defect.

[0017] Figures 5A1-5A4 A process for singulating a semiconductor wafer using plasma dicing that may be used with the described arrangement is illustrated in a series of cross-sectional views. Figure 5B A process cycle for a plasma chamber to perform plasma dicing of semiconductor wafers that may be used with the described arrangement is described. Figure 5C Two replicated semiconductor dies with solder bumps and scribe lines between the semiconductor dies are illustrated in projection view. Figure 5D Another projection view shows the cutting operation along the cutting path after the cutting operation. Figure 5C Replicated semiconductor die. Figure 5E The cross-sectional view illustrates details of the scribe streets and scribe separation areas between two semiconductor dies.

[0018] Figures 6A-6F Selected process steps for forming the arrangement are illustrated in a series of cross-sectional views. Figure 6G A close-up cross-sectional view is provided to illustrate details of a semiconductor die including an example arrangement, and Figure 6H A semiconductor wafer having an alternative arrangement is illustrated in cross-sectional view.

[0019] Figures 7A-7H Selected steps for forming an alternative arrangement are illustrated in another series of cross-sectional views. Fig.7I Another close-up cross-sectional view illustrates the Figure 7H Details of the arrangement.

[0020] Figure 8 The steps for forming the arrangement are illustrated in a flow chart.

[0021] Fig. 9 The steps for forming an alternative arrangement are illustrated in another flow chart. DETAILED DESCRIPTION

[0022] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are not necessarily drawn to scale.

[0023] Elements are described herein as being “coupled.” The term “coupled” encompasses directly connected elements and indirectly connected elements, as well as elements that are electrically connected even through coupled intermediate elements or wires.

[0024] The term "semiconductor device" is used herein. A semiconductor device may be a discrete semiconductor device such as a bipolar transistor, several discrete devices such as a pair of power field effect transistor ("FET") switches fabricated together on a single semiconductor die, or a semiconductor device may be an integrated circuit having multiple semiconductor devices, such as multiple capacitors in an A / D converter. A semiconductor device may include passive devices such as resistors, inductors, filters, sensors, or active devices such as transistors. A semiconductor device may be an integrated circuit having hundreds or thousands of transistors coupled to form a functional circuit such as a microprocessor or memory device. A semiconductor device may be a radio transceiver or a radar transceiver. A semiconductor device may be a receiver, a transmitter, or a transceiver. When a semiconductor device is fabricated on a semiconductor wafer and then individually separated from the semiconductor wafer, the individual units are referred to as "semiconductor dies". A semiconductor die is also a semiconductor device.

[0025] The term "semiconductor device package" is used herein. The semiconductor device package has at least one semiconductor die electrically coupled to a terminal, and has a package body that protects and covers the semiconductor die. The semiconductor device package may include additional elements. Passive components such as capacitors, resistors, and inductors or coils may be included. In some arrangements, multiple semiconductor dies may be packaged together. The semiconductor die is mounted to a package substrate that provides conductive leads; a portion of the conductive leads forms a terminal for a packaged device. The semiconductor die may be mounted to a package substrate, wherein the device side surface faces away from the substrate and the back side surface faces and is mounted to a die pad of the package substrate. In a wire-bonded semiconductor device package, a bonding wire couples the conductive leads of the package substrate to a bonding pad on the semiconductor die. Alternatively, the semiconductor die may be mounted in a flip-chip package using a conductive column connector so that the device side faces the package substrate. After the semiconductor die is mounted to the package substrate, a polymer material may be applied to the device side surface of the semiconductor die. In an example of a semiconductor die with a flip chip installation, an underfill may be applied between the device side surface of the semiconductor die and the package substrate. In a molded package, a molding compound may be used to form a package body that fills the space between the semiconductor die and the package substrate. The semiconductor device package may have a package body formed by a thermosetting epoxy resin in a molding process or formed by using an epoxy, plastic, or a resin that is liquid at room temperature and subsequently cured. The package body may provide an airtight package for a packaged device. An encapsulation process may be used to form the package body in a mold, however, a portion of the leads of the package substrate is not covered during encapsulation, and these exposed lead portions provide terminals for microelectronic device packaging. In an alternative package type that may be used with the arrangement, a lid or cover may be attached to the package substrate and to the back side of the semiconductor die to form a package body.

[0026] The term "package substrate" is used herein. A package substrate is a substrate arranged to receive a semiconductor die and support the semiconductor die in a completed semiconductor device package. Package substrates that can be used with the arrangement include conductive lead frames, molded interconnect substrates (MIS), partially etched lead frames, pre-molded lead frames (PMLF), and multi-layer package substrates. The multi-layer package substrate may include an organic substrate having a plurality of conductors arranged in a dielectric material to form a ball grid array (BGA) or chip scale package (CSP) type, wherein the solder balls on the board side surface are arranged for surface mounting to a board or module. In some arrangements, a flip chip semiconductor die mount is used, wherein a column connector or solder bump extending from a bonding pad on a semiconductor device is attached to a conductive pad on the device side surface of the package substrate by a solder joint. The column connector may be a solder bump or other conductive material, such as copper or gold, wherein the solder is on the far end. Copper column bumps may be used. In an alternative arrangement using wire bond packaging, bond wires may couple bond pads on the semiconductor die to leads on the device side surface of the package substrate. Flip chip BGA packages (FCBGA), flip chip CSP packages (FCCSP), and flip chip on leads (FCOL) packages may be used with and will benefit from the arrangement.

[0027] When encapsulating example microelectronics and semiconductor devices, polymer materials such as molding compounds or bottom fillers may be used to partially cover the package substrate, cover components, cover semiconductor die, and cover electrical connections from semiconductor die to the package substrate. The process for applying polymer materials may be referred to as an "encapsulation" process, but some parts of the package substrate are not covered during encapsulation, such as terminals and leads are exposed to achieve electrical connection with the semiconductor device package. Encapsulation is usually a compression molding process, in which thermosetting molding compounds such as epoxy resins may be used. Room temperature solid or powder electronic molding compounds may be heated to a liquid state, and then molding may be performed by pressing the liquid molding compound into a mold through a chute or channel. Transfer molding may be used. Unit molds shaped to surround individual devices may be used, or block molding may be used to form multiple packages of several devices simultaneously from a molding compound. The device to be molded may be arranged in an array or matrix of several, hundreds, or even thousands of devices that are subsequently molded together in rows and columns.

[0028] After the molding or underfill deposition process is completed, the individual semiconductor device packages are separated from each other in a sawing operation by cutting through the package substrate in saw streets formed between the devices. Portions of the package substrate leads are exposed from the molding compound package to form terminals for the packaged semiconductor devices.

[0029] When forming certain FCBGA packages, an underfill material is used around the solder bumps or pillar connectors on the device side of the semiconductor die. The underfill material provides mechanical support for the solder bumps and provides stress relief for the solder joints between the solder from the die and the device side of the package substrate under thermal cycling. The material of the package substrate may have a CTE that is completely different from the thermal expansion coefficient of the semiconductor die, thereby generating thermal cycling stresses between the materials during testing and field use. The underfill is a polymer material that will contact the protective overcoat (PO) directly in the periphery of the semiconductor die.

[0030] When an underfill is used between the device side surface of a semiconductor die and a package substrate, such as in a flip chip CSP package, the underfill may be an epoxy that is liquid at a process temperature such as 100°C and may be dispensed along the side of the semiconductor die or at the corner of the semiconductor die. The underfill flows into and fills the space between the semiconductor die and the package substrate by capillary action and surrounds the solder bumps or column connectors. The underfill may have up to 60-70% filler by weight, and the filler may be, for example, silicon dioxide. The underfill may be cured at high temperatures to form a solid that protects the solder joints between the semiconductor die and the package substrate during thermal cycles during testing or use.

[0031] The term "scribe lane" is used herein. A scribe lane is a portion of a semiconductor wafer between semiconductor dies. The term "scribe lane" is sometimes used in the relevant literature. Once semiconductor processing is completed and the semiconductor device is completed, the semiconductor device is separated into individual semiconductor dies by cutting the semiconductor wafer along the scribe lane. The separated dies can then be removed and processed individually for further processing. This process of removing dies from a wafer is called "singularization" or sometimes "dicing". The scribe lanes are arranged on four sides of a semiconductor die, and when the dies are singulated from each other, rectangular semiconductor dies are formed.

[0032] The term "saw lanes" is used herein. Saw lanes are areas between molded electronic devices that are used to allow a saw, such as a mechanical blade, laser, or other cutting tool, to pass between the molded electronic devices to separate the devices from one another. This process is another form of singulation. When the molded electronic devices are provided in the form of strips and one device is adjacent to another device along the strip, the saw lanes are parallel and perpendicular to the length of the strip. When the molded electronic devices are provided in the form of an array of devices in rows and columns, the saw lanes include two sets of parallel saw lanes that are perpendicular to each other, and the saw will traverse the molded electronic devices in two different directions to cut the packaged electronic devices in the array form from each other.

[0033] The term "quad flat no-lead" (QFN) is used herein for a type of electronic device package. A QFN package has conductive leads that extend coextensively with the sides of a molded package body, and in a quad flat no-lead package, the leads are located on four sides. Alternative flat no-lead packages may have leads on both sides or only on one side. These may be referred to as small outline no-lead or SON packages. Leadless packaged electronic devices may be surface mounted to a board. Small outline no-lead (SON) packages may be used with the described arrangement. The microelectronic device package of the example arrangement may be mounted to a system board using solder, such as using surface mount technology ("SMT") solder mounting.

[0034] The term "scribe spacer region" is used herein. In an example arrangement, a portion of a semiconductor die has a device region that forms a component. In a peripheral region between the device region and an outer edge of the semiconductor die, a "scribe spacer region" is formed. When the semiconductor die is part of a semiconductor wafer, the scribe spacer region is between the device region and the scribe street and surrounds the device region.

[0035] The term "polymer anchor" is used herein. A polymer anchor is a recess, cavity or groove extending from a device side surface of a semiconductor die into a semiconductor substrate, and when a polymer material such as a molding compound, an underfill or other polymer material is used to cover the device side surface, the polymer anchor is filled with a polymer material. In the arrangement, the dicing spacing area includes a polymer anchor. In an example arrangement, the polymer anchor may be formed by etching before or simultaneously with slicing the semiconductor wafer in a slicing tool. In an example process, the polymer anchor is a recess or cavity formed simultaneously with a plasma slicing process performed in a plasma slicing tool. In this example, the polymer anchor is a cavity with scalloped sides, which is produced by cyclic plasma etching used in plasma slicing. In an alternative process, the polymer anchor is a recess formed in a plasma processing tool before the plasma slicing step, and may be an open groove shape, a rectangular recess or groove, a circular recess, a cavity or groove. In a further alternative process, the polymer anchor is a recess formed by an etching process, and subsequently, the semiconductor die are singulated from the semiconductor wafer using a plasma dicing process. In a further alternative arrangement, the polymer anchor is formed by an etching process, and subsequently, the semiconductor wafer may be diced by a plasma dicing tool, a mechanical saw, or a laser cutting tool.

[0036] When a semiconductor die formed with the arrangement is mounted to a packaging substrate and subsequently covered with a polymer material used as an encapsulant such as a molding compound or bottom fill, the polymer material extends into and fills the recess of the polymer anchor, thereby increasing adhesion. The polymer anchor is a recess, cavity or groove that extends through the oxide and dielectric layers on the device side surface of the semiconductor die in the scribe space area, thereby preventing any cracks formed in the dielectric from extending laterally into the device area, preventing defects due to cracking. Cracking is more likely in the scribe space area where the polymer material directly contacts the protective oxide (PO), which has poor adhesion to the polymer material. The filled polymer anchor acts as a crack stopper, improving reliability and reducing discarded devices.

[0037] Figure 1A and 1B Two projection views are used to illustrate a semiconductor wafer having a semiconductor die device formed thereon and an individual semiconductor die. Figure 1A , semiconductor wafer 101 is shown as having an array of semiconductor die 105 formed on a surface in rows and columns. Semiconductor die 105 may be formed using processes in a semiconductor fabrication facility, including ion implantation, doping, annealing, oxidation, dielectric and metal deposition, photolithography, patterning, etching, chemical mechanical polishing (CMP), electroplating, and other processes for fabricating semiconductor devices. Scribe streets 103 and 104, which are perpendicular to each other and extend in parallel groups across wafer 101, separate rows and columns of finished semiconductor die 105 and provide areas for dicing wafer 101 to separate semiconductor die 105 from each other.

[0038] Figure 1B A single semiconductor die 105 is illustrated as being taken from a semiconductor wafer 101. The semiconductor die 105 includes a bonding pad 108, which is a conductive pad electrically coupled to a device (not shown) formed in the semiconductor die 105. The scribe streets 103, 104 (see FIG. 1 ) are then cut into the semiconductor die 105. Figure 1A ), separating the semiconductor die 105 by dicing, or singulating the semiconductor die.

[0039] Figure 2 A semiconductor device package 100 that may be used with the arrangement is illustrated in a projection view from a top side surface. Figure 2 , the semiconductor device package 100 illustrated is a quad flat leadless semiconductor device package having a terminal 110. The terminal 110 may be formed as part of a lead of a lead frame (not visible) as a package substrate. In an example, a pre-molded lead frame (PMLF) is used, or a molded interconnect substrate (MIS) is used. The terminal portion of the lead is exposed on the board side surface, and sometimes as Figure 2As shown in the figure, the lead is exposed on the side portion of the semiconductor device package, and the remaining part of the lead is partially surrounded by a dielectric such as a resin, epoxy or electronic molding compound. Thermoplastic materials can be used. A thermosetting film such as ajinomoto stacked film, which can be obtained from Ajinomoto Co. Ltd. in Tokyo, Japan, can be used as a dielectric. In an example, the lead can be copper or a copper alloy. Portions of the terminals can be plated with palladium, nickel, gold, platinum, silver, alloys or a combination of these to enhance solderability and reduce discoloration and corrosion. The exposed terminals can be tinned for soldering. The semiconductor device package 100 is arranged to be mounted on a system board or a printed circuit board (PCB) by surface mounting technology (SMT), wherein solder is applied to the device to form an electrical connection between the terminal 110 and the conductor trace or conductive pad on the system board, and the electrical connection also mechanically attaches the semiconductor device package 100 to the system board.

[0040] Figure 3A An alternative semiconductor device package 300 that may be used with the described arrangement is illustrated in a projection view taken from a side surface of the board. Figure 3A , semiconductor device package 300 is a "flip chip on leads" or "FCOL" type leadless package. Figure 3A A device known as HotRod is available from Texas Instruments Incorporated of Dallas, Texas. TM The semiconductor device package of the package. Terminal 310 carries a signal, and rail 312 can be a ground or voltage supply terminal. When a high voltage semiconductor device such as a power field effect transistor (power FET) is mounted in the semiconductor device package 300, multiple bonding pads of the semiconductor die can be mounted in parallel to rail 312, thereby providing a low resistance path to ground or another potential, and carrying heat energy outside the semiconductor device within the molding compound 323 of the semiconductor device package 300. The terminal 310 and rail 312 are exposed from the molding compound for surface mounting to a board or module. For example, the FCOL package of the semiconductor device package 300 can be made smaller than a conventional QFN package because there is no die pad or paddle to carry the semiconductor die, as in the case of a face-up wire bond package, thereby saving board area and reducing the package size.

[0041] Figure 3B An FC-BGA package 309 that may be used with the described arrangement is illustrated in cross-sectional view. Figure 3BIn the example, FC-BGA package 309 has a semiconductor die 305 that is flip-chip mounted to a package substrate 312. In this example, package substrate 312 is a multi-layer package substrate that is arranged to provide ball grid array solder balls 316 on a board side surface for surface mounting FC-BGA package 309 to a board. Semiconductor die 305 has solder balls or bumps 316 that form mechanical and electrical connections between semiconductor die 305 and package substrate 312. Cover or lid 313 protects semiconductor die 305 and package substrate 312. Thermal interface material 311 that can be thermally conductive is used to attach the cover to the backside surface (on the back side). Figure 3B 312). The cover or cover 313 (which may be a heat sink to transfer heat from the FC-BGA package 309) is attached to the package substrate 312. The package substrate 312 may mount external passives such as capacitors 314 on the board side surface and internal passives such as capacitors 317 on the device surface. An underfill material 319 is shown that is formed between the device side surfaces of the semiconductor die 305 and protects the solder bumps 316 from mechanical stress. After the semiconductor die is placed on the package substrate 312, the underfill material 319 may be dispensed under the semiconductor die 305. The underfill material 319 may be an epoxy, epoxy resin, or silicone. In the example process, epoxy resin with silica filler is used. The epoxy may be dispensed as a liquid at a process temperature of about 100° C. and may be dispensed between the semiconductor die 305 and the package substrate 312 along the edge of the semiconductor die 305. Under capillary action, the underfill epoxy will flow under and fill the space between the semiconductor die 305 and the package substrate 312, and will surround the solder bumps 316. The underfill epoxy may be cured at high temperature to harden into a solid. In the area of ​​the semiconductor die 316 near the periphery of the semiconductor die, the underfill epoxy, a polymer material, will directly contact the protective outer coating on the semiconductor die 305.

[0042] Figure 3C In an alternative example, a flip chip chip scale package (FCCSP) 390 is illustrated in another cross-sectional view as a partial view. Figure 3C, a semiconductor device package 390 has a semiconductor die 305 mounted to a package substrate 312 that carries solder balls 315 on a board side surface. The semiconductor die 305 is flip chip mounted to the device side of the package substrate 312 using solder bumps or pillar connectors 316. A molding compound 323 is formed to cover the device side of the package substrate 312 and to cover the semiconductor die 305. At the periphery of the semiconductor die 305, the molding compound 323 will directly contact the protective overcoat on the device side surface of the semiconductor die 305.

[0043] Figure 4A A cross-sectional view similar to Figure 3A A leadless semiconductor device package 400 is shown in FIG. 400 of the semiconductor device package 300 in FIG. This leadless semiconductor package 400 is used as an illustrative example, however, in other arrangements, an FCCSP package or an FCBGA package is used. In the arrangement, a polymer material such as an underfill or a molding compound directly contacts the protective outer coating of the semiconductor die in the scribe space area at the periphery of the semiconductor die. Similar to Figure 1B 1. The semiconductor die 405 is shown as flip chip mounted to a package substrate 412. Although an example FCOL type package substrate is shown, in additional arrangements, the package substrate may be an organic multilayer package substrate, such as a FCCSP package substrate or a FCBGA package substrate.

[0044] exist Figure 4A 4, solder bumps 416 extend from bonding pads 408 on semiconductor die 405 and are shown in a flip chip on leads (FCOL) configuration. Solder bumps 416 electrically connect bonding pads 408 of semiconductor die 405 to terminals 410 of package substrate 412.

[0045] Figure 4B Another cross-sectional view is shown in more detail Figure 4A The semiconductor die 405 and solder bumps 416 are provided. Figure 4B , a semiconductor die 405 is shown before being mounted in a semiconductor device package. The semiconductor die 405 is shown arranged with the device side surface 420 facing upward (eg, Figure 4B oriented in ( ) and with backside surface 421 facing downward. Solder bump 416 is shown extending from bonding pad 408. Protective overcoat (PO) 425 is shown over device side surface 420 of semiconductor die 405. Polyimide layer (PI) 427 is shown over a portion of semiconductor die 405 and covering a portion of PO layer 425. Semiconductor die 405 has a side 429 that is formed along a scribe street (see Figure 1A 103, 104) cut the semiconductor wafer (see Figure 1AThe semiconductor die 405 is formed when the semiconductor die 405 is cut into a wafer 101 of the semiconductor die 405, and the side 429 is the boundary of the semiconductor die 405 formed along the cut street. The polyimide layer 427 does not extend all the way to the side 429. This is done to enable the dicing operation to cut through the semiconductor wafer in the cut street without having to cut through the polyimide layer. A protective overcoat (PO) 425 extends over the surface of the semiconductor die, and the protective overcoat may be an inorganic dielectric, such as silicon nitride (SiN), silicon oxynitride (SiON), or another dielectric. The area between the device area in the central portion of the semiconductor die 405 and the periphery of the semiconductor die 405 is referred to herein as a "cutting spacer area" 430, which extends between the device area and the side 429. The cut spacer area is covered by the PO layer 425 or mostly covered by the PO layer. In some examples, scribe seals may be formed at the periphery of the semiconductor die 405, which are vertical structures formed by metal layers and vias between metal layers, and are located near the side 429 in the scribe spacing region 430. The scribe seals may prevent cracks formed during the dicing operation from propagating from the side 429 of the semiconductor die into the layers below the protective overcoat layer 425, and the scribe seals are described in more detail below.

[0046] Solder bumps 416 may be formed in a wafer bumping process while the semiconductor die is still part of the semiconductor wafer (see Figure 1A , for example, a wafer 101 with semiconductor die 105). Solder can be applied to the bond pads by a template, by solder ball dropping, by inkjet or drop-on-demand technology, and then heated to reflow into the shape of solder bumps. Alternative processes include using a reconstituted wafer after wafer dicing so that a pick-and-place tool places the individual die on a support film or tape, and then the bumping operation can be performed on the reconstituted wafer, allowing for larger spacing between devices during the bumping process.

[0047] Figure 4C The die mounting process for semiconductor die 405 is illustrated in another cross-sectional view. Semiconductor die 405 is arranged with device side surface 420 facing the device side of package substrate 412. Solder bumps 416 extending from bonding pads 408 are positioned to contact terminals 410 on the device side of package substrate 412. PO layer 425 and PI layer 427 are shown.

[0048] Figure 4D Description After additional processing steps Figure 4C Components. Figure 4D , semiconductor die 405 is shown mounted to package substrate 412. In a thermal reflow process, solder bumps 416 form solder joints with terminals 410 of package substrate 412. Protective overcoat 425 and polyimide layer 427 are shown spaced apart from the device surface of package substrate 412.

[0049] Figure 4E Describes the process of encapsulation or molding after depositing polymer material over the semiconductor die. Figure 4D Components. Figure 4E In the example shown in , the semiconductor die 405 is shown with a molding compound 423 over the backside surface 421 and over the side 429 of the semiconductor die 405. The molding compound 423 covers the portion of the device surface of the package substrate 412 including the terminals 410 and the space between the terminals 410. The molding compound 423 contacts the protective overcoat 425 in the scribed spacer area 430 between the side 429 and the device area covered by the polyimide 427. In an alternative arrangement, see, for example, Figure 3B In the semiconductor device package 309 in FIG. 4 , when an underfill material is used, at least the device side surface 420 of the semiconductor die 405 will be covered by the underfill. In the example, the underfill will directly contact the PO layer 425 .

[0050] In an example molding process, when a molding compound is used as a polymer material for encapsulation, a semiconductor die is mounted to a device surface of a package substrate (e.g., 412) arranged in strips or arrays or matrices. Tens, hundreds, or more semiconductor die devices can be molded simultaneously to increase throughput, and then the molded package is divided into individual semiconductor device packages. The package substrate carrying the semiconductor die can be loaded into a mold groove of a transfer molding tool. A thermosetting epoxy molding compound, such as an electronic molding compound (EMC), can be used in the transfer molding operation. EMC can be provided as a solid disc or as a powder that is solid at room temperature. EMC can be heated to a liquid state. A mechanical punch can be used to force the liquid molding compound to enter the mold groove through a chute under pressure. The molding compound flows into and fills the mold groove surrounding the semiconductor device and the portion of the package substrate. The molding compound is cured to a solid state and forms the body of the semiconductor device package 400. For example, a portion of the lead in the package substrate is exposed from the molding compound to form a terminal 410.

[0051] For example, the protective overcoat 425 may be a dielectric such as silicon oxide, silicon oxynitride, or silicon carbide. The polyimide layer 427 acts as a stress buffer between the molding compound 423 and the protective overcoat 425 in the device region of the semiconductor die 405, however, in the dicing spacer region 430 between the side 429 of the semiconductor die 405 (the side 429 is formed from the wafer in the dicing operation) and the device region, the molding compound 423 directly contacts the PO layer 425. The molding compound 423 does not easily adhere to the PO layer 425. Weak adhesion at the interface between different materials may lead to crack formation during thermal cycle (TC) testing or in the field. Figure 4E Marked as " Figure 4F The area is in Figure 4FA close-up view is shown to illustrate an example of where cracking may occur.

[0052] Figure 4F yes Figure 4E 4 is a close-up of one side 429 of the semiconductor die 405 in FIG. 4 and showing additional details. For example, the molding compound 423 may have a filler 451, which is a particulate material added to the molding compound to enhance heat transfer. The polyimide layer 427 is shown as being above the device side surface 420 of the semiconductor die 405, in the device area 432 where the electronic device (not shown for simplicity of illustration) will be formed in the semiconductor die 405. The protective overcoat layer 425 is shown as being partially covered by the polyimide layer 427, but not covered in the scribe spacer area 430. In the scribe spacer area 430 located between the side 429 of the semiconductor die 405 and the device area 432 at the periphery of the semiconductor die 405, the molding compound 423 directly contacts the protective overcoat layer 425. The back-end process metal layer 424 includes a metal layer and an oxide, the metal may be, for example, copper, and a conductor may be formed in a damascene process using a chemical mechanical process (CMP) to planarize the metal layer. For example, the front-end process layer 422 may include local interconnect metal and doped polysilicon to form source and drain contacts and to form a gate conductor of a metal oxide semiconductor field effect transistor (MOSFET). The front-end process layer 422 also includes dielectric materials between metal layers, and conductive vias can couple conductors in the metal layers through the dielectric. The semiconductor die 405 is shown with a molding compound 423 covering the side surface 429 and a backside surface 421 facing away from the device side surface 420.

[0053] exist Figure 4F 4, the scribe seal 453 is shown in block form. The scribe seal 453 may be formed using the back-end process layer 424, wherein the vias extend through the dielectric between the metal layers to form a vertical metal barrier layer. The scribe seal may include local interconnects in the front-end layer 422 to extend to the device side surface 420 of the semiconductor die 405. For example, the scribe seal 453 may protect the semiconductor die 405 from cracks and residues that may invade from the side 429 during the wafer dicing operation. In the scribe spacing area 430 near the side 429, one or more scribe seals may be formed at the edge of the semiconductor die. When viewed from a top view of the device side surface 420 of the semiconductor die 405, the scribe seal 453 may extend along each edge to form a four-side seal.

[0054] exist Figure 4F, the occurrence of crack propagation in the PO layer is illustrated. Crack 460 initiates at the interface between the molding compound 423 and the protective overcoat 425 and propagates laterally toward the device area 432 at the right side of the figure. This type of crack may occur because the interface between the molding compound 423 (or another polymer material, such as an underfill) and the protective overcoat 425 is not strong, that is, the molding compound 423 does not easily adhere to the protective overcoat 425. Various materials have different coefficient of thermal expansion (CTE) values, so that during thermal cycling, such as during testing or in operation, the materials can expand at different rates, and crack 460 may initiate without a stress buffer layer between the materials, such as in FIG. Figure 4F Once a crack occurs, it may propagate laterally and vertically through the layers, leading to failure.

[0055] In the arrangement, the polymer anchor is formed in the device side surface of the semiconductor die in the scribe space region, wherein the protective overcoat (see Figure 4F 425) contact molding compound (see Figure 4F 423 in ) or another polymer material, such as an underfill material. In one example method arrangement, a plasma dicing tool is used to simultaneously form the polymer anchors and singulate the wafer into individual semiconductor dies. In an alternative arrangement, a plasma dicing tool may be used in a first etching operation to form the polymer anchors, and then the plasma dicing tool may be used to diced the wafer. In a further alternative method, a silicon wet etch process may be used to form the polymer anchors, and then the semiconductor wafer may be diced; using a plasma dicing tool, or in yet another alternative method, using a saw or laser dicing tool.

[0056] In the arrangement, the polymer anchor extends through the dielectric layer above the side surface of the semiconductor die device and into the semiconductor substrate. When the encapsulation operation covers at least a portion of the semiconductor device with a polymer material (e.g., underfill or electronic molding compound), the polymer material fills the polymer anchor and creates a strong physical attachment. If a crack later starts in the scribe spacing area, the polymer anchor provides a crack stop feature and the propagation of the crack will be interrupted by the polymer anchor extending vertically through the dielectric layer. The crack will not propagate into the device area, thereby preventing device failure, improving reliability and reducing the number of failed devices.

[0057] Figures 5A1-5A4 Selected steps of a plasma slicing process that can be used to form an arrangement are illustrated in a series of cross-sectional views. Fig.5A15. In step 571, a portion of semiconductor wafer 501 is shown with replicated semiconductor dies 5051 and 5052 on both sides of scribe street 503. Bump metal 516 is shown in block form on device side surfaces 520 of semiconductor dies 5051, 5052.

[0058] exist Figure 5A2 At step 573 in FIG. 5 , the wafer 501 is shown mounted device-side down on a backgrinding tape or support 560 for a backgrinding operation. The bump metal 516 is temporarily adhered to the backgrinding tape 560. The backside surface 521 is exposed for processing. In step 573, the backgrinding operation thins the semiconductor wafer 501.

[0059] exist Figure 5A3 At step 575 in FIG. 5 , wafer 501 is shown mounted backside down to wafer support frame 562 with replicated die 5051, 5052 having bump metal 516 facing upward. In step 573, wafer 501 has been thinned by grinding backside surface 521 using a mechanical grinding or chemical mechanical polishing tool, then mounted to wafer support 562, and back grinding tape 560 has been removed.

[0060] At step 575, a photoresist (PR) layer ( Figure 5A3 The photoresist layer is patterned to open scribe streets 503 for etching. The semiconductor wafer is then transferred to a plasma etching tool.

[0061] exist Figure 5A4 At step 577 in FIG. 5 , the semiconductor wafer 501 is shown in a plasma chamber 581. The plasma tool may perform various operations depending on the chemistry used and the electric field applied. In an example process, the semiconductor wafer is transferred to the plasma chamber. The plasma chamber is evacuated to form a vacuum. Process gases are introduced at low pressure. Example process gases include argon (Ar), oxygen (O2), and fluorine (e.g., C4F8, SF6); this depends on the process performed. Plasma is generated by applying a high-frequency signal, such as a standard 13.56 MHz signal, to the gas. By applying an electric field between the upper plate and the semiconductor wafer, ions from the gas can be accelerated onto the semiconductor wafer in the chamber. When the ions bombard the semiconductor wafer, the semiconductor substrate can be etched. In alternative process steps, by changing the chemistry of the gas used, oxide or nitride etching can be performed, or deposition can be performed.

[0062] At step 577, in an example, a silicon etch is performed to singulate semiconductor die 5051, 5052 by opening semiconductor wafer 501 in scribe streets 503. Additionally, the plasma tool may also perform a photoresist stripping step after etching is complete, an example stripping process using O2 gas in an "ashing" operation.

[0063] Plasma dicing of semiconductor wafers forms deep vertical cuts into and through the semiconductor material. To perform this highly anisotropic etch, a cycle of steps is used.

[0064] Figure 5B An example plasma slicing process is illustrated in a series of cross-sectional views, which details Figure 5A4 577. PR layer 540 is shown on the surface of semiconductor wafer 501, where the openings define scribe streets 503. At step 5771, polymer deposition is performed. This step coats the sidewalls of the previously etched portions of semiconductor wafer 501 in scribe streets 503 with polymer coating 541. Polymer coating 541 can be deposited in a plasma tool using, for example, a fluorocarbon polymer.

[0065] At step 5772, the plasma dicing cycle continues to perform etching to remove the polymer coating from the bottom of the scribe street trench 543 in preparation for semiconductor etching. The polymer coating remains on the sidewalls of the scribe street 503, thereby maintaining the scribe street etch vertical profile as the scribe street advances, making the etch more or less anisotropic.

[0066] At step 5773, a semiconductor (e.g., silicon) etching process is performed to produce a new groove 545 extending below the previous groove 543, and this etching cycle is performed multiple times. Line 547 shows the cycle, and the process returns to step 5771 and continues until the semiconductor wafer is etched through in the scribe road 503. In the example, more than 150 cycles are performed to cut through the semiconductor wafer. The number of cycles required depends on the semiconductor material, the thickness of the wafer, and the chemical used. The amount of time for each cycle can also be adjusted. Because different etching types require different chemicals and run at different rates, a multi-station plasma tool can be used, which has several plasma chambers around a central robot wafer processor, and the central robot wafer processor transfers materials into and out of the plasma chamber as the method proceeds forward. Because plasma etching is cyclic, and the periodic process coats the sidewalls with a polymer at each cycle, the vertical side of the semiconductor die will have a "fan-shaped" shape, which indicates that a plasma semiconductor dicing tool is used.

[0067] Once the semiconductor singulation process is complete, the method transitions to step 5774. The individual semiconductor die are now separated along the scribe lines (see, e.g., in conjunction with semiconductor die 105). Figure 1A The scribe lines 103, 104 in the wafer are separated from each other. The advantages of the plasma dicing process compared to mechanical sawing and laser cutting dicing tools include that the width of the dicing lines can be smaller, thereby increasing the available semiconductor wafer area and increasing the number of dies per wafer, reducing costs. The problem of debris and particle residues that occurs during mechanical sawing is reduced or eliminated. The heat-affected zone generated by laser cutting tools or invisible laser dicing tools is eliminated, thereby reducing the stress on the semiconductor device. The polymer coating formed during the plasma dicing process can remain on the side of the device. A big advantage is that, unlike a multi-pass sawing operation, the plasma dicing process cuts all dicing lines on the wafer simultaneously, thereby increasing the throughput and reducing the device cost. As already mentioned, the semiconductor wafer area required for the dicing lines is reduced, thereby increasing the yield.

[0068] As an example, Figure 5C Illustrated are two semiconductor dies 5051 and 5052 on both sides of a scribe street 503 prior to dicing semiconductor wafer 501 in a plasma dicing process. Solder bumps 516 are shown on the device-side surface of semiconductor wafer 501.

[0069] Figure 5D Another projection view illustrates the plasma dicing process after the dicing street 503 is opened to singulate the device from the semiconductor wafer 501. Figure 5C The two semiconductor dies 5051, 5052. The singulated dies can then be mounted on a packaging substrate and packaged, for example, see Figures 4A-4E .

[0070] Figure 5E A close-up cross-sectional view is used to illustrate e.g. Figure 5C 5051, 5052 are duplicate units that are joined in the scribe lanes 503 extending between the devices through the semiconductor wafer prior to dicing. The dicing lanes 503 are designed to be free of metal structures so that the dicing operation can be performed without cutting through any metal. The dicing lanes 503 are covered with a protective overcoat 525, which may be an inorganic dielectric layer, such as SiN, SiON, SiC, or a similar material. However, even though portions of the device side surfaces of the semiconductor dies 5051, 5052 may have a polyimide layer above the dielectric, the dicing lanes 503 do not have a polyimide layer, which also enhances the dicing process.

[0071] exist Figure 5E, the scribe seal 553 is shown extending through the front-end process layer 524 and the back-end process layer 522 to the device side surface 520 of the semiconductor dies 5051, 5052. The scribe seal 553 is at the edge of the scribe spacing region 530 adjacent to the scribe street 503. The scribe seal 553 can be formed by a back-end process metal layer, wherein vias extend between the metal layers to form a vertical stack through the back-end process layer 524, and contacts extend through the front-end process layer 522 to the device side surface 520. The scribe seal 553 helps prevent cracks from the sides formed when the wafer 501 is cut from propagating into the semiconductor dies 5051, 5052. However, the scribe seal is located below the protective overcoat layer 525 and cannot prevent cracks from propagating from the polymer material interface to the protective overcoat layer 525 (see Figure 4F ). The scribe streets 503 have a minimum width of about 8 microns, and in the example process, a width of 10 microns was used. Figure 5E This width, labeled "SLw" in FIG. 1 , is much smaller than the minimum scribe street width of 60-80 microns for saw dicing operations and a similar width for laser cutting dicing operations. Reducing the scribe street width SLw increases the wafer area available for devices, thereby reducing unit cost and increasing yield.

[0072] In the arrangement, a polymer anchor is formed in the scribe spacer region between the edge of the semiconductor die and the device region. The polymer anchor is formed in the scribe spacer region where a polymer material (e.g., EMC or underfill material) directly contacts a protective overcoat dielectric layer in a semiconductor device package. The polymer anchor is a recess that extends through the protective overcoat and through an additional dielectric layer above the device side surface of the semiconductor die and into the semiconductor substrate. When the encapsulation process covers the semiconductor die with a polymer material to form a semiconductor device package, the polymer fills the polymer anchor, thereby creating a strong attachment between the polymer material and the semiconductor die. The vertically filled polymer anchor prevents cracks from propagating from the scribe spacer region to the device region of the semiconductor die.

[0073] Figures 6A-6F Selected steps for forming a semiconductor device including a polymer anchor in an example arrangement are illustrated in a series of cross-sectional views. Fig. 6A In FIG. 6 , an example semiconductor wafer 601 is shown with a scribe line 603, and portions of replicated semiconductor die 6051, 6052 are shown on both sides of the scribe line 603. The scribe line 603 has a width "SLw" that can be about 8 microns or more, and in the example, 10 microns are used. For example, a similar Figure 5EA protective outer coating 625 of the PO layer 525 in the scribe line may be present in the scribe spacing region 630, but is not shown for simplicity of illustration. (See, e.g., Figure 5E The cut seal 553 in the embodiment. )

[0074] Semiconductor wafer 601 can be any material used in semiconductor processing, and most semiconductor wafers manufactured today are silicon. Germanium, gallium arsenide, silicon carbide, indium phosphide, and other semiconductor materials can be used for wafer 601.

[0075] A protective overcoat 625 is formed on the device side surface 620 of the semiconductor wafer 601, however, to simplify the illustration, additional layers are not shown, such as front-end process layers including local interconnect conductors and contacts to the semiconductor substrate, and back-end process layers, such as multi-level metal conductors, separated from each other by dielectrics and connected by conductive vias. (See, e.g., Figure 5E ) A protective overcoat 625 is located over any of these metal layers.

[0076] Figure 6B Another cross-sectional view is shown after performing photoresist layer deposition. Fig. 6A Element. Photoresist layer 640 is above protective overcoat layer 625 and will protect areas that are not etched. For example, photoresist (PR) layer 640 can be a liquid or gel that is deposited and spun on and then baked to harden the PR layer. Example scribe lanes 603 have a width SLw of about 10 microns or less, but wider scribe lanes can be used. As described above, narrow scribe lanes that can be used with plasma dicing tools increase the area of ​​semiconductor wafers on which devices can be formed.

[0077] Figure 6C Another cross-sectional view is shown after the photoresist layer 640 is patterned. Figure 6B An opening 642 is formed in the scribe space region 630 extending from the boundary of the scribe street 603. A scribe street opening 644 is formed in the PR layer 640 corresponding to the position of the scribe street 603. The PR may be patterned using photolithography, applying a mask, exposing the PR through the mask, and developing the PR to form a pattern having openings in the region to be etched.

[0078] Fig.6D Another cross-sectional view shows the Figure 6C Components. Fig.6D, the protective overcoat 625 after dielectric etching is shown. In the example process, the oxide etching is performed using a plasma etching tool. In the example plasma etching process, process gases of Ar, C4F8, and O2 are used in a plasma tool to etch the protective overcoat from the semiconductor device in the opening in the PR layer 640. Any dielectric material below the PO layer 625 is also etched to expose the semiconductor wafer 601 in the opening.

[0079] Fig. 6E Another cross-sectional view illustrates the semiconductor device after an additional process step (i.e., semiconductor etching). Fig.6D The semiconductor wafer 601 is silicon in this example and can be etched using a plasma tool and process gases of C4F8 and SF6. Figure 5B As shown in , at steps 5771, 5772, and 5773, in an example plasma silicon etch, a polymer deposition step is performed, a punch-through etch is performed to open the bottom of the previous recess, and a silicon etch is performed, the cycle is repeated to coat the sidewalls with polymer between silicon etch cycles until the semiconductor wafer 601 is etched through in the scribe street 603. In the arrangement, a polymer anchor 645 is formed in the surface of the semiconductor wafer 601 in the scribe spacer region 630. The polymer anchor 645 is placed to be spaced apart from any scribe seal so as not to etch metal through the scribe seal. The polymer anchor 645 is a recess, cavity, or trench extending through the protective overcoat 640 and any underlying dielectric layer and into the device side surface 620 of the semiconductor wafer 601. In an example, the polymer anchor can be a cavity having a circular shape when viewed from a top view. The polymer anchor 645 has a depth marked as "Ad", which is determined by the width of the opening 642, and as the opening becomes wider, the depth increases, and vice versa. By controlling this depth Ad, the polymer anchor 645 can be positioned and sized as needed. In an example process, the anchor depth Ad is about 50 microns, where the anchor diameter is between 10 microns and 50 microns. The anchor depth Ad can vary in the range of about 20 microns to about 200 microns, depending on the thickness of the semiconductor die and the PR pattern opening used and the plasma etching process used. The plasma dicing tool forms a fan on the sidewalls of the polymer anchor and the side of the die, and in an example plasma etching process, the height and width of the fan can be between 3-6 microns. The dicing lane width SLw can be a width greater than about 8 microns, and in an example process, a width SLw of about 10 microns is used, which is much smaller than the minimum width required for other dicing processes such as saws or laser cutting tools. When the polymer anchor 645 is formed in a plasma etching cycle, the side surface will have a scalloped sidewall formed by repeated plasma etching processes, such as Fig. 6E as shown in .

[0080] The polymer anchors 645 may be placed anywhere in the scribe spacer regions 630. In one approach, experimental data from failed parts or mechanical simulation results are used to determine the areas on the device side surface of the semiconductor die where cracks in the PO layer are most likely to occur. Typically, the areas with the greatest distance to neutral point ("DNP"), which are typically near the semiconductor die corners, are most likely to benefit from the use of polymer anchors. Thus, in one approach, polymer anchors are placed in the scribe spacer regions at the periphery of the semiconductor die around the die corners. In another example approach, polymer anchors may be placed around the entire periphery of the die between the scribe seal at the die edge and the device region.

[0081] Fig. 6F The PR stripping step is performed to remove the PR layer 640 from the protective overcoat layer 625. Fig. 6E The polymer anchor 645 is shown as being open at the top surface of the protective overcoat 625 and is a recess or cavity extending into the semiconductor substrate 601. In this example arrangement, a plasma silicon dicing process performed in a plasma etching tool is used to simultaneously form the polymer anchor 645, and a single PR mask process is used to etch through the semiconductor wafer 601 in the dicing street 603. This approach advantageously forms the polymer anchor 645 in conjunction with the dicing process, thereby saving time and additional process steps. However, as further described below, in an alternative approach, the polymer anchor 645 may be formed prior to the semiconductor wafer dicing step. When using Figure 5B When the polymer anchor 645 is formed in the semiconductor wafer dicing step by the cyclic method, the side of the polymer anchor 645 will be as follows Fig. 6E The fan shape shown in .

[0082] exist Fig. 6F , two semiconductor dies 6051, 6052 are now singulated from the semiconductor wafer 601. Each semiconductor die 6051, 6052 includes a polymer anchor 645 in the scribe spacing region 630. The scribe spacing region 630 may also include a scribe seal (see, e.g., Figure 5E scribe seal 553 in the embodiment, and in those example arrangements, the polymer anchor 645 will be spaced apart from the scribe seal to avoid etching through the scribe seal metal.

[0083] Figure 6G Description of the die-to-package process (see, for example, Figures 4A-4F ) after being covered by a polymer material such as molding compound 623 Fig. 6F In an alternative packaging type, the device side surface 620 may be covered by an underfill material (e.g., see Figure 3BFIG. 6 is an FCBGA package 309 with an underfill material 319 in FIG. 6 . The semiconductor die 6052 has a die edge 629 formed by a plasma silicon etch process, and the polymer anchor 645 is shown in the scribe spacer region 630 . Figure 6G 6052 is shown in a partial view, with the semiconductor die 6052 having a device side surface 620, a board side surface 621, and four sides extending between the board side and the device side, namely, a first side, a second side, a third side, and a fourth side. Side 629 is one of the four sides. The polymer anchor 645 will be filled with a polymer material (here, the molding compound 623) to increase the attachment strength between the molding compound 623 and the PO layer 625, and the filled polymer anchor 645 will also act as a crack propagation stopper, so that if a crack starts in a polymer material such as the molding compound 623 or at the interface between the molding compound 623 and the PO layer 625, the crack will not propagate from the dicing spacer region 630 into the device region 632 of the semiconductor die 6052.

[0084] Figure 6H Another cross-sectional view illustrates an alternative polymer anchor pattern that can be formed in a plasma dicing tool while dicing a semiconductor wafer. Figure 6H , the scribe line 603 is shown disposed between two semiconductor dies 6051, 6052, wherein the scribe spacing region 630 begins at the boundary of the scribe line 603 at the edge of each semiconductor die. The polymer anchor 646 is patterned as an open groove extending through the protective overcoat 625 and into the device side surface 620 of the semiconductor wafer 601. In this arrangement, the polymer anchor 646 has a horizontal length parallel to the device side surface of the semiconductor die 6051, which is greater than the depth of the anchor into the surface of the semiconductor die. When the semiconductor dies 6051, 6052 are covered with a polymer material such as a molding compound or an underfill in a subsequent packaging process, the polymer material will contact the semiconductor wafer 601 in the polymer anchor 646, thereby reducing contact with the protective overcoat 625. Because the polymer material has better adhesion to the semiconductor wafer than to the protective overcoat 625, the possibility of cracks forming in the protective overcoat 625 and extending into the device area of ​​the semiconductor device is reduced or eliminated. In using Figure 6H In mechanical simulations of the arrangement of the invention, when cracks were observed to occur in the example using the molding compound, the cracks remained in the molding compound and did not extend into other materials. These simulations show that by using the arrangement, cracks did not reach the device area of ​​the semiconductor device, but remained in the molding compound.

[0085] Figures 7A-7GSelected steps for forming alternative arrangements of polymer anchors having various shapes using plasma slicing, plasma etching, or alternatively using wet or chemical etching processes are illustrated in a series of cross-sectional views.

[0086] Fig. 7A A portion of a semiconductor wafer 701 is illustrated in cross-sectional view with replicated semiconductor die 7051, 7052 on both sides of a scribe street 703. Fig. 7A In the embodiment, semiconductor wafer 701 has a device side surface 720 covered by a protective outer coating 725, which may be an inorganic dielectric such as silicon nitride, silicon oxide, or silicon carbide. In device region 732, protective outer coating 725 may be covered by polyimide layer 727, while in scribe space region 730 between device region 732 and scribe street 703, protective outer coating 725 is not covered by polyimide layer 727. As described above, when semiconductor die 7051, 7052 are packaged in a semiconductor device package (see Figures 4A-4F ), polymer materials such as molding compounds or underfill materials will directly contact the protective overcoat 725, and adhesion problems and cracking defects may occur in this area of ​​the packaged semiconductor device.

[0087] exist Fig. 7A , the scribe spacer region 730 includes a scribe seal 753 at the edge of the semiconductor die 7051 where the scribe street 703 meets the scribe spacer region 730. In addition, a second scribe seal inserted from the edge scribe seal may be used as shown. In the described arrangement, the polymer anchor will be formed to be spaced apart from the scribe seal because the scribe seal includes a metal structure (see Figure 5E Detailed view of example scribe seal 553 in FIG. 5 and corresponding description above). To prevent damage from the etching process used to form the polymer anchor, the polymer anchor will be formed to be spaced apart from the scribe seal.

[0088] Figure 7B Another cross-sectional view illustrates the structure of a substrate after photoresist deposition and patterning process. Fig. 7A Components. Figure 7B As shown in , photoresist 740 is deposited and patterned to form openings 742 spaced apart from scribe seal 753, for example, in this example, if two scribe seals are used on semiconductor dies 7051, 7052, the openings are placed between and inserted from the two scribe seals, but other patterns may be used. Figures 6A-6HCompared to the arrangement of FIG. 1 , in this alternative method, at this step, the retained scribe line 703 is covered; in this alternative method, the polymer anchor will be formed before the dicing process; this allows the use of different shapes and different etch profiles, the etch for the polymer anchor being different from the etch used for dicing.

[0089] Figure 7C Another cross-sectional view illustrates the Figure 7B Components. Figure 7C In the embodiment, the protective overcoat layer 725 and any other underlying dielectric layers (not shown for simplicity of illustration, see the description of the front-end process layers and the back-end process layers above and Figure 5E ) is etched through in the opening 742 to the device side surface 720 of the semiconductor wafer 701. The dielectric etch may be performed in a plasma singulation tool as a nitride or oxide etch. In an alternative approach, a wet etch for oxides and nitrides may be used to etch the dielectric layer in the opening 742.

[0090] Fig.7D Another cross-sectional view is shown after an additional etching process. Figure 7C Components. Fig.7D , polymer anchors 755 and 756 are shown. The cross-section of the example polymer anchor 755 is rectangular, while the cross-section of the example polymer anchor 756 is circular or oval. Additional polymer anchor shapes may be formed as additional alternatives, such as Figure 6H In an example process, a plasma etching tool (a dry etching process, such as a deep reactive ion etching (DRIE) plasma process) can be used to perform semiconductor etching on the semiconductor wafer 701 in the opening 742 to form the polymer anchor 755 or 756. For example, a plasma dicing tool can be used. In an additional alternative, a wet etch, such as a wet etching process, can be used to form the polymer anchor 755 or 756. Depending on whether the etching process selected for use is more anisotropic or more isotropic, different polymer anchor shapes can be formed. Figures 6A-6H Compared to the method of , the etching process used to form the polymer anchors in this method does not etch the semiconductor wafer 701 in the scribe streets 703, which remain covered by the PR 740 at this stage.

[0091] With respect to where the polymer anchors 755 or 756 should be placed, as described above, using experimental data collected on failed devices or using a mechanical simulator, areas in the scribe space region of the semiconductor die where cracking is most likely to occur in the protective overcoat or at the interface between the protective overcoat and the polymer material can be identified. Observations indicate that the corner regions of the semiconductor die where the distance to the neutral point (DNP) at the center of the semiconductor die is the greatest are where cracking issues are most likely to occur. The polymer anchors can be placed at the corner regions and reduce or eliminate the likelihood that cracks will propagate into the device region of the semiconductor device. Alternatively, the polymer anchors can be placed throughout the scribe space region surrounding the semiconductor die.

[0092] Fig. 7E Another cross-sectional view shows the Fig.7D Components. Fig. 7E In the process, the photoresist layer 740 is removed from the semiconductor wafer 701. In one example process, a plasma ashing process is used to strip the photoresist layer 740. In an alternative process, a chemical stripper may be used to remove the photoresist layer 740.

[0093] Figure 7F Additional cross-sectional views are shown after additional processing. Fig. 7E A second photoresist layer 748 is deposited and patterned and covers the semiconductor dies 7051 , 7052 , while forming an opening 744 to expose the protective overcoat layer 725 above the semiconductor wafer 701 in the scribe street 703 .

[0094] Figure 7G Additional cross-sectional views are shown after additional processing. Figure 7F Components. Figure 7G In the embodiment of the present invention, a plasma dicing process is used to etch through the semiconductor wafer 701 in the dicing streets 703, while the PR layer 740 protects the semiconductor die 7051, 7052 from the etching process. As described above, in the plasma dicing tool, a first dielectric etch, such as using argon, fluorine, or oxygen, can remove the protective overcoat 725 in the opening 744. ... Figure 5B In an additional plasma etching process of the cyclic etching and polymer deposition steps shown in , the semiconductor wafer 701 can be etched through in the scribe streets 703, thereby singulating the semiconductor wafer. Figure 7G In the method, the formation of the polymer anchor is performed in sequence before the wafer dicing process.

[0095] While the illustrated example uses a plasma dicing process, in another alternative method, after forming the polymer anchors 755 or 756 and stripping the photoresist 740, a mechanical saw or laser cutting tool may be used to diced the semiconductor wafer. However, as described above, plasma dicing has several advantages over other dicing methods, including narrower dicing street requirements, thereby increasing the semiconductor wafer area available for devices. Plasma dicing also dices along all dicing streets on the wafer simultaneously, thereby increasing the throughput of multi-pass sawing or laser operations.

[0096] Figure 7H Another cross-sectional view Figure 7G 7052, illustrating die side 729 (showing a scalloped shape indicative of the plasma dicing process used in the illustrated example). For simplicity of illustration, the polymer sidewall coating is not shown (see FIG. Figure 5B 541). Slice seals 753 are shown with polymer anchors 756 positioned between and inserted from the scribe seals. In some examples, scribe seals 753 are positioned only at the edge of semiconductor die 7052. Protective overcoat 725 is covered by polyimide layer 727 in the device area, but in scribe spacer area 730, polyimide layer 727 is not present.

[0097] Fig.7I The example molding process is described after covering the semiconductor die 7052 with a polymer material as an electronic molding compound (when the semiconductor die 7052 is packaged in a semiconductor device package, see, for example, Figures 4A-4F )of Figure 7H When the polymer material (here, the molding compound 723) covers the device side of the semiconductor die 7052, the molding compound fills the polymer anchor 756. The polymer anchor 756 extends into the semiconductor wafer 701, and if a crack starts in the protective overcoat 725 or the molding compound 723, the polymer anchor will act as a crack stopper so that the crack will not propagate into the device area of ​​the semiconductor die 7052.

[0098] Figure 8 The method for forming the arrangement is illustrated in a flow chart. At step 801, the method begins by depositing a photoresist layer over a protective overcoat layer over a semiconductor wafer having semiconductor dies formed on a device side surface, the semiconductor dies being separated from each other by scribe lines. (See, e.g., Figure 6B . )

[0099] At step 803, the method continues by patterning the photoresist layer to form openings corresponding to polymer anchor locations in the scribe space regions between the device region and the scribe streets on the device side surface of the semiconductor die. (See, e.g., Figure 6C The opening 642 in the PR layer 640 in FIG. )

[0100] At step 805, the method continues by etching through the protective overcoat layer in openings using the patterned photoresist layer to expose the device side surface of the semiconductor wafer at the location of the polymer anchor. (See, e.g., Fig.6D )

[0101] At step 807, the method continues by etching into the semiconductor wafer at the polymer anchor location using the opening in the patterned photoresist layer to form a polymer anchor, which is a recess, cavity or trench extending into the semiconductor wafer. (See, e.g., Fig. 6E The polymer anchor 645 in the embodiment of the present invention. )

[0102] At step 809, the method continues by dicing the semiconductor wafer to form individual semiconductor die having four sides formed in the dicing process, the semiconductor die having polymer anchors in the dicing spacer regions at the periphery of the semiconductor die. Fig. 6F The polymer anchor 645 in FIG. 60 is shown, for example, in die 6051, 6052. )

[0103] Fig. 9 An alternative method for forming an arrangement is illustrated in another flow chart.

[0104] exist Fig. 9 In the method, the method begins at step 901, depositing a photoresist layer over a protective overcoat layer over a semiconductor wafer, the semiconductor wafer having semiconductor dies formed on a device side surface, the semiconductor dies being separated from each other by scribe lines defined between the semiconductor dies. (See, e.g., Figure 6B PR layer 640 and cut street 603. )

[0105] The method continues at step 903 by patterning the photoresist layer to form openings corresponding to polymer anchor locations in the scribe space regions between the device region and the scribe streets on the device side surface of the semiconductor die and forming openings in the scribe streets. (See, e.g., Figure 6C The openings 642, 644 in the PR layer 640 are shown in FIG.

[0106] The method continues at step 905 by using the openings in the patterned photoresist layer to etch through the protective overcoat layer in the openings using a plasma etching process to expose the device side surface of the semiconductor wafer at the polymer anchor locations and in the scribe streets. (See, for example, the openings 642, 644 at Fig.6D The dielectric etch shown in . )

[0107] The method then continues at step 907 by etching into the semiconductor wafer at the polymer anchor locations using the openings in the patterned photoresist layer using a plasma process to form polymer anchors, which are recesses, cavities, or trenches extending into the semiconductor wafer. (See, e.g., Fig. 6E The polymer anchor 645 in the embodiment of the present invention. )

[0108] The method is completed at step 909 by simultaneously etching through the semiconductor wafer in scribe streets, singulating the semiconductor wafer to form individual semiconductor dies having polymer anchors in scribe spacer regions at the periphery of the semiconductor die. (See Fig. 6E The etching in which the semiconductor wafer 601 is removed from the scribe line 603 is performed. Fig. 9 In the method, the polymer anchor and the slicing operation are performed simultaneously using a plasma etching process, so the sidewalls of the polymer anchor will have a fan-shaped shape formed in the cyclic plasma etching process.

[0109] The use of the arrangement provides the advantage of reducing crack propagation in the cut region of the semiconductor device, where the protective outer coating directly contacts the polymer material, such as a molding compound or an underfill. In some example arrangements, polymer anchors extending through the dielectric layer into the semiconductor substrate are formed in a plasma cutting tool simultaneously with the cutting process. This allows the polymer anchors to be formed using the same process steps as those used for wafer cutting and using the same photoresist deposition and patterning steps, thereby allowing the arrangement to be formed with little or no additional cost. In an alternative arrangement, an etchant is used to etch through the protective outer coating into the semiconductor substrate, forming polymer anchors in the cut spacing region at the periphery of the semiconductor die before the cutting step. The polymer anchors can be formed using plasma etching or using a wet etching process. The semiconductor wafer is then cut. In some example arrangements, the semiconductor wafer is cut using a plasma cutting process. In other examples, a sawing or laser cutting tool can be used. When the device side surface of the semiconductor die is subsequently covered with a polymer material such as a molding compound or an underfill material, the polymer material fills the polymer anchors, and the filled polymer anchors act as crack stops, thereby reducing or eliminating crack propagation from the protective overcoat into the device area of ​​the semiconductor die, thereby preventing defects and device failures that may occur without the use of the described arrangement.

[0110] Modifications may be made in the arrangements described, and other alternative arrangements are possible, within the scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: depositing a photoresist layer over the protective overcoat layer over a semiconductor wafer having semiconductor dies formed on a device-side surface, the semiconductor dies being spaced apart from one another by scribe streets; patterning the photoresist layer to form openings corresponding to polymer anchor locations in scribe space regions between device regions and scribe streets on the device side surface of the semiconductor die; using a patterned photoresist layer, etching through the protective overcoat layer in the opening to expose the device-side surface of the semiconductor wafer at the location of the polymer anchor; etching into the semiconductor wafer at the polymer anchor location using the opening in the patterned photoresist layer to form a polymer anchor, the polymer anchor being a recess extending into the semiconductor wafer; as well as The semiconductor wafer is diced to separate the semiconductor dies, thereby forming individual semiconductor dies having the polymer anchors in the dicing space regions at the peripheries of the individual semiconductor dies. 2 . The method of claim 1 , wherein etching through the protective overcoat layer in the openings using the patterned photoresist layer further comprises etching through the protective overcoat layer in the scribe streets. 3 . The method of claim 2 , wherein etching into the semiconductor wafer using the openings in the patterned photoresist layer further comprises etching through the semiconductor wafer in the scribe streets to perform the singulation of the semiconductor wafer.

4. The method according to claim 1, wherein the following steps are performed simultaneously using a plasma dicing process: etching into the semiconductor wafer at the location of the polymer anchor using the opening in the patterned photoresist layer, the polymer anchor being a recess extending into the semiconductor wafer; and dicing the semiconductor wafer to form individual semiconductor dies.

5. The method according to claim 4, wherein the following steps are performed in sequence using a plasma dicing process: using the opening in the patterned photoresist layer, etching into the semiconductor wafer at the location of the polymer anchor, the polymer anchor being a recess extending into the semiconductor wafer; and singulating the semiconductor wafer to form individual semiconductor dies, the plasma singulation process first forming the polymer anchors and then etching through the semiconductor wafer in the scribe streets to perform the singulation of the semiconductor wafer. The method of claim 1 , wherein the polymer anchor has scalloped edges on sidewalls in the semiconductor wafer.

7. The method according to claim 1, wherein the following The steps further include etching using a wet etching process: using the patterned photoresist layer, etching through the protective overcoat layer in the opening to expose the device side surface of the semiconductor wafer at the location of the polymer anchor; and etching into the semiconductor wafer at the polymer anchor location using the opening in the patterned photoresist layer to form a polymer anchor, the polymer anchor being a recess extending into the semiconductor wafer.

8. The method of claim 1, wherein etching into the semiconductor wafer at the polymer anchor location to form a polymer anchor using the opening in the patterned photoresist layer comprises forming a polymer anchor having a rectangular cross-section.

9. The method of claim 1, wherein etching into the semiconductor wafer at the polymer anchor location to form a polymer anchor using the opening in the patterned photoresist layer comprises forming a polymer anchor having an elliptical or circular cross-section.

10. The method of claim 1, and further comprising: mounting individual semiconductor dies to a package substrate; as well as At least a portion of the individual semiconductor die is covered with a polymer material that fills the recess of the polymer anchor to form a filled polymer anchor.

11. The method of claim 10, wherein the polymer material is an electronic molding compound, an epoxy, a resin, an epoxy, or an underfill material.

12. The method of claim 11, wherein the polymer material is an underfill material comprising epoxy and silicon dioxide fillers.

13. The method of claim 1, wherein patterning the photoresist layer to form openings corresponding to polymer anchor positions in a scribe spacing region between a device region on the device side surface of the semiconductor die and the scribe lane further comprises forming openings corresponding to polymer anchor positions in a corner region of the semiconductor die.

14. The method of claim 1, wherein the following steps further include forming a polymer anchor as an open trench in the scribe spacing region: using the opening in the patterned photoresist layer, etching into the semiconductor wafer at the polymer anchor location to form a polymer anchor, the polymer anchor being a recess extending into the semiconductor wafer.

15. A method for manufacturing a semiconductor device, comprising: depositing a photoresist layer over the protective overcoat layer over a semiconductor wafer having semiconductor dies formed on a device-side surface, the semiconductor dies being spaced apart from one another by scribe streets defined between the semiconductor dies; patterning the photoresist layer to form openings corresponding to polymer anchor locations in scribe space regions between a device region on the device side surface of the semiconductor die and the scribe streets, and forming openings in the scribe streets; using the openings in the patterned photoresist layer, etching through the protective overcoat layer in the openings using a plasma etching process to expose the device side surface of the semiconductor wafer at the polymer anchor locations and in the scribe streets; using the opening in the patterned photoresist layer, etching into the semiconductor wafer at the polymer anchor location using the plasma etching process to form a polymer anchor, the polymer anchor being a recess extending into the semiconductor wafer; as well as The semiconductor wafer is simultaneously etched through the scribe streets, singulating the semiconductor wafer to form individual semiconductor dies having the polymer anchors in scribe space regions at the periphery of the individual semiconductor dies.

16. The method of claim 15, wherein the polymer anchor comprises a recess having vertical sidewalls with scalloped sides.

17. The method of claim 15, wherein the semiconductor die has vertical sides with scalloped sides.

18. The method of claim 15, wherein the polymer anchor locations are located in the scribe space regions at corners of the semiconductor die.

19. The method of claim 15, and further comprising: mounting the selected individual semiconductor die to a package substrate; as well as At least a portion of the selected individual semiconductor die is covered with a polymer material that fills the recess of the polymer anchor to form a filled polymer anchor.

20. The method of claim 19, wherein covering at least a portion of the selected individual semiconductor die with a polymer material further comprises the polymer material being an electronic molding compound, an epoxy, a resin, an epoxy, or an underfill material.

21. The method of claim 19, wherein the polymer material is an underfill material, the underfill material being an epoxy with a silica filler.

22. A semiconductor device comprising: a semiconductor die formed on a semiconductor substrate and having a device-side surface, a backside surface opposite the device-side surface, and a side surface between the device-side surface and the backside surface at an edge of the semiconductor die; The semiconductor die has a device region including electrical devices formed on the semiconductor die and a scribe spacer region between the device region and the edge of the semiconductor die; the semiconductor die having a polymer anchor in the scribe space region, the polymer anchor comprising a recess extending through a protective overcoat dielectric layer over the device-side surface of the semiconductor die and into the semiconductor substrate of the semiconductor die; as well as A polymer material covers at least a portion of the semiconductor die, the polymer material filling the recess of the polymer anchor.

23. The semiconductor device of claim 22, wherein the polymer material is an electronic molding compound, an epoxy, a resin, an epoxy resin, or an underfill material.

24. The semiconductor device of claim 23, wherein the polymer material is an underfill material comprising epoxy and silicon dioxide fillers.

25. The semiconductor device of claim 22, wherein the polymer anchor has a sidewall with a scalloped side in the semiconductor substrate.

26. A semiconductor device according to claim 22, wherein the polymer anchor includes an open trench formed at the device side surface of the semiconductor die and extending into the semiconductor substrate, and the length of the open trench extending parallel to the device side surface of the semiconductor die is greater than the depth of the trench extending into the device side surface of the semiconductor die.

27. The semiconductor device of claim 22, wherein the polymer anchor has a rectangular cross-section.

28. The semiconductor device of claim 22, wherein the polymer anchor has a circular cross-section.

29. The semiconductor device of claim 22, wherein the polymer anchor is located in a corner region of a scribe area of ​​the semiconductor die.

30. A semiconductor device package, comprising: a semiconductor die having a device-side surface, a backside surface opposite the device-side surface, and a side surface extending between the device-side surface and the backside surface at an edge of the semiconductor die; The semiconductor die has a device region including electrical devices formed on the semiconductor die and a scribe spacer region between the device region and the edge of the semiconductor die; the semiconductor die having a polymer anchor in the scribe space region, the polymer anchor being a recess extending through a protective overcoat dielectric layer over the device side surface of the semiconductor die and into the semiconductor substrate of the semiconductor die; a package substrate having a device surface and a board side surface opposite to the device surface, and having conductive terminals on the board side surface, the semiconductor die being mounted to the device surface of the package substrate; as well as A polymer material covers at least a portion of the semiconductor die and at least a portion of the package substrate, the polymer material fills the recess of the polymer anchor, and the terminal is exposed from the polymer material.

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