Converter package with integrated inductor

Abstract

The invention relates to a converter package with an integrated inductor. A semiconductor package (101) includes an integrated circuit die (102) covered by a molding compound (108) to form a quadrilateral package having a top surface and a bottom surface. A first group of leadless contacts (103) is exposed on the first side of the package and the bottom surface. A second group of leadless contacts (103) is exposed on a second side of the package and the bottom surface, wherein the second side is opposite the first side. A first external lead (104) extends from a third side of the package. A second external lead (104) extends from a fourth side of the package opposite the third side. The first outer lead (104) and the second outer lead (104) are curved to extend over the top surface of the package. The first external lead (104) and the second external lead (104) have a gull wing shape or a J shape.

Description

Technical Field

[0001] The present disclosure relates to a converter package with an integrated inductor. Background Art

[0002] Semiconductor device integrated circuits are becoming smaller, semiconductor packages are becoming smaller, and systems are becoming smaller. As a result, the density of component mounting on the system PCB is increasing, and space-saving design is required. Summary of the invention

[0003] In one arrangement, a semiconductor package includes an integrated circuit (IC) die covered by a molding compound to form a four-sided package having a top surface and a bottom surface. A first group of leadless contacts are exposed on a first side of the package and the bottom surface. A second group of leadless contacts are exposed on a second side of the package and the bottom surface, wherein the second side is opposite to the first side. A first external lead extends from a third side of the package. A second external lead extends from a fourth side of the package opposite to the third side. The first external lead and the second external lead are bent to extend above the top surface of the package.

[0004] The first external lead and the second external lead may be shaped as gull-wing leads, each having a top end that bends away from the package. Alternatively, the first external lead and the second external lead may be J-shaped leads, each having a top end that bends above the top surface of the package. An opening may be formed in one or more of the first external lead and the second external lead.

[0005] The first external leads and one or more of the first group of leadless contacts are part of a continuous leadframe segment attached to the IC die.

[0006] The second external lead includes a half-etched end portion within the mold compound. The end portion has a half-etched tab extending laterally from the second external lead. The tab is not exposed on the bottom surface of the package. The second external lead is not directly electrically coupled to the IC die.

[0007] Each of the leadless contacts includes a half-etched portion that is not exposed through the mold compound on the bottom surface of the package.

[0008] In another arrangement, a semiconductor package includes a semiconductor die electrically coupled to one or more lead frame segments, and an encapsulation covering the semiconductor die and at least a portion of the lead frame segments. The lead frame segments form a first set of leadless contacts along a first bottom edge of the package. The lead frame segments also form a first external lead on a second bottom edge of the package. The second external lead is formed on a third bottom edge of the package opposite the second edge. The first external lead and the second external lead extend above a top surface of the encapsulation. The second set of leadless contacts is positioned along a fourth bottom edge of the package opposite the first edge.

[0009] The first external lead and the second external lead are shaped as gull-wing leads or J-shaped leads. The gull-wing leads each have a top end that bends away from the package. The J-shaped leads each have a top end that bends above the top surface of the encapsulation. An opening is formed in one or more of the first external lead and the second external lead. The first external lead is electrically coupled to one or more of the first set of leadless contacts. The first external lead and one or more of the first set of leadless contacts are part of a continuous lead frame segment.

[0010] The second external lead is not directly electrically coupled to the semiconductor die. The second external lead includes a half-etched end portion within the encapsulation. The end portion has two half-etched tabs extending laterally from the second external lead. The tabs are not exposed on the bottom surface of the package.

[0011] The first set of leadless contacts includes half-etched portions that are not exposed through the encapsulant on the bottom surface of the package.

[0012] An electrical device such as an inductor, capacitor, or other passive component is attached to the top ends of the first and second external leads over the top surface of the encapsulant. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Having thus generally described the invention, reference will now be made to the accompanying drawings, in which:

[0014] Figure 1A and 1B are top and bottom isometric views of an electronic system, such as a DC power converter.

[0015] Figure 2 is a side view of an electronic system having a semiconductor package with gull-wing leads mounted on a top surface of a printed circuit board.

[0016] Figure 3 is a side view of an electronic system having an alternative semiconductor package with J-shaped leads.

[0017] Figure 4Ais an isometric view showing how the leadframe portion of a semiconductor package is attached to a semiconductor die and encapsulated in a molding compound.

[0018] Figure 4B yes Figure 4A A top cross-sectional view of a semiconductor package in FIG.

[0019] Figure 5A A lead frame strip is shown illustrating an example arrangement of leads for use with a hybrid package as described herein.

[0020] Figure 5B yes Figure 5A Detailed view of a portion of a leadframe strip shown in , showing how the IC die is positioned relative to the leadframe elements.

[0021] Figure 6 Show Figure 5A Portion of a leadframe sheet having contact segments half-etched on the bottom side.

[0022] Figure 7 Is used as Figure 6 A bottom isometric view of a semiconductor package assembled from a leadframe sheet as shown in FIG.

[0023] Figure 8 A top isometric view of a semiconductor package having end leads having an alternative configuration is shown. DETAILED DESCRIPTION

[0024] The present disclosure is described with reference to the accompanying drawings. The figures are not drawn to scale, and the figures are provided only to illustrate the present disclosure. Several aspects of the present disclosure are described below with reference to exemplary applications for illustration. It should be understood that many specific details, relationships and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the order of the actions or events shown, because some actions can occur in different orders and / or simultaneously with other actions or events. In addition, not all described actions or events are required to implement methods according to the present disclosure.

[0025] Unless otherwise indicated, corresponding reference numerals and symbols in different figures generally refer to corresponding parts. The drawings are not necessarily drawn to scale. In the drawings, the same reference numerals refer to the same elements throughout the text, and various features are not necessarily drawn to scale. In the following discussion and claims, the terms "including", "includes", "having", "has", "with" or their variations are intended to be inclusive in a manner similar to the term "comprising", and should therefore be interpreted as meaning "including but not limited to...". In addition, the terms "coupled", "coupled" and / or "couples" are intended to include indirect or direct electrical or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled to a second device, the connection may be a direct electrical connection, or may be an indirect electrical connection via one or more intervening devices and / or connections. Elements electrically connected to intervening wires or other conductors are considered to be coupled. For example, terms such as "top", "bottom", "front", "rear", "above", "above", "below", "below" may be used in the present disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but are used to provide spatial relationships between structures or elements.

[0026] The term "semiconductor die" is used herein. A semiconductor die refers to a thin slice of material such as crystalline silicon used to make integrated circuits. A large number of integrated circuits can be created on the active surface of a semiconductor die. A discrete semiconductor device may be an integrated circuit having hundreds or thousands of transistors coupled to form functional circuits such as a microprocessor or memory device. A semiconductor device may also be referred to herein as a semiconductor wafer or an integrated circuit (IC) die.

[0027] The term "semiconductor package" is used herein. A semiconductor package has at least one semiconductor die electrically coupled to a terminal, and has a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies may be packaged together. For example, a power metal oxide semiconductor (MOS) field effect transistor (FET) semiconductor device and a second semiconductor device (e.g., a gate driver die or a controller die) may be packaged together to form a single packaged electronic device. Additional components such as passive components (e.g., capacitors, resistors, and inductors or coils) may be included in the packaged electronic device. The semiconductor die is mounted with a package substrate that provides conductive leads. A portion of the conductive leads forms a terminal for the packaged device. In a wire-bonded integrated circuit package, bonding wires couple the conductive leads of the package substrate to bonding pads on the semiconductor die. The semiconductor die may be mounted to a package substrate with the device side surface facing away from the substrate and the back side surface facing the die pad of the package substrate and mounted to the die pad. The semiconductor package may have a package body formed by a thermosetting epoxy molding compound in a molding process or by using an epoxy, plastic, or resin that is liquid at room temperature and subsequently cured. The package body may provide a hermetic package for a packaged device. The package body may be formed in a mold using an encapsulation process, however, a portion of the leads of the package substrate are not covered during encapsulation, and these exposed lead portions form terminals for the semiconductor package. Semiconductor packaging may also be referred to as "integrated circuit packaging", "microelectronic device packaging", or "semiconductor device packaging".

[0028] The term "external leads" is used herein. In a packaged integrated circuit, the external leads provide electrical connections from contacts or pads on the outside of the semiconductor package to the internal leadframe, which is coupled to the semiconductor die within the package. The external leads are the portions of the leadframe that are exposed outside the mold compound or other protective encapsulant used for the semiconductor package. The leadframe and external leads may be etched, stamped, or cut to have the desired cross-sectional shape.

[0029] The terms "gull wing" and "J-shaped leads" are used herein to describe the shape of the external leads. As used herein, a "gull wing shape" refers to a pair of external leads, each of which has a terminal end attached to a semiconductor package and a free end. The free ends of each pair of gull wing leads are bent away from each other and away from the semiconductor package. As used herein, a "J-shape" refers to a pair of external leads, each of which has a terminal end attached to a semiconductor package and a free end. The free ends of each pair of J-shaped leads are bent toward each other. The free ends of each pair of J-shaped leads extend toward or above the semiconductor package.

[0030] Figure 1A and 1B1 is a top and bottom isometric view of an electronic system, such as a direct current (DC)-DC power converter, generally designated 100. A semiconductor package 101 includes a power control integrated circuit (IC) 102. Leadframe segments (not shown) inside the semiconductor package 101 couple the power control IC 102 to several external contacts 103, 104. Leadless contacts 103, such as the leads found on quad flat no-lead (QFN) and dual flat no-lead (DFN) devices, allow the semiconductor package 101 to be surface mounted directly on a printed circuit board (PCB). Gull-wing leads 104 allow other devices to be mounted to the semiconductor package 101. The gull-wing leads 104 have portions extending upward from a bottom surface 105 of the semiconductor package 101 and reaching above a top surface 106 of the semiconductor package 101. The gull-wing leads 104 are electrically coupled to passive components 107, such as an inductor. In other arrangements, passive component 107 may be a capacitor, resistor, coil, or the like.Semiconductor package 101 includes an encapsulant or mold compound 108 that covers and protects at least a portion of IC 102 and leadframe segments.

[0031] Semiconductor package 101 is a quad pin layout package having inverted gull-wing leads 104 on both sides. Gull-wing leads 104 take advantage of the capabilities of existing package designs, such as small outline IC (SOIC), small outline package (SOP), or small outline transistor (SOT). However, the inverted gull-wing leads extend in the opposite direction compared to typical package designs (i.e., gull-wing leads 104 extend upward from bottom surface 105 instead of downward).

[0032] Figure 2 2 is a side view of an electronic system, generally designated 200, having a semiconductor package 201, such as a power control package, mounted on a top surface 202 of a PCB 203. Solder paste is applied to pads 204 on surface 202 on the PCB 203 using a stencil or screen. The semiconductor package 201 is placed on the pads 204. Leadless contacts 205 and gull-wing leads 206 are attached to the PCB pads 204 by reflow. The semiconductor package 201 has a hybrid design in which rows of leadless contacts 205 are located on opposite sides of the package and gull-wing leads 206 are attached to opposite ends of the package. An inductor 207 or another passive component is attached to the semiconductor package 201 at the upper end of the gull-wing leads 206. The electronic system 200 has a smaller footprint than a typical micro system-in-package (SiP) module and utilizes existing assembly processes with changes to the lead design and layout.

[0033] Figure 3300 is a side view of an electronic system having an alternative hybrid semiconductor package 301. Similar to semiconductor package 201, semiconductor package 301 is mounted on a top surface 302 of a PCB 303. Semiconductor package 301 is placed on surface 302, and leadless contacts 305 and J-wing leads 306 are soldered to PCB pads 304. Semiconductor package 301 has an alternative hybrid design in which rows of leadless contacts 305 are located on opposite sides of the package and J-wing leads 306 are attached to opposite ends of the package. An inductor 307 or another passive component is attached to semiconductor package 301 at the upper ends of J-wing leads 306.

[0034] with Figure 2 Compared to the gull-wing leads 206 that bend outward in FIG. 1 , the J-wing leads 306 are folded over the top surface 308 of the semiconductor package 301, which allows for attachment to an inductor 307 that is shorter than the inductor 207 and allows for a narrower overall width of the system 300. Additionally, the electronic system 300 has a smaller footprint than a typical micro-SiP module and utilizes existing assembly processes with changes to the lead design and layout.

[0035] Figure 4A 4 is an isometric view of a lead frame portion 400 of a semiconductor package 401 according to one arrangement. The mold compound 402 and IC die 403 in the semiconductor package 401 are shown in phantom to illustrate their positions relative to the lead frame segment 400. The IC die 403 is mounted to the lead frame segment 400 in a flip chip on lead (FCOL) manner. In another arrangement,

[0036] Figure 4B yes Figure 4A 4 is a top cross-sectional view of a semiconductor package 401 in , which shows the molding compound 402 and the IC die 403 in phantom relative to the lead frame segment 400. Figure 4B The lead frame contacts in are further labeled to identify example pin names. Lead frame segment 400 has a first set of leadless contact areas 404a-d on one side of semiconductor package 401 and a second set of leadless contact areas 404e-h on the opposite side. Gull-wing leads 405a, b are located on opposite ends of semiconductor package 401.

[0037] The bottom surface of each leadless contact 404a-h and each gull-wing lead 405a,b is exposed on the bottom surface 406 of the semiconductor package 401. This allows electrical connection to external circuitry when the semiconductor package 401 is mounted on a PCB surface, for example.

[0038] The bonding pads on IC die 403 are electrically connected to die mounting contacts 407a-f on lead frame segment 400. One or more copper pillars 408 are used to connect die mounting contacts 407a-f to IC die 403. Die mounting contacts 407a-e are each individually and electronically tied to leadless contacts 404a-e on the side of semiconductor package 401. Leadless contact 404a is the portion of the lead frame trace that ends in die mounting contact 407a. Leadless contact 404b is the portion of the lead frame trace that ends in die mounting contact 407b. Leadless contact 404c is the portion of the lead frame trace that ends in die mounting contact 407c. Leadless contact 404d is the portion of the lead frame trace that ends in die mounting contact 407d. The leadless contact 404h is the portion of the leadframe trace that ends in the die mounting contact 407e.

[0039] Leadless contacts 404e-g and gull-wing leads 405a are connected to die mounting contacts 407f as part of a common leadframe trace. Top portions 409a, b of gull-wing leads 405a, b flare outwardly away from semiconductor package 401 and are suitable for attachment of external components such as inductors, capacitors or other passive devices. In an alternative arrangement, gull-wing leads 405a, b may be replaced with J-shaped leads having top portions that bend inwardly and over the top of semiconductor package 401. In the illustrated arrangement, gull-wing leads 405b do not include leadframe traces with die mounting contacts that would provide a direct connection to IC die 402. In practice, gull-wing leads 405b would provide a connection from the PCB to one end of an external component attached at 409b.

[0040] Figure 4B An example pin configuration for one arrangement of a DC-DC converter is shown. Leadless contact 404a is a voltage supply (Vin) pin that receives the main input voltage for the converter. Leadless contact 404b is an enable (EN) pin that turns the converter on and off. For example, setting the EN pin will enable the device, while a low voltage will disable the device. Leadless contact 404c is a power good (PG) pin that provides a signal indicating when device startup is complete. Leadless 404d is a feedback (FB) pin that provides a feedback input to the device, such as voltage feedback to an internal control loop. Leadless contact 404e is a ground (GND) pin.

[0041] Leadless contacts 404f-h and gull-wing lead contact 405a are coupled together through a common lead frame segment. Gull-wing lead contact 405a is connected to one end of an external (Ext) component such as an inductor. Gull-wing contact 405b is connected to the other end of the external component and provides an output voltage (Vout) for the device.

[0042] Figure 5A Lead frame strip 500 is shown, which shows an example arrangement of DFN and SOT leads for use with a square pin-out package as described herein. Lead frame strip 500 can be made from a copper sheet that is etched or stamped to form a lead frame such as a square pin-out package. Figure 5A 504. The IC die 501 is shown in dotted lines to illustrate its position when mounted on the lead frame sheet 500. After the IC die 501 is mounted, the IC die 501 and portions of the lead frame strip 500 are encapsulated in a molding compound or encapsulant material 503. The IC die 501 are separated from each other by sawing streets 504. The sawing streets 504 are defined areas of the lead frame strip 500 and the molding compound 504, in which groups of integrated circuit devices 501 can be separated in a later process step by cutting through the sawing streets 504 to form individual packages 505. Such singulation is typically achieved via a sawing process. In a conventional mechanical sawing process, a saw blade (or dicing blade) typically advances along the sawing streets 504, which extend in a prescribed pattern to separate the lead frame segments from each other. After singulation of the individual packages 505, the exposed lead frame segments 506a, b are bent upward into a gull-wing or J-lead shape.

[0043] Figure 5B Detailed view of a portion of leadframe strip 500 showing how IC die 501 are positioned relative to the leadframe elements for attachment. Each IC die 501 is mounted on six contact segments 507a-f. For example, IC die 501 has six bonding pads (not shown) that are aligned with the six contact segments 507a-f during flip chip mounting. The IC die bonding pads may be attached to the contacts by metal pillars or bumps such as copper pillars. Although Figure 5B The arrangement shown in Figure 5 shows a FCOL mounting for IC die 501, but in other arrangements, IC die 501 can be mounted using chip on lead (COL) technology, where the die is mounted on a lead frame with its active surface on top. The die is then connected to the lead frame using wire bonding. Die mounting contacts 502a-f are attached to lead segments including leadless pins 508a-h or leads 506a,b. After applying molding compound and singulating individual packages, the lead frame segments 506a,b are then bent upward into gull-wing or J-shaped lead shapes as desired.

[0044] like Figure 66. As shown in FIG. 6, the portion of the lead frame sheet 500 that forms the contact segments 507a-f is half-etched on the bottom side 601. When the molding compound 503 is applied, the molding material will cover the top and side surfaces of the IC bare die 501 and the contact segments 507a-f. The molding compound 503 will also flow below the half-etched contact segments 507a-f to cover and protect the bottom 601 lead frame sheet 500 in those areas. On the other hand, the portion that forms the leadless pins 508a-h is not half-etched. Therefore, the molding compound 503 will not cover the bottom leadless pins 508a-h, which will be exposed after singulation for installation on a PCB or other surface.

[0045] A portion of the lead frame segment 506b that forms the terminal lead after singulation of the individual device may also be half-etched. The lead frame segment 506b has two tabs 602 extending laterally from the terminal 603. In one arrangement, at least a portion of the terminal 603 and the tabs 602 are half-etched. This allows the mold compound 503 to flow under a portion of the segment 506b. The terminal 603 is then locked into place by the mold compound 503 so that the segment 506b can be bent into a gull-wing or J-shaped lead shape after singulation of the individual device.

[0046] Figure 7 Is used as Figure 6 506b. The bottom isometric view of a semiconductor package 701 assembled from a lead frame sheet 500 shown in FIG. The semiconductor package has a first group of leadless pins 508a-d on one side and a second group of leadless pins 508e-h on the opposite side. Gull-wing leads 702 have been formed by lead frame segment 506b. The half-etched tabs 602 on the ends 603 of segment 506b are enclosed within the mold compound 503. The half-etched tabs 602 on the ends 603 hold the leads 702 securely in place because the leads are not attached to any other internal lead frame structures after singulation.

[0047] Reference again Figure 5A , an alternative structure for the end leads 506a, b is shown as lead segments 516a, b having holes 509. The holes 509 may be formed by etching or stamping the lead frame sheet 500. The holes 509 provide stress relief when the end leads 506a, b are bent into a gull-wing or J-lead shape. In addition, the holes 509 slightly reduce the amount of lead frame material and the overall weight of the semiconductor package.

[0048] Figure 8A top isometric view of a semiconductor package 801 with terminal leads 802a, b having an alternative configuration is shown. The semiconductor package 801 can be assembled from a lead frame sheet 500 having holes 509. The terminal leads 802a and leadless contacts 803 are internally connected to an IC die 804. After singulation from the lead frame sheet 500, the terminal leads 802a, b are bent into a gull-wing shape. In another arrangement, the terminal leads can instead be bent over the top of the semiconductor package 801 to form a J-shaped lead. The opening 805 in the gull-wing leads 802a, b is formed as a hole 509 in the lead frame sheet.

[0049] An exemplary embodiment of a semiconductor package includes an IC die covered by a molding compound to form a four-sided package having a top surface and a bottom surface. A first group of leadless contacts are exposed on a first side and a bottom surface of the package. A second group of leadless contacts are exposed on a second side and a bottom surface of the package. The second side is opposite to the first side. A first external lead extends from a third side of the package. A second external lead extends from a fourth side of the package opposite to the third side. The first external lead and the second external lead are bent to extend above the top surface of the package. The first external lead and the second external lead may be formed as gull-wing leads, each having a top end bent away from the package. The first external lead and the second external lead may be J-shaped leads, each having a top end bent above the top surface of the package. The semiconductor package may further include an opening formed in one or more of the first external lead and the second external lead.

[0050] The first external leads and one or more of the first group of leadless contacts can be part of a continuous leadframe segment attached to the IC die.

[0051] The second external lead includes a half-etched end portion within the mold compound. The end portion has a half-etched tab extending laterally from the second external lead and not exposed on the bottom surface of the package. In some embodiments, the second external lead may not be directly electrically coupled to the IC die.

[0052] Each of the leadless contacts may include a half-etched portion that is not exposed through the mold compound on the bottom surface of the package.

[0053] In another arrangement, the semiconductor package includes a semiconductor die electrically coupled to one or more lead frame segments. The encapsulation covers at least a portion of the semiconductor die and the lead frame segments. The lead frame segments form a first set of leadless contacts along a first bottom edge of the package. The lead frame segments form a first external lead on a second bottom edge of the package. The second external lead is located on a third bottom edge of the package opposite to the second edge. The first external lead and the second external lead extend above the top surface of the encapsulation. The first external lead and the second external lead are formed as gull-wing leads, wherein the gull-wing leads each have a top end that bends away from the package. Alternatively, the first external lead and the second external lead are J-shaped leads, wherein the J-shaped leads each have a top end that bends above the top surface of the encapsulation. The second set of leadless contacts are positioned along a fourth bottom edge of the package opposite to the first edge. The semiconductor package may further include an electrical device attached to the top ends of the first external lead and the second external lead above the top surface of the encapsulation.

[0054] An opening may be formed in one or more of the first external lead and the second external lead.In some configurations, the first external lead is electrically coupled to one or more of the first set of leadless contacts.

[0055] One or more of the first external leads and the first set of leadless contacts may be part of a continuous leadframe segment.

[0056] In some configurations, the second external lead may not be directly electrically coupled to the semiconductor die.

[0057] The second external lead includes a half-etched end portion within the encapsulant. The end portion has a half-etched tab extending laterally from the second external lead and not exposed on the bottom surface of the package.

[0058] Each of the first set of leadless contacts may include a half-etched portion that is not exposed through the encapsulant on the bottom surface of the package.

[0059] Although various examples of the present disclosure have been described above, it should be understood that the examples are presented only by way of example and not limitation. Without departing from the spirit or scope of the present disclosure, numerous changes may be made to the disclosed examples according to the disclosure herein. Modifications may be made in the described embodiments, and other embodiments are possible within the scope of the claims. Therefore, the breadth and scope of the present invention should not be limited by any of the examples described above. In fact, the scope of the present disclosure should be limited according to the attached claims and their equivalents.

Claims

1. A semiconductor package, comprising: an integrated circuit IC die covered by a molding compound to form a four-sided package having a top surface and a bottom surface; a first group of leadless contacts exposed on a first side of the package and on the bottom surface; a second group of leadless contacts exposed on a second side of the package and on the bottom surface, wherein the second side is opposite the first side; a first external lead extending from a third side of the package; as well as A second external lead extends from a fourth side of the package opposite to the third side, the first external lead and the second external lead being bent to extend above the top surface of the package. 2 . The semiconductor package of claim 1 , wherein the first outer lead and the second outer lead are shaped as gull-wing leads each having a top end bent away from the package. 3 . The semiconductor package according to claim 1 , wherein the first external lead and the second external lead are J-shaped leads each having a top end bent above the top surface of the package.

4. The semiconductor package according to claim 1, further comprising: An opening is formed in one or more of the first external lead and the second external lead.

5. The semiconductor package of claim 1, wherein the first external leads and one or more of the first group of leadless contacts are part of a continuous leadframe segment attached to the IC die.

6. The semiconductor package according to claim 1, wherein the second external lead comprises: A half-etched end portion within the mold compound has a half-etched tab extending laterally from the second external lead and not exposed on the bottom surface of the package, and the second external lead is not directly electrically coupled to the IC die. 7 . The semiconductor package of claim 1 , wherein each of the leadless contacts includes a half-etched portion that is not exposed through the mold compound on the bottom surface of the package.

8. A semiconductor package, comprising: a semiconductor die electrically coupled to the one or more leadframe segments; an encapsulant covering the semiconductor die and at least a portion of the leadframe segment; The lead frame segments form a first set of leadless contacts along a first bottom edge of the package; The lead frame segment forms a first external lead on a second bottom edge of the package; as well as A second external lead is on a third bottom edge of the package opposite the second edge, the first external lead and the second external lead extending above the top surface of the encapsulant. 9 . The semiconductor package of claim 8 , wherein the first outer lead and the second outer lead are shaped as gull-wing leads.

10. The semiconductor package of claim 9, wherein the gull-wing leads each have a top end that bends away from the package. 11 . The semiconductor package according to claim 8 , wherein the first external lead and the second external lead are J-shaped leads. 12 . The semiconductor package of claim 11 , wherein the J-shaped leads each have a top end bent above the top surface of the encapsulant.

13. The semiconductor package according to claim 8, further comprising: A second set of leadless contacts is provided along a fourth bottom edge of the package opposite the first edge.

14. The semiconductor package according to claim 8, further comprising: An opening is formed in one or more of the first external lead and the second external lead.

15. The semiconductor package of claim 8, wherein the first external lead is electrically coupled to one or more of the first set of leadless contacts.

16. The semiconductor package of claim 8, wherein one or more of the first external leads and the first set of leadless contacts are part of a continuous leadframe segment.

17. The semiconductor package of claim 8, wherein the second external lead is not directly electrically coupled to the semiconductor die.

18. The semiconductor package according to claim 8, wherein the second external lead comprises: A half-etched end portion is within the encapsulant, the end portion having a half-etched tab extending laterally from the second external lead and not exposed on a bottom surface of the package.

19. The semiconductor package of claim 8, wherein each of the first set of leadless contacts comprises a half-etched portion that is not exposed through the encapsulant on a bottom surface of the package.

20. The semiconductor package according to claim 8, further comprising: An electrical device is attached to top ends of the first external lead and the second external lead over the top surface of the encapsulant.

Images