Semiconductor package including plurality of semiconductor chips

Abstract

The semiconductor package includes a first chip and a second chip horizontally spaced apart from each other on a substrate. An underfill layer is interposed between the substrate and the first and second chips. An upper mold layer is disposed on the substrate to cover side surfaces of the first chip and the second chip. The second chip includes vertically stacked sub-chips and a chip molding layer covering side surfaces of the sub-chips. The underfill layer extends into a space between the chip molding layer and a lower side surface of the first chip. The upper molding layer extends into a space between the chip molding layer and an upper side surface of the first chip to cover an uppermost surface of the underfill layer. An upper side surface of the chip molding layer is recessed inward relative to a lower side surface of the chip molding layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0101247 filed in the Korean Intellectual Property Office on August 2, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package on which a plurality of semiconductor chips are mounted. Background Art

[0004] Semiconductor packaging is configured to facilitate the incorporation of integrated circuit (IC) chips as components into electronic products. Typically, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and electrically connected to the PCB via bonding wires or bumps. With the development of the electronics industry, miniaturized, lightweight, and multifunctional electronic devices are produced. Multi-chip packaging technology has been developed for mounting multiple chips in a single semiconductor package. System-in-package technology has been developed for providing different types of chips that are mounted in a single semiconductor package to be used as a single system. Summary of the invention

[0005] The semiconductor package includes a first semiconductor chip and a second semiconductor chip which are arranged on an upper substrate and are horizontally spaced apart from each other. An upper bottom filling layer is between the upper substrate and the first semiconductor chip and between the upper substrate and the second semiconductor chip. An upper molding layer is arranged on the upper substrate and covers the side surfaces of the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a sub-semiconductor chip stacked in a vertical direction perpendicular to the upper surface of the upper substrate and a chip molding layer covering the side surfaces of the sub-semiconductor chips. The upper bottom filling layer extends into a space between a lower side surface of the chip molding layer and a lower side surface of the first semiconductor chip. The upper molding layer extends into a space between an upper side surface of the chip molding layer and an upper side surface of the first semiconductor chip, and covers the uppermost surface of the upper bottom filling layer. Relative to the lower side surface of the chip molding layer, the upper side surface of the chip molding layer is recessed toward the inside of the chip molding layer.

[0006] The semiconductor package includes a first semiconductor chip and a second semiconductor chip which are arranged on an upper substrate and are horizontally spaced apart from each other. An upper bottom filling layer is interposed between the upper substrate and the first semiconductor chip and between the upper substrate and the second semiconductor chip. An upper molding layer is interposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes at least one sub-semiconductor chip and a chip molding layer covering the side surface of at least one sub-semiconductor chip. The lower side surface of the chip molding layer faces the lower side surface of the first semiconductor chip. The upper side surface of the chip molding layer faces the upper side surface of the first semiconductor chip. Relative to the lower side surface of the chip molding layer, the upper side surface of the chip molding layer is recessed toward the inside of the chip molding layer. The upper bottom filling layer extends into the space between the lower side surface of the chip molding layer and the lower side surface of the first semiconductor chip. The uppermost surface of the upper bottom filling layer is located at a height lower than the upper surfaces of the first semiconductor chip and the second semiconductor chip. The upper molding layer fills the space between the upper side surface of the chip molding layer and the upper side surface of the first semiconductor chip and covers the uppermost surface of the upper bottom filling layer.

[0007] The method for manufacturing a semiconductor package includes mounting a first semiconductor chip and a second semiconductor chip horizontally spaced apart from each other on an upper substrate. The second semiconductor chip includes at least one sub-semiconductor chip and a chip molding layer covering the side surface of the at least one sub-semiconductor chip. The side surface of the chip molding layer is partially recessed so that the chip molding layer has a lower side surface and an upper side surface recessed toward the inside of the chip molding layer relative to the lower side surface. An upper bottom filling layer is formed. The upper bottom filling layer is between the upper substrate and the first semiconductor chip and between the upper substrate and the second semiconductor chip, and extends into the space between the lower side surface of the chip molding layer and the lower side surface of the first semiconductor chip. An upper molding layer is formed. The upper molding layer fills the space between the upper side surface of the chip molding layer and the upper side surface of the first semiconductor chip, and covers the uppermost surface of the upper bottom filling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the present disclosure and its many attendant aspects may be obtained as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a plan view showing a semiconductor package according to an embodiment of the inventive concept;

[0010] Figure 2 is along Figure 1 A cross-sectional view taken along line AA';

[0011] Figure 3 , Figure 5 , Figure 7 and Fig. 9is a plan view showing a method of manufacturing a semiconductor package according to an embodiment of the inventive concept;

[0012] Figure 4 , Figure 6 , Figure 8 and Fig.10 Along Figure 3 , Figure 5 , Figure 7 and Fig. 9 A cross-sectional view taken along line AA';

[0013] Fig.11 is a plan view showing a semiconductor package according to an embodiment of the inventive concept;

[0014] Fig. 12A and Fig. 12B is along Fig.11 A cross-sectional view taken along line AA';

[0015] Fig.13 is a plan view showing a semiconductor package according to an embodiment of the inventive concept;

[0016] Fig.14 is along Fig.13 A cross-sectional view taken along line BB';

[0017] Fig.15 , Fig.17 , Fig.19 and Fig.21 is a plan view showing a method of manufacturing a semiconductor package according to an embodiment of the inventive concept;

[0018] Fig.16 , Fig.18 , Fig. 20 and Fig. 22 Along Fig.15 , Fig.17 , Fig.19 and Fig.21 A cross-sectional view taken along line BB';

[0019] Fig.23 is a plan view showing a semiconductor package according to an embodiment of the inventive concept; and

[0020] Fig.24 is along Fig.23 A cross-sectional view taken along line BB'. DETAILED DESCRIPTION

[0021] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings.

[0022] Figure 1 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept. Figure 2 is along Figure 1 A cross-sectional view taken along line AA'.

[0023] Reference Figure 1 and Figure 2 , the semiconductor package 1000 may include an upper substrate 100. The first semiconductor chip 200 and the second semiconductor chip 300 are disposed on the upper substrate 100 and are horizontally spaced apart from each other. The upper substrate 100 may have a first surface 100a and a second surface 100b opposite to each other, and the first semiconductor chip 200 and the second semiconductor chip 300 may be mounted on the first surface 100a of the upper substrate 100.

[0024] In an embodiment, a plurality of first semiconductor chips 200 may be mounted on a first surface 100a of an upper substrate 100 and may be spaced apart from each other in a first direction D1 parallel to the first surface 100a of the upper substrate 100. A plurality of second semiconductor chips 300 may be mounted on the first surface 100a of the upper substrate 100 and may be disposed on both sides of each first semiconductor chip 200. The second semiconductor chips 300 may form a first column and a second column, wherein the second semiconductor chips 300 in the first column are spaced apart from each other in the first direction D1 on one side of each first semiconductor chip 200, and the second semiconductor chips 300 in the second column are spaced apart from each other in the first direction D1 on the opposite side of each first semiconductor chip 200. The second semiconductor chips 300 in the second column may be spaced apart from the second semiconductor chips 300 in the first column in a second direction D2, the second direction D2 being parallel to the first surface 100a of the upper substrate 100 and not parallel to the first direction D1. The first semiconductor chip 200 may be disposed between the second semiconductor chips 300 in the first column and the second semiconductor chips 300 in the second column.

[0025] The upper substrate 100 may include a semiconductor substrate 110, a plurality of penetration electrodes 120 penetrating the semiconductor substrate 110, and an interconnection layer 130 disposed on the semiconductor substrate 110. The interconnection layer 130 may be adjacent to a first surface 100a of the upper substrate 100, and the semiconductor substrate 110 may be adjacent to a second surface 100b of the upper substrate 100.

[0026] In an embodiment, the semiconductor substrate 110 may be a silicon substrate. The penetration electrodes 120 in the semiconductor substrate 110 may be spaced apart from each other in a horizontal direction (e.g., a first direction D1 or a second direction D2). Each penetration electrode 120 may extend along a third direction D3 perpendicular to the first surface 100a of the upper substrate 100, and may penetrate the semiconductor substrate 110. The penetration electrode 120 may include a conductive material and / or a metal (e.g., copper). The interconnection layer 130 may include an interconnection pattern 132 and an interconnection insulating layer 134 covering the interconnection pattern 132. The penetration electrode 120 may be connected (e.g., electrically connected) to the corresponding interconnection pattern 132. The interconnection pattern 132 may include a conductive material (e.g., metal), and the interconnection insulating layer 134 may include an electrically insulating material.

[0027] In an embodiment, the upper substrate 100 may be an interposer substrate.

[0028] The connection terminal 140 may be disposed on the second surface 100b of the upper substrate 100. The penetration electrode 120 may be connected (eg, electrically connected) to the connection terminal 140. The connection terminal 140 may include a conductive material and may be a solder ball, a bump, and / or a pillar.

[0029] The first semiconductor chip 200 may have an upper surface 200U and a lower surface 200L opposite to each other, and the lower surface 200L of the first semiconductor chip 200 may face the first surface 100a of the upper substrate 100. The first semiconductor chip 200 may include a circuit layer 210 and a chip pad 220 disposed adjacent to the lower surface 200L of the first semiconductor chip 200. The circuit layer 210 may include an integrated circuit, and the chip pad 220 may be electrically connected to the integrated circuit in the circuit layer 210. The chip pad 220 may include a conductive material (e.g., a metal).

[0030] The first bump 230 may be disposed on the lower surface 200L of the first semiconductor chip 200 and on the chip pad 220. The first bump 230 may be connected (e.g., electrically connected) to the chip pad 220. The first bump 230 may be disposed between the lower surface 200L of the first semiconductor chip 200 and the first surface 100a of the upper substrate 100, and may be connected (e.g., electrically connected) to the corresponding interconnection pattern 132 in the interconnection layer 130. The first semiconductor chip 200 may be electrically connected to the upper substrate 100 through the chip pad 220, the first bump 230, and the corresponding interconnection pattern 132. The first bump 230 may be formed of or may include at least one conductive material, and may be a solder ball, a bump, and / or a pillar.

[0031] The second semiconductor chip 300 may have an upper surface 300U and a lower surface 300L opposite to each other, and here, the lower surface 300L of the second semiconductor chip 300 may face the first surface 100a of the upper substrate 100. The second semiconductor chip 300 may include a buffer semiconductor chip 310 and a plurality of sub-semiconductor chips 320 stacked on the buffer semiconductor chip 310 along a third direction D3. The lower surface 300L of the second semiconductor chip 300 may correspond to the lower surface of the buffer semiconductor chip 310, and the upper surface 300U of the second semiconductor chip 300 may correspond to the upper surface of the uppermost sub-semiconductor chip among the sub-semiconductor chips 320. In this specification, the third direction D3 may be referred to as a vertical direction.

[0032] The buffer semiconductor chip 310 may include a buffer penetration electrode 315 that penetrates the buffer semiconductor chip 310 along the third direction D3. The buffer penetration electrode 315 may include a conductive material (e.g., metal). Each sub-semiconductor chip 320 may include a sub-penetration electrode 325 that penetrates each sub-semiconductor chip 320 along the third direction D3. In an embodiment, the uppermost sub-semiconductor chip 320 may not include the sub-penetration electrode 325. The sub-penetration electrode 325 may include a conductive material (e.g., metal).

[0033] The second semiconductor chip 300 may further include a sub-bump 330 disposed between the sub-semiconductor chips 320 and between the lowermost sub-semiconductor chip in the sub-semiconductor chips 320 and the buffer semiconductor chip 310. The sub-bump 330 may be connected (e.g., electrically connected) to the sub-penetrating electrodes 325 and the buffer penetration electrodes 315. The buffer semiconductor chip 310 and the sub-semiconductor chip 320 may be electrically connected to each other through the sub-penetrating electrodes 325, the buffer penetration electrodes 315, and the sub-bump 330. The sub-bump 330 may include a conductive material and may be a solder ball, a bump, and / or a pillar.

[0034] The second semiconductor chip 300 may further include a chip molding layer 340 disposed on the buffer semiconductor chip 310 and may cover side surfaces of the sub-semiconductor chips 320. The chip molding layer 340 may extend into a region between the sub-semiconductor chips 320 and between the lowermost sub-semiconductor chip 320 and the buffer semiconductor chip 310, and may cover the sub-bumps 330. The chip molding layer 340 may include an epoxy molding compound.

[0035] The second bump 350 may be disposed on the lower surface 300L of the second semiconductor chip 300, and may be connected (e.g., electrically connected) to the buffer penetration electrode 315. The second bump 350 may be disposed between the lower surface 300L of the second semiconductor chip 300 and the first surface 100a of the upper substrate 100, and may be connected (e.g., electrically connected) to the corresponding interconnection pattern 132 in the interconnection layer 130. The second semiconductor chip 300 may be electrically connected to the upper substrate 100 through the second bump 350 and the corresponding interconnection pattern 132. The second bump 350 may be formed of or may include at least one conductive material, and may be a solder ball, a bump, and / or a pillar.

[0036] The first semiconductor chip 200 and the second semiconductor chip 300 may be two different chips selected from a memory chip, a logic chip, an application processor (AP) chip, and a system on chip (SOC). As an example, the first semiconductor chip 200 may be one of a logic chip, an application processor (AP) chip, and a system on chip (SOC), and the second semiconductor chip 300 may be a memory chip. As an example, the buffer semiconductor chip 310 may include a logic circuit, a memory circuit, or a combination thereof, and the sub-semiconductor chip 320 may be a memory chip of the same type. For example, the second semiconductor chip 300 may be a high bandwidth memory (HBM) chip in which memory chips of the same kind are stacked.

[0037] The side surface 340LS or 340US of the chip molding layer 340 of the second semiconductor chip 300 may face the side surface 200S of the first semiconductor chip 200. The side surface 340LS or 340US of the chip molding layer 340 may have a stepped structure. The upper side surface 340US of the chip molding layer 340 may be recessed toward the inside of the chip molding layer 340 relative to the lower side surface 340LS of the chip molding layer 340. The side surface 200S of the first semiconductor chip 200 may include an upper side surface 200US facing the upper side surface 340US of the chip molding layer 340 and a lower side surface 200LS facing the lower side surface 340LS of the chip molding layer 340. The upper side surface 200US of the first semiconductor chip 200 and the lower side surface 200LS of the first semiconductor chip 200 may be aligned with each other in the third direction D3. The upper side surface 200US of the first semiconductor chip 200 may be coplanar with the lower side surface 200LS of the first semiconductor chip 200. The side surface 200S of the first semiconductor chip 200 may be perpendicular to the first surface 100a of the upper substrate 100.

[0038] A first distance DS1 between the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200 may be greater than a second distance DS2 between the lower side surface 340LS of the chip molding layer 340 and the lower side surface 200LS of the first semiconductor chip 200. In an embodiment, the second distance DS2 may be in a range of 30 μm to 90 μm. A length L of the upper side surface 340US of the chip molding layer 340 in the third direction D3 may be in a range of 50 μm to 600 μm. The upper side surface 340US of the chip molding layer 340 may be recessed by a first width W1 relative to the lower side surface 340LS of the chip molding layer 340, wherein the first width W1 is measured in a direction parallel to the first surface 100a of the upper substrate 100 (e.g., the second direction D2). In an embodiment, the first width W1 may be greater than or equal to 50 μm.

[0039] The upper bottom filling layer 400 may be interposed between the upper substrate 100 and the first semiconductor chip 200 and between the upper substrate 100 and the second semiconductor chip 300. The upper bottom filling layer 400 may fill the space between the first bumps 230 and the space between the second bumps 350. The upper bottom filling layer 400 may extend into the space between the first semiconductor chip 200 and the second semiconductor chip 300. The upper bottom filling layer 400 may extend into the space between the lower side surface 340LS of the chip molding layer 340 and the lower side surface 200LS of the first semiconductor chip 200, and may expose the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200. The uppermost surface 400U of the upper bottom filling layer 400 may be located at a height lower than the upper surface 200U of the first semiconductor chip 200 and the upper surface 300U of the second semiconductor chip 300. In this specification, the height may be a distance measured from the first surface 100 a of the upper substrate 100 in the third direction D3 .

[0040] The upper molding layer 500 may be disposed on the upper substrate 100 and may cover the side surfaces of the first semiconductor chip 200 and the second semiconductor chip 300. The upper molding layer 500 may extend into the space between the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200, and may cover the uppermost surface 400U of the upper bottom filling layer 400. The upper molding layer 500 may fill the space between the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200, and may be in direct contact with the uppermost surface 400U of the upper bottom filling layer 400. The upper surface 500U of the upper molding layer 500 may be located at the same height as the upper surface 200U of the first semiconductor chip 200 and the upper surface 300U of the second semiconductor chip 300. An upper surface 500U of the upper mold layer 500 may be coplanar with an upper surface 200U of the first semiconductor chip 200 and an upper surface 300U of the second semiconductor chip 300 .

[0041] The upper bottom filling layer 400 may include an insulating polymer material (e.g., epoxy resin). The upper molding layer 500 may include an epoxy molding compound (EMC). The thermal expansion coefficient of the upper molding layer 500 may be less than the thermal expansion coefficient of the upper bottom filling layer 400. As an example, the thermal expansion coefficient of the upper molding layer 500 may be in the range of 7ppm to 10ppm, and the thermal expansion coefficient of the upper bottom filling layer 400 may be in the range of 24ppm to 30ppm. Each of the upper molding layer 500 and the upper bottom filling layer 400 may include a filler, and in an embodiment, the filler may include silicon dioxide (SiO 2 ). The amount of the filler included in the upper molding layer 500 may be greater than the amount of the filler included in the upper bottom filling layer 400. In an embodiment, the amount of the filler included in the upper molding layer 500 may be in the range of about 80wt% to 99wt%, and the amount of the filler included in the upper bottom filling layer 400 may be in the range of about 50wt% to 60wt%. The size (e.g., volume) of the filler in the upper molding layer 500 may be greater than the size (e.g., volume) of the filler in the upper bottom filling layer 400. In an embodiment, the size (e.g., volume) of the filler in the upper molding layer 500 may be greater than or equal to 1.5 times the size (e.g., volume) of the filler in the upper bottom filling layer 400.

[0042] In the case where the distance between the first semiconductor chip 200 and the second semiconductor chip 300 is relatively small, the upper bottom filling layer 400 can be extended into the space between the first semiconductor chip 200 and the second semiconductor chip 300 by capillary force, and can be extended to the same height as the upper surface 200U of the first semiconductor chip 200 and the upper surface 300U of the second semiconductor chip 300. Therefore, the upper bottom filling layer 400 can fill the space between the first semiconductor chip 200 and the second semiconductor chip 300, and can be exposed to the outside of the semiconductor package 1000. In this case, since the upper bottom filling layer 400 has a relatively large thermal expansion coefficient, cracks may occur between the first semiconductor chip 200 and the second semiconductor chip 300, and such cracks may spread into the semiconductor package 1000. In addition, a warpage failure may occur in the semiconductor package 1000.

[0043] In contrast, according to an embodiment of the inventive concept, a portion of the chip molding layer 340 of the second semiconductor chip 300 may be removed from the region between the first semiconductor chip 200 and the second semiconductor chip 300. Therefore, the upper side surface 340US of the chip molding layer 340 may be recessed toward the inside of the chip molding layer 340 relative to the lower side surface 340LS of the chip molding layer 340, and the side surface 340LS or 340US of the chip molding layer 340 may have a stepped structure. A first distance DS1 between the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200 may be greater than a second distance DS2 between the lower side surface 340LS of the chip molding layer 340 and the lower side surface 200LS of the first semiconductor chip 200. In this case, the upper underfill layer 400 may be extended into a relatively narrow space between the lower side surface 340LS of the chip molding layer 340 and the lower side surface 200LS of the first semiconductor chip 200 by capillary force, and may not be extended into a relatively wide space between the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200. The uppermost surface 400U of the upper underfill layer 400 may be located at a lower height than the upper surface 200U of the first semiconductor chip 200 and the upper surface 300U of the second semiconductor chip 300. The upper molding layer 500 may fill the space between the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200, and cover the uppermost surface 400U of the upper underfill layer 400. Since the upper underfill layer 400 is covered by the upper molding layer 500, the upper underfill layer 400 may not be exposed to the outside of the semiconductor package 1000. Since the upper mold layer 500 has a smaller thermal expansion coefficient than the upper under-fill layer 400 , a crack failure between the first semiconductor chip 200 and the second semiconductor chip 300 may be reduced, and a warpage failure of the semiconductor package 1000 may also be reduced.

[0044] Since crack and warpage problems are suppressed, highly reliable semiconductor packaging can be achieved.

[0045] Figure 3 , Figure 5 , Figure 7 and Fig. 9 is a plan view illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept. Figure 4 , Figure 6 , Figure 8 and Fig.10 Along Figure 3 , Figure 5 , Figure 7 and Fig. 9 For the sake of simplicity, refer to Figure 1 and Figure 2 Described elements may be identified with the same reference numerals, and it will be understood that, without describing an element in detail with reference to this figure, the element is at least similar to a corresponding element that has been described elsewhere in the disclosure.

[0046] Reference Figure 3 and Figure 4 , an upper substrate 100 may be disposed on a carrier substrate 600, and an adhesive layer 610 may be disposed between the carrier substrate 600 and the upper substrate 100. The carrier substrate 600 may be, for example, a glass substrate. The adhesive layer 610 may include an adhesive material.

[0047] The upper substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. The upper substrate 100 may include a semiconductor substrate 110 adjacent to the second surface 100b, an interconnection layer 130 adjacent to the first surface 100a, and a plurality of penetration electrodes 120 penetrating the semiconductor substrate 110. The interconnection layer 130 may include an interconnection pattern 132 and an interconnection insulating layer 134 covering the interconnection pattern 132, and the penetration electrode 120 may penetrate the semiconductor substrate 110 and may be connected (e.g., electrically connected) to the corresponding interconnection pattern 132. The upper substrate 100 may be, for example, an interposer substrate. A connection terminal 140 may be provided on the second surface 100b of the upper substrate 100.

[0048] The adhesive layer 610 may be disposed between the second surface 100 b of the upper substrate 100 and the carrier substrate 600. The connection terminal 140 may be disposed in the adhesive layer 610. The upper substrate 100 may be attached to the carrier substrate 600 using the adhesive layer 610.

[0049] The first semiconductor chip 200 and the second semiconductor chip 300 may be mounted on the first surface 100 a of the upper substrate 100 .

[0050] The first semiconductor chip 200 may have an upper surface 200U and a lower surface 200L opposite to each other, and the lower surface 200L of the first semiconductor chip 200 may face the first surface 100a of the upper substrate 100. The first semiconductor chip 200 may include a circuit layer 210 and a chip pad 220 disposed adjacent to the lower surface 200L of the first semiconductor chip 200. A first bump 230 may be disposed on the lower surface 200L of the first semiconductor chip 200 and on the chip pad 220. The first bump 230 may be connected (e.g., electrically connected) to a corresponding interconnection pattern 132 in the interconnection layer 130 of the upper substrate 100. The first semiconductor chip 200 may be electrically connected to the upper substrate 100 through the chip pad 220, the first bump 230, and the corresponding interconnection pattern 132.

[0051] The second semiconductor chip 300 may have an upper surface 300U and a lower surface 300L opposite to each other, and the lower surface 300L of the second semiconductor chip 300 may face the first surface 100a of the upper substrate 100. The second semiconductor chip 300 may include a buffer semiconductor chip 310 and a plurality of sub-semiconductor chips 320 stacked on the buffer semiconductor chip 310 along a third direction D3. The buffer semiconductor chip 310 may include a buffer penetration electrode 315 that penetrates the buffer semiconductor chip 310 along the third direction D3. Each sub-semiconductor chip 320 may include a sub-penetration electrode 325 that penetrates each sub-semiconductor chip 320 along the third direction D3. The second semiconductor chip 300 may also include a sub-bump 330 that is disposed between the sub-semiconductor chips 320 and between the lowermost sub-semiconductor chip in the sub-semiconductor chips 320 and the buffer semiconductor chip 310. The sub-bump 330 may be connected (e.g., electrically connected) to the sub-penetration electrode 325 and the buffer penetration electrode 315. The buffer semiconductor chip 310 and the sub semiconductor chip 320 may be electrically connected to each other through the sub through-electrodes 325, the buffer through-electrodes 315, and the sub bumps 330. The second semiconductor chip 300 may be disposed on the buffer semiconductor chip 310, and may further include a chip mold layer 340 covering side surfaces of the sub semiconductor chip 320.

[0052] The second bumps 350 may be disposed on the lower surface 300L of the second semiconductor chip 300 and may be connected (e.g., electrically connected) to the buffer penetration electrodes 315. The second bumps 350 may be connected (e.g., electrically connected) to corresponding interconnection patterns 132 in the interconnection layer 130 of the upper substrate 100. The second semiconductor chip 300 may be electrically connected to the upper substrate 100 through the second bumps 350 and the corresponding interconnection patterns 132.

[0053] Reference Figure 5 and Figure 6 , a portion of the chip molding layer 340 of the second semiconductor chip 300 may be removed from the region between the first semiconductor chip 200 and the second semiconductor chip 300. The partial removal of the chip molding layer 340 may be performed using, for example, a laser process. Due to the partial removal of the chip molding layer 340, a trench T may be formed in the chip molding layer 340. The trench T may penetrate a portion of the chip molding layer 340 and extend along the first direction D1.

[0054] The upper side surface 340US and the lower side surface 340LS of the chip molding layer 340 may be defined by the trench T. The upper side surface 340US of the chip molding layer 340 may be recessed toward the inside of the chip molding layer 340 relative to the lower side surface 340LS of the chip molding layer 340, and thus the side surface 340LS or 340US of the chip molding layer 340 may have a stepped structure. The side surface 200S of the first semiconductor chip 200 may include an upper side surface 200US facing the upper side surface 340US of the chip molding layer 340 and a lower side surface 200LS facing the lower side surface 340LS of the chip molding layer 340. The upper side surface 200US of the first semiconductor chip 200 and the lower side surface 200LS of the first semiconductor chip 200 may be aligned with each other in the third direction D3.

[0055] In an embodiment, the depth T_D of the trench T in the third direction D3 may be in the range of 50 μm to 600 μm. The depth T_D of the trench T may correspond to the length of the upper side surface 340US of the chip molding layer 340 in the third direction D3. The width T_W of the trench T may be greater than or equal to 50 μm. The width T_W of the trench T may be measured in a direction parallel to the first surface 100a of the upper substrate 100 (e.g., the second direction D2). The upper side surface 340US of the chip molding layer 340 may be recessed by the width T_W of the trench T relative to the lower side surface 340LS of the chip molding layer 340.

[0056] Reference Figure 7 and Figure 8 , an upper underfill layer 400 may be formed between the upper substrate 100 and the first semiconductor chip 200 and between the upper substrate 100 and the second semiconductor chip 300. The upper underfill layer 400 may fill the space between the first bumps 230 and the space between the second bumps 350. The upper underfill layer 400 may extend into the space between the lower side surface 340LS of the chip molding layer 340 and the lower side surface 200LS of the first semiconductor chip 200 by capillary force.

[0057] Due to the trench T, the space between the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200 may be wider than the space between the lower side surface 340LS of the chip molding layer 340 and the lower side surface 200LS of the first semiconductor chip 200. Therefore, the upper underfill layer 400 may not extend into the space between the upper side surface 340US of the chip molding layer 340 and the upper side surface 200US of the first semiconductor chip 200. The uppermost surface 400U of the upper underfill layer 400 may be located at a lower height than the upper surface 200U of the first semiconductor chip 200 and the upper surface 300U of the second semiconductor chip 300.

[0058] Reference Fig. 9 and Fig.10 , an upper mold layer 500 may be formed on the upper substrate 100 to cover the side surfaces of the first semiconductor chip 200 and the second semiconductor chip 300. The upper mold layer 500 may extend into the space between the upper side surface 340US of the chip mold layer 340 and the upper side surface 200US of the first semiconductor chip 200, and may cover the uppermost surface 400U of the upper bottom filling layer 400. Forming the upper mold layer 500 may include: forming the upper mold layer 500 on the upper substrate 100 to cover the first semiconductor chip 200 and the second semiconductor chip 300; and grinding the upper mold layer 500 to expose the upper surface 200U of the first semiconductor chip 200 and the upper surface 300U of the second semiconductor chip 300. As a result of the grinding process, the upper surface 500U of the upper mold layer 500 may be located at the same height as the upper surface 200U of the first semiconductor chip 200 and the upper surface 300U of the second semiconductor chip 300.

[0059] Return to reference Figure 1 and Figure 2 , the carrier substrate 600 and the adhesive layer 610 may be removed from the upper substrate 100 to expose the connection terminals 140. Thus, the semiconductor package 1000 according to an embodiment of the inventive concept may be formed.

[0060] Fig.11 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept. Fig. 12A and Fig. 12B is along Fig.11 For the sake of simplicity, the following mainly describes the cross-sectional view taken along the line A-A'. Figure 1 and Figure 2 Different features of the semiconductor package are described, and it will be appreciated that where an element is not described in detail with reference to this figure, the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure.

[0061] Reference Fig.11 , Fig. 12A and Fig. 12B , the semiconductor package 1100 may include a lower substrate 700 , an upper substrate 100 on the lower substrate 700 , and a first semiconductor chip 200 and a second semiconductor chip 300 mounted on the upper substrate 100 .

[0062] The lower substrate 700 may include a first substrate pad 710 adjacent to an upper surface 700U of the lower substrate 700 and a second substrate pad 720 adjacent to a lower surface 700L of the lower substrate 700. The first substrate pad 710 and the second substrate pad 720 may include a conductive material. The first substrate pad 710 may be electrically connected to the second substrate pad 720 through internal wiring in the lower substrate 700. In an embodiment, the lower substrate 700 may be a printed circuit board (PCB). The external terminals 730 may be disposed on the lower surface 700L of the lower substrate 700 and may be connected to the second substrate pads 720, respectively.

[0063] The upper substrate 100 and the first and second semiconductor chips 200 and 300 may have the same Figure 1 and Figure 2 The upper substrate 100 and the first and second semiconductor chips 200 and 300 are described to have substantially the same features.

[0064] The connection terminals 140 may be disposed between the upper substrate 100 and the lower substrate 700, and may be connected (eg, electrically connected) to the first substrate pads 710 of the lower substrate 700, respectively. The connection terminals 140 may have a Figure 1 and Figure 2 The upper substrate 100 may be electrically connected to the lower substrate 700 through the connection terminal 140 .

[0065] The lower under-fill layer 740 may be disposed between the upper substrate 100 and the lower substrate 700 to fill the space between the connection terminals 140. The lower under-fill layer 740 may include an electrically insulating polymer material (eg, epoxy resin).

[0066] The first bump 230 may be disposed between the first semiconductor chip 200 and the upper substrate 100, and the first semiconductor chip 200 may be electrically connected to the upper substrate 100 through the first bump 230. The second bump 350 may be disposed between the second semiconductor chip 300 and the upper substrate 100, and the second semiconductor chip 300 may be electrically connected to the upper substrate 100 through the second bump 350. The first bump 230 and the second bump 350 may have the same Figure 1 and Figure 2 The first bump 230 and the second bump 350 are described as having substantially the same features.

[0067] The upper underfill layer 400 may be interposed between the upper substrate 100 and the first semiconductor chip 200 and between the upper substrate 100 and the second semiconductor chip 300, and may extend into the space between the first semiconductor chip 200 and the second semiconductor chip 300. The upper underfill layer 400 may extend into the space between the lower side surface 340LS of the chip molding layer 340 of the second semiconductor chip 300 and the lower side surface 200LS of the first semiconductor chip 200. The upper molding layer 500 may be disposed on the upper substrate 100 and may cover the side surfaces of the first semiconductor chip 200 and the second semiconductor chip 300. The upper molding layer 500 may extend into the space between the upper side surface 340US of the chip molding layer 340 of the second semiconductor chip 300 and the upper side surface 200US of the first semiconductor chip 200, and may cover the uppermost surface 400U of the upper underfill layer 400. The upper underfill layer 400 and the upper molding layer 500 may have the same Figure 1 and Figure 2 The upper under-fill layer 400 and the upper molding layer 500 are described to have substantially the same features.

[0068] In an embodiment, the semiconductor package 1100 may further include a heat dissipation structure 750 disposed on the lower substrate 700. Fig.11 and Fig. 12A The heat dissipation structure 750 may be disposed on the upper surface 700U of the lower substrate 700 and refer to Figure 1 and Figure 2 The semiconductor package 1000 described may be placed inside the heat dissipation structure 750. The heat dissipation structure 750 may include at least one thermally conductive material. The thermally conductive material may include a metal (e.g., copper and / or aluminum, etc.) or a carbon-containing material (e.g., graphene, graphite and / or carbon nanotubes, etc.). As an example, the heat dissipation structure 750 may include one or more metal layers. As another example, the heat dissipation structure 750 may include a radiator or a heat pipe. As another example, the heat dissipation structure 750 may have a water cooling structure.

[0069] In an embodiment, the semiconductor package 1100 may further include a reinforcement member 760 disposed on the lower substrate 700, such as Fig.11 and Fig. 12B The reinforcing member 760 may be disposed on the upper surface 700U of the lower substrate 700 and refer to Figure 1 and Figure 2 The described semiconductor package 1000 may be placed inside the stiffener 760. The stiffener 760 may include at least one metal.

[0070] Fig.13 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept. Fig.14 is along Fig.13A cross-sectional view taken along the line BB'. Fig.13 The cross-sectional view taken along the line A-A' can be compared with Figure 2 For the sake of simplicity, the following description will mainly be compared with the previous reference Figure 1 and Figure 2 Different features of the semiconductor package are described, and it will be appreciated that where an element is not described in detail with reference to this figure, the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure.

[0071] Reference Fig.13 and Fig.14 , the semiconductor package 1200 may include an upper substrate 100, and first semiconductor chips 200 and second semiconductor chips 300 disposed on the upper substrate 100 and horizontally spaced apart from each other. In an embodiment, a plurality of first semiconductor chips 200 may be mounted on the first surface 100a of the upper substrate 100, and may be spaced apart from each other in the first direction D1. A plurality of second semiconductor chips 300 may be mounted on the first surface 100a of the upper substrate 100, and may be disposed on both sides of each first semiconductor chip 200. The second semiconductor chips 300 may form a first column and a second column, wherein the second semiconductor chips 300 in the first column are spaced apart from each other in the first direction D1 on one side of each first semiconductor chip 200, and the second semiconductor chips 300 in the second column are spaced apart from each other in the first direction D1 on the opposite side of each first semiconductor chip 200.

[0072] The second semiconductor chip 300 may include a pair of second semiconductor chips 300 that are most adjacent to each other in the first direction D1. Each of the pair of second semiconductor chips 300 may include a buffer semiconductor chip 310 and a plurality of sub-semiconductor chips 320 stacked on the buffer semiconductor chip 310 along a third direction D3. The buffer semiconductor chip 310 may include a buffer penetration electrode 315 that penetrates the buffer semiconductor chip 310 along the third direction D3, and each sub-semiconductor chip 320 may include a sub-penetration electrode 325 that penetrates the sub-semiconductor chip 320 along the third direction D3, respectively. In an embodiment, the uppermost sub-semiconductor chip 320 may not include the sub-penetration electrode 325.

[0073] Each of the paired second semiconductor chips 300 may further include a sub-bump 330 disposed between the sub-semiconductor chips 320 and between the lowermost sub-semiconductor chip of the sub-semiconductor chips 320 and the buffer semiconductor chip 310. The sub-bump 330 may be connected (e.g., electrically connected) to the sub-through-electrodes 325 and the buffer through-electrodes 315. Each of the paired second semiconductor chips 300 may include a chip molding layer 340 disposed on the buffer semiconductor chip 310 and covering the side surface of the sub-semiconductor chip 320.

[0074] Reference Fig.13 and Figure 2 , the chip molding layer 340 of each of the paired second semiconductor chips 300 may have a first side surface 340LS1 or 340US1 facing the side surface 200S of the first semiconductor chip 200. The first side surface 340LS1 or 340US1 of the chip molding layer 340 may correspond to the reference Figure 2 The side surface 340LS or 340US of the chip molding layer 340 described above. The first side surface 340LS1 or 340US1 of the chip molding layer 340 may have a stepped structure. The first upper side surface 340US1 of the chip molding layer 340 may be recessed toward the inside of the chip molding layer 340 relative to the first lower side surface 340LS1 of the chip molding layer 340. The first upper side surface 340US1 and the first lower side surface 340LS1 of the chip molding layer 340 may correspond to the reference Figure 2 The chip molding layer 340 is depicted with an upper side surface 340US and a lower side surface 340LS.

[0075] Return to reference Fig.13 and Fig.14 , the chip mold layer 340 of each of the paired second semiconductor chips 300 may have second side surfaces 340LS2 and 340US2. The second side surface 340LS2 or 340US2 of the chip mold layer 340 in one of the paired second semiconductor chips 300 may face the second side surface 340LS2 or 340US2 of the chip mold layer 340 in the other of the paired second semiconductor chips 300.

[0076] The second side surface 340LS2 or 340US2 of the chip molding layer 340 may have a stepped structure. The second upper side surface 340US2 of the chip molding layer 340 may be recessed toward the inside of the chip molding layer 340 relative to the second lower side surface 340LS2 of the chip molding layer 340. The second upper side surface 340US2 of the chip molding layer 340 in one of the paired second semiconductor chips 300 may face the second upper side surface 340US2 of the chip molding layer 340 in the other of the paired second semiconductor chips 300. The second lower side surface 340LS2 of the chip molding layer 340 in one of the paired second semiconductor chips 300 may face the second lower side surface 340LS2 of the chip molding layer 340 in the other of the paired second semiconductor chips 300. A third distance DS3 between the second upper side surfaces 340US2 of the chip mold layers 340 of the pair of second semiconductor chips 300 may be greater than a fourth distance DS4 between the second lower side surfaces 340LS2 of the chip mold layers 340 of the pair of second semiconductor chips 300 .

[0077] The second bump 350 may be disposed between each of the paired second semiconductor chips 300 and the upper substrate 100, and may be connected (eg, electrically connected) to the buffer penetration electrode 315. Each of the paired second semiconductor chips 300 may be electrically connected to the upper substrate 100 through the second bump 350.

[0078] The upper bottom filling layer 400 may be interposed between each of the paired second semiconductor chips 300 and the upper substrate 100 to fill the space between the second bumps 350. The upper bottom filling layer 400 may extend into the space between the paired second semiconductor chips 300. The upper bottom filling layer 400 may extend into the space between the second lower side surfaces 340LS2 of the chip molding layers 340 of the paired second semiconductor chips 300, and may expose the second upper side surfaces 340US2 of the chip molding layers 340 of the paired second semiconductor chips 300. The uppermost surface 400U of the upper bottom filling layer 400 may be located at a height lower than the upper surface 300U of the paired second semiconductor chips 300.

[0079] The upper molding layer 500 may be disposed on the upper substrate 100 to cover the side surfaces of the pair of second semiconductor chips 300. The upper molding layer 500 may extend into the space between the second upper side surfaces 340US2 of the chip molding layers 340 of the pair of second semiconductor chips 300, and may cover the uppermost surface 400U of the upper bottom filling layer 400. The upper molding layer 500 may fill the space between the second upper side surfaces 340US2 of the chip molding layers 340 of the pair of second semiconductor chips 300, and directly contact the uppermost surface 400U of the upper bottom filling layer 400. The upper surface 500U of the upper molding layer 500 may be located at the same height as the upper surface 300U of the pair of second semiconductor chips 300. The upper surface 500U of the upper molding layer 500 may be coplanar with the upper surface 300U of the pair of second semiconductor chips 300.

[0080] In the case where the distance between the paired second semiconductor chips 300 is relatively small, the upper bottom filling layer 400 may be extended into the space between the paired second semiconductor chips 300 by capillary force, and may be extended to the same height as the upper surface 300U of the paired second semiconductor chips 300. Therefore, the upper bottom filling layer 400 may fill the space between the paired second semiconductor chips 300, and may be exposed to the outside of the semiconductor package 1200. In this case, since the upper bottom filling layer 400 has a relatively large thermal expansion coefficient, cracks may occur between the paired second semiconductor chips 300, and such cracks may spread into the semiconductor package 1200. In addition, a warpage failure may occur in the semiconductor package 1200.

[0081] According to an embodiment of the present inventive concept, the chip molding layer 340 of each of the pair of second semiconductor chips 300 may be partially removed from the region between the pair of second semiconductor chips 300. The second upper side surface 340US2 of the chip molding layer 340 may be recessed toward the inside of the chip molding layer 340 relative to the second lower side surface 340LS2 of the chip molding layer 340. The second side surface 340LS2 or 340US2 of the chip molding layer 340 may have a stepped structure. The third distance DS3 between the second upper side surfaces 340US2 of the chip molding layers 340 of the pair of second semiconductor chips 300 may be greater than the fourth distance DS4 between the second lower side surfaces 340LS2 of the chip molding layers 340 of the pair of second semiconductor chips 300. In this case, the upper bottom filling layer 400 may be extended into a relatively narrow space between the second lower side surfaces 340LS2 of the chip molding layers 340 of the pair of second semiconductor chips 300 by capillary force, but may not be extended into a relatively wide space between the second upper side surfaces 340US2 of the chip molding layers 340 of the pair of second semiconductor chips 300. The uppermost surface 400U of the upper bottom filling layer 400 may be located at a height lower than the upper surface 300U of the pair of second semiconductor chips 300. The upper molding layer 500 may fill the space between the second upper side surfaces 340US2 of the chip molding layers 340 of the pair of second semiconductor chips 300, and may cover the uppermost surface 400U of the upper bottom filling layer 400. Since the upper bottom filling layer 400 is covered by the upper molding layer 500, the upper bottom filling layer 400 may not be exposed to the outside of the semiconductor package 1200. Since the upper mold layer 500 has a smaller thermal expansion coefficient than the upper under-fill layer 400 , a crack failure between the pair of second semiconductor chips 300 may be reduced, and a warpage failure of the semiconductor package 1200 may also be reduced.

[0082] Since crack and warpage problems are suppressed, highly reliable semiconductor packaging can be achieved.

[0083] Fig.15 , Fig.17 , Fig.19 and Fig.21 is a plan view illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept. Fig.16 , Fig.18 , Fig. 20 and Fig. 22 Along Fig.15 , Fig.17 , Fig.19 and Fig.21 A cross-sectional view taken along the line BB'. Fig.15 , Fig.17 , Fig.19 and Fig.21 The cross-sectional views taken along the line A-A' can be respectively Figure 4 , Figure 6 , Figure 8 and Fig.10 For the sake of simplicity, the following will mainly describe the cross-sectional view shown in FIG. Figures 3 to 10 Different features of the manufacturing method are described, and it will be appreciated that where an element has not been described in detail with reference to this figure, the element is at least similar to a corresponding element that has been described elsewhere in the disclosure.

[0084] Reference Fig.15 and Fig.16 , an upper substrate 100 may be disposed on the carrier substrate 600, and an adhesive layer 610 may be disposed between the carrier substrate 600 and the upper substrate 100. The first semiconductor chip 200 and the second semiconductor chip 300 may be mounted on the first surface 100a of the upper substrate 100.

[0085] In an embodiment, a plurality of first semiconductor chips 200 may be mounted on the first surface 100a of the upper substrate 100, and the plurality of first semiconductor chips 200 may be spaced apart from each other in the first direction D1. A plurality of second semiconductor chips 300 may be mounted on the first surface 100a of the upper substrate 100, and the plurality of second semiconductor chips 300 may be disposed on both sides of each first semiconductor chip 200. The second semiconductor chips 300 may form a first column and a second column, wherein the second semiconductor chips 300 in the first column are spaced apart from each other in the first direction D1 on one side of each first semiconductor chip 200, and the second semiconductor chips 300 in the second column are spaced apart from each other in the first direction D1 on the opposite side of each first semiconductor chip 200.

[0086] The second semiconductor chips 300 may include a pair of second semiconductor chips 300 that are most adjacent to each other in the first direction D1. Each of the second semiconductor chips in the pair 300 may include a buffer semiconductor chip 310, a plurality of sub-semiconductor chips 320 stacked on the buffer semiconductor chip 310 along the third direction D3, and a chip molding layer 340 disposed on the buffer semiconductor chip 310 to cover the side surface of the buffer semiconductor chip 310. Each of the second semiconductor chips in the pair 300 may also include a sub-bump 330 disposed between the sub-semiconductor chips 320 and between the lowermost sub-semiconductor chip in the sub-semiconductor chips 320 and the buffer semiconductor chip 310.

[0087] A second bump 350 may be disposed between each of the paired second semiconductor chips 300 and the upper substrate 100, and the second bump 350 may be connected (e.g., electrically connected) to the buffer penetration electrode 315. Each of the paired second semiconductor chips 300 may be electrically connected to the upper substrate 100 through the second bump 350.

[0088] Reference Fig.17 and Fig.18 , a portion of the chip molding layer 340 of each of the paired second semiconductor chips 300 may be removed from an area between each of the paired second semiconductor chips 300 and the first semiconductor chip 200. In addition, another portion of the chip molding layer 340 of each of the paired second semiconductor chips 300 may be removed from an area between the paired second semiconductor chips 300. Partial removal of the chip molding layer 340 may be performed using, for example, a laser process. Since a portion of the chip molding layer 340 is removed, a trench T may be formed in the chip molding layer 340. The trench T may penetrate a portion of the chip molding layer 340 and extend along the first direction D1 and the second direction D2.

[0089] The chip molding layer 340 may have a first upper side surface 340US1, a first lower side surface 340LS1, a second upper side surface 340US2, and a second lower side surface 340LS2 defined by the trench T. The first upper side surface 340US1 of the chip molding layer 340 may be recessed toward the inside of the chip molding layer 340 relative to the first lower side surface 340LS1 of the chip molding layer 340, and thus the first side surface 340LS1 or 340US1 of the chip molding layer 340 may have a stepped structure. The first upper side surface 340US1 and the first lower side surface 340LS1 of the chip molding layer 340 may correspond to the reference Figure 6 The upper side surface 340US and the lower side surface 340LS of the chip molding layer 340 are described. The second upper side surface 340US2 of the chip molding layer 340 may be recessed toward the inside of the chip molding layer 340 relative to the second lower side surface 340LS2 of the chip molding layer 340, so the second side surface 340LS2 or 340US2 of the chip molding layer 340 may have a stepped structure.

[0090] Reference Fig.19 and Fig. 20, an upper bottom filling layer 400 may be formed between each second semiconductor chip in the pair of second semiconductor chips 300 and the upper substrate 100. The upper bottom filling layer 400 may fill the space between the second bumps 350. The upper bottom filling layer 400 may extend into the space between the pair of second semiconductor chips 300 by capillary force. The upper bottom filling layer 400 may extend into the space between the second lower side surfaces 340LS2 of the chip molding layer 340 of the pair of second semiconductor chips 300.

[0091] Due to the trench T, the space between the second upper side surfaces 340US2 of the chip molding layers 340 of the pair of second semiconductor chips 300 may be larger than the space between the second lower side surfaces 340LS2 of the chip molding layers 340 of the pair of second semiconductor chips 300. Therefore, the upper underfill layer 400 may not extend into the space between the second upper side surfaces 340US2 of the chip molding layers 340 of the pair of second semiconductor chips 300. The uppermost surface 400U of the upper underfill layer 400 may be located at a height lower than the upper surface 300U of the pair of second semiconductor chips 300.

[0092] Reference Fig.21 and Fig. 22 , an upper molding layer 500 may be formed on the upper substrate 100 to cover the side surfaces of the pair of second semiconductor chips 300. The upper molding layer 500 may extend into the space between the second upper side surfaces 340US2 of the chip molding layers 340 of the pair of second semiconductor chips 300, and may cover the uppermost surface 400U of the upper bottom filling layer 400. Forming the upper molding layer 500 may include: forming the upper molding layer 500 to cover the pair of second semiconductor chips 300; and grinding the upper molding layer 500 to expose the upper surfaces 300U of the pair of second semiconductor chips 300. As a result of the grinding process, the upper surface 500U of the upper molding layer 500 may be located at the same height as the upper surface 300U of the pair of second semiconductor chips 300.

[0093] Return to reference Fig.13 and Fig.14 , the carrier substrate 600 and the adhesive layer 610 may be removed from the upper substrate 100, and the connection terminals 140 may be exposed. Thus, the semiconductor package 1200 according to an embodiment of the inventive concept may be formed.

[0094] Fig.23 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept. Fig.24 is along Fig.23 A cross-sectional view taken along the line BB'. Fig.23 The cross-sectional view taken along the line A-A' can be compared with Fig. 12AFor the sake of simplicity, the following description will mainly be compared with the previous reference Fig.11 , Fig. 12A and Fig. 12B Different features of the semiconductor package are described, and it will be appreciated that where an element is not described in detail with reference to this figure, the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure.

[0095] Reference Fig.23 and Fig.24 , the semiconductor package 1300 may include a lower substrate 700 and a heat dissipation structure 750 disposed on the lower substrate 700. Fig.13 and Fig.14 The described semiconductor package 1200 may be mounted on the lower substrate 700 and may be disposed in the heat dissipation structure 750 .

[0096] The lower substrate 700 may include a first substrate pad 710 adjacent to the upper surface 700U of the lower substrate 700 and a second substrate pad 720 adjacent to the lower surface 700L of the lower substrate 700. In an embodiment, the lower substrate 700 may be a printed circuit board (PCB). The external terminals 730 may be disposed on the lower surface 700L of the lower substrate 700 and may be connected to the second substrate pads 720, respectively.

[0097] The connection terminals 140 may be disposed between the upper substrate 100 and the lower substrate 700, and may be respectively connected (e.g., electrically connected) to the first substrate pads 710 of the lower substrate 700. The upper substrate 100 may be electrically connected to the lower substrate 700 through the connection terminals 140. A lower bottom filling layer 740 may be disposed between the upper substrate 100 and the lower substrate 700 to fill the space between the connection terminals 140.

[0098] The heat dissipation structure 750 may have the same Fig.11 and Fig. 12A The heat dissipation structure 750 described above has substantially the same features. Fig.11 and Fig. 12B The reinforcing member 760 described above may be disposed on the lower substrate 700 and refer to Fig.13 and Fig.14 The described semiconductor package 1200 may be disposed in the stiffener 760 .

[0099] According to an embodiment of the present invention, the chip molding layer of the second semiconductor chip can be partially removed, so the upper side surface of the chip molding layer can be recessed toward the inside of the chip molding layer relative to the lower side surface of the chip molding layer. The first distance between the upper side surface of the chip molding layer and the upper side surface of the first semiconductor chip can be greater than the second distance between the lower side surface of the chip molding layer and the lower side surface of the first semiconductor chip. In this case, the upper bottom filling layer can be extended into a relatively small space between the lower side surface of the chip molding layer and the lower side surface of the first semiconductor chip by capillary force, but may not extend into a relatively large space between the upper side surface of the chip molding layer and the upper side surface of the first semiconductor chip. The upper molding layer can fill the space between the upper side surface of the chip molding layer and the upper side surface of the first semiconductor chip, and can cover the uppermost surface of the upper bottom filling layer. Since the upper bottom filling layer is covered by the upper molding layer, the upper bottom filling layer may not be exposed to the outside of the semiconductor package. Since the thermal expansion coefficient of the upper molding layer is smaller than that of the upper under-fill layer, crack and warpage problems in the semiconductor package can be suppressed.

[0100] Since crack and warpage problems are suppressed, a highly reliable semiconductor package and a method for manufacturing the same can be realized.

[0101] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: A first semiconductor chip and a second semiconductor chip are disposed on the upper substrate and horizontally spaced apart from each other; an upper bottom filling layer, interposed between the upper substrate and the first semiconductor chip and between the upper substrate and the second semiconductor chip; as well as an upper molding layer disposed on the upper substrate and covering side surfaces of the first semiconductor chip and the second semiconductor chip, Wherein, the second semiconductor chip comprises: sub-semiconductor chips stacked in a vertical direction perpendicular to the upper surface of the upper substrate; and a chip molding layer, covering the side surface of the sub-semiconductor chip, The upper bottom filling layer extends into a space between a lower side surface of the chip molding layer and a lower side surface of the first semiconductor chip. The upper molding layer extends into a space between an upper side surface of the chip molding layer and an upper side surface of the first semiconductor chip, and covers an uppermost surface of the upper bottom filling layer, and Wherein, relative to the lower side surface of the chip molding layer, the upper side surface of the chip molding layer is recessed toward the inside of the chip molding layer.

2. The semiconductor package according to claim 1, wherein A first distance between an upper side surface of the chip mold layer and an upper side surface of the first semiconductor chip is greater than a second distance between a lower side surface of the chip mold layer and a lower side surface of the first semiconductor chip.

3. The semiconductor package according to claim 2, wherein: An upper side surface of the first semiconductor chip and a lower side surface of the first semiconductor chip are aligned with each other in the vertical direction.

4. The semiconductor package according to claim 1, wherein: The upper molding layer has a thermal expansion coefficient that is smaller than a thermal expansion coefficient of the upper under-filling layer.

5. The semiconductor package according to claim 1, wherein The mass of filler in the upper molding layer is greater than the mass of filler in the upper bottom filling layer.

6. The semiconductor package according to claim 1, wherein The volume of the filler in the upper molding layer is greater than the volume of the filler in the upper bottom filling layer.

7. The semiconductor package according to claim 1, wherein: The upper substrate has a first surface and a second surface opposite to each other, Wherein, the upper substrate comprises: an interconnect layer, adjacent to the first surface, the interconnect layer comprising an interconnect pattern; a semiconductor substrate adjacent to the second surface; and a plurality of penetration electrodes penetrating the semiconductor substrate and connected to corresponding interconnection patterns, and The first semiconductor chip and the second semiconductor chip are disposed on the first surface of the upper substrate and are connected to corresponding interconnection patterns in the interconnection layer. 8 . The semiconductor package according to claim 7 , further comprising a connection terminal provided on the second surface of the upper substrate and connected to the penetration electrode.

9. The semiconductor package according to claim 8, further comprising a lower substrate spaced apart from the second surface of the upper substrate with the connection terminal interposed therebetween, in, The upper substrate is electrically connected to the lower substrate through the connection terminals.

10. The semiconductor package according to claim 1, wherein The first semiconductor chip and the second semiconductor chip are two different semiconductor chips selected from a memory chip, a logic chip, an application processor AP chip, and a system on chip SOC.

11. A semiconductor package, comprising: A first semiconductor chip and a second semiconductor chip are disposed on the upper substrate and horizontally spaced apart from each other; an upper bottom filling layer, interposed between the upper substrate and the first semiconductor chip and between the upper substrate and the second semiconductor chip; as well as an upper molding layer, disposed between the first semiconductor chip and the second semiconductor chip, Wherein, the second semiconductor chip comprises: at least one semiconductor sub-chip; and a chip molding layer, covering the side surface of the at least one sub-semiconductor chip, wherein the lower side surface of the chip molding layer faces the lower side surface of the first semiconductor chip, wherein the upper side surface of the chip molding layer faces the upper side surface of the first semiconductor chip, Wherein, relative to the lower side surface of the chip molding layer, the upper side surface of the chip molding layer is recessed toward the inside of the chip molding layer, The upper bottom filling layer extends into a space between a lower side surface of the chip molding layer and a lower side surface of the first semiconductor chip. The uppermost surface of the upper bottom filling layer is located at a height lower than the upper surfaces of the first semiconductor chip and the second semiconductor chip, and The upper molding layer fills the space between the upper side surface of the chip molding layer and the upper side surface of the first semiconductor chip, and covers the uppermost surface of the upper bottom filling layer.

12. The semiconductor package according to claim 11, wherein A first distance between an upper side surface of the chip mold layer and an upper side surface of the first semiconductor chip is greater than a second distance between a lower side surface of the chip mold layer and a lower side surface of the first semiconductor chip.

13. The semiconductor package according to claim 11, wherein The upper under-fill layer exposes an upper side surface of the chip molding layer and an upper side surface of the first semiconductor chip.

14. The semiconductor package according to claim 11, wherein An upper side surface of the first semiconductor chip and a lower side surface of the first semiconductor chip are aligned with each other in a vertical direction perpendicular to an upper surface of the upper substrate.

15. The semiconductor package according to claim 11, wherein The upper molding layer has a lower thermal expansion coefficient than the upper under-fill layer.

16. The semiconductor package according to claim 11, wherein The mass of filler in the upper molding layer is greater than the mass of filler in the upper bottom filling layer.

17. The semiconductor package according to claim 11, wherein Each of the upper molding layer and the chip molding layer includes epoxy molding compound.

18. The semiconductor package according to claim 11, wherein The upper substrate is an interposer substrate, and The first semiconductor chip and the second semiconductor chip are two different semiconductor chips selected from a memory chip, a logic chip, an application processor AP chip and a system on chip SOC.

19. The semiconductor package according to claim 18, wherein: The second semiconductor chip includes a plurality of sub-semiconductor chips stacked in a vertical direction perpendicular to an upper surface of the upper substrate, and The chip molding layer covers the side surface of the sub-semiconductor chip.

20. The semiconductor package according to claim 11, wherein The upper substrate has a first surface and a second surface opposite to each other, Wherein, the upper substrate comprises: an interconnect layer, adjacent to the first surface, the interconnect layer comprising an interconnect pattern; a semiconductor substrate adjacent to the second surface; and a plurality of penetration electrodes penetrating the semiconductor substrate and connected to corresponding interconnection patterns, The first semiconductor chip and the second semiconductor chip are disposed on the first surface of the upper substrate and are electrically connected to corresponding interconnection patterns in the interconnection layer.

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