Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a substrate, a memory component and a heat dissipation component, the memory component is arranged on the substrate. The heat dissipation assembly is arranged on the substrate. The heat dissipation assembly has a thermal conductivity greater than a thermal conductivity of silicon.

Description

Technical Field

[0001] The invention relates to a semiconductor device. Background Art

[0002] The front side (wafer front-end line, FEOL / back-end line, BEOL side) of ultra-thin memory, such as cache memory, SRAM (static random access memory), NAND or DRAM, and multiple dummy silicon chips are bonded to the back side of an ultra-thin, high-power processor (e.g., 100W or more per chip) with a front-end power delivery network using copper hybrid bonding involving oxide-to-oxide direct bonding. The processor with the memory mounted is bonded to a substrate. The substrate is mounted on a socket for electrical connection. However, the heat generated by a relatively high-power processor (e.g., 100W) may cause processor blistering / delamination / cracking failures because the heat generated by the processor is difficult to dissipate through the oxide layer where the memory (e.g., cache) is bonded to the processor. Summary of the invention

[0003] The present invention relates to a semiconductor device which can improve the above-mentioned known problems.

[0004] First embodiment: A semiconductor device includes a substrate, a memory component and a heat dissipation component. The memory component is disposed on the substrate. The heat dissipation component is disposed on the substrate. The heat dissipation component has a thermal conductivity greater than the thermal conductivity of silicon.

[0005] A second embodiment based on the first embodiment: the heat dissipation component is formed of a material including diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, metal or a combination thereof.

[0006] A third embodiment based on the first embodiment: the memory component and the heat dissipation component are arranged side by side.

[0007] A fourth embodiment based on the first embodiment: the semiconductor device further comprises a plurality of heat dissipation components, and the memory component is disposed between the heat dissipation components.

[0008] A fifth embodiment based on the first embodiment: the semiconductor device further comprises a plurality of the memory components, and the heat dissipation component is disposed between the memory components.

[0009] A sixth embodiment based on the first embodiment: the semiconductor device further comprises a molding compound. The molding compound is disposed between the heat dissipation component and the memory component.

[0010] A seventh embodiment based on the first embodiment: the semiconductor device further comprises a plurality of heat dissipation components and a molding compound, wherein the molding compound is disposed between the heat dissipation components.

[0011] An eighth embodiment based on the first embodiment: the semiconductor device further comprises a plurality of memory components and a molding compound, wherein the molding compound is disposed between the memory components.

[0012] A ninth embodiment based on the first embodiment: The semiconductor device further includes a heat sink, a cooling component, and a fan and / or a heat exchanger. The heat sink includes a vapor chamber, covers the memory component and the heat dissipation component, and has an upper surface. The cooling component is disposed on the upper surface of the heat sink and has a fluid channel. The fan and / or a heat exchanger are thermally coupled to the cooling component.

[0013] A tenth embodiment based on the ninth embodiment: the semiconductor device further comprises a molding compound. The molding compound is located on a side surface of the heat dissipation component and has a side surface. The side surface of the molding compound is flush with a side surface of the substrate.

[0014] An eleventh embodiment based on the first embodiment: The semiconductor device further includes a power rail layer, a power supply layer, and an intermediate layer. The power supply layer is connected to the power rail layer. The intermediate layer is disposed adjacent to the source supply layer and is thermally coupled to the power supply layer, wherein the intermediate layer is formed of a material including diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, metal, or a combination thereof.

[0015] A twelfth embodiment based on the first embodiment: the substrate includes a back-end-of-line (BEOL) structure and a thermal isolation structure. The thermal isolation structure is disposed on or within the BEOL structure.

[0016] A thirteenth embodiment based on the first embodiment: the substrate includes a back-end process structure and a heat spreading structure. The heat spreading structure is disposed on or inside the back-end process structure.

[0017] A fourteenth embodiment based on the first embodiment: The substrate includes a processor core, a cache memory, and a thermal metamaterial structure. The cache memory is disposed adjacent to the processor core. The thermal metamaterial structure is disposed between the processor core and the cache memory, and between the cache memory and the memory component, to respectively minimize thermal cross-talk between the processor core and the cache memory, and between the cache memory and the memory component.

[0018] A fifteenth embodiment based on the fourteenth embodiment: The thermal metamaterial structure includes a first layer, a second layer, and a third layer. The first layer has a first thermal conductivity. The second layer has a second thermal conductivity and surrounds the first layer. The third layer has a third thermal conductivity and surrounds the second layer. The second thermal conductivity is greater than the first thermal conductivity, and the first thermal conductivity is greater than the third thermal conductivity.

[0019] A sixteenth embodiment based on the fifteenth embodiment: the first layer is formed of silicon, the second layer is formed of graphene, and the third layer is formed of silicon dioxide.

[0020] A seventeenth embodiment based on the sixteenth embodiment: The semiconductor device is mounted on a high thermal conductivity (HTC) and low thermal expansion coefficient (LCTE) substrate.

[0021] An eighteenth embodiment based on the first embodiment: the substrate includes a front-end process structure and a heat insulation structure. The heat insulation structure is disposed on and / or in the front-end process structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 FIG. 1 is a schematic diagram of a semiconductor device 10 according to an embodiment of the present invention.

[0024] Figure 2 FIG. 2 is a schematic diagram of a semiconductor device 20 according to another embodiment of the present invention.

[0025] Figure 3A FIG. 1 is a schematic diagram of a semiconductor device 30 according to another embodiment of the present invention.

[0026] Figure 3B Show Figure 3A A cross-sectional view of the semiconductor device 30 along a direction 3B- 3B′.

[0027] Figure 4A FIG. 4 is a schematic diagram of a semiconductor device 40 according to another embodiment of the present invention.

[0028] Figure 4B Show Figure 4A A cross-sectional view of the semiconductor device 40 along a direction 4B- 4B′.

[0029] Figure 5 FIG. 5 is a schematic diagram of a semiconductor device 50 according to another embodiment of the present invention.

[0030] Fig. 6A FIG. 6 is a schematic diagram of a semiconductor device 60 according to another embodiment of the present invention.

[0031] Figure 6B Show Fig. 6A Schematic diagram of a substrate 610 of a semiconductor device 60.

[0032] Figure 7 FIG. 7 is a schematic diagram of a semiconductor device 70 according to another embodiment of the present invention.

[0033] Figure 8 FIG. 8 is a schematic diagram of a semiconductor device 80 according to another embodiment of the present invention.

[0034] Fig. 9 Show Figure 1 Schematic diagram of a silicon base 111 of a substrate 110.

[0035] Fig. 10A A schematic diagram of a substrate 910A according to another embodiment of the present invention is shown.

[0036] Fig. 10B A schematic diagram of a substrate 910B according to another embodiment of the present invention is shown.

[0037] Fig. 10C A schematic diagram of a substrate 910C according to another embodiment of the present invention is shown.

[0038] Fig. 10D A schematic diagram of a substrate 910D according to another embodiment of the present invention is shown.

[0039] Figures 11A to 11G Show Figure 1 FIG. 1 is a diagram of a manufacturing process of a semiconductor chip 100 .

[0040] Figures 12A to 12L Show Figure 6B FIG. 6 is a diagram showing a manufacturing process of the first substrate 610 .

[0041] Figures 13A to 13C FIG. 5 is a diagram showing a manufacturing process of a diamond layer DL according to an embodiment of the present invention.

[0042] Figures 14A to 14I FIG. 5 is a diagram showing a manufacturing process of a diamond layer DL according to another embodiment of the present invention.

[0043] Figures 15A to 15H FIG. 5 is a diagram showing a manufacturing process of a diamond layer DL according to another embodiment of the present invention.

[0044] Reference numerals:

[0045] 1:Substrate

[0046] 1A: Adhesion layer

[0047] 10,20,30,40,50,60,70,80:Semiconductor devices

[0048] 11,31: First substrate

[0049] 11A, 31A: Grid array pads

[0050] 12: Second substrate

[0051] 12A: Pin

[0052] 13: Electrical contacts

[0053] 14: Primer

[0054] 21: Radiator

[0055] 21u: upper surface

[0056] 22: First adhesive layer

[0057] 23: Second adhesive layer

[0058] 24: First cooling component

[0059] 24a: Fluid channel

[0060] 25: Second cooling component

[0061] 26: The third adhesive layer

[0062] 100,300,400,500,600,700,800:Semiconductor chips

[0063] 110,910A,910B:Substrate

[0064] 110s,130s,140s,320s,610s: side surface

[0065] 111,911:Silicon substrate

[0066] 111A: Processor core

[0067] 111B: Level 3 cache

[0068] 111C: Thermal metamaterial structures

[0069] 111C1: First floor

[0070] 111C2: Second floor

[0071] 111C3: Third floor

[0072] 112,912: Front-end process layer

[0073] 113,913: Back-end process layer

[0074] 114: first conductive contact

[0075] 115,125,912D,913B: Conductive holes

[0076] 116: second conductive contact

[0077] 117,127,321,912C,913A,L4,L5: Dielectric layer

[0078] 120,320,520,720,820: memory components

[0079] 121:Silicon substrate

[0080] 122: Front-end process layer

[0081] 123: Back-end process layer

[0082] 124: first conductive contact

[0083] 126: second conductive contact

[0084] 130: Heat dissipation component

[0085] 140:Molding compound

[0086] C1: Coolant

[0087] 322,618A,619B: Conductive pads

[0088] 528: first dielectric layer

[0089] 529: Second dielectric layer

[0090] 527: High thermal conductivity layer

[0091] 613,617A,619A,619D,619: Heavy cloth layer

[0092] P1: Power rail

[0093] 614: first conductive hole

[0094] 615: second conductive hole

[0095] 616: Power supply routing

[0096] 619: Intermediary layer

[0097] 619C: Diamond layer

[0098] 619E: Diamond Through Hole

[0099] 728: Thermal insulation layer

[0100] 829: Thermal vias

[0101] 914A,914B,914C,914D: Thermal parts

[0102] 912A,912B: Transistor

[0103] C1: First carrier

[0104] C2: Second carrier

[0105] C3: First silicon substrate

[0106] C4: Second silicon substrate

[0107] C5: Temporary carrier

[0108] DL: Diamond Layer

[0109] DP: Diamond Particles

[0110] DM: Diamond Material

[0111] DMu,S1u: Upper surface

[0112] L1: Buffer stop layer

[0113] L2: Silicon cap

[0114] L3: Silicon layer

[0115] L4: Silicon dioxide layer

[0116] M1a: Open

[0117] M1,M2,M3: Photomask

[0118] M2a, M3a: Through hole

[0119] R1, R2: Release film

[0120] S1: Silicon substrate

[0121] S1a: Depression

[0122] SD:Silicon dioxide

[0123] SL': Seed layer material

[0124] SL:Seed layer

[0125] t1: thickness

[0126] W1: Length DETAILED DESCRIPTION

[0127] Please refer to Figure 1 , which shows a schematic diagram of a semiconductor device 10 according to an embodiment of the present invention. The semiconductor device 10 includes a semiconductor chip 100, a first substrate 11, a second substrate 12, at least one electrical contact 13, and a packaging material such as an underfill 14 (which may also be a non-conductive paste or film). The semiconductor chip 100 is disposed on the first substrate 11 through a plurality of electrical contacts 13 such as solder balls. The underfill 14 is disposed between the semiconductor chip 100 and the first substrate 11 and covers the electrical contacts 13. The first substrate 11 is disposed between the second substrate 12 and the semiconductor chip 100. The first substrate 11 includes at least one Land Grid Array (LGA) pad 11A, and the second substrate 12 includes at least one pin 12A, wherein the first substrate 11 and the second substrate 12 are electrically connected to the Land Grid Array pad 11A through the pin 12A. In another embodiment, the first substrate 11 and the second substrate may be connected through a plurality of solder balls such as Ball Grid Array (BGA) balls. This also applies to other similar structures disclosed herein, which will not be repeated for the sake of brevity.

[0128] In one embodiment, the first substrate 11 is, for example, a laminate substrate. The electrical contacts 13 are, for example, solder balls, conductive copper pillars, micro-bumps, etc. The second substrate 12 is, for example, a printed circuit board (PCB).

[0129] like Figure 1 As shown, the semiconductor chip 100 includes a substrate 110, at least one memory component 120, at least one heat dissipation component 130, and a molding compound 140. The heat dissipation component 130 is disposed on the substrate 110. The heat dissipation component 130 has a thermal conductivity greater than the thermal conductivity of silicon. Therefore, the heat dissipation component 130 can quickly conduct heat to the outside of the semiconductor device 10.

[0130] like Figure 1As shown, the substrate 110 includes a silicon base 111, a front-end-of-line (FEOL) layer 112, a back-end-of-line (BEOL) layer 113, a plurality of first conductive contacts 114, a plurality of conductive vias 115, a plurality of second conductive contacts 116, and a dielectric layer 117. In one embodiment, the substrate 110 is, for example, a central processing unit (CPU), for example, having at least one core and at least one cache memory (e.g., a level 3 cache (L3 catch)). In one embodiment, the substrate 110 is, for example, an ultra-thin CPU (only ~30 microns thick), and the effective thermal conductivity of its ultra-thin silicon is much lower than that of bulk Si (~140W / mK). In another embodiment, the substrate 11 can be, for example, another memory component. The structures disclosed herein are particularly suitable for the integration of "ultra-thin" devices such as static random-access memory (SRAM) or logic that may be low-power devices or high-power devices in "ultra-thin" high-power logic.

[0131] like Figure 1 As shown, the silicon substrate 111 is, for example, a portion of a silicon wafer. At least one processor core 111A and at least one L3 cache 111B are formed in the silicon substrate 111. In this embodiment, the heat generated by the processor core 111A can be quickly conducted through the heat dissipation assembly 130. The front-end process layer 112 is formed on the silicon substrate 111. The back-end process layer 113 is formed on the front-end process layer 112 and includes a first conductive contact 114 formed in the back-end process layer 113. The conductive via 115 connects the second conductive contact 116 with the first conductive contact 114.

[0132] like Figure 1 As shown, the memory component 120 and the heat dissipation component 130 can be arranged side by side. The memory component 120 includes a silicon substrate 121, a front-end process layer 122, a back-end process layer 123, a plurality of first conductive contacts 124, a plurality of conductive vias 125, a plurality of second conductive contacts 126 and a dielectric layer 127. The memory component 120 is, for example, a static random access memory.

[0133] like Figure 1As shown, the silicon substrate 121 is, for example, a portion of a silicon wafer. A front-end process layer 122 is formed on the silicon substrate 121 and includes at least one memory cell (not shown). A back-end process layer 123 is formed on the front-end process layer 122 and includes a first conductive contact 124 formed in the back-end process layer 123. A dielectric layer 127 is formed on the back-end process layer 123. A conductive via 125 and a second conductive contact 126 are formed in the dielectric layer 127, wherein the conductive via 125 connects the second conductive contact 126 to the first conductive contact 124.

[0134] In this embodiment, the memory component 120 and the substrate 110 are connected to each other. For example, the memory component 120 and the substrate 110 are directly connected to each other. By means of copper hybrid bonding technology, the second conductive contact 116 of the substrate 110 and the second conductive contact 126 of the memory component 120 can be directly connected to each other, and the dielectric layer 117 of the substrate 110 and the dielectric layer 127 of the memory component 120 can be directly connected to each other.

[0135] In one embodiment, the heat dissipation element 130 may be made of a high thermal conductivity (High TC) and low coefficient-of-thermal-expansion material, such as diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, a suitable HTC and LCTE material such as a composite metal (e.g., copper / invar / copper), or a combination thereof. The heat dissipation element 130 may be formed of diamond of different thicknesses by high-quality microwave plasma chemical vapor deposition (MPCVD) technology or other suitable methods. In one embodiment, the thermal conductivity (TC) of diamond may be as high as 2400 W / m·K.

[0136] like Figure 1 As shown, the heat dissipation component 130 can be directly configured (or bonded) on the silicon substrate 111 of the substrate 110. In another embodiment, the heat dissipation component 130 can be configured on the silicon substrate 111 of the substrate 110 through an oxide layer (not shown) using, for example, an oxide bonding technique, wherein the oxide layer is disposed between the heat dissipation component 130 and the silicon substrate 111 of the substrate 110.

[0137] like Figure 1As shown, the molding compound 140 is formed between the memory component 120 and the heat dissipation component 130, and covers the side surface 130s of each heat dissipation component 130. The molding compound 140 can be a novolac-based resin, an epoxy-based resin, a silicone-based resin, or other suitable encapsulants. The molding compound 140 can also include a suitable filler, such as powdered silicon dioxide. The molding compound 140 can be formed using several packaging techniques, such as compression molding, liquid encapsulation, injection molding, or transfer molding. In addition, the molding compound 140 has a side surface 140s, and the substrate 110 has a side surface 110s, wherein the side surface 140s of the molding compound 140 and the side surface 110s of the substrate 110 are flush with each other.

[0138] Please refer to Figure 2 , which shows a schematic diagram of a semiconductor device 20 according to another embodiment of the present invention. The semiconductor device 20 includes a semiconductor chip 100, a first substrate 11, a second substrate 12, at least one electrical contact 13, an underfill 14, a heat spreader 21, a first adhesive layer 22, a second adhesive layer 23, a first cooling element 24, a second cooling element 25 and a third adhesive layer 26.

[0139] The semiconductor device 20 includes the same or similar features as the semiconductor device 10 , with at least one difference being that the semiconductor device 20 further includes a heat sink 21 , a first adhesive layer 22 , a second adhesive layer 23 , a first cooling element 24 , a second cooling element 25 and a third adhesive layer 26 .

[0140] like Figure 2As shown, the heat sink 21 includes a vapor chamber (or a structure made of a high TC material such as diamond or a high TC material and a vapor chamber), which covers the memory component 120 and the heat sink component 130 and has an upper surface 21u. In addition, the memory component 120 and the heat sink component 130 are configured in the vapor chamber. The first cooling component 24 is configured on the upper surface 21u of the heat sink 21 and has a fluid channel 24a. The heat sink 21 is configured on the first substrate 11 through the first adhesive layer 22, wherein the first adhesive layer 22 is configured between the heat sink 21 and the first substrate 11. The heat sink 21 is configured on the semiconductor chip 100 through the second adhesive layer 23, wherein the second adhesive layer 23 is configured between the heat sink 21 and the semiconductor chip 100. The first cooling component 24 is configured on the heat sink 21 and thermally coupled to the second cooling component 25, wherein the second cooling component 25 is set between the first cooling component 24 and an external heat exchanger. In one embodiment, the first adhesive layer 22, the second adhesive layer 23 and the third adhesive layer 26 may be formed of, for example, a high-TC thermal interface material (TIM) or an appropriate high-TC material. In one embodiment, the second cooling assembly 25 includes, for example, a fan, a heat exchanger, a direct-to-chip liquid cooling device, a direct-to-chip cooling device, a liquid immersion cooling device, or a combination thereof. Similar descriptions may also be used for other similar structures, and for the sake of brevity, they are not repeated.

[0141] In another embodiment, the semiconductor device 20 further includes a high TC plate (not shown) disposed between the third adhesive layer 26 and the heat sink 21 .

[0142] like Figure 2 As shown, the semiconductor chip 100 includes a substrate 110, at least one memory component 120, at least one heat dissipation component 130 and a molding compound 140. The memory component 120 is disposed on the substrate 110. The heat dissipation component 130 is disposed on the substrate 110. The heat dissipation component 130 is disposed on the substrate 110. The heat dissipation component 130 has a thermal conductivity greater than the thermal conductivity of silicon. In this way, the heat dissipation component 130 can quickly conduct heat to the outside of the semiconductor device 20.

[0143] like Figure 2As shown, the substrate 110 includes a silicon substrate 111, a front-end process layer 112, a back-end process layer 113, a plurality of first conductive contacts 114, a plurality of conductive holes 115, a plurality of second conductive contacts 116 and a dielectric layer 117. The silicon substrate 111 is, for example, a portion of a silicon wafer. At least one processor core 111A and at least one third-level cache 111B are formed in the silicon substrate 111. In this embodiment, the heat generated by the processor core 111A can be quickly conducted through the heat dissipation component 130. The heat generated by the processor core 111A can be quickly conducted to the first cooling component 24 through the heat dissipation component 130 and the heat sink 21. The heat can be conducted to the coolant C1 in the fluid channel 24a and transferred to the outside of the semiconductor device 20 through the coolant C1.

[0144] Please refer to Figures 3A and 3B. Figure 3A FIG. 1 is a schematic diagram showing a semiconductor device 30 according to another embodiment of the present invention. Figure 3B Show Figure 3A A cross-sectional view of the semiconductor device 30 along a direction 3B- 3B′.

[0145] like Figure 3B As shown, the semiconductor device 30 includes a semiconductor chip 300, a first substrate 31, a second substrate 12, at least one electrical contact 13 and an underfill 14. The semiconductor chip 300 is disposed on the first substrate 31 through a plurality of electrical contacts 13. The underfill 14 is disposed between the semiconductor chip 300 and the first substrate 31 and covers the electrical contacts 13. The first substrate 31 is disposed between the second substrate 12 and the semiconductor chip 300. The first substrate 11 includes at least one grid array pad 31A, and the second substrate 12 includes at least one pin 12A, wherein the first substrate 31 and the second substrate 12 are electrically connected through the pin 12A and the grid array pad 31A. In another embodiment, the first substrate 31 is, for example, an interposer, such as a silicon interposer, a glass interposer, a glass substrate, an interposer of a high TC material or a combination thereof. In another embodiment, the first substrate can be a combination of an interposer and a laminate substrate.

[0146] like Figure 3B As shown, the semiconductor chip 300 includes a substrate 110, at least one memory component 320, at least one heat dissipation component 130 and a molding compound 140. The memory component 320 is disposed on the substrate 110. The heat dissipation component 130 is disposed on the substrate 110. The heat dissipation component 130 has a thermal conductivity greater than the thermal conductivity of silicon. In this way, the heat dissipation component 130 can quickly conduct heat to the outside of the semiconductor device 30.

[0147] like Figure 3BAs shown, in this embodiment, at least one heat dissipation element 130 is disposed between a plurality of memory elements 320. A molding compound 140 is formed between the memory elements 320 and the heat dissipation element 130 and covers a side surface 320s of each memory element 320.

[0148] like Figure 3B As shown, each memory component 320 is, for example, a high-bandwidth-memory (HBM) DRAM stack or a chip stack structure including memory functions (or both memory and logic functions). The memory component 320 includes at least a dielectric layer 321 and at least one conductive pad 322, wherein the conductive pad 322 is formed in the dielectric layer 321. The memory component 320 and the substrate 110 are directly connected to each other. By means of copper hybrid bonding technology, the second conductive contact 116 of the substrate 110 and the conductive pad 322 of the memory component 320 can be directly connected to each other, and the dielectric layer 117 of the substrate 110 and the dielectric layer 321 of the memory component 320 can be directly connected to each other.

[0149] Please refer to Figures 4A to 4B As shown, Figure 4A FIG. 4 is a schematic diagram showing a semiconductor device 40 according to another embodiment of the present invention. Figure 4B Show Figure 4A A cross-sectional view of the semiconductor device 40 along a direction 4B- 4B′.

[0150] The semiconductor device 40 includes a semiconductor chip 400, a first substrate 31, a second substrate 12, at least one electrical contact 13 and an underfill 14. The semiconductor chip 400 is disposed on the first substrate 31 through a plurality of electrical contacts 13. The underfill 14 is disposed between the semiconductor chip 400 and the first substrate 31 and covers the electrical contacts 13. The first substrate 31 is disposed between the second substrate 12 and the semiconductor chip 300. The first substrate 31 includes at least one grid array pad 31A, and the second substrate 12 includes at least one pin 12A, wherein the first substrate 31 and the second substrate 12 are electrically connected through the pin 12A and the grid array pad 31A. In the present embodiment, the first substrate 31 is, for example, an interposer, such as a silicon interposer, a glass interposer, a glass substrate, an interposer of a high TC material or a combination thereof. In another embodiment, the first substrate may be a combination of an interposer and a laminate substrate.

[0151] like Figure 4B As shown, the semiconductor chip 400 includes a substrate 110, at least one memory component 320, at least one heat dissipation component 130 and a molding compound 140. The memory component 320 is disposed on the substrate 110. The heat dissipation component 130 is disposed on the substrate 110. The heat dissipation component 130 has a thermal conductivity greater than the thermal conductivity of silicon. In this way, the heat dissipation component 130 can quickly conduct heat to the outside of the semiconductor device 40.

[0152] like Figure 4B As shown, in this embodiment, at least one memory component 320 is disposed between a plurality of heat dissipation components 130. A molding compound 140 is formed between the plurality of memory components 320, between the heat dissipation components 130 and the memory components 320, and covers the side surface 320s of each heat dissipation component 130.

[0153] like Figure 4B As shown, each memory component 320 is, for example, a high-bandwidth memory (HBM) or a chip stack structure including a memory function (or both memory and logic functions). The memory component 320 includes at least a dielectric layer 321 and at least one conductive pad 322, wherein the conductive pad 322 is formed in the dielectric layer 321. The memory component 320 and the substrate 110 are directly connected to each other. By means of copper hybrid bonding technology, the second conductive contact 116 of the substrate 110 and the conductive pad 322 of the memory component 320 can be directly connected to each other, and the dielectric layer 117 of the substrate 110 and the dielectric layer 321 of the memory component 320 can be directly connected to each other.

[0154] Please refer to Figure 5 , which shows a schematic diagram of a semiconductor device 50 according to another embodiment of the present invention. The semiconductor device 50 includes a semiconductor chip 500, a first substrate 11, a second substrate 12, at least one electrical contact 13, a primer 14, a heat sink 21, a first adhesive layer 22, a second adhesive layer 23, a first cooling element 24, a second cooling element 25 and a third adhesive layer 26.

[0155] The semiconductor device 50 includes the same or similar features as the semiconductor device 10 , with at least one difference being that the semiconductor device 50 further includes a heat sink 21 , a first adhesive layer 22 , a second adhesive layer 23 , a first cooling element 24 , a second cooling element 25 and a third adhesive layer 26 .

[0156] like Figure 5As shown, the heat sink 21 includes a vapor chamber (or a structure made of a high TC material such as diamond or a high TC material and a vapor chamber), which covers the memory component 520 and the heat dissipation component 130 and has an upper surface 21u. In addition, the memory component 520 and the heat dissipation component 130 are configured in the vapor chamber. The first cooling component 24 is configured on the upper surface 21u of the heat sink 21 and has a fluid channel 24a. The heat sink 21 is configured on the first substrate 11 through the first adhesive layer 22, wherein the first adhesive layer 22 is configured between the heat sink 21 and the first substrate 11. The heat sink 21 is configured on the semiconductor chip 500 through the second adhesive layer 23, wherein the third adhesive layer 26 is configured between the heat sink 21 and the first cooling component 24. The first cooling component 24 is configured on the heat sink 21 and thermally coupled to the second cooling component 25. In one embodiment, the first adhesive layer 22, the second adhesive layer 23 and the third adhesive layer 26 can be formed of, for example, a high TC thermal interface material or an appropriate high TC material. In one embodiment, the second cooling component 25 includes, for example, a fan, a heat exchanger, a direct chip liquid cooling device, a direct chip cooling device, a liquid immersion cooling device, or a combination thereof.

[0157] In another embodiment, the semiconductor device 50 further includes a high TC plate (not shown) disposed between the third adhesive layer 26 and the heat sink 21 .

[0158] like Figure 5 As shown, the semiconductor chip 500 includes a substrate 110, at least one memory component 520, at least one heat dissipation component 130 and a molding compound 140. The memory component 120 is disposed on the substrate 110. The heat dissipation component 130 is disposed on the substrate 110. The heat dissipation component 130 is disposed on the substrate 110. The heat dissipation component 130 has a thermal conductivity greater than the thermal conductivity of silicon. In this way, the heat dissipation component 130 can quickly conduct heat to the outside of the semiconductor device 50.

[0159] like Figure 5 As shown, the memory component 520 and the heat dissipation component 130 can be arranged side by side. The memory component 520 includes a silicon substrate 121, a front-end process layer 122, a back-end process layer 123, a plurality of first conductive contacts 124, a plurality of conductive holes 125, a plurality of second conductive contacts 126 and a dielectric layer 127. The memory component 520 is, for example, a static random access memory.

[0160] In one embodiment, the heat sink 130 may be made of a high thermal conductivity (HTC) and low thermal expansion coefficient (LCTE) material, such as diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, a suitable HTC and LCTE material such as a composite metal (e.g., copper / invar / copper), or a combination thereof. The heat sink 130 may be formed of diamond of varying thicknesses by high-quality microwave plasma chemical vapor deposition (MPCVD) technology or other suitable methods. In one embodiment, the thermal conductivity (TC) of diamond may be as high as 2400 W / m·K.

[0161] like Figure 5 As shown, the heat dissipation component 130 can be directly configured (or bonded) on the substrate 110. In another embodiment, the heat dissipation component 130 can be configured on the substrate 110 through an oxide layer (not shown) using, for example, an oxide bonding technique, wherein the oxide layer is disposed between the heat dissipation component 130 and the substrate 110.

[0162] like Figure 5 As shown, the molding compound 140 is formed between the memory component 520 and the heat dissipation component 130, and covers the side surface 130s of each heat dissipation component 130. The molding compound 140 can be a phenolic resin, an epoxy resin, a silicone resin or other suitable encapsulant. The molding compound 140 may also include a suitable filler, such as powdered silicon dioxide. The molding compound 140 can be formed using several packaging technologies, such as compression molding, liquid packaging, injection molding or transfer molding. In addition, the molding compound 140 has a side surface 140s, and the substrate 110 has a side surface 110s, wherein the side surface 140s of the molding compound 140 and the side surface 110s of the substrate 110 are flush with each other.

[0163] like Figure 5 As shown, the memory component 520 and the heat dissipation component 130 can be arranged side by side. The memory component 120 includes a silicon substrate 121, a front-end process layer 122, a back-end process layer 123, a plurality of first conductive contacts 124, a plurality of conductive holes 125, a plurality of second conductive contacts 126, and a high-thermal conductivity (high-TC) layer 527 such as a diamond layer (or an aluminum nitride layer), a first dielectric layer 528, and a second dielectric layer 529. The memory component 520 is, for example, a static random access memory.

[0164] like Figure 5As shown, the silicon substrate 121 is, for example, a portion of a silicon wafer. The front-end process layer 122 is formed on the silicon substrate 121 and includes at least one memory cell (not shown). The back-end process layer 123 is formed on the front-end process layer 122. The first dielectric layer 528 and the second dielectric layer 529 are respectively formed on two adjacent sides of the diamond layer 527. The first conductive contact 124 is formed in the first dielectric layer 528, and the second conductive contact 126 is formed in the second dielectric layer 529. The first conductive contact 124 can be electrically connected to the back-end process layer 123, and electrically connected to the second conductive contact 126 through the conductive hole 125. The conductive hole 125 is, for example, a through-diamond via (TDV).

[0165] Please refer to Figures 6A-6B , Fig. 6A FIG. 4 is a schematic diagram showing a semiconductor device 60 according to another embodiment of the present invention. Figure 6B Show Fig. 6A Schematic diagram of a substrate 610 of a semiconductor device 60. The semiconductor device 60 includes a semiconductor chip 600, a first substrate 11, a second substrate 12, at least one electrical contact 13 and an underfill 14. The semiconductor chip 600 is configured on the first substrate 11 through a plurality of electrical contacts 13. The underfill 14 is configured between the semiconductor chip 600 and the first substrate 11 and covers the electrical contacts 13. The first substrate 11 is configured between the second substrate 12 and the semiconductor chip 600. The first substrate 11 includes at least one grid array pad 11A, and the second substrate 12 includes at least one pin 12A, wherein the first substrate 11 and the second substrate 12 are electrically connected to the grid array pad 11A through the pin 12A.

[0166] In one embodiment, the first substrate 11 is, for example, a laminate substrate. The electrical contacts 13 are, for example, solder balls, copper pillars, micro bumps, etc. The second substrate 12 is, for example, a printed circuit board. In another embodiment, the first substrate 11 is an interposer, such as a silicon interposer, a glass interposer, a glass substrate, an interposer made of a high TC material, or a combination thereof. In another embodiment, the first substrate may be a combination of an interposer and a laminate substrate.

[0167] like Fig. 6A As shown, the semiconductor chip 600 includes a substrate 610, at least one memory component 120, at least one heat dissipation component 130 and a molding compound 140. The memory component 120 is disposed on the substrate 610. The heat dissipation component 130 is disposed on the substrate 610. The heat dissipation component 130 has a thermal conductivity greater than the thermal conductivity of silicon. In this way, the heat dissipation component 130 can quickly conduct heat to the outside of the semiconductor device 60.

[0168] like Fig. 6AAs shown, the memory component 120 and the heat dissipation component 130 can be arranged side by side. The memory component 120 includes a silicon substrate 121, a front-end process layer 122, a back-end process layer 123, a plurality of first conductive contacts 124, a plurality of conductive vias 125, a plurality of second conductive contacts 126 and a dielectric layer 127. The memory component 520 is, for example, a static random access memory.

[0169] In one embodiment, the heat sink 130 may be made of a high thermal conductivity (HTC) and low thermal expansion coefficient (LCTE) material, such as diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, a suitable HTC and LCTE material such as a composite metal (e.g., copper / invar / copper), or a combination thereof. The heat sink 130 may be formed of diamond of varying thicknesses by high-quality microwave plasma chemical vapor deposition (MPCVD) technology or other suitable methods. In one embodiment, the thermal conductivity (TC) of diamond may be as high as 2400 W / m·K.

[0170] like Fig. 6A As shown, the heat dissipation component 130 can be directly configured (or bonded) on the substrate 610. In another embodiment, the heat dissipation component 130 can be configured on the substrate 610 through an oxide layer (not shown) using, for example, an oxide bonding technique, wherein the oxide layer is disposed between the heat dissipation component 130 and the substrate 610.

[0171] like Fig. 6A As shown, the molding compound 140 is formed between the memory component 120 and the heat dissipation component 130, and covers the side surface 130s of each heat dissipation component 130. The molding compound 140 can be a phenolic resin, an epoxy resin, a silicone resin or other suitable encapsulant. The molding compound 140 may also include a suitable filler, such as powdered silicon dioxide. The molding compound 140 can be formed using several packaging technologies, such as compression molding, liquid packaging, injection molding or transfer molding. In addition, the molding compound 140 has a side surface 140s, and the substrate 610 has a side surface 610s, wherein the side surface 140s of the molding compound 140 and the side surface 610s of the substrate 610 are flush with each other.

[0172] like Figure 6BAs shown, the substrate 610 is a substrate having a backside power delivery network (BSPDN). In addition, the substrate 610 includes a silicon substrate 111, a front-end process layer 112, a back-end process layer 113 (which may be composed of a local interconnect layer and an intermediate interconnect layer), a redistribution layer (RDL) 613, at least one power rail (power rail layer) P1, at least one first conductive via 614, at least one second conductive via 615, at least one power trace (power transmission and signal layer) 616, a silicon layer L3, a dielectric layer L4 (which and the power trace 616 may form a BEOL global interconnect layer), a redistribution layer 617A, at least one conductive pad 618A and an intermediate layer 619. The power rail P1 formed on the silicon substrate 111 is coupled to the front-end process layer 112. The first conductive via 614 is connected to the power rail P1 through the silicon layer L3. The second conductive via 615 is formed in the silicon layer L3. The dielectric layer L4 is formed on the silicon layer L3. The power trace 616 is formed in the dielectric layer L4 and is electrically connected to the first conductive via 614 and the second conductive via 615. The redistribution layer 617A is formed in the dielectric layer L4 and is electrically connected to the power trace 616. The conductive pad 618A is formed in the redistribution layer 617A. In addition, the front-end process layer 112 includes a plurality of transistors (not shown), and the transistors include, for example, a fin field-effect transistor (fin-FET) structure, a nano-sheet structure, or a gate-all-around (GAA) structure.

[0173] like Figure 6BAs shown, the interposer 619 is a high thermal conductivity (HTC) and low thermal expansion coefficient (LCTE) substrate, which is adjacent to and electrically connected to the power (signal) supply layer, wherein the high thermal conductivity and low thermal expansion coefficient substrate can be made of diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, suitable HTC and LCTE materials such as composite metals (such as copper / invar / copper), or a combination thereof. In addition, the interposer 619 includes a redistribution layer 619A, at least one conductive pad 619B, a diamond layer 619C (or a HTC and LCTE layer), a redistribution layer 619D, and at least one diamond through hole (TDV) 619E. The redistribution layer 619A and the redistribution layer 619D are respectively formed adjacent to two adjacent sides of the diamond layer 619C. The diamond through hole 619E is formed in the diamond layer 619C and connects the redistribution layer 619A and the redistribution layer 619D. Conductive pads 619B are formed in redistribution layer 619A. Interposer 619 is connected to redistribution layer 617A through the connection of conductive pads 618A and conductive pads 619B. In this embodiment, memory device 120 is disposed on substrate 610 including HTC and LCTE materials.

[0174] Please refer to Figure 7 , which is a schematic diagram of a semiconductor device 70 according to another embodiment of the present invention.

[0175] like Figure 7 As shown, the semiconductor device 70 includes a semiconductor chip 700, a first substrate 11, a second substrate 12, at least one electrical contact 13 and an underfill 14. The semiconductor chip 700 is disposed on the first substrate 11 through a plurality of electrical contacts 13. The underfill 14 is disposed between the semiconductor chip 700 and the first substrate 11 and covers the electrical contacts 13. The first substrate 11 is disposed between the second substrate 12 and the semiconductor chip 700. The first substrate 11 includes at least one grid array pad 11A, and the second substrate 12 includes at least one pin 12A, wherein the first substrate 11 and the second substrate 12 are electrically connected to the grid array pad 11A through the pin 12A.

[0176] like Figure 7 As shown, the semiconductor chip 700 includes a substrate 610, at least one memory component 720, at least one heat dissipation component 130 and a molding compound 140. The memory component 720 is disposed on the substrate 610. The heat dissipation component 130 is disposed on the substrate 610. The heat dissipation component 130 has a thermal conductivity greater than the thermal conductivity of silicon. In this way, the heat dissipation component 130 can quickly conduct heat to the outside of the semiconductor device 70.

[0177] In one embodiment, the heat sink 130 may be made of a high thermal conductivity (HTC) and low thermal expansion coefficient (LCTE) material, such as diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, a suitable HTC and LCTE material such as a composite metal (e.g., copper / invar / copper), or a combination thereof. The heat sink 130 may be formed of diamond of varying thicknesses by high-quality microwave plasma chemical vapor deposition (MPCVD) technology or other suitable methods. In one embodiment, the thermal conductivity (TC) of diamond may be as high as 2400 W / m·K.

[0178] like Figure 7 As shown, the heat dissipation component 130 can be directly configured (or bonded) on the substrate 610. In another embodiment, the heat dissipation component 130 can be configured on the substrate 610 through an oxide layer (not shown) using, for example, an oxide bonding technique, wherein the oxide layer is disposed between the heat dissipation component 130 and the substrate 610.

[0179] like Figure 7 As shown, the molding compound 140 is formed between the memory component 720 and the heat dissipation component 130, and covers the side surface 130s of each heat dissipation component 130. The molding compound 140 can be a phenolic resin, an epoxy resin, a silicone resin or other suitable encapsulant. The molding compound 140 may also include a suitable filler, such as powdered silicon dioxide. The molding compound 140 can be formed using several packaging technologies, such as compression molding, liquid packaging, injection molding or transfer molding. In addition, the molding compound 140 has a side surface 140s, and the substrate 610 has a side surface 610s, wherein the side surface 140s of the molding compound 140 and the side surface 610s of the substrate 610 are flush with each other.

[0180] like Figure 7 As shown, the memory component 720 and the heat dissipation component 130 can be arranged side by side. The memory component 720 includes a silicon substrate 121, a front-end process layer 122, a back-end process layer 123, a plurality of first conductive contacts 124, a plurality of conductive vias 125, a plurality of second conductive contacts 126, a dielectric layer 127 and a thermal isolation layer 728. The memory component 720 is, for example, a static random access memory.

[0181] The memory component 720 includes the same or similar technical features as the memory component 120 , with at least one difference being that the thermal isolation layer 728 of the memory component 720 is formed between the back-end process layer 123 and the dielectric layer 127 .

[0182] Please refer to Figure 8 , which is a schematic diagram of a semiconductor device 80 according to another embodiment of the present invention.

[0183] like Figure 8 As shown, the semiconductor device 80 includes a semiconductor chip 800, a first substrate 11, a second substrate 12, at least one electrical contact 13 and an underfill 14. The semiconductor chip 800 is disposed on the first substrate 11 through a plurality of electrical contacts 13. The underfill 14 is disposed between the semiconductor chip 800 and the first substrate 11 and covers the electrical contacts 13. The first substrate 11 is disposed between the second substrate 12 and the semiconductor chip 800. The first substrate 11 includes at least one grid array pad 11A, and the second substrate 12 includes at least one pin 12A, wherein the first substrate 11 and the second substrate 12 are electrically connected to the grid array pad 11A through the pin 12A.

[0184] like Figure 8 As shown, the semiconductor chip 800 includes a substrate 610, at least one memory component 820, at least one heat dissipation component 130, and a molding compound 140. The memory component 820 is disposed on the substrate 610. The heat dissipation component 130 is disposed on the substrate 610. The heat dissipation component 130 has a thermal conductivity greater than the thermal conductivity of silicon. In this way, the heat dissipation component 130 can quickly conduct heat to the outside of the semiconductor device 80.

[0185] In one embodiment, the heat sink 130 may be made of a high thermal conductivity (HTC) and low thermal expansion coefficient (LCTE) material, such as diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, a suitable HTC and LCTE material such as a composite metal (e.g., copper / invar / copper), or a combination thereof. The heat sink 130 may be formed of diamond of varying thicknesses by high-quality microwave plasma chemical vapor deposition (MPCVD) technology or other suitable methods. In one embodiment, the thermal conductivity (TC) of diamond may be as high as 2400 W / m·K.

[0186] like Figure 8 As shown, the heat dissipation component 130 can be directly configured (or bonded) on the substrate 610. In another embodiment, the heat dissipation component 130 can be configured on the substrate 610 through an oxide layer (not shown) using, for example, an oxide bonding technique, wherein the oxide layer is disposed between the heat dissipation component 130 and the substrate 610.

[0187] like Figure 8As shown, the molding compound 140 is formed between the memory component 820 and the heat dissipation component 130, and covers the side surface 130s of each heat dissipation component 130. The molding compound 140 can be a phenolic resin, an epoxy resin, a silicone resin or other suitable encapsulant. The molding compound 140 may also include a suitable filler, such as powdered silicon dioxide. The molding compound 140 can be formed using several packaging technologies, such as compression molding, liquid packaging, injection molding or transfer molding. In addition, the molding compound 140 has a side surface 140s, and the substrate 610 has a side surface 610s, wherein the side surface 140s of the molding compound 140 and the side surface 610s of the substrate 610 are flush with each other.

[0188] like Figure 8 As shown, the memory component 820 and the heat dissipation component 130 can be arranged side by side. The memory component 820 includes a silicon substrate 121, a front-end process layer 122, a back-end process layer 123, a plurality of first conductive contacts 124, a plurality of conductive holes 125, a plurality of second conductive contacts 126, a dielectric layer 127, a thermal isolation layer 728 and at least one thermal via 829. The memory component 820 is, for example, a static random access memory.

[0189] Memory component 820 includes the same or similar technical features as memory component 720, with at least one difference being that thermal vias 829 extend from thermal isolation layer 728 through front-end process layer 122 and back-end process layer 123 to silicon substrate 121 (which only makes sense when the thermal vias are coupled with a heat spreading layer).

[0190] Please refer to Fig. 9 , which shows Figure 1 Schematic diagram of a silicon substrate 111 of a substrate 110. The substrate 110 includes a processor core 111A, a third-level cache 111B, and a thermal metamaterial structure 111C. The third-level cache 111B is disposed adjacent to the processor core 111A. The thermal metamaterial structure 111C is disposed between the processor core 111A and the third-level cache 111B and between the third-level cache 111B and the memory component 120 to minimize the distance between the processor core and the third-level cache and between the third-level cache and the memory component 120 (shown in FIG. 1 ). Figure 1 ) between thermal cross-talk.

[0191] like Fig. 9As shown, the thermal metamaterial structure 111C is a thermal-guiding ring. The thermal metamaterial structure 111C includes a first layer 111C1, a second layer 111C2, and a third layer 111C3. The first layer 111C1 has a first thermal conductivity. The second layer 111C2 has a second thermal conductivity and surrounds the first layer 111C1. The third layer 111C3 has a third thermal conductivity and surrounds the second layer 111C2. The second thermal conductivity is greater than the first thermal conductivity, and the first thermal conductivity is greater than the third thermal conductivity. In one embodiment, the first layer 111C1 is formed of silicon, the second layer 111C2 is formed of graphene, and the third layer 111C3 is formed of silicon dioxide.

[0192] Please refer to Fig. 10A , which shows a schematic diagram of a substrate 910A according to another embodiment of the present invention. The substrate 910A includes a silicon substrate 911, a front-end process layer 912, a back-end process layer 913, and a thermal component 914A located on the top of the back-end process layer 913 (another thermal component 914A may also appear inside the back-end process layer 913 and / or in the front-end process layer 912). The front-end process layer 912 is formed on the silicon substrate 911 and includes a plurality of transistors 912A and 912B, a dielectric layer 912C, and at least one conductive via 912D. The transistors 912A and 912B are formed in the silicon substrate 911 and the dielectric layer 912C. The conductive via 912D is electrically connected to the transistors 912A and 912B through the dielectric layer 912C. The back-end process layer 913 includes a plurality of dielectric layers 913A and a plurality of conductive vias 913B. The dielectric layers 913A are stacked on each other, and each conductive hole 913B is formed in the corresponding dielectric layer 913A and is electrically connected to the corresponding conductive hole 913B. The thermal component 914A is formed above the back-end process layer 913. In detail, the thermal component 914A is formed on the entire upper surface of the top dielectric layer 913A of the back-end process layer 913. The thermal component 914A is, for example, a thermal isolation structure or a heat spreading structure.

[0193] Please refer to Fig. 10B, which shows a schematic diagram of a substrate 910B according to another embodiment of the present invention. The substrate 910B includes a silicon base 911, a front-end process layer 912, a back-end process layer 913 and a thermal component 914B (another thermal component 914A may also appear inside the back-end process layer 913 and / or in the front-end process layer 912). The substrate 910B includes the same or similar features as the substrate 910A, with at least one difference being that the thermal component 914B is formed on a portion of the upper surface of the topmost dielectric layer 913A of the back-end process layer 913 (or inside the back-end process layer 913, in the front-end process layer 912, or in both the back-end process layer and the front-end process layer). The thermal component 914B is, for example, a heat insulation structure or a heat dissipation structure.

[0194] Please refer to Fig. 10C , which shows a schematic diagram of a substrate 910C according to another embodiment of the present invention. The substrate 910C includes a silicon base 911, a front-end process layer 912, a back-end process layer 913, and a thermal element 914C. The substrate 910C includes features that are the same or similar to those of the substrate 910B, with at least one difference being that the thermal element 914C is covered by a dielectric layer 913A of the back-end process layer 913.

[0195] Please refer to Fig. 10D , which shows a schematic diagram of a substrate 910D according to another embodiment of the present invention. The substrate 910D includes a silicon base 911, a front-end process layer 912, a back-end process layer 913, and a thermal element 914D. The substrate 910D includes the same or similar features as the substrate 910C, with at least one difference being that the thermal element 914D is located between two adjacent conductive holes 913B and can contact the two adjacent conductive holes 913B.

[0196] Please refer to Figures 11A to 11G , which shows Figure 1 FIG. 1 is a diagram of a manufacturing process of a semiconductor chip 100 .

[0197] like Fig.11A As shown, a front-end process layer 112 is formed in a silicon substrate 111, and a conductive hole 115 extending into the silicon substrate 111 is formed, and a back-end process layer 113 and a first conductive contact 114 are formed on the front-end process layer 112, wherein the first conductive contact 114 is connected to the conductive hole 115. Then the aforementioned structure is turned over and bonded to a temporary first carrier C1 with a release layer. The first carrier C1 is, for example, a glass carrier including an ultraviolet laser release layer. Although not shown, a release film may be set between the first carrier C1 and the back-end process layer 113.

[0198] Then, if Fig. 11BAs shown, the silicon substrate 111 can be planarized by, for example, chemical-mechanical polishing (CMP) to expose the conductive hole 115. Then, a dielectric layer 117 is formed on the silicon substrate 111, and a second conductive contact 116 electrically connected to the conductive hole 115 is formed in the dielectric layer 117 to form the substrate 110.

[0199] like Fig. 11C As shown, the memory component 120 is disposed on the silicon substrate 111 of the substrate 110 by using copper hybrid bonding technology, wherein the memory component 120 is electrically connected to the substrate 110, and the heat dissipation component 130 is bonded to the silicon substrate 111 of the substrate 110 by using direct bonding technology.

[0200] Then, the molding compound 140 is applied to fill the gap between the heat dissipation component 130 and the memory component 120 and cover the side surface of the heat dissipation component 130 .

[0201] like Fig.11D As shown, etching is performed, for example, through a mask M1 having a plurality of openings M1a to remove a portion of the molding compound 140. After etching, the semiconductor chip 100 is formed.

[0202] like Fig.11E As shown, the second carrier C2 is disposed on the semiconductor chip 100 by a release film R1. The second carrier C2 is, for example, a glass carrier, and the release layer is, for example, an ultraviolet laser release layer.

[0203] like Fig.11F As shown, a plurality of electrical contacts 13 are formed on the back-end process layer 113 .

[0204] like Fig.11G As shown, upon releasing the second carrier C2, Fig.11F The structure is configured on the first substrate 11 through the electrical contacts 13. Then, a primer 14 covering the electrical contacts 13 is formed between the first substrate 11 and the substrate 110.

[0205] Please refer to Figures 12A to 12L , which shows Figure 6B FIG. 6 is a diagram showing a manufacturing process of the first substrate 610 .

[0206] like Fig. 12A As shown, a buffer stop layer L1 is formed on a first silicon substrate C3 by, for example, chemical vapor deposition (CVD) technology.

[0207] like Fig. 12BAs shown, a silicon cap L2 is formed on the buffer stop layer L1 by, for example, epitaxial growth technology, etc. Then, the silicon cap L2 is thinned by, for example, etching, back grinding, CMP, etc.

[0208] like Fig. 12C As shown, the front-end process layer 112 is formed on the silicon cap L2. The front-end process layer 112 includes a plurality of transistors (not shown), and the transistors include, for example, a fin field effect transistor structure, a nanosheet structure, or a surrounding gate structure. The power rail P1 is embedded in the front-end process layer 112 and the silicon cap L2.

[0209] like Fig.12D As shown, by techniques such as deposition and photolithography, a back-end process layer 113 (which may include a local interconnect layer and an intermediate interconnect layer) is formed on the front-end process layer 112. By techniques such as deposition and photolithography, a redistribution layer 613 is formed on the back-end process layer 113.

[0210] like Fig.12E As shown, Fig.12D The redistribution layer 613 of the structure shown may be disposed on the second silicon substrate C4.

[0211] like Fig.12F As shown, the first silicon substrate C3 and the buffer stop layer L1 are removed by techniques such as chemical mechanical polishing and etching to expose the silicon cap L2.

[0212] like Figure 12G As shown, a silicon dioxide layer L4 is formed on the silicon cap L2.

[0213] like Fig.12H As shown, a first conductive via 614 extending to the power rail P1 is formed in the silicon dioxide layer L4 and the silicon cap L2 through a technique such as a photolithography process, and a second conductive via 615 is formed in the silicon dioxide layer L4 and the silicon cap L2.

[0214] like Fig.12I As shown, a dielectric layer L5 is formed to cover the first conductive via 614 and the second conductive via 615. Then, a power trace 616 connected to the first conductive via 614 and the second conductive via 615 is formed in the dielectric layer L5 through techniques such as photolithography and deposition. Then, a redistribution layer 617A including a conductive pad 618A is formed above the dielectric layer L5 and the power trace 616.

[0215] like Fig.12JAs shown, the interposer 619 is disposed on the redistribution layer 617A, wherein the conductive pad 619B of the interposer 619 is electrically connected to the conductive pad 618A.

[0216] like Figure 12K As shown, the electrical contact 13 is formed on the redistribution layer 619D of the interposer 619 .

[0217] like Figure 12L As shown, the second silicon substrate C4 is removed.

[0218] The diamond layer in the above embodiment can be formed through the following process.

[0219] Please refer to Figures 13A to 13C , which shows a manufacturing process diagram of a diamond layer DL according to an embodiment of the present invention.

[0220] like Fig.13A As shown, through the mask M2, a plurality of diamond particles DP are formed on the substrate 1. The mask M2 has a plurality of through holes M2a. The diamond particles DP are formed on the substrate 1 through the through holes M2a. The substrate 1 is formed of a material including, for example, Mo (molybdenum). The substrate 1 has a length W1, which is, for example, 1 cm, 2 cm, 4 cm, etc. The mask M2 is formed of a material including, for example, Mo. The spacing P1 between two adjacent diamond particles DP is, for example, 20 microns. In addition, the diamond particles DP can be formed (or adhered) on the substrate 1 through a plurality of adhesive layers 1A.

[0221] like Fig. 13B As shown, a diamond layer DL is formed on a substrate 1 by growing diamond particles DP through MPCVD, for example. The diamond layer DL has a thickness t1, which is, for example, 10 micrometers, 30 micrometers, 50 micrometers, 100 micrometers, etc.

[0222] like Fig. 13C As shown, it can be removed by, for example, thermomechanical techniques. Fig. 13B The substrate 1 is shown.

[0223] Please refer to Figures 14A to 14I , which shows a manufacturing process diagram of a diamond layer DL according to another embodiment of the present invention.

[0224] like Fig.14A As shown, a silicon substrate S1 is provided.

[0225] like Fig. 14B As shown, a mask M3 having a plurality of through holes M3a is formed on a silicon substrate S1. The mask M3 may be formed of a material including, for example, photosensitive polyimide (PSPI).

[0226] like Fig. 14C As shown, using, for example, dry etching (using SF6 ), through the plurality of through holes M3a of the mask M3, a plurality of recesses S1a are formed in the silicon substrate S1 to form a patterned substrate. Then, the mask M3 can be removed.

[0227] In another embodiment, Fig. 14C The patterned substrate shown may be formed by, for example, laser etching, wet etching, etc.

[0228] like Fig.14D As shown, a seed layer material SL' is formed at Fig. 14C The seed layer material SL' comprises, for example, Ir on Si, SrTiO 3 / Ir on Si (Ir on SrTiO 3 ) or Ir on YSZ / Si (Ir on YSZ / Si). Then, a diamond material DM can be formed on the silicon substrate S1 through the seed layer material SL' by, for example, MPCVD. Then, silicon dioxide SD can be formed on the diamond material DM by, for example, CVD.

[0229] like Fig.14E As shown, a portion of the seed layer material SL', a portion of the diamond material DM, a portion of the silicon substrate S1, and the silicon dioxide SD are removed by, for example, CMP. After CMP, the remaining portion of the diamond material DM forms a plurality of diamond particles DP. The diamond particles DP have an upper surface DMu, and the silicon substrate S1 has an upper surface S1u, and the upper surface DMu and the upper surface S1u are flush with each other. After CMP, the plurality of diamond particles DP are located in the recess S1a and above the plurality of seed layers SL.

[0230] like Fig.14F As shown, a portion of the silicon substrate S1 is removed through a mask (not shown), dry etching or other techniques to expose the side surface of each diamond particle DP. The spacing P1 between two adjacent diamond particles DP is, for example, 20 microns. In addition, multiple diamond particles DP can be located on the silicon substrate S1 through multiple seed layers SL.

[0231] like Figure 14G As shown, a diamond layer DL is formed on a silicon substrate S1 by growing diamond particles DP through MPCVD, for example. The diamond layer DL has a thickness t1, which is, for example, 10 micrometers, 30 micrometers, 50 micrometers, 100 micrometers, etc.

[0232] like Fig.14H As shown, Figure 14G The structure can be bonded to the temporary carrier C5 through the release layer R2.

[0233] like Fig.14I As shown, wet etching, CMP, dry etching and other techniques can be used to remove Fig.14H Then, the temporary carrier C5 and the diamond layer DL are separated through the release layer R2.

[0234] Please refer to Figures 15A to 15H , which shows a manufacturing process diagram of a diamond layer DL according to another embodiment of the present invention.

[0235] like Fig.15A As shown, a silicon substrate S1 is provided.

[0236] like Fig. 15B As shown, a photomask M3 having a plurality of through holes M3a is formed on a silicon substrate S1. The photomask M3 may be formed of a material including, for example, photosensitive polyimide.

[0237] like Fig. 15C As shown, using, for example, dry etching (using SF 6 ), through the plurality of through holes M3a of the mask M3, a plurality of recesses S1a are formed in the silicon substrate S1 to form a patterned substrate. Then, the mask M3 can be removed.

[0238] like Fig.15D As shown, a seed layer material SL' is formed at Fig. 15C The seed layer material SL' comprises, for example, Ir on Si, SrTiO 3 / Ir on Si (Ir on SrTiO 3 ) or Ir on YSZ / Si (Ir on YSZ / Si). Then, a diamond material DM can be formed on the silicon substrate S1 through the seed layer material SL' by, for example, MPCVD. Then, silicon dioxide SD can be formed on the diamond material DM by, for example, CVD.

[0239] like Fig.15E As shown, a portion of the diamond material DM and the silicon dioxide SD are removed by, for example, CMP. After CMP, the remaining portion of the diamond material DM still covers the seed layer material SL' and the silicon substrate S1.

[0240] like Fig.15F As shown, a diamond layer DL is formed on a silicon substrate S1 by growing a diamond material DM through, for example, MPCVD.

[0241] like Figure 15G As shown, Fig.15F The structure can be bonded to the temporary carrier C5 through the release layer R2.

[0242] like Fig.15H As shown, wet etching, CMP, dry etching and other techniques can be used to remove Figure 15GThe diamond layer DL is formed on a silicon substrate S1. The diamond layer DL has a thickness t1, which is, for example, 10 micrometers, 30 micrometers, 50 micrometers, 100 micrometers, etc. Then, the temporary carrier C5 and the diamond layer DL are separated through the release layer R2.

[0243] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.

Claims

1. A semiconductor device comprising: a substrate; a memory component, disposed on the substrate; as well as A heat dissipation component is disposed on the substrate; The heat dissipation component has a thermal conductivity greater than that of silicon.

2. The semiconductor device according to claim 1, wherein The heat dissipation component is formed of a material including diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, metal or a combination thereof.

3. The semiconductor device according to claim 1, wherein: The memory component and the heat dissipation component are arranged side by side.

4. The semiconductor device according to claim 1, wherein: Also includes: A plurality of the heat dissipation components; Wherein, the memory component is configured between the multiple heat dissipation components.

5. The semiconductor device according to claim 1, wherein Also includes: a plurality of such memory components; Wherein, the heat dissipation component is configured between the multiple memory components.

6. The semiconductor device according to claim 1, wherein: Also includes: A mold sealing compound is disposed between the heat dissipation component and the memory component.

7. The semiconductor device according to claim 1, wherein Also includes: A plurality of the heat dissipation components; as well as A molding compound is disposed between the plurality of heat dissipation components.

8. The semiconductor device according to claim 1, wherein Also includes: a plurality of such memory components; as well as A molding compound is disposed between the plurality of memory components.

9. The semiconductor device according to claim 1, wherein: Also includes: A heat sink, including a vapor chamber, covering the memory component and the heat dissipation component, and having an upper surface; a cooling assembly disposed on the upper surface of the radiator and having a fluid channel; and A fan and / or a heat exchanger are thermally coupled to the cooling assembly.

10. The semiconductor device according to claim 9, wherein: Also includes: A molding compound is located on one side surface of the heat dissipation component and has a side surface; The side surface of the molding compound is flush with a side surface of the substrate.

11. The semiconductor device according to claim 1, wherein The substrate includes: a power rail layer; a power supply layer connected to the power rail layer; and An intermediary layer is disposed adjacent to the power supply layer and thermally coupled to the power supply layer, wherein the intermediary layer is formed of a material including diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, metal or a combination thereof.

12. The semiconductor device according to claim 1, wherein The substrate includes: a back-end-of-line (BEOL) structure; and A thermal isolation structure is disposed on or within the post-process structure.

13. The semiconductor device according to claim 1, wherein: The substrate includes: A back-end process structure; and A heat spreading structure is disposed on or within the back-end process structure.

14. The semiconductor device according to claim 1, wherein: The substrate includes: A processor core; a cache memory disposed adjacent to the processor core; A thermal metamaterial structure is disposed between the processor core and the cache, and between the cache and the memory component, to respectively minimize thermal cross-talk between the processor core and the cache, and thermal cross-talk between the cache and the memory component.

15. The semiconductor device according to claim 14, wherein: The thermal metamaterial structure comprises: a first layer having a first thermal conductivity; a second layer having a second thermal conductivity and surrounding the first layer; and a third layer having a third thermal conductivity and surrounding the second layer; The second thermal conductivity is greater than the first thermal conductivity, and the first thermal conductivity is greater than the third thermal conductivity.

16. The semiconductor device according to claim 15, wherein: The first layer is formed of silicon, the second layer is formed of graphene, and the third layer is formed of silicon dioxide.

17. The semiconductor device according to claim 1, wherein: The semiconductor device is mounted on a substrate with high thermal conductivity and low thermal expansion coefficient.

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