Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a first substrate, a first chip, a second chip and a first substrate conductive column, the first chip is disposed on the first substrate and has a first side surface. The second chip is disposed on the first chip and includes a first protruding portion protruding relative to the first side surface. The first substrate conductive column is connected with the first protruding part and the first substrate.

Description

Technical Field

[0001] The invention relates to a semiconductor device. Background Art

[0002] A semiconductor device may include multiple chips stacked or electrically connected to each other. The electrical connection interface of these chips determines the signal transmission speed and manufacturing cost. Therefore, proposing a semiconductor device that can take into account both signal transmission speed and manufacturing cost is one of the goals of technicians in this technical field. Summary of the invention

[0003] Therefore, the present invention provides a semiconductor device which can improve the above-mentioned known problems.

[0004] An embodiment of the present invention provides a semiconductor device. The semiconductor device includes a first substrate, a first chip, a second chip, and a first substrate conductive column. The first chip is disposed on the first substrate and has a first side surface. The second chip is disposed on the first chip and includes a first protrusion protruding relative to the first side surface. The first substrate conductive column connects the first protrusion to the first substrate.

[0005] Another embodiment of the present invention provides a semiconductor device. The semiconductor device includes a substrate module and a chip module. The substrate module includes a first substrate and a plurality of substrate conductive pillars. The substrate conductive pillars are formed on the first substrate and each substrate conductive pillar has an end surface, and the end surfaces of the substrate conductive pillars are different in height position. The chip module has a plurality of lower surfaces with different height positions. A first connector of the substrate conductive pillars connects a first of the lower surfaces, and a second connector of the substrate conductive pillars connects a second of the lower surfaces.

[0006] Another embodiment of the present invention provides a semiconductor device. The semiconductor device includes a first substrate, a chip module and an interposer module. The chip module is disposed on the first substrate and has a plurality of upper surfaces at different height positions. The interposer module includes a second substrate and a plurality of interposer conductive pillars. The interposer conductive pillars are formed on the second substrate, and each interposer conductive pillar has an end face, and the end faces of the interposer conductive pillars are different in height positions. A first one of the interposer conductive pillars is connected to the first substrate, and a second one of the interposer conductive pillars is connected to one of the upper surfaces.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0010] Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0011] Figure 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0012] Figure 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0013] Figure 6 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0014] Figure 7 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0015] Fig. 8A is a schematic three-dimensional diagram of a semiconductor device according to another embodiment of the present invention.

[0016] Figure 8B yes Fig. 8A A top view of a semiconductor device.

[0017] Description of reference numerals:

[0018] 100, 200, 300, 400, 500, 600, 700, 800: Semiconductor devices

[0019] 110, 410, 510, 610, 810: Baseboard module

[0020] 111, 411, 511, 611, 841: first substrate

[0021] 1111, 1112, 4111, 4211, 5111: pads

[0022] , 2211, 2212, 2221, 2231, 3212, 3213, 6111: bump

[0023] 112, 1113, 1114: first substrate conductive column

[0024] 112e, 113e, 642e, 643e: end face

[0025] 113: Second substrate conductive column

[0026] 120, 220, 320, 420, 520, 620, 720, 820: chip module

[0027] 121, 321, 421: The first chip

[0028] 121s, 321s, 421s: First side

[0029] 122, 222, 322, 522, 722: Second chip

[0030] 122b, 123b, 322b, 323b: bottom surface

[0031] 122s, 222s, 322s, 522s: Second side

[0032] 122P, 222P, 322P: First protrusion

[0033] 123, 223, 323, 523, 723: The third chip

[0034] 123P, 223P, 323P: Second protrusion

[0035] 124: Adhesive layer

[0036] 130: Plastic packaging material

[0037] 141, 142, 143, 144, 341, 342, 651, 652: solder

[0038] 150: Primer

[0039] 321u,322u: upper surface

[0040] 3211,3222: Virtual pad

[0041] 3221,3231: Virtual convex blocks

[0042] 450: Welding wire

[0043] 523s: The third side

[0044] 524,724: The fourth chip

[0045] 524P: Third protrusion

[0046] 640,740,840: Intermediary module

[0047] 641,741: Second substrate

[0048] 642,643,744,745,746: Intermediary conductive pillars

[0049] 842: First interposer conductive column

[0050] 843: Second interposer conductive column

[0051] 844: The third interposer conductive column

[0052] 845,846: Conductive holes

[0053] 847: First circuit layer

[0054] 848: Second circuit layer

[0055] SP1, SP2: Interval DETAILED DESCRIPTION

[0056] Please refer to Figure 1 , which is a cross-sectional view of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a substrate module 110, a chip module 120, a molding compound 130, at least one solder (eg, solder 141-144) and an underfill 150.

[0057] like Figure 1 As shown, the substrate module 110 includes a first substrate 111 and a plurality of substrate conductive pillars (eg, a first substrate conductive pillar 112 and a second substrate conductive pillar 113 ). The substrate conductive pillars are formed on the first substrate 111 and protrude relative to the upper surface of the first substrate 111 .

[0058] like Figure 1 As shown, each substrate conductive column has an end surface, and these end surfaces of these substrate conductive columns are different in height position. For example, the first substrate conductive column 112 and the second substrate conductive column 113 are different in height position, wherein the first substrate conductive column 112 has an end surface 112e, and the second substrate conductive column 113 has an end surface 113e, and the end surface 112e and the end surface 113e are different in height position (for example, in the Z-axis direction). In addition, the "conductive column" herein is formed of a conductive material such as copper.

[0059] like Figure 1 As shown, the first substrate 111 includes pads 1111~1112 and conductive columns 1113~1114, wherein the pads 1111~1112 are formed in a circuit layer within the first substrate 111, the conductive column 1113 is formed on the pad 1111 and protrudes relative to the upper surface of the first substrate 111, and the conductive column 1114 is formed on the pad 1112 and protrudes relative to the upper surface of the first substrate 111.

[0060] like Figure 1As shown, the chip module 120 includes a plurality of chips (e.g., a first chip 121, a second chip 122, and a third chip 123) and at least one adhesive layer 124. The first chip 121 is disposed on the first substrate 111 and has a first side surface 121s. The second chip 122 is disposed on the first chip 121 and includes a first protrusion 122P protruding relative to the first side surface 121s. The first substrate conductive column 112 connects the first protrusion 122P and the first substrate 111. In this example, without the need for through silicon vias (TSV) and metal wires, the first substrate conductive column 112 connects the first substrate 111 and the chip module 120 along the Z-axis direction, which can shorten the electrical conduction path (compared to the bonding wire, suitable for high-frequency signal transmission) and reduce the manufacturing cost (compared to the through silicon via).

[0061] The chip of the chip module 120 is, for example, a chip with a low number of input / output contacts (Low I / O port). For example, the number of input / output contacts of the chip of the chip module 120 is equal to or less than 200. In semiconductor manufacturing, input / output contacts refer to the input and output interfaces on the chip, which are used to communicate and exchange data with other devices or systems. Chips with a low number of input / output contacts can be suitable for some specific applications, and the demand for their input / output contacts is relatively small. This design can save occupied area and reduce power consumption, and it is easier to achieve high performance and low cost. Chips with a low number of input / output contacts have application prospects in some specific fields, such as Internet of Thing (IoT) devices, embedded systems, etc.

[0062] like Figure 1 As shown, the first chip 121 is, for example, a flip chip. The first chip 121 has an active surface, which faces the first substrate 111 and is electrically connected to the first substrate 111 downward. For example, the first chip 121 is connected to the conductive column 1113 of the first substrate 111 through the solder 143, and is connected to the conductive column 1114 of the first substrate 111 through the solder 144. The primer 150 covers the solder 143-144 and the conductive columns 1113-1114. The solder herein is, for example, tin solder, which has conductivity.

[0063] like Figure 1As shown, the second chip 122 has a second side surface 122s, and the third chip 123 is disposed on the second chip 122 and includes a second protrusion 123P protruding relative to the second side surface 122s. The second substrate conductive pillar 113 connects the second protrusion 123P and the first substrate 111. In this example, without silicon vias and wire bonding, the second substrate conductive pillar 113 connects the first substrate 111 and the chip module 120 along the Z-axis direction, which can shorten the electrical conduction path (compared to wire bonding) and reduce the manufacturing cost (compared to silicon vias).

[0064] like Figure 1 As shown, the chip module 120 has a plurality of lower surfaces at different height positions. A first connector of the substrate conductive pillars connects a first one of the lower surfaces of the chip module 120, and a second connector of the substrate conductive pillars connects a second one of the lower surfaces. For example, the second chip 122 has a lower surface 122b, and the third chip 123 has a lower surface 123b, the first substrate conductive pillar 112 (e.g., the first connector of the substrate conductive pillars) connects the lower surface 122b of the second chip 122 (e.g., the first one of the lower surfaces), and the second substrate conductive pillar 113 (e.g., the second connector of the substrate conductive pillars) connects the lower surface 123b of the third chip 123 (e.g., the second one of the lower surfaces).

[0065] like Figure 1 As shown, the first protrusion 122P of the second chip 122 has the lower surface 122b, and the first substrate conductive column 112 connects the lower surface 122b of the first protrusion 122P and the first substrate 111. The second protrusion 123P of the third chip 123 has the lower surface 123b, and the second substrate conductive column 113 connects the lower surface 123b of the second protrusion 123P and the first substrate 111. The first substrate conductive column 112 can be connected to the lower surface 122b of the second chip 122 through the solder 141, and the second substrate conductive column 113 can be connected to the lower surface 123b of the third chip 123 through the solder 142.

[0066] like Figure 1 As shown, one adhesive layer 124 can bond the first chip 121 and the second chip 122, and another adhesive layer 124 can bond the second chip 122 and the third chip 123. The adhesive layer 124 is, for example, epoxy or die attach film (DAF).

[0067] like Figure 1 As shown, the molding compound 130 may be formed on the first substrate 111 and cover the substrate conductive pillars, the chip module 120 and the solders 141 ˜ 142 .

[0068] Please refer to Figure 2, which is a cross-sectional view of a semiconductor device 200 according to another embodiment of the present invention. The semiconductor device 200 includes a substrate module 110, a chip module 220, a molding compound 130, at least one solder (eg, solders 141-144) and an underfill 150.

[0069] The semiconductor device 200 of the present embodiment includes similar or identical technical features to the semiconductor device 100 , and one of the differences is that the chip module 220 is different from the chip module 120 in structure.

[0070] like Figure 2 As shown, the chip module 220 includes a plurality of chips (eg, a first chip 221 , a second chip 222 , and a third chip 223 ) and at least one adhesive layer 124 .

[0071] like Figure 2 As shown, the first chip 221 is disposed on the first substrate 111 and has a first side surface s221s. The second chip 222 is disposed on the first chip 221 and includes a first protrusion 222P protruding relative to the first side surface 221s. The first substrate conductive pillar 112 connects the first protrusion 222P and the first substrate 111. In this example, without silicon vias and wire bonding, the first substrate conductive pillar 112 connects the first substrate 111 and the chip module 220 along the Z-axis direction, which can shorten the electrical conduction path (compared to wire bonding) and reduce the manufacturing cost (compared to silicon vias).

[0072] like Figure 2 As shown, the first chip 221 includes at least one bump, such as bumps 2211 and 2212. The bump 2211 of the first chip 221 is connected to the conductive column 1113 of the first substrate 111 through solder 143, and the bump 2212 of the first chip 221 is connected to the conductive column 1114 of the first substrate 111 through solder 144.

[0073] like Figure 2 As shown, the second chip 222 has a second side surface 222s, and the third chip 223 is disposed on the second chip 222 and includes a second protrusion 223P protruding relative to the second side surface 222s. The second substrate conductive pillar 113 connects the second protrusion 223P and the first substrate 111. In this example, without silicon vias and wire bonding, the second substrate conductive pillar 113 connects the first substrate 111 and the chip module 220 along the Z-axis direction, which can shorten the electrical conduction path (compared to wire bonding) and reduce the manufacturing cost (compared to silicon vias).

[0074] like Figure 2As shown, the second chip 222 includes at least one bump 2221, and the third chip 223 includes at least one bump 2231. The first substrate conductive column 112 is connected to the bump 2221. For example, the first substrate conductive column 112 is connected to the bump 2221 through the solder 141. The second substrate conductive column 113 is connected to the bump 2231. For example, the second substrate conductive column 113 is connected to the bump 2231 through the solder 142. The "bump" herein is, for example, an under bump metallurgy (UMB) or a copper column, and its material includes, for example, copper.

[0075] Please refer to Figure 3 , which is a cross-sectional view of a semiconductor device 300 according to another embodiment of the present invention. The semiconductor device 300 includes a substrate module 110, a chip module 320, a molding compound 130, at least one solder (eg, solders 141-144 and solders 341-342) and a primer 150.

[0076] The semiconductor device 300 of the present embodiment includes similar or identical technical features to the semiconductor device 200 , and one of the differences is that the chip module 320 is different from the chip module 220 in structure.

[0077] like Figure 3 As shown, the chip module 320 includes a plurality of chips (e.g., a first chip 321, a second chip 322, and a third chip 323). The first chip 321 is disposed on the first substrate 111 and has a first side surface 321s. The second chip 322 is disposed on the first chip 321 and includes a first protrusion 322P protruding relative to the first side surface 321s. The first substrate conductive column 112 connects the first protrusion 322P and the first substrate 111. In this example, without the need for silicon vias and wire bonding, the first substrate conductive column 112 connects the first substrate 111 and the chip module 320 along the Z-axis direction, which can shorten the electrical conduction path (compared to wire bonding) and reduce the manufacturing cost (compared to silicon vias).

[0078] like Figure 3 As shown, in this embodiment, the first chip 321 further includes bumps 2211-2212. The bumps 2211 and 2212 of the first chip 321 are respectively connected to the conductive pillars 1113 and 1114 of the first substrate 111. For example, the bump 2211 of the first chip 321 is connected to the conductive pillar 1113 of the first substrate 111 through the solder 143, and the bump 2212 of the first chip 321 is connected to the conductive pillar 1114 of the first substrate 111 through the solder 144.

[0079] like Figure 3As shown, the second chip 322 has a second side surface 322s, and the third chip 323 is disposed on the second chip 322 and includes a second protrusion 323P protruding relative to the second side surface 322s. The second substrate conductive pillar 113 connects the second protrusion 323P and the first substrate 111. In this example, without silicon vias and wire bonding, the second substrate conductive pillar 113 connects the first substrate 111 and the chip module 320 along the Z-axis direction, which can shorten the electrical conduction path (compared to wire bonding) and reduce the manufacturing cost (compared to silicon vias).

[0080] like Figure 3 As shown, the first chip 321 includes at least one dummy pad 3211, and the second chip 322 includes at least one dummy bump 3221, wherein the dummy bump 3211 is connected to the dummy pad 3221. For example, the dummy bump 3211 and the dummy pad 3221 are connected by solder 341. In this example, the dummy bump 3221, the dummy pad 3211 and the solder 341 raise the height of the second chip 322, so that there is a gap SP1 between the upper surface 321u of the first chip 321 and the lower surface 322b of the second chip 322, wherein the gap SP1 has a substantially uniform height. In this way, the second chip 322 can be arranged roughly horizontally. Due to the equally spaced gap SP1, the plastic encapsulation material 130 can fill this gap SP1 more evenly during the molding process. The dummy bumps and dummy pads herein refer to conductors that do not have circuit functions, which are, for example, formed of copper.

[0081] like Figure 3 As shown, the second chip 322 includes at least one virtual pad 3222, and the third chip 323 includes at least one virtual bump 3231, wherein the virtual bump 3231 is connected to the virtual pad 3222. For example, the virtual bump 3231 is connected to the virtual pad 3222 through the solder 342. In this example, the virtual bump 3231, the virtual pad 3222 and the solder 342 raise the height of the third chip 323, so that there is a gap SP2 between the upper surface 322u of the second chip 322 and the lower surface 323b of the third chip 323, wherein the gap SP2 has a substantially uniform height. In this way, the second chip 322 is roughly horizontally configured. Due to the equally spaced gap SP2, the plastic encapsulation material 130 can fill this gap SP2 more evenly during the molding process.

[0082] In one embodiment, the intervals SP1 and SP2 are at least greater than 30 microns, so that the molding compound 130 can fully fill the intervals during the molding process. In another embodiment, depending on the process, the intervals SP1 and SP2 can be equal to or less than 30 microns.

[0083] Please refer to Figure 4, which is a cross-sectional view of a semiconductor device 400 according to another embodiment of the present invention. The semiconductor device 400 includes a substrate module 410, a chip module 420, a molding compound 130, at least one solder (eg, solder 141-142) and at least one bonding wire 450.

[0084] The semiconductor device 400 of the present embodiment includes similar or identical technical features to the semiconductor device 200 , with one difference being that the chip module 420 is structurally different from the chip module 220 , and the semiconductor device 400 further includes bonding wires.

[0085] like Figure 4 As shown, the substrate module 410 includes a first substrate 411, at least one first substrate conductive pillar 112 and at least one second substrate conductive pillar 113. The chip module 420 includes a plurality of chips (e.g., a first chip 421, a second chip 222 and a third chip 223). The first chip 421 is disposed on the first substrate 411 and has a first side surface 421s. The second chip 222 is disposed on the first chip 421 and includes a first protrusion 222P protruding relative to the first side surface 421s. The first substrate conductive pillar 112 connects the first protrusion 222P and the first substrate 411. In this example, without the need for silicon vias and wire bonding, the first substrate conductive pillar 112 connects the first substrate 411 and the second chip 222 along the Z-axis direction, which can shorten the electrical conduction path (compared to wire bonding) and reduce the manufacturing cost (compared to silicon vias).

[0086] like Figure 4 As shown, the first chip 421 can be disposed on the first substrate 411 through the adhesive layer 124. In this embodiment, the first chip 421 has an active surface facing upward. For example, the first chip 421 includes at least one pad 4211, which is exposed from the active surface of the first chip 421 to be connected to the bonding wire 450.

[0087] like Figure 4 As shown, the second chip 222 has a second side surface 222s, and the third chip 223 is disposed on the second chip 222 and includes a second protrusion 223P protruding relative to the second side surface 222s. The second substrate conductive pillar 113 connects the second protrusion 223P and the first substrate 411. In this example, without silicon vias and wire bonding, the second substrate conductive pillar 113 connects the first substrate 411 and the third chip 223 along the Z-axis direction, which can shorten the electrical conduction path (compared to wire bonding) and reduce the manufacturing cost (compared to silicon vias).

[0088] like Figure 4As shown, the bonding wire 450 connects the first chip 421 and the first substrate 411 . For example, one end of the bonding wire 450 may be bonded to the pad 4211 of the first chip 421 , and the other end of the bonding wire 450 may be bonded to the pad 4111 of the first substrate 411 .

[0089] like Figure 4 As shown, the molding compound 130 is formed on the first substrate 411 and covers the substrate conductive pillars, the chip module 420 and the bonding wires 450 .

[0090] Please refer to Figure 5 , which is a cross-sectional view of a semiconductor device 500 according to another embodiment of the present invention. The semiconductor device 500 includes a substrate module 510, a chip module 520, a molding compound 130 and at least one bonding wire 450.

[0091] The semiconductor device 500 of the present embodiment includes similar or identical technical features to the semiconductor device 100 , with one difference being that the substrate module 510 is structurally different from the substrate module 110 , and the chip module 520 is structurally different from the chip module 120 .

[0092] like Figure 5 As shown, the substrate module 510 includes a first substrate 511 , but the first substrate conductive pillars 112 and the second substrate conductive pillars 113 may be omitted. The first substrate 511 includes at least one pad 5111 for connecting with at least one bonding wire 450 .

[0093] like Figure 5 As shown, the chip module 520 includes a plurality of chips (e.g., a first chip 421, a second chip 522, a third chip 523, and a fourth chip 524). In the present embodiment, the chip module 520 may omit the substrate conductive column. The first chip 421 is disposed on the first substrate 511 and has a first side surface 421s. The second chip 122 is disposed on the first chip 421 and includes a first protrusion 522P protruding relative to the first side surface 421s. The second chip 522 has a second side surface 522s. The third chip 523 is disposed on the second chip 522 and includes a second protrusion 523P protruding relative to the second side surface 522s. The third chip 123 has a third side surface 523s. The fourth chip 524 is disposed on the third chip 523 and includes a third protrusion 524P protruding relative to the third side surface 523s.

[0094] like Figure 5As shown, the first chip 421 can be disposed on the first substrate 511 through the adhesive layer 124. In the present embodiment, the first chip 421 has an active surface facing upward. For example, the first chip 421 includes at least one pad 4211, which is exposed from the upper surface of the first chip 421. The second chip 522, the third chip 523 and the fourth chip 524 include structures similar to the first chip 421. In this way, the first chip 421, the second chip 522, the third chip 523, the fourth chip 524 and the first substrate 511 can be connected by at least one bonding wire 450.

[0095] Please refer to Figure 6 , which is a cross-sectional view of a semiconductor device 600 according to another embodiment of the present invention. The semiconductor device 600 includes a substrate module 610, a chip module 620, a molding compound 130, an interposer module 640, and at least one solder (eg, solders 141-142 and 651-652).

[0096] The semiconductor device 600 of the present embodiment includes similar or identical technical features to the semiconductor device 200 , with one difference being that the substrate module 610 is structurally different from the substrate module 210 , and the semiconductor device 600 further includes an interposer module 640 .

[0097] like Figure 6 As shown, the substrate module 610 includes a first substrate 611 , at least one first substrate conductive column 112 and at least one second substrate conductive column 113 . The first substrate 611 includes at least one pad 1111 and at least one bump 6111 .

[0098] like Figure 6 As shown, the intermediary layer module 640 includes a second substrate 641 and a plurality of intermediary layer conductive pillars (e.g., a first intermediary layer conductive pillar 642 and a second intermediary layer conductive pillar 643). The intermediary layer conductive pillars are formed on the second substrate 641, and each intermediary layer conductive pillar has an end face, and these end faces of these intermediary layer conductive pillars are different in height position. For example, the first intermediary layer conductive pillar 642 has an end face 642e, and the second intermediary layer conductive pillar 643 has an end face 643e, and the end face 642e and the end face 643e are different in height position (e.g., in the Z-axis direction). In addition, the end face 642e of the first intermediary layer conductive pillar 642 is connected to the bump 6111 through the solder 651, and the end face 643e of the second intermediary layer conductive pillar 643 is connected to the pad 4211 through the solder 652.

[0099] like Figure 6As shown, the chip module 620 includes a plurality of chips (e.g., a first chip 421, a second chip 222, and a third chip 223). The first chip 421 is disposed on the first substrate 611 and has a first side surface 421s. The second chip 222 is disposed on the first chip 421 and includes a first protrusion 222P protruding relative to the first side surface 421s. The second chip 222 has a second side surface 222s. The third chip 223 is disposed on the second chip 222 and includes a second protrusion 223P protruding relative to the second side surface 222s.

[0100] like Figure 6 As shown, since the second chip 222 is shifted to the left relative to the first chip 421 , the upper surface of the first chip 421 is exposed, and the interposer module 640 is connected to the exposed first chip 421 .

[0101] like Figure 6 As shown, one of the interposer conductive pillars is connected to the first substrate 611, one of the first chip 421 and the second chip 222, and the other of the interposer conductive pillars is connected to the other of the first substrate 611, the first chip 421 and the second chip 222. For example, the first interposer conductive pillar 642 is connected to the first substrate 611 through the solder 651, and the second interposer conductive pillar 643 is connected to the first chip 421 through the solder 652.

[0102] Please refer to Figure 7 , which is a cross-sectional view of a semiconductor device 700 according to another embodiment of the present invention. The semiconductor device 700 includes a substrate module 510, a chip module 720, a molding compound 130, an interposer module 740, and at least one solder (eg, solder 651-652).

[0103] The semiconductor device 700 of this embodiment includes similar or identical technical features to the semiconductor device 600, and one difference is that the interposer module 740 of the semiconductor device 700 is structurally different from the interposer module 640. Compared with the interposer module 640, the interposer module 740 includes more interposer conductive pillars.

[0104] like Figure 7As shown, the chip module 720 includes a plurality of chips (e.g., a first chip 421, a second chip 722, a third chip 723, and a fourth chip 724). The interposer module 740 includes a second substrate 741, interposer conductive pillars 642, 643, 744, 745, and 746. The interposer conductive pillars 642, 643, 744, 745, and 746 are connected to the first substrate 511, the first chip 421, the second chip 722, the third chip 723, and the fourth chip 724, respectively. The connection method of the interposer conductive pillar 643 and the first chip 421 has been described above. The connection method of the interposer conductive pillar 744 and the second chip 722, the connection method of the interposer conductive pillar 745 and the third chip 723, and the connection method of the interposer conductive pillar 746 and the fourth chip 724 are similar or the same as the connection method of the interposer conductive pillar 643 and the first chip 421, and will not be repeated here.

[0105] Please refer to Figures 8A-8B. Fig. 8A is a three-dimensional schematic diagram of a semiconductor device 800 according to another embodiment of the present invention, and Figure 8B yes Fig. 8A The semiconductor device 800 includes a substrate module 810, a chip module 820, a molding compound 130 and an interposer module 840.

[0106] The interposer module 840 includes a second substrate 841 and at least one interposer conductive pillar (e.g., at least one first interposer conductive pillar 842, at least one second interposer conductive pillar 843, and at least one third interposer conductive pillar 844), at least one conductive via (e.g., vias 845 and 846), and at least one circuit layer (e.g., at least one first circuit layer 847 and at least one second circuit layer 848). One of the first interposer conductive pillars 842, one of the second interposer conductive pillars 843, and / or one of the third interposer conductive pillars 844 may be connected to one of the first circuit layers 847, and extend from the first circuit layer 847 toward the substrate module 810, and be connected to the substrate module 810. Another one of the first intermediary layer conductive pillars 842, another one of the second intermediary layer conductive pillars 843, and / or another one of the third intermediary layer conductive pillars 844 can be connected to another one of the plurality of first circuit layers 847, and extend from the first circuit layer 847 toward the substrate module 810, and connected to the substrate module 810. Conductive vias 845 and 846 are formed inside the intermediary layer module 840, which connect the first circuit layer 847 and the second circuit layer 848, wherein the second circuit layer 848 and the first circuit layer 847 are different layers with a height difference. In an embodiment, the first circuit layer 847 is closer to the substrate module 810 than the second circuit layer 848 along the Z-axis direction. As described above, through the conductive vias, the first circuit layer, and the second circuit layer, two of the first intermediary layer conductive pillars, the second intermediary layer conductive pillars, and the third intermediary layer conductive pillars can be electrically connected, two of the plurality of first intermediary layer conductive pillars can be electrically connected, two of the plurality of second intermediary layer conductive pillars can be electrically connected, and / or two of the plurality of third intermediary layer conductive pillars can be electrically connected.

[0107] In summary, an embodiment of the present invention provides a semiconductor device. In one embodiment, the semiconductor device includes a substrate module and a chip module, wherein the substrate module includes a first substrate and a plurality of substrate conductive pillars, and these substrate conductive pillars protrude relative to a surface of the first substrate. The plurality of substrate conductive pillars have a height difference to connect the plurality of chips with a height difference in the chip module. In this way, without the need for silicon vias and wire bonds, the substrate conductive pillars connect the first substrate and the chip module along the thickness direction of the semiconductor device, which can not only shorten the electrical conduction path but also reduce the manufacturing cost. In another embodiment, the semiconductor device includes a substrate module, a chip module and an interposer module, wherein the interposer module includes a second substrate and a plurality of interposer conductive pillars, and these interposer conductive pillars protrude relative to a surface of the second substrate. The plurality of interposer conductive pillars have a height difference to connect the plurality of chips with a height difference in the chip module and / or the first substrate of the substrate module.

[0108] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.

Claims

1. A semiconductor device comprising: a first substrate; A first chip, disposed on the first substrate and having a first side surface; a second chip, disposed on the first chip and comprising a first protrusion protruding relative to the first side surface; A first substrate conductive column connects the first protrusion and the first substrate.

2. The semiconductor device according to claim 1, wherein the second chip has a second side, and the semiconductor device further comprises: a third chip, disposed on the second chip and comprising a second protrusion protruding relative to the second side surface; as well as A second substrate conductive column connects the second protrusion and the first substrate. 3 . The semiconductor device according to claim 2 , wherein the second substrate conductive pillar and the first substrate conductive pillar are different in height position.

4. The semiconductor device according to claim 1, further comprising: An intermediate layer module, comprising: a second substrate; and A plurality of intermediate layer conductive pillars are formed on the second substrate, and each of the intermediate layer conductive pillars has an end surface, and the end surfaces of the intermediate layer conductive pillars are different in height position; One of the intermediate layer conductive pillars is connected to the first substrate, one of the first chip and the second chip, and the other of the intermediate layer conductive pillars is connected to the other of the first substrate, the first chip and the second chip.

5. A semiconductor device comprising: A baseboard module, comprising: a first substrate; A plurality of substrate conductive pillars are formed on the first substrate and each of the substrate conductive pillars has an end surface, and the end surfaces of the substrate conductive pillars are different in height position; A chip module having a plurality of lower surfaces at different height positions; A first connector of the substrate conductive pillars is connected to a first one of the lower surfaces, and a second connector of the substrate conductive pillars is connected to a second one of the lower surfaces.

6. The semiconductor device according to claim 5, wherein the chip module comprises: A first chip having a first side surface; as well as a second chip including a first protrusion protruding relative to the first side surface, the first protrusion having the first of the lower surfaces; The first connector of the substrate conductive pillars connects the first protrusion and the first substrate.

7. The semiconductor device according to claim 6, wherein the second chip has a second side and further comprises: a third chip, disposed on the second chip and comprising a second protrusion protruding relative to the second side surface, the second protrusion having the second of the lower surfaces; The second one of the substrate conductive pillars connects the second protrusion and the first substrate.

8. The semiconductor device according to claim 6, further comprising: An intermediate layer module, comprising: a second substrate; and A plurality of intermediate layer conductive pillars are formed on the second substrate, and each of the intermediate layer conductive pillars has an end surface, and the end surfaces of the intermediate layer conductive pillars are different in height position; One of the intermediate layer conductive pillars is connected to the first substrate, one of the first chip and the second chip, and the other of the intermediate layer conductive pillars is connected to the other of the first substrate, the first chip and the second chip.

9. A semiconductor device comprising: a first substrate; a chip module, disposed on the first substrate and having a plurality of upper surfaces at different height positions; as well as An intermediate layer module, comprising: a second substrate; and A plurality of intermediate layer conductive pillars are formed on the second substrate, and each of the intermediate layer conductive pillars has an end surface, and the end surfaces of the intermediate layer conductive pillars are different in height position; A first one of the intermediate layer conductive pillars is connected to the first substrate, and a second one of the intermediate layer conductive pillars is connected to one of the upper surfaces.

10. The semiconductor device according to claim 9, wherein the q chip module comprises: a first chip including a protrusion; a second chip having a side surface; and The protruding portion of the first chip protrudes relative to the side surface of the second chip, and the second of the intermediate layer conductive pillars is connected to the protruding portion.

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