Hybrid substrate and method for manufacturing same

Abstract

The present technology is directed to hybrid substrates and methods of making the same. In various embodiments, the present technology provides a semiconductor device including a first circuit characterized by a first coefficient of thermal expansion (CTE) and a substrate characterized by a second CTE. The ratio of the first CTE to the second CTE is greater than or equal to 3: 5, which ensures harmonious thermal behavior, thereby improving yield and reducing warpage. In some embodiments, one or more circuit elements may be embedded in the substrate. Other embodiments are also present.

Description

[0001] Related Applications Cross Reference

[0002] This application claims priority to U.S. Provisional Application No. 63 / 517,747, filed on August 4, 2023, which is commonly owned and incorporated herein by reference for all purposes. Technical Field

[0003] The present technology is directed to semiconductor devices and methods of manufacturing. Background Art

[0004] Over the past few decades, semiconductor packaging materials and processes have continued to develop. With the advancement of high-performance computing and related applications, there is an urgent need for substrates that can meet the needs of high integration. Various approaches involve heterogeneous integration, which allows different types of devices (e.g., silicon and / or memory components) to be integrated on a single package. However, ensuring seamless communication, efficient and high-density wiring, and effectively integrating both active and passive components onto the substrate remains a challenging task.

[0005] Various methods for enhancing substrates have been explored, but have proven to be inadequate.It is important to recognize the need for new and improved substrates and processes for their manufacture. Summary of the invention

[0006] In one aspect, the present disclosure is directed to a semiconductor device, comprising: a first circuit comprising a silicon material, the first circuit being characterized by a first coefficient of thermal expansion; a substrate coupled to the first circuit, the substrate being characterized by a second coefficient of thermal expansion, the substrate comprising: a first layer coupled to the first circuit; a second layer coupled to the first layer, the second layer comprising a first wiring; a third layer coupled to the second layer, the third layer comprising a first through hole, the third layer being characterized by a third coefficient of thermal expansion, the third coefficient of thermal expansion being associated with the second coefficient of thermal expansion; and a fourth layer coupled to the third layer, the fourth layer comprising a second wiring; wherein a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than or equal to 3:5.

[0007] In another aspect, the present disclosure is directed to a semiconductor device, comprising: a first circuit, the first circuit being characterized by a first coefficient of thermal expansion; a substrate coupled to the first circuit, the substrate being characterized by a first thickness and a second coefficient of thermal expansion, the substrate comprising: a first layer coupled to the first circuit; a second layer coupled to the first layer, the second layer comprising a first wiring, and the second layer being characterized by a second thickness; a third layer coupled to the second layer, the third layer comprising a first through hole, the third layer being characterized by a third thickness, and the third thickness being greater than the second thickness; and a fourth layer coupled to the third layer, the fourth layer comprising a second wiring, the fourth layer being characterized by a fourth thickness, and the third thickness being greater than the fourth thickness; wherein the third thickness is greater than 60% of the first thickness.

[0008] In another aspect, the present disclosure is directed to a semiconductor device formed by a process, the process comprising: providing a substrate, the substrate comprising a first side and a second side; providing a wafer coupled to the second side; forming a first through hole in the substrate; forming a first layer coupled to the first through hole; forming a second layer coupled to the first layer, the second layer comprising a metal material; forming a third layer coupled to the first side, the third layer comprising a first dielectric material; forming a first wiring in the third layer, the first wiring comprising a metal material; forming a fourth layer coupled to the first layer, the fourth layer comprising a first connector; and detaching the wafer from the second side. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and to the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of a plurality of similar components. When a reference numeral is cited without specifying an existing sub-label, the reference numeral is intended to refer to all such plurality of similar components.

[0010] Figure 1 is a simplified diagram illustrating a semiconductor device having a substrate according to an embodiment of the present technology.

[0011] Figure 2 is a simplified diagram illustrating a substrate of a semiconductor device according to an embodiment of the present technology.

[0012] Figure 3 is a flowchart illustrating a method for manufacturing a substrate for a semiconductor device according to an embodiment of the present technology. DETAILED DESCRIPTION

[0013] The present technology is directed to semiconductor devices and manufacturing methods. In various embodiments, the present technology provides a semiconductor device comprising a first circuit characterized by a first coefficient of thermal expansion (CTE) and a substrate characterized by a second CTE. The ratio of the first CTE to the second CTE is greater than or equal to 3:5, which ensures harmonious thermal behavior, thereby improving the yield and reducing warpage. In some embodiments, one or more circuit elements may be embedded in the substrate. Other embodiments also exist.

[0014] As previously described, various approaches for semiconductor fabrication have proven inadequate to meet the demands of high computing applications. For example, some approaches involve using silicon interposers as substrates, which are constrained by the size of photomasks in photolithography, thus facing limitations in size and complexity. Additionally, due to their rigidity and suboptimal thermal conductivity, interposers offer limited utility in co-packaging scenarios, such as integrating both active and passive components with computing and memory units.

[0015] On the other hand, various technologies involve using organic substrates to provide support and electrical connections to integrated circuit (IC) chips. However, the significant difference in the coefficient of thermal expansion (CTE) between the IC chip and the organic substrate poses a challenge. The term "coefficient of thermal expansion" may refer to a measurement of the extent to which a material expands or contracts when subjected to a change in temperature. For example, an IC chip typically made of silicon may have a CTE of less than 3ppm / °C, while an organic substrate may have a higher CTE value ranging from 10ppm / °C to 20ppm / °C. This CTE mismatch may lead to potential warping and subsequent structural reliability challenges such as cracks, delamination, or solder joint failures.

[0016] In various embodiments, the present technology introduces systems and methods for producing hybrid substrates. For example, the hybrid substrate can be characterized by an asymmetric configuration that combines an interposer-like structure on one side with an organic substrate-like structure on the other side. By integrating the architectural features of silicon interposers and organic substrates, the hybrid substrate advantageously addresses the challenges of the current state of the art mask-limited interposers, allowing high-density wiring to meet the needs of high-performance applications. In addition, with CTE values ​​that closely match silicon IC chips and enhanced modulus, the substrate is more resistant to warping during manufacturing and deployment, thereby improving yield and reliability. Moreover, the hybrid substrate is well suited for co-packaging active and passive components with computing and memory devices to enhance performance.

[0017] The following description is presented to enable one skilled in the art to make and use the invention and to incorporate the invention into the context of a particular application. Various modifications and various uses in different applications will be readily apparent to one skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Therefore, it is not intended to limit the invention to the embodiments presented, but rather to give the invention the widest scope consistent with the principles and novel features disclosed herein.

[0018] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form (rather than in detail) in order to avoid obscuring the present invention.

[0019] The reader is advised to pay attention to all papers and documents filed concurrently with this specification and available for public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any accompanying claims, abstracts and drawings) may be replaced by alternative features serving the same, equivalent or similar purposes. Therefore, unless otherwise expressly stated, each disclosed feature is only an example of a series of generic equivalent or similar features.

[0020] In addition, any element in the technical solution that does not explicitly state a "means" for performing a specified function or a "step" for performing a specified function should not be interpreted as a "means" or "step" clause as provided in 35 U.S.C. Section 112, paragraph 6. Specifically, the use of "step" or "action" in the claims herein is not intended to refer to the provisions of 35 U.S.C. Section 112, paragraph 6.

[0021] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0022] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed near, or disposed in some other relative manner), it is understood that the element may be directly disposed relative to the other element (e.g., disposed directly on the other element) or there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct disposition does not exclude other instances in which there may be intervening elements.

[0023] Similarly, when an element is referred to herein as being "joined" to another element, it is understood that the element may be directly joined to the other element (without any intervening elements) or have intervening elements between the joined elements. In contrast, when an element is referred to as being "directly joined" to another element, it is understood that there are no intervening elements in the "direct" joining between the elements. However, the presence of direct joining does not exclude other forms of joining in which there may be intervening elements.

[0024] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intervening elements present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of directly coupled or connected layers does not exclude other connections in which there may be intervening elements.

[0025] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, the terms are only used to indicate the relative position and / or direction between various parts of an object and / or component.

[0026] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intervening processes may occur before and / or after any portion of the described process, and that various other procedures may be reordered, added, and / or omitted according to various embodiments.

[0027] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc. should be understood to be modified by the term "about" in all instances. In this application, the use of the singular includes the plural (unless otherwise specifically stated), and the use of the terms "and" and "or" means "and / or" (unless otherwise indicated). In addition, the use of the terms "including" and "having" and other forms (such as "includes, included", "has, have and had") should be considered non-exclusive. Moreover, unless otherwise specifically stated, terms such as "element" or "component" encompass both elements and components that include one unit and elements and components that include more than one unit.

[0028] As used herein, the phrase "at least one of..." preceding a list of items (with the terms "and" or "or" separating any of the items) modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of the items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where selection of "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is intended, it is expressly described as such.

[0029] One general aspect includes a semiconductor device including a first circuit, the first circuit including a silicon material, the first circuit being characterized by a first coefficient of thermal expansion. The semiconductor device further includes a substrate coupled to the first circuit, the substrate being characterized by a second coefficient of thermal expansion. The substrate includes a first layer coupled to the first circuit. The substrate further includes a second layer coupled to the first layer, the second layer including a first wire. The substrate further includes a third layer coupled to the second layer, the third layer including a first via, the third layer being characterized by a third coefficient of thermal expansion, the third coefficient of thermal expansion being associated with the second coefficient of thermal expansion. The substrate further includes a fourth layer coupled to the third layer, the fourth layer including a second wire. A ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than or equal to 3:5.

[0030] Embodiments may include one or more of the following features. The first layer includes a passivation material. The second layer includes a first dielectric material, and the first dielectric material includes an organic material. The fourth layer includes a second dielectric material, and the second dielectric material includes an inorganic material. The first wiring is coupled to the third layer and the second wiring is coupled to the third layer. The first circuit is coupled to the first layer via a first joint, the first layer includes a first connector, and the first connector is coupled to the first joint. The first circuit includes a memory, a thermal component, a mechanical component, an optical component, or an electrical component. The third layer includes a glass material, a ceramic material, a diamond material, or a silicon material. The first wiring includes a second through hole, and the second through hole includes a metal material. The second wiring includes a third through hole, and the third through hole includes a metal material. The second thermal expansion coefficient is less than 10ppm / ℃.

[0031] According to another embodiment, the present technology provides a semiconductor device including a first circuit, the first circuit being characterized by a first coefficient of thermal expansion. The semiconductor device further includes a substrate coupled to the first circuit, the substrate being characterized by a first thickness and a second coefficient of thermal expansion. The substrate includes a first layer coupled to the first circuit. The substrate further includes a second layer coupled to the first layer, the second layer including a first wiring, and the second layer being characterized by a second thickness. The substrate further includes a third layer coupled to the second layer, the third layer including a first via, the third layer being characterized by a third thickness, and the third thickness being greater than the second thickness. The substrate further includes a fourth layer coupled to the third layer, the fourth layer including a second wiring, the fourth layer being characterized by a fourth thickness, and the third thickness being greater than the fourth thickness. The third thickness is greater than 60% of the first thickness.

[0032] The embodiment may include one or more of the following features. The first circuit includes a memory, a thermal component, a mechanical component, an optical component, or an electrical component. The third layer includes a glass material, a ceramic material, a diamond material, or a silicon material. The ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 3:5. The third layer further includes a second circuit, and the second circuit includes a memory, a thermal component, a mechanical component, an optical component, or an electrical component. The second thermal expansion coefficient is less than 10ppm / °C. The first wiring is coupled to the third layer. The second thickness is less than or equal to 30um, and the fourth thickness is less than or equal to 30um. The third thickness is greater than 100um and less than 2000um.

[0033] According to another embodiment, the present technology provides a semiconductor device formed by a process, the process including providing a substrate, the substrate including a first side and a second side. The process further includes providing a wafer coupled to the second side. The process further includes forming a first through hole in the substrate. The process further includes forming a first layer coupled to the first through hole. The process further includes forming a second layer coupled to the first layer, the second layer including a metal material. The process further includes forming a third layer coupled to the first side, the third layer including a first dielectric material. The process further includes forming a first wiring in the third layer, the first wiring including a metal material. The process further includes forming a fourth layer coupled to the first layer, the fourth layer including a first connector. The process further includes detaching the wafer from the second side. In various embodiments, the process further includes embedding a circuit in the substrate.

[0034] Figure 1 1 is a simplified diagram illustrating a semiconductor device 100 having a substrate according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. As shown, the semiconductor device 100 includes a circuit 102 (e.g., the first circuit set forth in technical solution 1). For example, the circuit 102 may include an integrated circuit, such as a microprocessor, a memory chip, a digital signal processor, a system-on-chip (SoC), and the like.

[0035] Depending on the implementation, the circuit 102 may include, but is not limited to, memory, thermal components, mechanical components, optical components, or electrical components, active and passive devices, die stacks, and the like. For example, the term "memory" may refer to a device capable of storing data for immediate or future use. The memory may include, but is not limited to, static random access memory (SRAM), dynamic random access memory (DRAM), or hybrid bandwidth memory (HBM), a voltage regulator, a capacitor, an inductor, and the like. The term "thermal component" may refer to a device that generates, transmits, or dissipates heat. The thermal component may include, but is not limited to, a heater, a heat sink, a thermoelectric generator, a heat pad, and the like. The term "mechanical component" may refer to a device that contributes to the physical and structural integrity or mobile functionality within a semiconductor device. The mechanical component may include, but is not limited to, a microelectromechanical system (MEMS) device, an actuator, a sensor, an oscillator, and the like. The term "optical component" may refer to a device that manages, generates, or detects light, including, but not limited to, a device that converts electrons into photons or vice versa, or a device that generates or transmits laser light. Optical components may include, but are not limited to, lenses, waveguides, photonic modulators, photonic integrated circuits, II-V semiconductors, light sources, photodetectors, and the like. The term "electrical component" may refer to a device that conducts, isolates, or switches electrical power. An electrical component may be active or passive. Active electrical components may include, but are not limited to, transistors, diodes, integrated circuits, and the like. Passive electrical components may include, but are not limited to, resistors, capacitors, inductors, and the like.

[0036] In various examples, the circuit 102 is characterized by a first coefficient of thermal expansion (CTE). The term "coefficient of thermal expansion" may refer to a measurement of the extent to which a material expands or contracts when subjected to a change in temperature. CTE may be expressed in parts per million per degree Celsius (ppm / °C). It may be measured using various methods, such as dilatometry, interferometry, thermomechanical analysis, strain gauges, direct image correlation (DIC), and the like. It should be appreciated that CTE is an important factor affecting the reliability and performance of semiconductor packages because differences in CTE values ​​between adjacent materials may introduce thermal stresses and deformations, leading to potential reliability issues. The CTE value of a material may be associated with various factors, such as material composition, microstructure, impurities, temperature range, and the like. In various embodiments, the circuit 102 includes a silicon material and the first CTE may be modulated and in some cases may be less than 3ppm / °C.

[0037] According to some embodiments, semiconductor device 100 further includes a substrate 106 coupled to circuit 102. For example, substrate 106 is coupled to circuit 102 through joint 104. The term "substrate" may refer to a material that provides support and electrical connection to electronic components. The substrate may also provide a means for connecting an IC chip (e.g., circuit 102) to an external circuit system (e.g., a PCB board). Substrate 106 may include, but is not limited to, one or more materials such as silicon, organic materials, ceramics, diamond, or any combination thereof. The term "joint" may refer to an electrical or mechanical connection between an IC chip and a substrate. Joint 104 may include a solder-based joint (e.g., a microbump) or a solderless joint (e.g., a hybrid or direct copper bond).

[0038] Depending on the implementation, the substrate 106 may be a hybrid substrate. The term "hybrid" indicates that the substrate combines the features and properties of multiple different types of materials and / or structures. In some examples, the substrate 106 includes a first structure (e.g., a quasi-interposer structure) on a first side (e.g., a front side) and a second structure (e.g., a quasi-organic substrate structure) on a second side (e.g., a back side). The first side may be opposite to the second side, or vice versa. The first structure may provide a dense conductive network that allows high-density wiring, thereby ensuring efficient communication across the semiconductor device 100. In some cases, the first structure may have the electrical and thermal properties of silicon, which ensures efficient signal transmission and heat dissipation. The second structure may be suitable for integration and co-packaging of both active and passive components, thereby providing flexibility and adaptability for enhancing overall system performance.

[0039] In various implementations, substrate 106 can be characterized by a second CTE. For example, the ratio of the first CTE to the second CTE is greater than or equal to 3:5. By closely matching the CTEs of substrate 106 and circuit 102, the risks associated with thermal stresses, such as warping or delamination, are significantly mitigated, thereby improving the reliability and life of semiconductor device 100. In some cases, substrate 106 can be coupled to other components (e.g., a printed circuit board) via mechanisms such as solder balls, bumps, and the like.

[0040] Figure 2 2 is a simplified diagram illustrating a substrate 200 of a semiconductor device according to an embodiment of the present technology. This diagram is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications.

[0041] As shown, substrate 200 includes layer 202 (e.g., the first layer set forth in technical solution 1). For example, layer 202 may be used as a passivation layer. The term "passivation layer" may refer to a material layer deposited on the surface of a semiconductor device to protect it from environmental factors (e.g., moisture, oxygen, pollutants, etc.). Layer 202 may include a passivation material, which may include but is not limited to one or more materials, such as organic materials (e.g., polyimide, polyparaxylene, benzocyclobutene, etc.), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), and the like.

[0042] Depending on the implementation, layer 202 may be configured to couple to external circuitry (e.g., Figure 1 For example, layer 202 may be connected via a first connector (e.g., Figure 1 The connector 104 of the semiconductor package is coupled to an external circuit. Layer 202 may include a connector 204 (e.g., the first connector described in technical solution 5). The term "connector" may refer to a mechanism or structure that realizes electrical or physical connection between different components (e.g., between an external circuit and layer 202). Connectors may include, but are not limited to, ultra-fine pitch bumps (uBumps), hybrid copper bonding (HCBs), wire bonding, flip chip bonding, and the like. For example, the term "uBump" or "ultra-fine pitch bumps" may refer to a type of solder bump having a very small diameter (e.g., less than 25um) and a pitch (e.g., less than 40um) and can be used to connect an IC chip in a semiconductor package to a substrate. The term "hybrid copper bonding" may refer to a mechanism or structure configured to connect a semiconductor die or device. Hybrid copper bonding may include bonding between copper or other metals (e.g., gold, etc.) and a dielectric material, which may be organic (e.g., small molecules or monomers, etc.) or inorganic (e.g., silicon oxide, other metal oxides, etc.).

[0043] In some embodiments, layer 210 (e.g., the second layer set forth in technical solution 1) may be coupled to layer 202. For example, layer 210 may include a dielectric layer. The term "dielectric layer" may refer to a non-conductive material layer used to isolate different electrical components and pathways to ensure that current is directed as intended. Layer 210 may include a first dielectric material, which includes but is not limited to one or more materials, such as organic materials (e.g., deposited films, polyimide or other polymer-based dielectrics), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), and the like. The composition, thickness, and number of dielectric layers may be tailored to meet specific requirements and may vary depending on the application.

[0044] In various embodiments, layer 210 may include a first wiring. The first wiring may be coupled to layer 212. The term "wiring" may refer to a conductive path configured to facilitate electrical connection between components or regions in a semiconductor device. Wiring may be made using a variety of materials such as copper, aluminum, gold, etc. For example, the first wiring may include a through hole 206 (e.g., the second through hole stated in technical solution 8), which may be filled with various materials, including but not limited to copper, aluminum, gold, etc. In some cases, copper electroplating may be used to make through hole 206. Depending on the implementation, the taper ratio of through hole 206 may vary between 80% and 100%. For example, a taper ratio of 80% may indicate that the diameter of the through hole at the top is 80% of the diameter of the through hole at the bottom. In some examples, the first wiring includes a conductive trace 208. The term "conductive trace" may refer to a conductive material strip used to connect electrical components. The conductive trace may include but is not limited to one or more materials, such as copper, aluminum, gold, etc. The size and configuration (eg, width, length, or thickness) of conductive traces 208 may vary depending on the application.

[0045] According to some embodiments, layer 212 (e.g., the third layer stated in technical solution 1) may be coupled to layer 210. Layer 212 may include, but is not limited to, one or more materials, such as glass, ceramic, diamond, silicon, and the like. For example, layer 212 may include a via 214 (e.g., the first via stated in technical solution 1). The term "via" may refer to an opening or hole in a substrate that allows electrical connection between different layers of the substrate. The via may include, but is not limited to, through-silicon vias (TSVs), through-glass vias (TGVs), through-ceramic vias (TCVs), through-diamond vias (TDVs), and the like. Various techniques including, but not limited to, laser drilling, mechanical drilling, chemical etching, and the like may be used to form the via 214. For example, depending on the drilling method, the diameters of the via 214 at opposite sides may be the same or different. In some cases, the via 214 may be drilled from opposite sides (e.g., the top side and the bottom side) of the layer 212, which may produce a tapered via. Depending on the particular application, the taper ratio of the via 214, which may be defined as the difference between the top region and the middle or bottom region of the via, may be adjusted. For example, the taper ratio of the via 214 may range from 80% to 100%. In various examples, the via 214 may be filled with a conductive material (e.g., copper, tungsten, titanium, aluminum, gold, silver, tin, nickel, lead, etc.) to ensure conductivity and structural integrity.

[0046] In some embodiments, layer 212 further includes layer 216 coupled to via 214 and layer 218 coupled to layer 216. For example, layer 218 may include a seed layer configured to promote copper deposition to ensure optimal connectivity and conductivity within substrate 200. Layer 218 may include, but is not limited to, one or more materials, such as titanium nitride, tungsten, silicon oxide, copper, and the like. Layer 216 may include a via plating layer, which may be deposited on the wall of a via (e.g., via 214) using an electrochemical process. Layer 216 may be configured to create a conductive path between different layers and fill via 214 with a metal material. This may improve the electrical performance, reliability, and thermal management of semiconductor devices. Layer 216 may include, but is not limited to, one or more materials, such as copper, an organic resin, and the like. In some cases, layer 212 further includes a circuit 226 (e.g., the second circuit set forth in technical solution 14). Circuit 226 may include active and / or passive components that may be embedded within the substrate (e.g., layer 212) to enhance the signal integrity and overall performance of the semiconductor device. For example, circuit 226 may include, but is not limited to, memory, thermal components, mechanical components, optical components, electrical components, and the like.

[0047] In various examples, layer 226 (e.g., the fourth layer set forth in technical solution 1) can be coupled to layer 212. For example, layer 226 can include a dielectric layer. Layer 210 can include a second dielectric material, which includes but is not limited to one or more materials, such as organic materials (e.g., deposited films, polyimide or other polymer-based dielectrics), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), etc. The composition, thickness, and number of dielectric layers can be tailored to meet specific requirements and can vary depending on the application.

[0048] In various embodiments, layer 226 may include a second wiring. The second wiring may be coupled to layer 212. For example, the second wiring may include a through hole 220 (e.g., the second through hole stated in technical solution 8), which may be filled with various materials, including but not limited to copper, aluminum, gold, etc. Through hole 220 may be made using copper plating. Depending on the implementation, the taper ratio of through hole 220 may vary between 80% and 100%. In some examples, the second wiring includes a conductive trace 222. The conductive trace may include but not limited to one or more materials, such as copper, aluminum, gold, etc. The size and configuration (e.g., width, length, or thickness) of conductive trace 222 may vary depending on the application. In some embodiments, layer 226 may be coupled to layer 224, which may include a solder resist material. The term "solder resist material" may refer to a material layer applied to the surface of a printed circuit board (PCB) and a semiconductor package to protect a circuit pattern from solder and other contaminants. The solder resist material may include but is not limited to one or more materials, such as epoxy resin, acrylic resin, polyimide resin, etc.

[0049] As previously described, the substrate 200 and external circuits (eg, Figure 2 Closely matching the CTE values ​​of the circuit 102 ... Layer 226 is characterized by a fourth thickness, which may be less than or equal to 30 um.

[0050] In various embodiments, the substrate 200 is characterized by an asymmetric configuration. The term "asymmetric" indicates that different sections or regions of the substrate 200 have different properties or configurations. In various examples, the first region 228 and the second region 230 are located at opposite sides of the substrate 200. The first region 228 may be characterized by features associated with a silicon interposer. For example, the first region 228 provides fine-pitch electrical interconnects, which enables high-density wiring and efficient connections across semiconductor devices. The second region 230 may be characterized by features associated with an organic substrate. For example, the second region 230 provides flexibility and enhanced thermal management capabilities, thereby allowing seamless integration of both passive and active components. This configuration improves CTE matching by strategically combining the rigidity of silicon-rich regions with the flexibility of organic-rich regions, which together minimize thermal stress and mitigate risks such as delamination and warping. The asymmetric configuration ensures high-density electrical interconnects and optimal thermal management while seamlessly aligning with existing assembly processes. For example, the fabrication of the substrate 200 can be achieved by masking one side, processing the other side, and then repeating a similar process on the other side.

[0051] Figure 3 is a flow chart illustrating a method 300 for manufacturing a substrate for a semiconductor device according to an embodiment of the present technology. This figure is merely an example, which should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, one or more steps may be added, deleted, repeated, modified, substituted, overlapped, and / or rearranged, and should not limit the scope of the claims.

[0052] In some embodiments, method 300 includes step 302 of providing a substrate, the substrate including a first side and a second side. For example, the first side and the second side may be opposite to each other. Figure 2 The substrate 200 of the present invention may include a first side including a top portion or a front side of the substrate and a second side including a bottom portion or a back side of the substrate. The substrate may include, but is not limited to, one or more materials such as glass, ceramic, diamond, silicon, etc.

[0053] In step 304, method 300 includes providing a wafer coupled to the second side. The wafer may be a carrier wafer. The term "carrier" or "carrier wafer" may refer to a material or device that holds and protects a semiconductor package during processing, storage, or transportation. Depending on the packaging technology and application, there are different types of wafers. For example, a wafer may include one or more materials, such as organic materials, core materials, glass materials, and / or other materials. Depending on the specific application, a wafer may have properties such as heat dissipation capabilities, identification codes, alignment marks, or other features. For example, a wafer may be designed and manufactured to provide structural rigidity and support the formation and processing of a semiconductor substrate.

[0054] In step 306, method 300 includes forming a first via in the substrate. The first via may include, but is not limited to, a through silicon via (TSV), a through glass via (TGV), a through ceramic via (TCV), a through diamond via (TDV), etc. Depending on the implementation, the first via may be formed using one or more techniques such as laser drilling, mechanical drilling, chemical etching, etc. In various examples, the first via may be filled with a conductive material (e.g., copper, tungsten, titanium, aluminum, gold, silver, tin, nickel, lead, etc.) to ensure conductivity and structural integrity.

[0055] In step 308, method 300 includes forming a first layer coupled to the first via. For example, the first layer may include a seed layer configured to promote copper deposition to ensure optimal connectivity and conductivity within the substrate. The first layer may include, but is not limited to, one or more materials such as titanium nitride, tungsten, silicon oxide, copper, and the like.

[0056] In step 310, method 300 includes forming a second layer coupled to the first layer. In some cases, the second layer includes a metal material. The second layer may include a through-hole plating layer that may be deposited on a wall of a through-hole (e.g., a first through-hole) using an electrochemical process. The second layer may be configured to create a conductive path between different layers and fill the first through-hole with a metal material. The second layer may include, but is not limited to, one or more materials such as copper, an organic resin, and the like.

[0057] In step 312, method 300 includes forming a third layer coupled to the first side. The third layer may include a first dielectric material, which may include, but is not limited to, one or more materials such as organic materials (e.g., built-up films, polyimide or other polymer-based dielectrics), inorganic materials (e.g., silicon nitride, silicon dioxide, silicon carbide, etc.), and the like.

[0058] In step 314, method 300 includes forming a first wiring in the third layer. For example, the first wiring includes a metal material. The first wiring can be made of a variety of materials such as copper, aluminum, gold, etc. For example, the first wiring can include one or more conductive pads, conductive traces, conductive vias, conductive microbumps, conductive solder balls, conductive pillars or pillars, and / or other suitable connectors or interconnects.

[0059] In step 316, method 300 includes forming a fourth layer coupled to the first layer. The fourth layer includes a first connector. The first connector may be configured to establish an electrical or physical connection between the substrate and the IC chip. The first connector may include, but is not limited to, ultra-fine pitch bumps, hybrid copper bonding, wire bonding, flip chip bonding, and the like. In step 318, method 300 includes detaching the wafer from the second side. In various implementations, method 300 further includes embedding a circuit in the substrate. The circuit may include active and / or passive components, which may be configured to enhance the signal integrity and overall performance of the semiconductor device. For example, the circuit may include, but is not limited to, a memory, a thermal component, a mechanical component, an optical component, an electrical component, and the like.

[0060] While the above is a comprehensive description of specific embodiments, various modifications, alternative constructions and equivalents may be used. Therefore, the above description and illustrations should not be taken as limiting the scope of the invention, which is defined by the appended claims.

Claims

1. A semiconductor device comprising: a first circuit comprising silicon material, the first circuit being characterized by a first coefficient of thermal expansion; a substrate coupled to the first circuit, the substrate being characterized by a second coefficient of thermal expansion, the substrate comprising: a first layer coupled to the first circuit; a second layer coupled to the first layer, the second layer comprising a first wiring; a third layer coupled to the second layer, the third layer comprising a first through hole, the third layer being characterized by a third coefficient of thermal expansion, the third coefficient of thermal expansion being associated with the second coefficient of thermal expansion; and a fourth layer coupled to the third layer, the fourth layer comprising a second wiring; The ratio of the first thermal expansion coefficient to the second thermal expansion coefficient is greater than or equal to 3:

5. The semiconductor device of claim 1 , wherein the first layer comprises a passivation material.

3. The semiconductor device according to claim 1, wherein: The second layer comprises a first dielectric material, and the first dielectric material comprises an organic material; and The fourth layer includes a second dielectric material, and the second dielectric material includes an inorganic material. 4 . The semiconductor device according to claim 1 , wherein the first wire is coupled to the third layer and the second wire is coupled to the third layer. 5 . The semiconductor device of claim 1 , wherein the first circuit is coupled to the first layer via a first connection, the first layer includes a first connector, and the first connector is coupled to the first connection. 6 . The semiconductor device of claim 1 , wherein the first circuit comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component. 7 . The semiconductor device according to claim 1 , wherein the third layer comprises a glass material, a ceramic material, a diamond material, or a silicon material.

8. The semiconductor device according to claim 1, wherein: The first wiring includes a second through hole, and the second through hole includes a metal material; and The second wiring includes a third through hole, and the third through hole includes a metal material. 9 . The semiconductor device according to claim 1 , wherein the second thermal expansion coefficient is less than 10 ppm / ° C.

10. A semiconductor device comprising: a first electrical circuit characterized by a first coefficient of thermal expansion; a substrate coupled to the first circuit, the substrate being characterized by a first thickness and a second coefficient of thermal expansion, the substrate comprising: a first layer coupled to the first circuit; a second layer coupled to the first layer, the second layer comprising a first wire, and the second layer being characterized by a second thickness; a third layer coupled to the second layer, the third layer comprising a first through hole, the third layer being characterized by a third thickness, and the third thickness being greater than the second thickness; and a fourth layer coupled to the third layer, the fourth layer comprising a second wiring, the fourth layer being characterized by a fourth thickness, the third thickness being greater than the fourth thickness; The third thickness is greater than 60% of the first thickness. 11 . The semiconductor device of claim 10 , wherein the first circuit comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component. 12 . The semiconductor device according to claim 10 , wherein the third layer comprises a glass material, a ceramic material, a diamond material, or a silicon material. 13 . The semiconductor device according to claim 12 , wherein a ratio of the first coefficient of thermal expansion to the second coefficient of thermal expansion is greater than or equal to 3:

5.

14. The semiconductor device of claim 10, wherein the third layer further comprises a second circuit, and the second circuit comprises a memory, a thermal component, a mechanical component, an optical component, or an electrical component.

15. The semiconductor device according to claim 10, wherein the second thermal expansion coefficient is less than 10 ppm / °C. The semiconductor device according to claim 10 , wherein the first wire is coupled to the third layer. 17 . The semiconductor device according to claim 10 , wherein the second thickness is less than or equal to 30 um, and the fourth thickness is less than or equal to 30 um. The semiconductor device according to claim 10 , wherein the third thickness is greater than 100 um and less than 2000 um.

19. A semiconductor device formed by a process, the process comprising: providing a substrate, the substrate comprising a first side and a second side; providing a wafer coupled to the second side; forming a first through hole in the substrate; forming a first layer coupled to the first via; forming a second layer coupled to the first layer, the second layer comprising a metallic material; forming a third layer coupled to the first side, the third layer comprising a first dielectric material; forming a first wiring in the third layer, the first wiring comprising a metal material; forming a fourth layer coupled to the first layer, the fourth layer comprising a first connector; and The wafer is detached from the second side.

20. The semiconductor device of claim 19, wherein the process further comprises embedding circuitry in the substrate.

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