Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging method comprises the steps: providing a bearing substrate which comprises a bearing surface; forming a plurality of grooves in the bearing surface, wherein the grooves comprise a first groove and a second groove which are adjacent to each other; providing a first chip; placing and attaching a first chip in the first groove; providing a chip set; a chip set is placed in the second groove and attached to the second groove; providing an interconnection chip, wherein the interconnection chip comprises a bonding surface; and an interconnection chip is bonded on the first chip and the chip set, the bonding surface is arranged opposite to the first chip and the chip set, and the interconnection chip is electrically connected with the first chip and the chip set. According to the embodiment of the invention, the performance of the packaging structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging, and in particular to a packaging structure and a packaging method. Background Art

[0002] Conventional chip manufacturing technologies are being pushed to their limits in terms of the size of a single chip. However, applications are eager to use the latest technology to achieve the capabilities of large-scale integrated circuits, and achieving high-speed and small-volume interconnections between chips is a major challenge.

[0003] One current solution is to use a smaller integrated circuit of a silicon bridge (Si Bridge) chip embedded in a silicon substrate to interconnect chips through the silicon bridge chip, thereby providing a heterogeneous chip package.

[0004] However, the performance of the current packaging structure still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method to improve the performance of the packaging structure.

[0006] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a carrier substrate, including a carrier surface; a plurality of grooves, located in the carrier surface, the plurality of grooves including adjacent first grooves and second grooves; a first chip, placed and attached in the first groove; a chipset, placed and attached in the second groove; an interconnection chip, bonded to the first chip and the chipset; the interconnection chip includes a bonding surface, the bonding surface is arranged opposite to the first chip and the chipset, and the interconnection chip electrically connects the first chip and the chipset.

[0007] Correspondingly, an embodiment of the present invention also provides a packaging method, comprising: providing a carrier substrate, comprising a carrier surface; forming a plurality of grooves in the carrier surface, comprising adjacent first grooves and second grooves; providing a first chip; placing and bonding the first chip in the first groove; providing a chipset; placing and bonding the chipset in the second groove; providing an interconnection chip, the interconnection chip comprising a bonding surface; bonding the interconnection chip to the first chip and the chipset, the bonding surface being arranged opposite to the first chip and the chipset, and the interconnection chip electrically connecting the first chip and the chipset.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the packaging structure provided by an embodiment of the present invention, a plurality of grooves are arranged in the carrying surface of the carrying substrate, including adjacent first grooves and second grooves, a first chip is placed and fitted in the first groove, a chipset is placed and fitted in the second groove, an interconnection chip is bonded to the first chip and the chipset to electrically connect the first chip and the chipset, so that high-density and high-speed communication between the first chip and the chipset can be achieved through the interconnection chip, and by embedding the first chip and the chipset in the carrying substrate, it is also beneficial to improve the packaging reliability.

[0010] In the packaging method provided by an embodiment of the present invention, a plurality of grooves are formed in the carrying surface of the carrying substrate, including adjacent first grooves and second grooves, and then a first chip is placed and bonded in the first groove, a chipset is placed and bonded in the second groove, and an interconnection chip is bonded on the first chip and the chipset, the interconnection chip electrically connects the first chip and the chipset, so that high-density and high-speed communication between the first chip and the chipset can be achieved through the interconnection chip, and by embedding the first chip and the chipset in the carrying substrate, it is also beneficial to improve the packaging reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural schematic diagram of an embodiment of a packaging structure of the present invention;

[0012] Figures 2 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention. DETAILED DESCRIPTION

[0013] As can be seen from the background technology, the performance of the current packaging structure needs to be improved.

[0014] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, wherein a plurality of grooves are arranged in the carrying surface of the carrying substrate, including adjacent first grooves and second grooves, a first chip is placed and fitted in the first groove, a chipset is placed and fitted in the second groove, an interconnection chip is bonded to the first chip and the chipset to electrically connect the first chip and the chipset, so that high-density and high-speed communication between the first chip and the chipset can be achieved through the interconnection chip, and by embedding the first chip and the chipset in the carrying substrate, it is also beneficial to improve the packaging reliability.

[0015] In order to solve the technical problem, an embodiment of the present invention further provides a packaging method, forming a plurality of grooves in a carrying surface of a carrying substrate, including adjacent first grooves and second grooves, and then placing and bonding a first chip in the first groove, placing and bonding a chipset in the second groove, and bonding an interconnection chip on the first chip and the chipset, wherein the interconnection chip electrically connects the first chip and the chipset, thereby enabling high-density and high-speed communication between the first chip and the chipset to be achieved through the interconnection chip, and embedding the first chip and the chipset in the carrying substrate is also beneficial to improving packaging reliability.

[0016] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0017] refer to Figure 1 , showing a schematic structural diagram of an embodiment of a packaging structure of the present invention.

[0018] like Figure 1 As shown, in this embodiment, the packaging structure includes: a carrier substrate 100, including a carrier surface 100a; a plurality of grooves 150, located in the carrier surface 100a, and the plurality of grooves 150 include adjacent first grooves 101 and second grooves 102; a first chip 10, placed and attached in the first groove 101; a chipset 200, placed and attached in the second groove 102; an interconnection chip 30, bonded to the first chip 10 and the chipset 200; the interconnection chip 30 includes a bonding surface 301, and the bonding surface 301 is arranged opposite to the first chip 10 and the chipset 200, and the interconnection chip 30 electrically connects the first chip 10 and the chipset 200.

[0019] The carrier substrate 100 is used to form a plurality of grooves 150 to accommodate the first chip 10 and the chipset 200. The carrier substrate 100 is also used to provide a process operation platform for bonding the interconnected chips 30 on the first chip 10 and the chipset 200. Specifically, the carrier surface 100a is used to provide a process operation platform.

[0020] In this embodiment, the carrier substrate 100 is a carrier wafer. In other embodiments, the carrier substrate may also be other types of substrates. In this embodiment, the material of the carrier substrate 100 may include one or more of silicon, glass, silicon oxide, and aluminum oxide.

[0021] The plurality of grooves 150 are used to provide space for accommodating the first chip 10 and the chip set 200 .

[0022] The first groove 101 is used to accommodate the first chip 10 , and the second groove 102 is used to accommodate the chipset 200 .

[0023] Accordingly, in this embodiment, the depth of the groove 150 is determined according to the thickness of the first chip 10 and the chipset 200 to ensure that the first groove 101 and the second groove 102 can provide sufficient space for accommodating the first chip 10 and the chipset 200 respectively.

[0024] Accordingly, in this embodiment, along a direction parallel to the carrying surface 100a, the size of the groove 150 is determined according to the area of ​​the first chip 10 and the chipset 200 to ensure that the first groove 101 and the second groove 102 can provide sufficient space for accommodating the first chip 10 and the chipset 200 respectively.

[0025] The first chip 10 is placed and attached to the first groove 101, so that the first chip 10 is contained and fixed in the first groove 101, so as to realize the package integration with the chipset 200, and also help save space. The first chip 10 is also electrically connected to the chipset 200 through the interconnection chip 30.

[0026] In this embodiment, the first chip 10 is a first logic chip, which is used to perform logic control on the chipset 200. Specifically, the first logic chip can be a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip or a SoC (System on Chip) chip.

[0027] In this embodiment, the first chip 10 includes adjacent first regions (not labeled) and second regions (not labeled), the first regions are used for bonding the interconnection chips 30 , and the second regions are used for forming conductive pillars 130 .

[0028] In this embodiment, the first chip 10 includes a first surface (not marked) and a second surface (not marked) relative to each other. The second surface of the first chip 10 is attached to the first groove 101 to expose the first surface, so as to achieve bonding between the first surface of the first chip 10 and the interconnection chip 30.

[0029] In this embodiment, the first surface is the back surface of the first chip 10, and the second surface is the front surface of the first chip 10. The front surface of the first chip 10 refers to the side of the first chip 10 facing the device, and the back surface of the first chip 10 refers to the side of the first chip 10 facing away from the device.

[0030] In this embodiment, one or more metal layers (not shown) are formed on the front side of the first chip 10 so as to bond an interconnection chip on a first area on the front side of the first chip 10, and a conductive column is formed on a second area on the front side of the first chip 10 so that the first chip 10 can be electrically connected to the interconnection chip 30 and to the conductive column 130 through the metal layer on the front side of the chip.

[0031] In this embodiment, in the step of placing and bonding the first chip 10 in the first groove 101, the top surface of the first chip 10 is flush with the carrying surface 100a, thereby improving the flatness of the top surfaces of the first chip 10 and the carrying surface 100a, facilitating the setting of the packaging layer 110 with a higher top surface flatness, and further providing a flat surface for forming an interconnection structure layer 120 with a high interconnection density and a small pitch.

[0032] More specifically, in this embodiment, the first surface of the first chip 10 is flush with the carrying surface 100 a.

[0033] In this embodiment, the packaging structure further includes: a first adhesive layer 111 located between the first chip 10 and the sidewall and bottom of the first groove 101 .

[0034] The first adhesive layer 111 is used to improve the adhesion between the sidewall and bottom of the first groove 101 and the first chip 10, and fix the first chip 10 in the first groove 101, thereby improving the mechanical strength and firmness between the first chip 10 and the carrier substrate 100, thereby helping to improve packaging reliability.

[0035] In this embodiment, the material of the first adhesion layer 111 includes epoxy resin.

[0036] The chipset 200 is used to be placed and fit in the second groove 102, so that the chipset 200 is accommodated and fixed in the second groove 102, so as to realize the package integration with the first chip 10, and it is also beneficial to save space. The chipset 200 is bonded to the interconnection chip 30, and then the electrical connection between the chipset 200 and the first chip 10 is realized through the interconnection chip 30, so as to form a corresponding packaging structure to realize the corresponding function.

[0037] In this embodiment, the chipset 200 includes adjacent third regions (not labeled) and fourth regions (not labeled), wherein the third region is used for bonding the interconnection chip 30 to achieve electrical connection between the chipset 200 and the interconnection chip 30; and the fourth region is used for forming a conductive column 130 to achieve electrical connection between the chipset 200 and the conductive column 130.

[0038] In this embodiment, the chipset 200 includes a third surface 203 and a fourth surface 204 that are opposite to each other.

[0039] Specifically, in this embodiment, the third area of ​​the third surface 203 is used to achieve bonding with the interconnection chip 30, thereby achieving electrical connection between the chipset 200 and the interconnection chip 30, and the fourth area of ​​the third surface 203 is used to form a conductive column 130; the fourth surface 204 is used to be placed in the second groove 102.

[0040] In this embodiment, the chipset 200 includes a plurality of second chips 20 stacked in a direction perpendicular to the third surface 203 and the fourth surface 204 , and the adjacent second chips 20 in the direction perpendicular to the third surface 203 and the fourth surface 204 are electrically connected.

[0041] In this embodiment, in the chipset 200, a plurality of second chips 20 stacked in the longitudinal direction (i.e., perpendicular to the third surface 203 and the fourth surface 204) constitute a high bandwidth memory structure (High Bandwidth Memory, HBM). By adopting the HBM structure, it is helpful to meet the requirements for higher information transmission speed.

[0042] In this embodiment, the adjacent second chips 20 are electrically connected along the direction perpendicular to the third surface 203 and the fourth surface 204, thereby realizing electrical integration between the second chips 20. Specifically, in this embodiment, the first conductive bumps 11 are formed between the adjacent second chips 20 along the direction perpendicular to the third surface 203 and the fourth surface 204, and the electrical connection between the adjacent second chips 20 is realized through the first conductive bumps 11.

[0043] In this embodiment, the material of the first conductive bump 11 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 11 is tin.

[0044] In this embodiment, along a direction perpendicular to the third surface 203 and the fourth surface 204 , a second chip 20 closest to the third surface 203 is used as the bottom chip 21 , and the remaining second chips 20 are used as the top chips 22 .

[0045] In this embodiment, the bottom chip 21 is a second logic chip, which is used to control the top chip 22 .

[0046] In this embodiment, the top chip 22 is a memory chip, such as a DRAM chip. In this embodiment, the number of the top chips 22 can be one or more. In this embodiment, four top chips 22 are used as an example for description. In other embodiments, the number of top chips can also be other numbers.

[0047] Specifically, in this embodiment, the bottom chip 21 is used as a logic control chip in the chipset 200 to control the memory chip.

[0048] In this embodiment, the top surface of the chipset 200 is flush with the carrier surface 100a, thereby improving the flatness of the top surfaces of the chipset 200 and the carrier surface 100a, and facilitating the setting of a packaging layer 110 with a higher top surface flatness, so that the packaging layer 110 can provide a flat surface for forming an interconnection structure layer 120 with a high interconnection density and a small pitch.

[0049] Specifically, in this embodiment, the third surface 203 of the chipset 200 is flush with the carrying surface 100 a.

[0050] Accordingly, in this embodiment, the top surface of the chipset 200 and the top surface of the first chip 10 are flush with the carrying surface 100 a , so as to provide a flat top surface for process operations.

[0051] In this embodiment, the packaging structure further includes: a second adhesive layer 112 located between the chipset 200 and the sidewall and bottom of the second groove 102 .

[0052] The second adhesive layer 112 is used to improve the adhesion between the sidewall and bottom of the second groove 102 and the chipset 200, and fix the chipset 200 in the second groove 102, thereby improving the mechanical strength and firmness between the chipset 200 and the carrier substrate 100, thereby facilitating improving packaging reliability.

[0053] In this embodiment, the material of the second adhesion layer 112 includes epoxy resin.

[0054] The interconnection chip 30 is bonded to the first chip 10 and the chipset 200, thereby realizing the interconnection between the first chip 10 and the chipset 200. Specifically, the interconnection chip 30 is used as a chip bridge to realize the interconnection between the first chip 10 and the chipset 200.

[0055] Specifically, in this embodiment, an interconnection chip 30 is bonded to the first chip 10 and the chipset 200, and the interconnection chip 30 electrically connects the first chip 10 and the chipset 200, so that high-density and high-speed communication between the first chip 10 and the chipset 200 can be achieved through the interconnection chip 30, and by embedding the first chip 10 and the chipset 200 into the carrier substrate 100, it is also beneficial to improve packaging reliability.

[0056] In this embodiment, the bonding surface 301 is used to achieve bonding with the first chip 10 and the chipset 200 , and further achieve electrical connection between the first chip 10 and the chipset 200 through the interconnection chip 30 .

[0057] In this embodiment, the interconnection chip 30 further includes a back surface 302 opposite to the bonding surface 301 .

[0058] In this embodiment, the interconnection chip 30 includes a base layer (not shown) and a conductive structure layer (not shown) located on the base layer, and the side of the conductive structure layer opposite to the base layer is used as the bonding surface 301, and the side of the base layer opposite to the conductive structure layer is used as the back surface 302.

[0059] In this embodiment, the base layer is used to provide support for forming the conductive structure layer. In this embodiment, the base layer is made of silicon.

[0060] The conductive structure layer is used for subsequently electrically connecting the first chip 10 and the chipset 200 .

[0061] As an example, the conductive structure layer is a first rewiring structure layer. The first rewiring structure layer can redistribute the connection ends of the interconnection chip 30 so as to set the second conductive bumps whose density and position meet the process requirements, thereby facilitating the electrical connection between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30 through the second conductive bumps, and the second conductive bumps have a small pitch and a high density, which is also conducive to improving the interconnection performance between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30, thereby improving the interconnection performance between the first chip 10 and the chipset 200.

[0062] Correspondingly, the conductive structure layer is also used to provide a process platform for forming the second conductive bump.

[0063] Specifically, the first redistribution structure layer may include one or more first redistribution layers. Specifically, the material of the first redistribution layer is a conductive material. As an example, the material of the first redistribution structure is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0064] Specifically, in this embodiment, the bonding surface 301 is disposed opposite to and bonded to the first surface of the first chip 10 and the third surface 203 of the chipset 200. More specifically, in this embodiment, the interconnection chip 30 is electrically connected to the bottom chip 21 in the chipset 200.

[0065] It should be noted that, in the present embodiment, the interconnection chip 30 is bonded to the top surfaces of the first chip 10 and the chipset 200 that are adjacent to each other, that is, the interconnection chip 30 also exposes a portion of the surface of the first surface and a portion of the surface of the third surface 203, so that the conductive pillars 130 are arranged on the first surface and the third surface 203 exposed by the interconnection chip 30.

[0066] In this embodiment, second conductive bumps 12 are formed between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30. The second conductive bumps 12 are used to achieve bonding between the first chip 10 and the interconnection chip 30, and bonding between the chipset 200 and the interconnection chip 30.

[0067] Specifically, in this embodiment, the second conductive bump 12 is located between the bottom chip 21 and the interconnection chip 30 of the chipset 200 to achieve electrical connection between the bottom chip 21 and the interconnection chip 30 .

[0068] In this embodiment, the material of the second conductive bump 12 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 12 is tin.

[0069] In this embodiment, the packaging structure further includes: a first sealing layer 305 , which is located between the first chip 10 and the interconnection chip 30 , and between the chipset 200 and the interconnection chip 30 , and seals the second conductive bumps 12 .

[0070] The first sealing layer 305 fills the gap between the first chip 10 and the interconnection chip 30 , and between the chipset 200 and the interconnection chip 30 , so as to seal the second conductive bumps 12 .

[0071] As an example, the material of the first sealing layer 305 is epoxy resin.

[0072] In this embodiment, the packaging structure further includes: a plurality of conductive pillars 130 , which are separated on the second area and the fourth area, and the conductive pillars 130 are electrically connected to the first chip 10 and the chipset 200 , respectively.

[0073] The conductive pillars 130 are used to realize electrical connection between the first chip 10, the chipset 200 and an external circuit. More specifically, the conductive pillars 130 are used to realize electrical connection between the first chip 10, the chipset 200 and the package substrate 300, respectively.

[0074] In this embodiment, the conductive pillars 130 can also compensate for the height difference between the first surface of the first chip 10 and the third surface 203 of the chipset 200 and the back surface 302 of the interconnection chip 30 , so as to provide a flat top surface for the bonding package substrate 300 .

[0075] In this embodiment, the material of the conductive column 130 is a conductive material. Specifically, the material of the conductive column 130 is a metal, including any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium. In this embodiment, the material of the conductive column 130 is copper, that is, the conductive column 130 is a copper column.

[0076] In this embodiment, along a direction perpendicular to the carrying surface 100 a and along a direction from the carrying substrate 100 to the interconnection chip 30 , the top surface of the conductive pillar 130 is higher than or flush with the back surface 302 of the interconnection chip 30 .

[0077] In this embodiment, the packaging structure further includes: a packaging layer 110 located on the supporting surface 100 a on the sides of the interconnection chip 30 and the conductive pillar 130 , the first chip 10 and the chipset 200 , and the packaging layer 110 exposes the top surface of the conductive pillar 130 .

[0078] Among them, the formation process of the packaging layer 110 includes the step of flattening the packaging material layer to expose the top surface of the conductive pillar 130. The top surface of the conductive pillar 130 is higher than or flush with the back side 302 of the interconnection chip 30. Therefore, in the step of flattening the packaging material layer, the top surface of the conductive pillar 130 can be used as the stop position of the flattening treatment to avoid flattening the back side 302 of the interconnection chip 30 as much as possible, thereby reducing the probability of damage to the interconnection chip 30 and improving the packaging reliability.

[0079] In this embodiment, the top surface of the packaging layer 110 is flush with the top surface of the conductive pillar 130 .

[0080] The packaging layer 110 is used to realize the packaging integration among the chipset 200, the first chip 10, the conductive pillars 130, the interconnection chip 30 and the carrier substrate 100. The packaging layer 110 can also play the role of insulation, sealing and moisture-proof, which is conducive to improving the packaging reliability.

[0081] In this embodiment, the packaging layer 110 is also used to provide a process operation platform for setting the interconnection structure layer 120 .

[0082] As an embodiment, the material of the encapsulation layer 110 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the encapsulation layer can also use other suitable encapsulation materials.

[0083] In this embodiment, the packaging structure further includes: an interconnection structure layer 120 located on the packaging layer 110 and the conductive pillars 130 , and the interconnection structure layer 120 is in contact with the conductive pillars 130 .

[0084] The interconnection structure layer 120 contacts the conductive pillars 130 to achieve electrical connection with the conductive pillars 130 .

[0085] Furthermore, in this embodiment, by forming the interconnection structure layer 120 , the connection ends of the conductive pillars 130 can be redistributed to facilitate bonding with the packaging substrate 300 .

[0086] More specifically, in the present embodiment, by embedding the first chip 10 and the chipset 200 into the carrier substrate 100, it is not only beneficial to improve the packaging reliability, but also beneficial to improve the top surface flatness and height consistency of the packaging layer 110 and the conductive pillar 130, thereby facilitating providing a flat operating surface for the interconnection structure layer 120 and improving the density of the interconnection structure layer 120.

[0087] In this embodiment, the interconnection structure layer 120 is a second rewiring structure layer. The second rewiring structure layer can redistribute the connection ends of the conductive pillars 130, so as to facilitate the arrangement of third conductive bumps whose density and position meet the process requirements, thereby facilitating the electrical connection between the interconnection structure layer 120 and the packaging substrate through the third conductive bumps, and correspondingly realizing the electrical connection between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate, and the third conductive bumps have a small pitch and a high density, which is also conducive to improving the interconnection performance between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate.

[0088] Correspondingly, the interconnect structure layer 120 is also used to provide a process platform for setting the third conductive bump.

[0089] Specifically, the second redistribution structure layer may include one or more second redistribution layers. Specifically, the material of the redistribution layer is a conductive material. As an example, the material of the second redistribution structure is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0090] In this embodiment, the packaging structure further includes: a packaging substrate 300, which is bonded to the conductive pillars 130 and electrically connected to the conductive pillars 130. The packaging substrate 300 is used to achieve packaging integration and electrical integration between the chipset 200 and the first chip 10.

[0091] In this embodiment, the packaging substrate 300 is a PCB (Printed Circuit Board).

[0092] The conductive pillars 130 are electrically connected to the packaging substrate 300 , so that electrical connections between the first chip 10 and the packaging substrate 300 , and between the chipset 200 and the packaging substrate 300 are achieved through the conductive pillars 130 .

[0093] In this embodiment, the packaging structure further includes: a third conductive bump 13 located between the conductive pillar 130 and the packaging substrate 300 , and the third conductive bump 13 electrically connects the conductive pillar 130 and the packaging substrate 300 .

[0094] Specifically, in this embodiment, the interconnection structure layer 120 is bonded to the packaging substrate 300 through the third conductive bumps 13 to achieve electrical connection between the interconnection structure layer 120 and the packaging substrate 300 .

[0095] In this embodiment, the third conductive bump 13 is a solder ball. As an embodiment, the material of the solder ball includes tin.

[0096] Specifically, the solder ball is C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of equal solder ball spacing, the number of I / Os of C4 can be very high. In addition, C4 is also suitable for mass production and greatly reduces size and weight. In other embodiments, the material of the third conductive bump includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0097] In this embodiment, the packaging structure further includes: a second sealing layer 205, which is located between the interconnection structure layer 120 and the packaging substrate 300 and seals the third conductive bump 13. The second sealing layer 205 is used to fill the gap between the interconnection structure layer 120 and the packaging substrate 300 to achieve sealing of the third conductive bump 13. As an example, the material of the second sealing layer 205 is epoxy resin.

[0098] In this embodiment, the package structure further includes: a fourth conductive bump 14, which is located on a surface of the package substrate 300 opposite to the first chip 10 and the chipset 200, and the fourth conductive bump 14 is used to achieve electrical connection between the package substrate 300 and an external circuit. In this embodiment, the fourth conductive bump 14 is a solder ball. As an example, the material of the fourth conductive bump 14 is tin.

[0099] The packaging structure may be formed by the packaging method provided by the embodiment of the present invention, or may be formed by other methods.

[0100] Correspondingly, the present invention also provides a packaging method. Figures 2 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a packaging method of the present invention.

[0101] The packaging method of this embodiment is described in detail below with reference to the accompanying drawings.

[0102] refer to Figure 2 , providing a carrier substrate 100, including a carrier surface 100a. The carrier substrate 100 is used to form a plurality of grooves to accommodate the first chip and the chipset; the carrier substrate 100 is also used to provide a process operation platform for bonding and interconnecting chips on the first chip and the chipset.

[0103] Specifically, the carrying surface 100a is used to provide a process operation platform for subsequent processes.

[0104] In this embodiment, the carrier substrate 100 is a carrier wafer. In other embodiments, the carrier substrate may also be other types of substrates. In this embodiment, the material of the carrier substrate 100 may include one or more of silicon, glass, silicon oxide, and aluminum oxide.

[0105] refer to Figure 3 A plurality of grooves 150 are formed in the carrying surface 100a, including adjacent first grooves 101 and second grooves 102. The plurality of grooves 150 are used to provide space for subsequently accommodating the first chip and the chip set.

[0106] The first groove 101 is used to accommodate a first chip, and the second groove 102 is used to accommodate a chipset.

[0107] Accordingly, in this embodiment, in the step of forming the groove 150, the depth of the groove 150 is determined according to the thickness of the subsequent first chip and the chipset to ensure that the first groove 101 and the second groove 102 can provide sufficient space for accommodating the first chip and the chipset respectively.

[0108] Accordingly, in this embodiment, along a direction parallel to the carrying surface 100a, the size of the groove 150 is determined according to the area of ​​the subsequent first chip and the chipset to ensure that the first groove 101 and the second groove 102 can provide sufficient space for accommodating the first chip and the chipset respectively.

[0109] In this embodiment, the step of forming a plurality of grooves 150 in the carrying surface 100a includes: forming a graphic layer (not shown) on the carrying surface 100a, wherein a plurality of graphic openings (not shown) are formed in the graphic layer; using the graphic layer as a mask, removing part of the thickness of the carrying substrate 100 at the bottom of the graphic openings, thereby forming a plurality of grooves 150 in the carrying surface 100a.

[0110] The pattern layer is used as a mask for forming the groove 150. In this embodiment, the material of the pattern layer includes photoresist.

[0111] The pattern opening is used to define the position and shape of the groove 150 .

[0112] In this embodiment, an anisotropic etching process is used to remove a portion of the thickness of the carrier substrate 100 at the bottom of the pattern opening. The anisotropic etching process can improve the controllability of the etching profile, thereby improving the accuracy of pattern transfer.

[0113] As an example, an anisotropic dry etching process is used to remove part of the thickness of the carrier substrate 100 at the bottom of the pattern opening. The anisotropic dry etching process has high etching precision and fast etching rate, which is conducive to improving the pattern precision and depth precision of the groove 150.

[0114] refer to Figure 4 , providing a first chip 10. The first chip 10 is used to be subsequently placed and attached to the first groove 101, and to realize electrical connection with the chipset through an interconnection chip.

[0115] In this embodiment, the first chip 10 is a first logic chip for performing logic control on the chipset. Specifically, the first logic chip may be a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip or a SoC (System on Chip) chip.

[0116] In this embodiment, the first chip 10 includes adjacent first regions (not labeled) and second regions (not labeled), the first region being used for subsequent bonding and interconnection of chips, and the second region being used for subsequent formation of conductive pillars.

[0117] In this embodiment, the first chip 10 includes a first surface (not marked) and a second surface (not marked) relative to each other. The second surface of the first chip 10 is subsequently attached to the first groove 101 to expose the first surface, so as to subsequently achieve bonding between the first surface of the first chip 10 and the interconnection chip.

[0118] In this embodiment, the first surface is the back surface of the first chip 10, and the second surface is the front surface of the first chip 10. The front surface of the first chip 10 refers to the side of the first chip 10 facing the device, and the back surface of the first chip 10 refers to the side of the first chip 10 facing away from the device.

[0119] In this embodiment, one or more metal layers (not shown) are formed on the front side of the first chip 10 to facilitate subsequent bonding of interconnected chips on a first region on the front side of the first chip 10, and to form conductive pillars on a second region on the front side of the first chip 10, so that the first chip 10 can achieve electrical connection with interconnected chips and with conductive pillars through the metal layer on the front side of the chip.

[0120] refer to Figure 5 , a chipset 200 is provided.

[0121] The chipset 200 is subsequently placed and attached to the second groove 102, and bonded to the subsequent interconnection chip, and then the chipset 200 is electrically connected to the first chip 10 through the interconnection chip, thereby forming a corresponding packaging structure to achieve corresponding functions.

[0122] In this embodiment, the chipset 200 includes adjacent third regions (not labeled) and fourth regions (not labeled), the third region is used for bonding the interconnected chip to achieve electrical connection between the chipset 200 and the interconnected chip; the fourth region is used for subsequently forming a conductive column to achieve electrical connection between the chipset 200 and the conductive column.

[0123] In this embodiment, the chipset 200 includes a third surface 203 and a fourth surface 204 that are opposite to each other.

[0124] Specifically, in this embodiment, the third area of ​​the third surface 203 is used to achieve bonding with the interconnected chip, thereby achieving electrical connection between the chipset 200 and the interconnected chip, and the fourth area of ​​the third surface 203 is used to form a conductive column; the fourth surface 204 is used to be placed in the second groove 102.

[0125] In this embodiment, the chipset 200 includes a plurality of second chips 20 stacked in a direction perpendicular to the third surface 203 and the fourth surface 204 , and the adjacent second chips 20 in the direction perpendicular to the third surface 203 and the fourth surface 204 are electrically connected.

[0126] In this embodiment, in the chipset 200, a plurality of second chips 20 stacked in the longitudinal direction (ie, perpendicular to the third surface 203 and the fourth surface 204) form a high-bandwidth memory storage structure. By adopting the HBM structure, it is helpful to meet the requirements for higher information transmission speed.

[0127] In this embodiment, the adjacent second chips 20 are electrically connected along the direction perpendicular to the third surface 203 and the fourth surface 204, thereby realizing electrical integration between the second chips 20. Specifically, in this embodiment, the first conductive bumps 11 are formed between the adjacent second chips 20 along the direction perpendicular to the third surface 203 and the fourth surface 204, and the electrical connection between the adjacent second chips 20 is realized through the first conductive bumps 11.

[0128] In this embodiment, the material of the first conductive bump 11 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the first conductive bump 11 is tin.

[0129] In this embodiment, along a direction perpendicular to the third surface 203 and the fourth surface 204 , a second chip 20 closest to the third surface 203 is used as the bottom chip 21 , and the remaining second chips 20 are used as the top chips 22 .

[0130] In this embodiment, the bottom chip 21 is a second logic chip, which is used to control the top chip 22 .

[0131] In this embodiment, the top chip 22 is a memory chip, such as a DRAM chip. In this embodiment, the number of the top chips 22 can be one or more. In this embodiment, four top chips 22 are used as an example for description. In other embodiments, the number of top chips can also be other numbers.

[0132] Specifically, in this embodiment, the bottom chip 21 is used as a logic control chip in the chipset 200 to control the memory chip.

[0133] refer to Figure 6 , placing and attaching the first chip 10 in the first groove 101 .

[0134] The first chip 10 is placed and attached in the first groove 101 , so that the first chip 10 is accommodated and fixed in the first groove 101 , so as to achieve packaging integration with the chipset 200 and save space.

[0135] In this embodiment, in the step of placing and bonding the first chip 10 in the first groove 101, the top surface of the first chip 10 is flush with the carrying surface 100a, thereby improving the flatness of the top surfaces of the first chip 10 and the carrying surface 100a, facilitating the subsequent formation of a packaging layer with a higher top surface flatness, and further providing a flat surface for the subsequent formation of an interconnection structure layer with a high interconnection density and a small pitch.

[0136] More specifically, in this embodiment, the first surface of the first chip 10 is flush with the carrying surface 100 a.

[0137] In this embodiment, the step of placing and bonding the first chip 10 in the first groove 101 includes: coating the first adhesion layer 111 on the side wall and the bottom of the first groove 101; placing the first chip 10 in the first groove 101, and fixing the first chip 10 by the first adhesion layer 111.

[0138] The first adhesive layer 111 is used to improve the adhesion between the sidewall and bottom of the first groove 101 and the first chip 10, and fix the first chip 10 in the first groove 101, thereby improving the mechanical strength and firmness between the first chip 10 and the carrier substrate 100, thereby helping to improve packaging reliability.

[0139] In this embodiment, the material of the first adhesion layer 111 includes epoxy resin.

[0140] Continue to refer Figure 6 , the chipset 200 is placed and attached in the second groove 102 .

[0141] The chipset 200 is placed and attached in the second groove 102 , so that the chipset 200 is accommodated and fixed in the second groove 102 , so as to achieve package integration with the first chip 10 and save space.

[0142] In this embodiment, in the step of placing and bonding the chipset 200 in the second groove 102, the top surface of the chipset 200 is flush with the carrying surface 100a, thereby improving the flatness of the top surfaces of the chipset 200 and the carrying surface 100a, facilitating the formation of a packaging layer with a higher top surface flatness, so as to provide a flat surface for the subsequent formation of an interconnection structure layer with a high interconnection density and a small pitch.

[0143] Specifically, in this embodiment, the third surface 203 of the chipset 200 is flush with the carrying surface 100 a.

[0144] Accordingly, in this embodiment, the top surface of the chipset 200 and the top surface of the first chip 10 are flush with the carrying surface 100 a , so as to provide a flat top surface for subsequent process operations.

[0145] In this embodiment, the step of placing and bonding the chipset 200 in the second groove 102 includes: coating a second adhesive layer 112 on the sidewalls and bottom of the second groove 102 ; placing the chipset 200 in the second groove 102 , and fixing the chipset 200 via the second adhesive layer 112 .

[0146] The second adhesive layer 112 is used to improve the adhesion between the sidewall and bottom of the second groove 102 and the chipset 200, and fix the chipset 200 in the second groove 102, thereby improving the mechanical strength and firmness between the chipset 200 and the carrier substrate 100, thereby facilitating improving packaging reliability.

[0147] In this embodiment, the material of the second adhesion layer 112 includes epoxy resin.

[0148] In a specific implementation, the first chip 10 may be placed and attached in the first groove 101, and the chipset 200 may be placed and attached in the second groove 102 in the same step. More specifically, a first adhesive layer 111 is coated on the sidewall and bottom of the first groove 101, and a second adhesive layer 112 is coated on the sidewall and bottom of the second groove 102; then, the first chip 10 is placed and attached in the first groove 101, and the chipset 200 is placed and attached in the second groove 102.

[0149] refer to Figure 7 , an interconnection chip 30 is provided, wherein the interconnection chip 30 includes a bonding surface 301.

[0150] An interconnection chip 30 is provided so that the interconnection chip 30 is subsequently bonded to the first chip 10 and the chipset 200 to achieve interconnection between the first chip 10 and the chipset 200. Specifically, the interconnection chip 30 is used as a chip bridge to achieve interconnection between the first chip 10 and the chipset 200.

[0151] The bonding surface 301 is used to subsequently realize bonding with the first chip 10 and the chipset 200 , and further realize electrical connection between the first chip 10 and the chipset 200 through the interconnection chip 30 .

[0152] In this embodiment, the interconnection chip 30 further includes a back surface 302 opposite to the bonding surface 301 .

[0153] In this embodiment, the interconnection chip 30 includes a base layer (not shown) and a conductive structure layer (not shown) located on the base layer, and the side of the conductive structure layer opposite to the base layer is used as the bonding surface 301, and the side of the base layer opposite to the conductive structure layer is used as the back surface 302.

[0154] In this embodiment, the base layer is used to provide support for forming the conductive structure layer.

[0155] In this embodiment, the material of the base layer is silicon.

[0156] The conductive structure layer is used for subsequently electrically connecting the first chip 10 and the chipset 200 .

[0157] As an example, the conductive structure layer is a first rewiring structure layer. The first rewiring structure layer can redistribute the connection ends of the interconnection chip 30 so as to subsequently form a second conductive bump whose density and position meet the process requirements, thereby facilitating the subsequent electrical connection between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30 through the second conductive bump. The second conductive bump has a small pitch and a high density, which is also conducive to improving the interconnection performance between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30, thereby improving the interconnection performance between the first chip 10 and the chipset 200.

[0158] Correspondingly, the conductive structure layer is also used to provide a process platform for forming the second conductive bump.

[0159] Specifically, the first redistribution structure layer may include one or more first redistribution layers. Specifically, the material of the first redistribution layer is a conductive material. As an example, the material of the first redistribution structure is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0160] refer to Figure 8 An interconnection chip 30 is bonded on the first chip 10 and the chipset 200 , the bonding surface 301 is arranged opposite to the first chip 10 and the chipset 200 , and the interconnection chip 30 electrically connects the first chip 10 and the chipset 200 .

[0161] In this embodiment, an interconnection chip 30 is bonded on the first chip 10 and the chipset 200, and the interconnection chip 30 electrically connects the first chip 10 and the chipset 200, so that high-density and high-speed communication between the first chip 10 and the chipset 200 can be achieved through the interconnection chip 30, and by embedding the first chip 10 and the chipset 200 into the carrier substrate 100, it is also beneficial to improve packaging reliability.

[0162] Specifically, in this embodiment, the bonding surface 301 is disposed opposite to and bonded to the first surface of the first chip 10 and the third surface 203 of the chipset 200. More specifically, in this embodiment, the interconnection chip 30 is electrically connected to the bottom chip 21 in the chipset 200.

[0163] In this embodiment, the step of bonding the interconnection chip 30 on the first chip 10 and the chipset 200 includes: forming a second conductive bump 12 between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30, and achieving bonding between the first chip 10 and the interconnection chip 30, and between the chipset 200 and the interconnection chip 30 through the second conductive bump 12.

[0164] Specifically, in this embodiment, the second conductive bump 12 is located between the bottom chip 21 and the interconnection chip 30 of the chipset 200 to achieve electrical connection between the bottom chip 21 and the interconnection chip 30 .

[0165] In this embodiment, the material of the second conductive bump 12 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride. As an example, the material of the second conductive bump 12 is tin.

[0166] In a specific implementation, the second conductive bump 12 may be formed on the bonding surface 301 of the interconnection chip 30; or, the second conductive bump 12 may be formed on the first surface of the first chip 10 and the third surface 203 of the chipset 200; and then, the bonding between the first chip 10 and the interconnection chip 30 and the bonding between the chipset 200 and the interconnection chip 30 are achieved through the second conductive bump 12.

[0167] It should be noted that, in the present embodiment, the interconnection chip 30 is bonded to the top surfaces of the first chip 10 and the chipset 200 that are adjacent to each other, that is, the interconnection chip 30 also exposes a portion of the surface of the first surface and a portion of the surface of the third surface 203, so that conductive pillars can be subsequently formed on the first surface and the third surface 203 exposed by the interconnection chip 30.

[0168] In this embodiment, the packaging method also includes: after the bonding between the first chip 10 and the interconnection chip 30 and the bonding between the chipset 200 and the interconnection chip 30 are achieved through the second conductive bump 12, a first sealing layer 305 for sealing the second conductive bump 12 is formed between the first chip 10 and the interconnection chip 30 and between the chipset 200 and the interconnection chip 30.

[0169] The first sealing layer 305 fills the gap between the first chip 10 and the interconnection chip 30 , and between the chipset 200 and the interconnection chip 30 , so as to seal the second conductive bumps 12 .

[0170] As an example, the first sealing layer 305 is formed by adopting an underfill process.

[0171] As an example, the material of the first sealing layer 305 is epoxy resin.

[0172] refer to Figure 8 The packaging method further includes: after placing and bonding the first chip 10 in the first groove 101 and placing and bonding the chipset 200 in the second groove 102, forming a plurality of conductive pillars 130 on the second area and the fourth area, the conductive pillars 130 being electrically connected to the first chip 10 and the chipset 200 respectively.

[0173] The conductive pillars 130 are used to realize electrical connection between the first chip 10, the chipset 200 and an external circuit. More specifically, the conductive pillars 130 are used to realize electrical connection between the first chip 10, the chipset 200 and a subsequent packaging substrate.

[0174] In this embodiment, the conductive pillars 130 can also compensate for the height difference between the first surface of the first chip 10 and the third surface 203 of the chipset 200 and the back surface 302 of the interconnection chip 30 , so as to provide a flat top surface for subsequent bonding of the package substrate.

[0175] Specifically, in this embodiment, after the interconnection chip 30 is bonded on the first chip 10 and the chipset 200, a plurality of conductive pillars 130 are formed on the second region and the fourth region. In other embodiments, after the plurality of conductive pillars are formed on the second region and the fourth region, an interconnection chip is bonded on the first chip and the chipset.

[0176] In this embodiment, after the conductive pillars 130 are formed and the interconnection chip 30 is bonded onto the first chip 10 and the chip set 200 , the top surface of the conductive pillars 130 is higher than or flush with the back surface 302 of the interconnection chip 30 .

[0177] Subsequent steps also include: forming a packaging layer on the supporting surface 100a, the first chip 10 and the chipset 200 on the sides of the interconnected chip 30 and the conductive pillar 130, the packaging layer exposing the top surface of the conductive pillar 130, wherein the process of forming the packaging layer includes a step of flattening the packaging material layer to expose the top surface of the conductive pillar 130, the top surface of the conductive pillar 130 is higher than or flush with the back side 302 of the interconnected chip 30, so that in the subsequent step of flattening the packaging material layer, the top surface of the conductive pillar 130 can be used as the stop position of the flattening treatment, so as to avoid flattening the back side 302 of the interconnected chip 30 as much as possible, thereby reducing the probability of damage to the interconnected chip 30 and improving the packaging reliability.

[0178] In this embodiment, the material of the conductive column 130 is a conductive material. Specifically, the material of the conductive column 130 is a metal, including any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium. In this embodiment, the material of the conductive column 130 is copper, that is, the conductive column 130 is a copper column.

[0179] As an example, the step of forming a plurality of conductive pillars 130 on the second area and the fourth area includes: forming a patterned layer (not shown) on the carrying surface 100a, the first surface of the first chip 10 and the third surface 203 of the chipset 200, wherein a plurality of through holes located in the second area and the fourth area are formed in the patterned layer; forming conductive pillars 130 filled in the through holes; and removing the patterned layer.

[0180] The patterned layer is used to provide support for forming the conductive pillar 130. The through hole is used to define the formation position, size and shape of the conductive pillar 130.

[0181] In this embodiment, the process of filling the through hole includes one or two of a chemical vapor deposition process, a physical vapor deposition process and an electrochemical plating process.

[0182] The patterned layer is removed to expose the carrier surface 100 a , the first surface of the first chip 10 , and the third surface 203 of the chipset 200 , thereby facilitating the subsequent formation of a packaging layer on the conductive pillars 130 and the sides of the interconnection chip 30 .

[0183] refer to Figures 9 and 10 A packaging layer 110 is formed on the supporting surface 100 a on the side of the interconnection chip 301 and the conductive pillar 130 , the first chip 10 , and the chipset 200 , wherein the packaging layer 110 exposes the top surface of the conductive pillar 130 .

[0184] The packaging layer 110 is used to realize the packaging integration among the chipset 200, the first chip 10, the conductive pillars 130, the interconnection chip 30 and the carrier substrate 100. The packaging layer 110 can also play the role of insulation, sealing and moisture-proof, which is conducive to improving the packaging reliability.

[0185] In this embodiment, the encapsulation layer 110 is also used to provide a process operation platform for the subsequent formation of an interconnection structure layer.

[0186] As an embodiment, the material of the encapsulation layer 110 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the encapsulation layer can also use other suitable encapsulation materials.

[0187] In this embodiment, the steps of forming the encapsulation layer 110 include: Fig. 9As shown, a packaging material layer 115 is formed on the carrying surface 100a, the first chip 10 and the chipset 200, and the packaging material layer 115 covers the top and side walls of the conductive pillars 130 and the top and side walls of the interconnection chip 30; Fig.10 As shown, the packaging material layer 115 is planarized, and the packaging material layer 115 above the top of the conductive pillar 130 is removed, and the remaining packaging material layer 115 is used as the packaging layer 110.

[0188] In this embodiment, a plastic encapsulation process is used to form the encapsulation material layer. In other embodiments, other suitable processes may be used to form the encapsulation material layer based on actual process requirements.

[0189] In this embodiment, a grinding process is used to planarize the packaging material layer 115 , thereby improving the flatness of the top surfaces of the packaging layer 110 and the conductive pillars 130 , which is beneficial to subsequent processes.

[0190] refer to Fig.11 The packaging method further includes: forming an interconnection structure layer 120 on the packaging layer 110 and the conductive pillars 130, wherein the interconnection structure layer 120 is in contact with the conductive pillars 130. The interconnection structure layer 120 is in contact with the conductive pillars 130, thereby achieving electrical connection with the conductive pillars 130.

[0191] Furthermore, in this embodiment, by forming the interconnection structure layer 120 , the connection ends of the conductive pillars 130 can be redistributed to facilitate subsequent bonding with the packaging substrate.

[0192] More specifically, in the present embodiment, by embedding the first chip 10 and the chipset 200 into the carrier substrate 100, it is not only beneficial to improve the packaging reliability, but also beneficial to improve the top surface flatness and height consistency of the packaging layer 110 and the conductive pillar 130, thereby facilitating providing a flat operating surface for the interconnection structure layer 120 and improving the density of the interconnection structure layer 120.

[0193] In this embodiment, the interconnection structure layer 120 is a second rewiring structure layer. The second rewiring structure layer can redistribute the connection ends of the conductive pillars 130 so as to form a third conductive bump whose density and position meet the process requirements, thereby facilitating the electrical connection between the interconnection structure layer 120 and the subsequent packaging substrate through the third conductive bump, and correspondingly realizing the electrical connection between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate, and the third conductive bump has a small pitch and a high density, which is also conducive to improving the interconnection performance between the first chip 10 and the packaging substrate, and between the chipset 200 and the packaging substrate.

[0194] Accordingly, the interconnect structure layer 120 is also used to provide a process platform for forming the third conductive bump.

[0195] Specifically, the second redistribution structure layer may include one or more second redistribution layers. Specifically, the material of the redistribution layer is a conductive material. As an example, the material of the second redistribution structure is a metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc or chromium.

[0196] refer to Fig.12 and Fig.13 The packaging method further includes: after forming the packaging layer 110, providing a packaging substrate 300; bonding the conductive pillar 130 to the packaging substrate 300, and electrically connecting the conductive pillar 130 to the packaging substrate 300. The packaging substrate 300 is used to realize packaging integration and electrical integration between the chipset 200 and the first chip 10.

[0197] In this embodiment, the packaging substrate 300 is a PCB (Printed Circuit Board).

[0198] The conductive pillars 130 are electrically connected to the packaging substrate 300 , so that electrical connections between the first chip 10 and the packaging substrate 300 , and between the chipset 200 and the packaging substrate 300 are achieved through the conductive pillars 130 .

[0199] In this embodiment, the step of bonding the conductive pillar 130 to the packaging substrate 300 includes: bonding the conductive pillar 130 to the packaging substrate 300 through a third conductive bump 13 , wherein the third conductive bump 13 electrically connects the conductive pillar 130 and the packaging substrate 300 .

[0200] Specifically, in this embodiment, the interconnection structure layer 120 is bonded to the packaging substrate 300 through the third conductive bumps 13 to achieve electrical connection between the interconnection structure layer 120 and the packaging substrate 300 .

[0201] In a specific implementation, a third conductive bump 13 may be formed on any one of the interconnect structure layer 120 and the packaging substrate 300, and then the electrical connection between the interconnect structure layer 120 and the packaging substrate 300 is achieved through the third conductive bump 13; or, a first sub-conductive bump may be formed on the interconnect structure layer 120, and a second sub-conductive bump may be formed on the packaging substrate 300, and bonding between the first sub-conductive bump and the second sub-conductive bump may be achieved.

[0202] In this embodiment, the third conductive bump 13 is a solder ball. As an embodiment, the material of the solder ball includes tin.

[0203] Specifically, the solder ball is C4 (Controlled Collapse Chip Connection), which has excellent electrical and thermal properties. Moreover, under the condition of equal solder ball spacing, the number of I / Os of C4 can be very high. In addition, C4 is also suitable for mass production and greatly reduces size and weight. In other embodiments, the material of the third conductive bump includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride.

[0204] In this embodiment, the packaging method further includes: forming a second sealing layer 205 for sealing the third conductive bump 13 between the interconnect structure layer 120 and the packaging substrate 300 .

[0205] The second sealing layer 205 is used to fill the gap between the interconnect structure layer 120 and the package substrate 300 to achieve sealing of the third conductive bump 13. As an example, the second sealing layer 205 is formed by a bottom filling process. As an example, the material of the second sealing layer 205 is epoxy resin.

[0206] In this embodiment, the packaging method further includes: forming a fourth conductive bump 14 on a surface of the packaging substrate 300 opposite to the first chip 10 and the chipset 200 , wherein the fourth conductive bump 14 is used to achieve electrical connection between the packaging substrate 300 and an external circuit.

[0207] In this embodiment, the fourth conductive bump 14 is a solder ball. As an example, the material of the fourth conductive bump 14 is tin.

[0208] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: A carrying substrate, including a carrying surface; A plurality of grooves are located in the bearing surface, and the plurality of grooves include adjacent first grooves and second grooves; A first chip is placed and attached to the first groove; A chipset is placed and attached to the second groove; An interconnection chip is bonded to the first chip and the chipset; the interconnection chip comprises a bonding surface, the bonding surface is arranged opposite to the first chip and the chipset, and the interconnection chip is electrically connected to the first chip and the chipset.

2. The packaging structure according to claim 1, characterized in that: The top surface of the first chip is flush with the carrying surface; the top surface of the chipset is flush with the carrying surface.

3. The packaging structure according to claim 1, characterized in that: The first chip includes a first region and a second region adjacent to each other, and the first region is used for bonding and interconnecting chips; the chipset includes a third region and a fourth region adjacent to each other, and the third region is used for bonding and interconnecting chips; The packaging structure also includes: a plurality of conductive pillars, which are separated on the second area and the fourth area, and the conductive pillars are electrically connected to the first chip and the chipset respectively; a packaging layer, which is located on the supporting surface of the interconnected chip and the side of the conductive pillars, the first chip and the chipset, and the packaging layer exposes the top surface of the conductive pillars.

4. The packaging structure according to claim 3, characterized in that: The packaging structure further includes: a packaging substrate bonded to the conductive pillars and electrically connected to the conductive pillars.

5. The packaging structure according to claim 4, characterized in that: The packaging structure further includes: a conductive bump located between the conductive pillar and the packaging substrate, wherein the conductive bump electrically connects the conductive pillar and the packaging substrate.

6. The packaging structure according to claim 4 or 5, characterized in that: The packaging structure further includes: an interconnection structure layer located on the packaging layer and the conductive pillars, and the interconnection structure layer is in contact with the conductive pillars.

7. The packaging structure according to claim 3, characterized in that: The interconnection chip also includes a back side opposite to the bonding surface; in a direction perpendicular to the carrying surface and in a direction from the carrying substrate to the interconnection chip, the top surface of the conductive column is higher than or flush with the back side of the interconnection chip.

8. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a first adhesive layer located between the first chip and the sidewall and bottom of the first groove; and a second adhesive layer located between the chipset and the sidewall and bottom of the second groove.

9. The packaging structure according to claim 1, characterized in that: The chipset includes a plurality of second chips stacked in a direction perpendicular to the carrying surface, and the adjacent second chips in the direction perpendicular to the carrying surface are electrically connected; the first chip is a logic chip, and the chipset is a high-bandwidth memory chipset.

10. A packaging method, characterized in that: include: Providing a carrier substrate, including a carrier surface; forming a plurality of grooves in the bearing surface, including adjacent first grooves and second grooves; providing a first chip; Placing and attaching a first chip in the first groove; Provide chipset; Placing and attaching a chipset in the second groove; providing an interconnect chip, the interconnect chip comprising a bonding surface; An interconnection chip is bonded onto the first chip and the chipset, the bonding surface is arranged opposite to the first chip and the chipset, and the interconnection chip electrically connects the first chip and the chipset.

11. The packaging method according to claim 10, characterized in that: In the step of placing and attaching the first chip in the first groove, the top surface of the first chip is flush with the carrying surface; In the step of placing and attaching the chipset in the second groove, the top surface of the chipset is flush with the carrying surface.

12. The packaging method according to claim 10, characterized in that: The first chip includes a first region and a second region adjacent to each other, and the first region is used for bonding and interconnecting chips; the chipset includes a third region and a fourth region adjacent to each other, and the third region is used for bonding and interconnecting chips; The packaging method further comprises: After placing and attaching a first chip in the first groove and placing and attaching a chipset in the second groove, a plurality of conductive pillars are formed on the second area and the fourth area, wherein the conductive pillars are electrically connected to the first chip and the chipset respectively; A packaging layer is formed on the supporting surface of the interconnected chip and the side of the conductive pillar, the first chip and the chip group, wherein the packaging layer exposes the top surface of the conductive pillar.

13. The packaging method according to claim 12, characterized in that: The packaging method further includes: after forming the packaging layer, providing a packaging substrate; bonding the conductive pillar to the packaging substrate, and electrically connecting the conductive pillar to the packaging substrate.

14. The packaging method according to claim 13, characterized in that: The step of bonding the conductive pillar to the packaging substrate includes: bonding the conductive pillar to the packaging substrate through a conductive bump, wherein the conductive bump electrically connects the conductive pillar and the packaging substrate.

15. The packaging method according to claim 13 or 14, characterized in that: The packaging method further includes: after forming the packaging layer and before bonding the conductive pillars to the packaging substrate, forming an interconnection structure layer on the packaging layer and the conductive pillars, wherein the interconnection structure layer contacts the conductive pillars.

16. The packaging method according to claim 12, characterized in that: The step of forming the packaging layer includes: forming a packaging material layer on the carrying surface, the first chip and the chipset, the packaging material layer covering the top and side walls of the conductive pillars and the top and side walls of the interconnection chip; The packaging material layer is planarized to remove the packaging material layer above the top of the conductive column, and the remaining packaging material layer is used as the packaging layer.

17. The packaging method according to claim 12 or 16, characterized in that: In the step of providing an interconnection chip, the interconnection chip also includes a back side opposite to the bonding side; after forming the conductive pillar and bonding the interconnection chip to the first chip and the chipset, the top surface of the conductive pillar is higher than or flush with the back side of the interconnection chip.

18. The packaging method according to claim 10, characterized in that: The step of forming a plurality of grooves in the carrying surface includes: forming a graphic layer on the carrying surface, wherein a plurality of graphic openings are formed in the graphic layer; using the graphic layer as a mask, removing part of the thickness of the carrying substrate at the bottom of the graphic openings, and forming a plurality of grooves in the carrying surface.

19. The packaging method according to claim 10, characterized in that: The step of placing and attaching the first chip in the first groove comprises: coating a first adhesive layer on the sidewall and bottom of the first groove; placing the first chip in the first groove and fixing the first chip by the first adhesive layer; The step of placing and attaching the chipset in the second groove includes: coating a second adhesive layer on the sidewall and bottom of the second groove; placing the chipset in the second groove and fixing the chipset by the second adhesive layer.

20. The packaging method according to claim 10, characterized in that: The chipset includes a plurality of second chips stacked in a direction perpendicular to the carrying surface, and the adjacent second chips in the direction perpendicular to the carrying surface are electrically connected; the first chip is a logic chip, and the chipset is a high-bandwidth memory chipset.

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