Semiconductor device

Abstract

A semiconductor device includes: a substrate; the plurality of gate structures are located on the substrate, and the plurality of gate structures comprise a first gate structure and a second gate structure adjacent to the first gate structure; a spacer structure on opposite sidewalls of the first gate structure; wherein the spacer structure includes: insulating spacers located on opposite sidewalls of the first gate structure; an inner protective layer on upper surfaces of the insulating spacer and the first gate structure; the outer protection layer is located on at least one part of the inner protection layer, the insulating filling layer is located on the spacing structure, and the insulating filling layer is located between the first gate structure and the second gate structure; and an upper cover layer on an upper surface of the insulating filling layer, where the upper cover layer includes the same material as the insulating filling layer.

Description

Technical Field

[0001] The inventive concept of the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a contact plug of a peripheral circuit region. Background Art

[0002] As electronic products are required to become more compact, multifunctional and high-performance, semiconductor devices with higher capacity and higher integration are required. As semiconductor devices become more capacitive and highly integrated, it is increasingly difficult to ensure the structural stability of the components that make up the semiconductor devices. Summary of the invention

[0003] The inventive concepts of the present disclosure may provide a semiconductor device in which a contact plug of a peripheral circuit region has improved structural stability.

[0004] Furthermore, problems to be solved by the inventive concept of the present disclosure are not limited to the above-mentioned objects, and other problems may be clearly understood by those skilled in the art from the following description.

[0005] According to one aspect of the inventive concept of the present disclosure, a semiconductor device is provided, which includes: a substrate; a plurality of gate structures located on the substrate, wherein the plurality of gate structures include a first gate structure and a second gate structure adjacent to the first gate structure; a spacer structure, the spacer structure is located on opposite side walls of the first gate structure; wherein the spacer structure includes: an insulating spacer, the insulating spacer is located on opposite side walls of the first gate structure; an inner protective layer, the inner protective layer is located on the upper surface of the insulating spacer and the first gate structure; and an outer protective layer, the outer protective layer is located on at least a portion of the inner protective layer, an insulating filling layer located on the spacer structure, wherein the insulating filling layer is located between the first gate structure and the second gate structure; and an upper covering layer, the upper covering layer is located on the upper surface of the insulating filling layer, wherein the upper covering layer includes the same material as the insulating filling layer.

[0006] According to another aspect of the inventive concept of the present disclosure, a semiconductor device is provided, which includes: a substrate; a plurality of gate structures located on the substrate; a spacing structure, the spacing structures are respectively located on the opposite side walls of the plurality of gate structures; wherein the spacing structure includes: a plurality of insulating spacers, the plurality of insulating spacers are respectively located on the opposite side walls of the plurality of gate structures; an inner protective layer, the inner protective layer is located on the upper surfaces of the plurality of insulating spacers and the plurality of gate structures; and an outer protective layer, the outer protective layer is located on at least a portion of the inner protective layer, an insulating filling layer, the insulating filling layer is located between adjacent gate structures among the plurality of gate structures, wherein the insulating filling layer is located on the spacing structure; an upper covering layer, the upper covering layer is located on the upper surface of the insulating filling layer, and a contact plug, the contact plug extends in the insulating filling layer and the upper covering layer along a first direction perpendicular to the upper surface of the substrate, wherein the insulating filling layer includes the same material as the upper covering layer.

[0007] According to another aspect of the inventive concept of the present disclosure, a semiconductor device is provided, which includes: a substrate; a plurality of gate structures located on the substrate; a spacer structure, the spacer structures are respectively located on opposite side walls of the plurality of gate structures; wherein the spacer structure includes: a plurality of insulating spacers, the plurality of insulating spacers are respectively located on opposite side walls of the plurality of gate structures; an inner protective layer, the inner protective layer is located on upper surfaces of the plurality of insulating spacers and the plurality of gate structures; and an outer protective layer, the outer protective layer is located on at least a portion of the inner protective layer, an insulating filling layer, the insulating filling layer is located between adjacent gate structures among the plurality of gate structures, wherein the insulating filling layer is located on the spacer structure; an upper covering layer located on the insulating filling layer; and a contact plug, the contact plug extends in the insulating filling layer and the upper covering layer along a first direction perpendicular to the upper surface of the substrate, wherein the insulating filling layer includes the same material as the upper covering layer, and the insulating filling layer includes a nitride layer and / or a silicon nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the inventive concept of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1A and Figure 1B is a layout diagram of a semiconductor device according to some embodiments;

[0010] Figure 2A It is along Figure 1A A cross-sectional view of the semiconductor device taken along line A1-A1' in FIG.

[0011] Figure 2B It is along Figure 1A A cross-sectional view of the semiconductor device taken along line A2-A2' in FIG.

[0012] Figure 3A It is along Figure 1B A cross-sectional view of the semiconductor device taken along line B1-B1' in FIG.

[0013] Figure 3B It is along Figure 1B A cross-sectional view of the semiconductor device taken along line B2-B2' in FIG.

[0014] Figure 3C yes Figure 3A A magnified view of a portion of AR1;

[0015] Figure 4A is a cross-sectional view for explaining a semiconductor device according to some embodiments;

[0016] Figure 4B is a cross-sectional view for explaining a semiconductor device according to some embodiments;

[0017] Figure 4C yes Figure 4A A magnified view of a portion of AR2;

[0018] Figure 5A is a cross-sectional view for explaining a semiconductor device according to some embodiments;

[0019] Figure 5B is a cross-sectional view for explaining a semiconductor device according to some embodiments;

[0020] Figure 5C yes Figure 5A A magnified view of a portion of AR3;

[0021] Fig. 6A is a cross-sectional view for explaining a semiconductor device according to some embodiments;

[0022] Figure 6B is a cross-sectional view for explaining a semiconductor device according to some embodiments;

[0023] Figure 6C yes Fig. 6A an enlarged view of a portion of AR4; and

[0024] 7A to 19A and FIG. 7B to FIG. 19B is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0025] Embodiments of the inventive concept of the present disclosure will now be described more fully with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals may refer to the same elements, and repeated description of the same elements may be omitted.

[0026] Figure 1A and Figure 1Bis a layout diagram of a semiconductor device according to some embodiments. Figure 2A It is along Figure 1A A cross-sectional view of the semiconductor device taken along line A1 - A1 ′ in FIG. Figure 2B It is along Figure 1A A cross-sectional view of the semiconductor device taken along line A2 - A2 ′ in FIG. Figure 3A It is along Figure 1B 0 is a cross-sectional view of the semiconductor device taken along line B1 - B1 ′ in FIG. Figure 3B It is along Figure 1B 2 is a cross-sectional view of the semiconductor device taken along line B2 - B2 ′ in FIG. Figure 3C yes Figure 3A A magnified view of a portion of AR1.

[0027] refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C , the semiconductor device 100 may include a substrate 110 including a cell array area MCA and a peripheral circuit area PCA.

[0028] An isolation trench 112T may be formed in the substrate 110, and an isolation layer 112 may be formed in the isolation trench 112T. In the cell array area MCA, a plurality of first active regions AC1 may be defined in the substrate 110 by the isolation layer 112, and in the peripheral circuit area PCA, a second active region AC2 may be defined in the substrate 110 by the isolation layer 112.

[0029] In this specification, the direction in which the substrate 110 extends may be defined as a first horizontal direction X, a direction intersecting the first horizontal direction X may be defined as a second horizontal direction Y, and a direction perpendicular to the upper surface of the substrate 110 may be defined as a vertical direction Z. For example, the upper surface of the substrate 110 may extend in the first horizontal direction X and the second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be parallel to the upper surface of the substrate 110. The vertical direction Z may be perpendicular to the upper surface of the substrate 110.

[0030] Each of the plurality of first active regions AC1 may be arranged to have a long axis in a diagonal direction relative to a first horizontal direction X (e.g., X direction) and a second horizontal direction Y (e.g., Y direction). A plurality of word lines WL may each extend parallel to each other along the first horizontal direction X across the plurality of first active regions AC1. On the plurality of word lines WL, a plurality of bit lines BL may extend parallel to each other in the second horizontal direction Y. A plurality of bit lines BL may be connected (e.g., electrically connected) to the plurality of first active regions AC1 via direct contact DC. For example, a plurality of word lines WL may overlap with a plurality of first active regions AC1 in a vertical direction Z, and a plurality of bit lines BL may overlap with a plurality of word lines WL in a vertical direction Z. As used herein, "element A overlaps element B in direction C" (or similar language) means that at least one line extends in direction C and intersects both elements A and B. It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly located at, connected to, or coupled to another element or layer, or one or more intermediate elements or layers may be present. In contrast, when an element is referred to as being "directly connected," "directly connected," or "directly responsive to" or "directly located at" another element, there are no intermediate elements. In addition, "electrically connected" conceptually includes physical connections and physical disconnections. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed terms.

[0031] A plurality of buried contacts BC may be formed between two bit lines BL adjacent to each other among the plurality of bit lines BL. The plurality of buried contacts BC may be arranged in a row in the first horizontal direction X and the second horizontal direction Y. A plurality of landing pads LP may be formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of landing pads LP may connect (e.g., electrically connect) a lower electrode (not shown) of a capacitor formed across the plurality of bit lines BL (on the plurality of bit lines BL) to the first active region AC1. The landing pad LP among the plurality of landing pads LP may be arranged to partially overlap (in the vertical direction Z) with the buried contact BC among the plurality of buried contacts BC. The terms "lower than," "higher than," "lower level," "higher level," etc. herein may refer to a relative distance from the upper / lower surface of the substrate 110 in the vertical direction Z. For example, when element A is described as being lower than element B, element A may be closer to the upper / lower surface of the substrate 110 than element B in the vertical direction Z.

[0032] The substrate 110 may include silicon, such as single crystal silicon, polycrystalline silicon and / or amorphous silicon. According to some embodiments, the substrate 110 may include, for example, Ge, SiGe, SiC, GaAs, InAs and / or InP. According to some embodiments, the substrate 110 may include a conductive region, such as a well doped with impurities or a structure doped with impurities. The isolation layer 112 may include, for example, an oxide layer, a nitride layer and / or a combination thereof.

[0033] In the cell array area MCA, a plurality of word line trenches 120T each extending in the first horizontal direction X may be provided in the substrate 110, and the plurality of word line trenches 120T may be (at least partially) filled with a plurality of buried gate structures 120. Each of the plurality of buried gate structures 120 may include a gate dielectric layer 122, a buried gate electrode 124, and a capping insulating layer 126. The buried gate electrodes 124 included in the plurality of buried gate structures 120 may correspond to the plurality of word lines WL of FIG. 1. The gate dielectric layer 122 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and / or a high-k dielectric film having a higher dielectric constant than the silicon oxide layer.

[0034] The buried gate electrode 124 may include a work function control layer 124A conformally disposed on the lower inner wall of the plurality of word line trenches 120T, and a buried conductive layer 124B filling the portion between the lower inner walls of the plurality of word line trenches 120T. For example, the work function control layer 124A may extend at least partially around (e.g., at least partially surrounding) the buried conductive layer 124B. For example, the work function control layer 124A may include, for example, a metal, a metal nitride and / or a metal carbide, such as Ti, TiN, TiAlN, TiAlC, TiAlCN, TiSiCN, Ta, TaN, TaAlN, TaAlCN and / or TaSiCN, and the buried conductive layer 124B may include, for example, W, WN, TiN, TaN and / or doped polysilicon. A capping insulating layer 126 may be disposed on the upper surface of the gate dielectric layer and the buried gate electrode 124. The capping insulating layer 126 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and / or a combination thereof.

[0035] The buffer layer 114 may be formed on the substrate 110 in the cell array area MCA. The buffer layer 114 may include a first insulating layer 1141 and a second insulating layer 1142. Each of the first insulating layer 1141 and the second insulating layer 1142 may include, for example, an oxide layer, a nitride layer, and / or a combination thereof.

[0036] A plurality of direct contacts DC may be formed in a plurality of direct contact plug holes DCH on the substrate 110. The plurality of direct contacts DC may be connected (e.g., electrically connected) to the plurality of first active regions AC1. The plurality of direct contacts DC may include, for example, doped polysilicon. For example, the plurality of direct contacts DC may include polysilicon including a relatively high concentration of n-type impurities such as phosphorus (P), arsenic (As), bismuth (Bi), and / or antimony (Sb).

[0037] A plurality of bit lines BL may each extend along a second horizontal direction Y on the substrate 110 and a plurality of direct contacts DC. The plurality of bit lines BL may be connected (e.g., electrically connected) to the first active region AC via direct contacts DC, respectively. Each of the plurality of bit lines BL may include a lower conductive pattern 132A, an intermediate conductive pattern 134A, and an upper conductive pattern 136A sequentially stacked on the substrate 110. The lower conductive pattern 132A may include, for example, doped polysilicon. Each of the intermediate conductive pattern 134A and the upper conductive pattern 136A may include, for example, TiN, TiSiN, W, W silicide, and / or a combination thereof. According to some embodiments, the intermediate conductive pattern 134A may include, for example, TiN, TiSiN, and / or a combination thereof, and the upper conductive pattern 136A may include, for example, W.

[0038] The plurality of bit lines BL may be covered by a plurality of insulating capping structures 140, respectively. Each of the plurality of insulating capping structures 140 may include a lower capping pattern 142A, an intermediate capping pattern 144A, and an upper capping pattern 146A. The lower capping pattern 142A, the intermediate capping pattern 144A, and the upper capping pattern 146A may include, for example, a silicon nitride layer. The plurality of insulating capping structures 140 may extend along the second horizontal direction Y on the plurality of bit lines BL.

[0039] The cell spacing structure 150 may be disposed on two (e.g., opposite) side walls of each of the plurality of bit lines BL. The cell spacing structure 150 may extend along the second horizontal direction Y on two (e.g., opposite) side walls of the plurality of bit lines BL, and a portion of the cell spacing structure 150 may extend to the inside of the direct contact plug hole DCH, and thus at least partially cover (e.g., overlap) the two (e.g., opposite) side walls of the direct contact DC. In some embodiments, the cell spacing structure 150 may be on two (e.g., opposite) side walls of each of the plurality of insulating cover structures 140.

[0040] According to some embodiments, the cell spacing structure 150 may include a first spacing layer 152, a second spacing layer 154, and a third spacing layer 156. The first spacing layer 152 may be conformally disposed on the sidewalls of the plurality of bit lines BL, the sidewalls of the insulating capping structure 140, and / or the inner wall (e.g., inner sidewall) of the direct contact plug hole DCH. The second spacing layer 154 and the third spacing layer 156 may be sequentially disposed on the first spacing layer 152. According to some embodiments, the first spacing layer 152 and the third spacing layer 156 may include, for example, silicon nitride, and the second spacing layer 154 may include, for example, silicon oxide. According to some embodiments, the first spacing layer 152 and the third spacing layer 156 may include, for example, silicon nitride, and the second spacing layer 154 may include, for example, air or a low-k dielectric material. The term "air" used herein may refer to a space including the atmosphere or other gases that may be present during the manufacturing process.

[0041] The buried insulating layer 158 may be disposed on the first spacer layer 152, may extend around (e.g., at least partially surround) a lower portion of the direct contact DC, and may fill a remaining space of the direct contact plug hole DCH. The buried insulating layer 158 may include, for example, silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof.

[0042] The direct contact DC may be formed within the direct contact plug hole DCH formed in the substrate 110, and may extend to a level higher than the upper surface of the substrate 110. For example, the upper surface of the direct contact DC may be disposed at the same level as the upper surface of the lower conductive pattern 132A, and the upper surface of the direct contact DC may be connected (e.g., electrically connected) to the lower surface of the middle conductive pattern 134A. The lower surface of the direct contact DC may be disposed at a level lower than the upper surface of the substrate 110.

[0043] A plurality of insulating fences 162 and a plurality of conductive plugs 166 may be arranged in a row along the second horizontal direction Y between the plurality of bit lines BL in pairs adjacent to each other. The plurality of insulating fences 162 may be disposed on the capping insulating layer 126 disposed in the respective upper portions of the plurality of word line trenches 120T, and may have an upper surface disposed at the same level as the upper surface of the insulating capping structure 140 (e.g., the upper surface of the upper capping pattern 146A). Each of the plurality of conductive plugs 166 may extend from the recessed space RS formed in the substrate 110 in the vertical direction (Z direction). Two (e.g., opposite) sidewalls of each of the plurality of conductive plugs 166 may be spaced apart (e.g., insulated) from each other in the second horizontal direction Y by the plurality of insulating fences 162. The plurality of insulating fences 162 may include, for example, a silicon nitride layer. The plurality of conductive plugs 166 may constitute the plurality of buried contacts BC of FIG. 1 .

[0044] A plurality of metal silicide layers 168A and a plurality of landing pads LP may be formed on the plurality of conductive plugs 166. The metal silicide layers 168A and the landing pads P may be arranged to vertically overlap the conductive plugs 166 (e.g., overlap in the vertical direction Z). Each metal silicide layer 168A may include, for example, cobalt silicide, nickel silicide, and / or manganese silicide. The plurality of landing pads LP may be respectively connected (e.g., electrically connected) to the conductive plugs 166 through the metal silicide layers 168A. Each of the plurality of landing pads LP may include a conductive barrier layer 172A and a conductive layer 174A.

[0045] The plurality of landing pads LP may be spaced apart from each other (e.g., electrically insulated) by an insulating pattern 180A that (at least partially) fills an insulating space 180S surrounding (extending around) the plurality of landing pads LP. Each insulating pattern 180A may fill an insulating space 180S disposed between a bit line BL and a conductive plug 166, and may be located on (e.g., covers or overlaps) a sidewall (e.g., two / opposite sidewalls) of the insulating cover structure 140.

[0046] According to some embodiments, the insulating pattern 180A may include, for example, silicon nitride, silicon oxynitride, silicon oxide, and / or a combination thereof. According to some embodiments, the insulating pattern 180A may be formed as a double-layer structure of a first material layer (not shown) and a second material layer (not shown), and the first material layer may include, for example, a low-k material such as SiO 2 , SiOCH and / or SiOC, and the second material layer may include, for example, silicon nitride and / or silicon oxynitride.

[0047] In the peripheral circuit area PCA, a gate structure PGT may be provided on the substrate 110. The gate structure PGT may include a gate dielectric layer 116, a gate electrode PG, and a gate capping pattern 142B sequentially stacked on the second active area AC2. The gate structure PGT may include a plurality of gate structures. The plurality of gate structures PGT may be spaced apart from each other in the first horizontal direction X.

[0048] The gate dielectric layer 116 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and / or a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer. The gate electrode PG may include a lower conductive pattern 132B, an intermediate conductive pattern 134B, and an upper conductive pattern 136B. The respective constituent materials of the lower conductive pattern 132B, the intermediate conductive pattern 134B, and the upper conductive pattern 136B in the peripheral circuit area PCA may be respectively the same as the respective constituent materials of the lower conductive pattern 132A, the intermediate conductive pattern 134A, and the upper conductive pattern 136A included in the bit line BL in the cell array area MCA. The gate capping pattern 142B may include, for example, a silicon nitride layer.

[0049] The spacer structure SP1 may include an insulating spacer PGS, an inner protection layer 144B, and an outer protection layer OPL. The spacer structure SP1 may be disposed on each of two (eg, opposite) sidewalls of the plurality of gate structures PGT.

[0050] A plurality of insulating spacers PGS may be respectively located on (e.g., covering or overlapping) two (e.g., opposite) side walls of a plurality of gate structures PGT. According to some embodiments, the insulating spacer PGS may include, for example, an oxide layer, a nitride layer and / or a combination thereof. Although not shown in the drawings, the insulating spacer PGS may include a double layer (e.g., composed of a double layer). For example, the insulating spacer PGS may include a first insulating spacer (not shown) located on (e.g., covering or overlapping) two (e.g., opposite) side walls of the gate structure PGT and a second insulating spacer (not shown) located on (e.g., covering or overlapping) the first insulating spacer. For example, the second insulating spacer (not shown) may be located on (e.g., covering or overlapping) two (e.g., opposite) side walls of the first insulating spacer (not shown). According to some embodiments, the first insulating spacer may include, for example, a nitride layer, and the second insulating spacer may include, for example, an oxide layer.

[0051] The inner protection layer 144B may be disposed on the insulating spacer PGS. The inner protection layer 144B may be located on (e.g., covers or overlaps) the respective upper surfaces of the plurality of gate structures PGT and the plurality of insulating spacers PGS. For example, the inner protection layer 144B may be located on (e.g., covers or overlaps) two (e.g., opposite) sidewalls of the insulating spacer PGS and the upper surface of the gate structure PGT. According to some embodiments, the inner protection layer 144B may include, for example, a silicon nitride layer.

[0052] The outer protective layer OPL may be disposed on the inner protective layer 144B. The outer protective layer OPL may cover (or overlap) at least a portion of the inner protective layer 144B. For example, the outer protective layer OPL may be disposed on two (e.g., opposite) sidewalls of the inner protective layer 144B. According to some embodiments, the outer protective layer OPL may not extend over the gate structure PGT and may not cover the inner protective layer 144B on the gate structure PGT. For example, the outer protective layer OPL may not be disposed on the upper surface of the inner protective layer 144B. The upper surface of the inner protective layer 144B may be exposed from the outer protective layer OPL. According to some embodiments, the outer protective layer OPL may extend over the gate structure PGT and may cover (or overlap) the inner protective layer 144B (the upper surface of the inner protective layer 144B) on the gate structure PGT. The thickness of the extended portion of the outer protective layer OPL over the gate structure PGT may be adjusted by chemical mechanical polishing (CMP) on the outer protective layer OPL.

[0053] According to some embodiments, the outer protection layer OPL may extend (at least partially) along the inner protection layer 144B, and thus may be disposed on (e.g., covers or overlaps) a portion of the upper surface of the substrate 110. For example, the outer protection layer OPL may cover a portion of the upper surface of the substrate 110 that is not covered by the gate structure PGT, the insulating spacer PGS, and the inner protection layer 144B. The outer protection layer OPL may be disposed on (e.g., covers or overlaps) an upper surface of the isolation layer 112. The outer protection layer OPL may contact a portion of the upper surface of the substrate 110 that is not covered by the gate structure PGT, the insulating spacer PGS, and the inner protection layer 144B, and / or may contact the upper surface of the isolation layer 112.

[0054] According to some embodiments, the outer protection layer OPL may include a material different from that of the inner protection layer 144B, and may have an etching rate different from that of the inner protection layer 144B. That is, the outer protection layer OPL and the inner protection layer 144B may have etching selectivity. According to some embodiments, the outer protection layer OPL may include, for example, an oxide layer, a silicon oxide layer, SiOCN, SiON, SiOC, and / or a combination thereof. The terms "SiOCN", "SiON", and "SiOC" used herein refer to materials composed of the elements respectively included in these terms, rather than chemical formulas representing stoichiometric relationships.

[0055] On the spacer structure SP1, an insulating filling layer 145 may be provided. The insulating filling layer 145 may (at least partially) fill the space between the plurality of gate structures PGT (adjacent gate structures PGT therein) that is not filled by the spacer structure SP1. The outer protection layer OPL may extend around (e.g., at least partially surround) the insulating filling layer 145. The sidewalls of the insulating filling layer 145 may be spaced apart from the inner protection layer 144B in a manner that the outer protection layer OPL is interposed between the sidewalls of the insulating filling layer 145 and the inner protection layer 144B, and the lower surface of the insulating filling layer 145 may be spaced apart from the substrate 110 (upper surface) in a manner that the outer protection layer OPL is interposed between the lower surface of the insulating filling layer 145 and the substrate 110 (upper surface).

[0056] According to some embodiments, the insulating filling layer 145 may include a material different from that of the outer protective layer OPL, and may have an etching rate different from that of the outer protective layer OPL. That is, the insulating filling layer 145 and the outer protective layer OPL may have an etching selectivity. The insulating filling layer 145 may include a material different from that of the inner protective layer 144B, and may have an etching rate different from that of the inner protective layer 144B. That is, the insulating filling layer 145 and the inner protective layer 144B may have an etching selectivity. According to some embodiments, the insulating filling layer 145 may include, for example, a nitride layer and / or a silicon nitride layer.

[0057] The upper cover layer 146B may be disposed on the insulating filling layer 145. The upper cover layer 146B may be located on (e.g., covers or overlaps) the upper surface of the insulating filling layer 145, and may be located on (e.g., covers or overlaps) the portion of the upper surface of the spacer structure SP1 that is not covered (or overlapped) by the insulating filling layer 145. According to some embodiments, the outer protection layer OPL may not extend over the gate structure PGT, and the upper cover layer 146B may contact the portion of the inner protection layer 144B that is not covered by the outer protection layer OPL. According to some embodiments, the outer protection layer OPL may extend over the gate structure PGT, and the upper cover layer 146B may be spaced apart from the inner protection layer 144B in a manner that the outer protection layer OPL is interposed between the upper cover layer 146B and the inner protection layer 144B. For example, the upper cover layer 146B may be disposed on (e.g., contacts) the upper surface of the insulating filling layer 145, the upper surface of the inner protection layer 144B, and / or the upper surface of the outer protection layer OPL.

[0058] According to some embodiments, the upper cover layer 146B may have an etching rate different from that of the outer protection layer OPL, and may have an etching rate that is the same (or substantially the same) as that of the insulating fill layer 145. That is, the upper cover layer 146B and the outer protection layer OPL may have a first etching selectivity, but the upper cover layer 146B and the insulating fill layer 145 may not have an etching selectivity or a second etching selectivity that is (substantially) less than the first etching selectivity. For example, the upper cover layer 146B may include a silicon nitride layer.

[0059] In the peripheral circuit area PCA, a contact plug CP may be provided on the second active area AC2. In order to form the contact plug CP, a contact plug hole CPH extending (e.g., passing through or penetrating) in the upper cover layer 146B, the insulating filling layer 145, and the outer protective layer OPL along the vertical direction Z may be provided in the peripheral circuit area PCA. The contact plug CP may extend along the contact plug hole CPH to the second active area AC2 of the substrate 110. The contact plug CP may include a conductive barrier layer 172B and a conductive layer 174B, similar to the plurality of landing pads LP formed in the cell array area MCA. The conductive barrier layer 172B may conformally extend along the inner wall (e.g., the inner side wall and / or the inner lower surface) of the contact plug hole CPH, and the conductive layer 174B may fill the remaining portion of the contact plug hole CPH not filled by the conductive barrier layer 172B on the conductive barrier layer 172B. A metal silicide layer (not shown) may also be included between the contact plug CP and the second active area AC2. The metal silicide layer may include, for example, cobalt silicide, nickel silicide, or manganese silicide.

[0060] According to some embodiments, the outer protective layer OPL may include a side OPL1 and a lower OPL2. The side OPL1 of the outer protective layer OPL may extend (at least partially) along the inner protective layer 144B, and may be spaced apart from the contact plug CP in a manner that the insulating filling layer 145 is interposed between the side OPL1 of the outer protective layer OPL and the contact plug CP. According to some embodiments, the thickness d1 of the side OPL1 of the outer protective layer OPL (in the first horizontal direction X) may be within 5 nanometers to 10 nanometers. The lower OPL2 of the outer protective layer OPL may extend from the side OPL1 of the outer protective layer OPL along the upper surface of the substrate 110, and may contact the contact plug CP (e.g., the conductive barrier layer 172B). According to some embodiments, the thickness d2 of the lower OPL2 of the outer protective layer OPL (in the vertical direction Z) may be within 5 nanometers to 10 nanometers. Although the side OPL1 and the lower OPL2 of the outer protective layer OPL are shown as extending conformally, the side OPL1 and the lower OPL2 of the outer protective layer OPL are not limited to extending conformally. The thickness d1 of the side OPL1 of the outer protective layer OPL and the thickness d2 of the lower OPL2 of the outer protective layer OPL may be different from each other, and the embodiments of the inventive concept are not limited thereto. The inner protective layer 144B may be spaced apart from the contact plug CP in a manner that the outer protective layer OPL and / or the insulating filling layer 145 are interposed between the inner protective layer 144B and the contact plug CP. The insulating spacer PGS may be spaced apart from the contact plug CP in a manner that the inner protective layer 144B, the outer protective layer OPL and / or the insulating filling layer 145 are interposed between the insulating spacer PGS and the contact plug CP.

[0061] A plurality of contact plugs CP may be connected (e.g., electrically connected) to a plurality of peripheral bit lines 176B. Each of the plurality of peripheral bit lines 176B may be connected (e.g., electrically connected) to the second active region AC2 via the contact plug CP. The plurality of peripheral bit lines 176B may be spaced apart (e.g., electrically insulated) from each other by an insulating pattern 180B surrounding (e.g., extending around) the plurality of peripheral bit lines 176B. The insulating pattern 180B may fill the space between the plurality of peripheral bit lines 176B (the adjacent peripheral bit lines 176B therein) and may cover two (e.g., opposite) sidewalls of the plurality of peripheral bit lines 176B (the adjacent peripheral bit lines 176B therein).

[0062] According to some embodiments, each insulating pattern 180B may include, for example, silicon nitride, silicon oxynitride, silicon oxide, and / or a combination thereof. According to some embodiments, the insulating pattern 180B may include a double-layer structure of a first material layer (not shown) and a second material layer (not shown), and the first material layer may include, for example, a low-k material such as SiO 2 , SiOCH and / or SiOC, and the second material layer may include, for example, silicon nitride and / or silicon oxynitride.

[0063] According to the comparative example, the insulating filling layer 145 may have an etching rate different from that of the upper cover layer 146B. That is, in the comparative example, the insulating filling layer 125 and the upper cover layer 146B may have an etching selectivity. Because the insulating filling layer 145 has an etching rate different from that of the upper cover layer 146B, during the etching of the contact plug hole CPH, the diameter of the portion of the contact plug hole CPH contacting the insulating filling layer 145 in the first horizontal direction X and the second horizontal direction Y may be larger than the diameter of the portion of the contact plug hole CPH contacting the upper cover layer 146B in the first horizontal direction X and the second horizontal direction Y. Because the diameter of the portion of the contact plug hole CPH contacting the insulating filling layer 145 is larger than the diameter of the portion of the contact plug hole CPH contacting the upper cover layer 146B, a void may be formed inside the portion of the contact plug CP connected (e.g., contacting) to the insulating filling layer 145.

[0064] According to some embodiments of the inventive concepts of the present disclosure, since the insulating filling layer 145 has the same etching rate as that of the upper cover layer 146B, during etching of the contact plug hole CPH, the diameter of a portion of the contact plug hole CPH contacting the insulating filling layer 145 in the first horizontal direction X and the second horizontal direction Y may be formed to be substantially the same as the diameter of a portion of the contact plug hole CPH contacting the upper cover layer 146B in the first horizontal direction X and the second horizontal direction Y. Therefore, formation of a void inside a portion of the contact plug CP contacting the insulating filling layer 145 may be reduced (e.g., prevented), and ultimately structural stability of the semiconductor device 100 may be improved.

[0065] According to some embodiments of the inventive concept of the present disclosure, the insulating filling layer 145 may have the same etching rate as that of the upper cover layer 146B. However, because the outer protection layer OPL is interposed between the insulating filling layer 145 and the inner protection layer 144B and has an etching rate different from that of the insulating filling layer 145 and the inner protection layer 144B, and therefore when CMP is performed on the insulating filling layer 145, the outer protection layer OPL may be used as an etching stop layer, which may prevent the gate structure PGT from being damaged by CMP.

[0066] Figure 4A is a cross-sectional view for explaining a semiconductor device according to some embodiments.

[0067] Figure 4B is a cross-sectional view for explaining a semiconductor device according to some embodiments.

[0068] Figure 4C yes Figure 4A A magnified view of a portion of AR2.

[0069] refer to Figure 4A , Figure 4B and Figure 4C , the semiconductor device 200 has the same Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C 1, 2 and 3. However, the semiconductor device 200 may include a spacing structure SP2 instead of the spacing structure SP1. Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 shown is the same as or similar to FIG. 4A to FIG. 4C The description of the configuration of the semiconductor device 100 and the difference between the semiconductor device 200 will now be described in detail.

[0070] The semiconductor device 200 may include a cell array area MCA and a peripheral circuit area PCA, and a gate structure PGT may be formed on a second active area AC2 in the peripheral circuit area PCA. The gate structure PGT may include a gate dielectric layer 116, a gate electrode PG, and a gate capping pattern 142B sequentially stacked on the second active area AC2. The gate structure PGT may include a plurality of gate structures. The plurality of gate structures PGT may be spaced apart from each other in the first horizontal direction X.

[0071] The spacer structure SP2 may include an insulating spacer PGS, an inner protection layer 144B, and an outer protection layer OPL. The spacer structure SP2 may be disposed on each of two (eg, opposite) sidewalls of the plurality of gate structures PGT.

[0072] A plurality of insulating spacers PGS may be respectively located on (e.g., covering or overlapping) two (e.g., opposite) side walls of a plurality of gate structures PGT. According to some embodiments, each insulating spacer PGS may include, for example, an oxide layer, a nitride layer and / or a combination thereof. Although not shown in the drawings, the insulating spacer PGS may include a double layer. For example, the insulating spacer PGS may include a first insulating spacer (not shown) located on (e.g., covering or overlapping) two (e.g., opposite) side walls of the gate structure PGT and a second insulating spacer (not shown) located on (e.g., covering or overlapping) the first insulating spacer. According to some embodiments, the first insulating spacer may include, for example, a nitride layer, and the second insulating spacer may include, for example, an oxide layer.

[0073] The inner protection layer 144B may be disposed on the insulating spacer PGS. The inner protection layer 144B may be located on (e.g., covers or overlaps) the upper surfaces of each of the plurality of gate structures PGT and the plurality of insulating spacers PGS. For example, the inner protection layer 144B may be located on the upper surface of the gate capping pattern 142B and on two (e.g., opposite) sidewalls of the insulating spacer PGS. According to some embodiments, the inner protection layer 144B may include, for example, a silicon nitride layer.

[0074] According to some embodiments, the inner protection layer 144B may extend (at least partially) along the insulating spacer PGS, and thus may be located on (e.g., covers or overlaps) a portion of the upper surface of the substrate 110. For example, the inner protection layer 144B may be located on (e.g., covers or overlaps) a portion of the upper surface of the substrate 110 that is not covered (or overlapped) by the gate structure PGT and the insulating spacer PGS. The inner protection layer 144B may be located on (e.g., covers or overlaps) an upper surface of the isolation layer 112. The inner protection layer 144B may contact a portion of the upper surface of the substrate 110 that is not covered (or overlapped) by the gate structure PGT and the insulating spacer PGS. The inner protection layer 144B may contact the upper surface of the isolation layer 112.

[0075] The outer protective layer OPL may be disposed on the inner protective layer 144B. The outer protective layer OPL may cover (or overlap) at least a portion of the inner protective layer 144B. According to some embodiments, the outer protective layer OPL may not extend over the gate structure PGT and may not cover (or may not overlap) the inner protective layer 144B on the gate structure PGT. For example, the outer protective layer OPL may not be located on the upper surface of the inner protective layer 144B or the upper surface of the gate covering pattern 142B. According to some embodiments, the outer protective layer OPL may extend over the gate structure PGT to cover (or overlap) the inner protective layer 144B on the gate structure PGT. For example, the outer protective layer OPL may be located on the upper surface of the inner protective layer 144B or the upper surface of the gate covering pattern 142B. The thickness of the extended portion of the outer protective layer OPL over the gate structure PGT may be adjusted by CMP on the outer protective layer OPL.

[0076] According to some embodiments, the outer protection layer OPL may extend (at least partially) along the inner protection layer 144B, and thus may be located at (e.g., covers or overlaps) a portion of the upper surface of the substrate 110. The inner protection layer 144B may be disposed between the outer protection layer OPL and a portion of the upper surface of the substrate 110. For example, the outer protection layer OPL may cover (or overlap) a portion of the upper surface of the substrate 110 that is not covered (or overlapped) by the gate structure PGT, the insulating spacer PGS, and the inner protection layer 144B. The outer protection layer OPL may be located at (e.g., covers or overlaps) an upper surface of the isolation layer 112. The inner protection layer 144B may be located between the outer protection layer OPL and an upper surface of the isolation layer 112. The outer protection layer OPL may be spaced apart from the upper surface of the substrate 110 and the upper surface of the isolation layer 112 in such a manner that the inner protection layer 144B is interposed between the outer protection layer OPL and the upper surface of the substrate 110 and the upper surface of the isolation layer 112.

[0077] According to some embodiments, the outer protection layer OPL may have an etching rate different from that of the inner protection layer 144B. That is, the outer protection layer OPL and the inner protection layer 144B may have an etching selectivity. According to some embodiments, the outer protection layer OPL may include, for example, an oxide layer, a silicon oxide layer, SiOCN, SiON, SiOC, and / or a combination thereof.

[0078] On the spacing structure SP2, an insulating filling layer 145 may be provided. The insulating filling layer 145 may (at least partially) fill the remaining space in the space between the plurality of gate structures PGT (adjacent gate structures PGT therein) that is not filled by the spacing structure SP2. The outer protection layer OPL may extend around (e.g., at least partially surround) the insulating filling layer 145. For example, the sidewalls of the insulating filling layer 145 may be spaced apart from the inner protection layer 144B in a manner that the outer protection layer OPL is interposed between the sidewalls of the insulating filling layer 145 and the inner protection layer 144B, and the lower surface of the insulating filling layer 145 may be spaced apart from the inner protection layer 144B in a manner that the outer protection layer OPL is interposed between the lower surface of the insulating filling layer 145 and the inner protection layer 144B.

[0079] According to some embodiments, the insulating filling layer 145 may have an etching rate different from that of the outer protection layer OPL, and may have an etching rate the same (or substantially the same) as that of the inner protection layer 144B. According to some embodiments, the insulating filling layer 145 may include, for example, a nitride layer and / or a silicon nitride layer.

[0080] The upper cover layer 146B may be disposed on the insulating filling layer 145. The upper cover layer 146B may be located on (e.g., covers or overlaps) the upper surface of the insulating filling layer 145, and may cover (or overlap) a portion of the upper surface of the spacer structure SP2 that is not covered (or does not overlap) by the insulating filling layer 145. According to some embodiments, the outer protection layer OPL may not extend above the gate structure PGT, and the upper cover layer 146B may contact a portion of the inner protection layer 144B that is not covered by the outer protection layer OPL. For example, the upper cover layer 146B may contact the upper surface of the inner protection layer 144B. According to some embodiments, the outer protection layer OPL may extend above the gate structure PGT, and the upper cover layer 146B may be spaced apart from (the upper surface of) the inner protection layer 144B in a manner that the outer protection layer OPL is interposed between the upper cover layer 146B and the inner protection layer 144B.

[0081] According to some embodiments, the upper cover layer 146B may have an etch rate different from that of the outer protection layer OPL, and may have an etch rate the same (or substantially the same) as that of the insulating filling layer 145. For example, the upper cover layer 146B may include a silicon nitride layer.

[0082] In the peripheral circuit area PCA, a contact plug CP may be disposed on the second active area AC2. To form the contact plug CP, a contact plug hole CPH extending (e.g., passing through or penetrating) in the upper cover layer 146B, the insulating filling layer 145, and the outer protection layer OPL along the vertical direction Z may be disposed in the peripheral circuit area PCA. The contact plug CP may extend along the contact plug hole CPH to the second active area AC2 of the substrate 110.

[0083] According to some embodiments, the outer protective layer OPL may include a side OPL1 and a lower OPL2. The side OPL1 of the outer protective layer OPL may extend (at least partially) along the sidewall of the inner protective layer 144B, and may be spaced apart from the contact plug CP in a manner that the insulating filling layer 145 is interposed between the side OPL1 of the outer protective layer OPL and the contact plug CP. According to some embodiments, the thickness d1 of the side OPL1 of the outer protective layer OPL (in the first horizontal direction X) may be within 5 nanometers to 10 nanometers. The lower OPL2 of the outer protective layer OPL may extend from the side OPL1 of the outer protective layer OP along the upper surface of the inner protective layer 144B, and may contact the contact plug CP. According to some embodiments, the thickness d2 of the lower OPL2 of the outer protective layer OPL (in the vertical direction Z) may be within 5 nanometers to 10 nanometers. Although the side OPL1 and the lower OPL2 of the outer protective layer OPL are shown as extending conformally, the side OPL1 and the lower OPL2 of the outer protective layer OPL are not limited to extending conformally. The thickness d1 of the side OPL1 of the outer protective layer OPL and the thickness d2 of the lower OPL2 of the outer protective layer OPL may be different from each other, and the embodiments of the inventive concepts disclosed herein are not limited thereto. The inner protective layer 144B may extend (at least partially) along the upper surface of the substrate 110 and may contact the contact plug CP. The insulating spacer PGS may be spaced apart from the contact plug CP in a manner such that the inner protective layer 144B, the outer protective layer OPL and / or the insulating filling layer 145 are interposed between the insulating spacer PGS and the contact plug CP.

[0084] Figure 5A is a cross-sectional view for explaining a semiconductor device according to some embodiments.

[0085] Figure 5B is a cross-sectional view for explaining a semiconductor device according to some embodiments.

[0086] Figure 5C yes Figure 5A A magnified view of a portion of AR3.

[0087] refer to Figure 5A , Figure 5B and Figure 5C , the semiconductor device 300 has the same Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 300 may include a spacer structure SP3 instead of the spacer structure SP1. Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 shown is the same FIG. 5A to FIG. 5C The description of the configuration of the semiconductor device 100 and the difference between the semiconductor device 100 and the semiconductor device 300 will now be described in detail.

[0088] The semiconductor device 300 may include a cell array area MCA and a peripheral circuit area PCA, and a gate structure PGT may be formed on a second active area AC2 in the peripheral circuit area PCA. The gate structure PGT may include a gate dielectric layer 116, a gate electrode PG, and a gate capping pattern 142B sequentially stacked on the second active area AC2. The gate structure PGT may include a plurality of gate structures. The plurality of gate structures PGT may be spaced apart from each other in the first horizontal direction X.

[0089] The spacer structure SP3 may include an insulating spacer PGS, an inner protection layer 144B, and an outer protection layer OPL. The spacer structure SP3 may be disposed on each of two (eg, opposite) sidewalls of the plurality of gate structures PGT.

[0090] A plurality of insulating spacers PGS may be respectively located on (e.g., covering or overlapping) two (e.g., opposite) side walls of a plurality of gate structures PGT. According to some embodiments, each insulating spacer PGS may include, for example, an oxide layer, a nitride layer and / or a combination thereof. Although not shown in the drawings, the insulating spacer PGS may include a double layer. For example, the insulating spacer PGS may include a first insulating spacer (not shown) located on (e.g., covering or overlapping) two (e.g., opposite) side walls of the gate structure PGT and a second insulating spacer (not shown) located on (e.g., covering or overlapping) the first insulating spacer. According to some embodiments, the first insulating spacer may include, for example, a nitride layer, and the second insulating spacer may include, for example, an oxide layer.

[0091] The inner protection layer 144B may be disposed on the insulating spacer PGS. The inner protection layer 144B may be located on (e.g., covers or overlaps) the upper surface of each of the plurality of gate structures PGT, and the inner protection layer 144B may be located on (e.g., covers or overlaps) the sidewalls of the plurality of insulating spacers PGS. According to some embodiments, the inner protection layer 144B may include, for example, a silicon nitride layer.

[0092] The outer protective layer OPL may be disposed on the inner protective layer 144B. The outer protective layer OPL may cover (or overlap) at least a portion of the inner protective layer 144B. According to some embodiments, the outer protective layer OPL may not extend over the gate structure PGT, and may not be located on (e.g., not cover or overlap) the inner protective layer 144B on the gate structure PGT. For example, the outer protective layer OPL may be located on the sidewall of the inner protective layer 144B, and may not be located on the upper surface of the inner protective layer 144B. According to some embodiments, the outer protective layer OPL may extend over the gate structure PGT to cover (or overlap) the inner protective layer 144B on the gate structure PGT. For example, the outer protective layer OPL may be located on (e.g., covers or overlaps) the upper surface of the inner protective layer 144B. The thickness of the extended portion of the outer protective layer OPL over the gate structure PGT may be adjusted by CMP on the outer protective layer OPL.

[0093] According to some embodiments, the outer protection layer OPL may have an etching rate different from that of the inner protection layer 144B. That is, the outer protection layer OPL and the inner protection layer 144B may have an etching selectivity. According to some embodiments, the outer protection layer OPL may include, for example, an oxide layer, a silicon oxide layer, SiOCN, SiON, SiOC, and / or a combination thereof.

[0094] On the spacer structure SP3, an insulating filling layer 145 may be provided. The insulating filling layer 145 may (at least partially) fill the (remaining) space in the space between the plurality of gate structures PGT (adjacent gate structures PGT therein) that is not filled by the spacer structure SP3. The outer protection layer OPL may extend around (e.g., at least partially surround) the insulating filling layer 145. The sidewalls of the insulating filling layer 145 may be spaced apart from the inner protection layer 144B in such a manner that the outer protection layer OPL is interposed between the sidewalls of the insulating filling layer 145 and the inner protection layer 144B, and the lower surface of the insulating filling layer 145 may contact (the upper surface of) the substrate 110.

[0095] According to some embodiments, the insulating filling layer 145 may extend (at least partially) along the outer protection layer OPL, and thus may be located on (e.g., covers or overlaps) a portion of the upper surface of the substrate 110. For example, the insulating filling layer 145 may be located on (e.g., covers or overlaps) a portion of the upper surface of the substrate 110 between the spacing structure SP3 and the contact plug CP. The insulating filling layer 145 may be located on (e.g., covers or overlaps) an upper surface of the isolation layer 112. The insulating filling layer 145 may contact a portion of the upper surface of the substrate 110 between the spacing structure SP3 and the contact plug CP. The insulating filling layer 145 may contact an upper surface of the isolation layer 112.

[0096] According to some embodiments, the insulating filling layer 145 may have an etching rate different from that of the outer protection layer OPL, and may have an etching rate the same (or substantially the same) as that of the inner protection layer 144B. According to some embodiments, the insulating filling layer 145 may include, for example, a nitride layer and / or a silicon nitride layer.

[0097] The upper cover layer 146B may be disposed on the insulating filling layer 145 (upper surface). The upper cover layer 146B may cover or overlap the upper surface of the insulating filling layer 145, and may be located at (e.g., covers or overlaps) a portion of the upper surface of the spacer structure SP3 that is not covered (or overlapped) by the insulating filling layer 145. According to some embodiments, the outer protection layer OPL may not extend above the gate structure PGT, and the upper cover layer 146B may contact a portion of the inner protection layer 144B that is not covered (or overlapped) by the outer protection layer OPL. For example, the upper cover layer 146B may contact the upper surface of the inner protection layer 144B. According to some embodiments, the outer protection layer OPL may extend above the gate structure PGT, and the upper cover layer 146B may be spaced apart from (the upper surface of) the inner protection layer 144B in a manner such that the outer protection layer OPL is interposed between the upper cover layer 146B and the inner protection layer 144B.

[0098] According to some embodiments, the upper cover layer 146B may have an etch rate different from that of the outer protection layer OPL, and may have an etch rate the same (or substantially the same) as that of the insulating filling layer 145. For example, the upper cover layer 146B may include a silicon nitride layer.

[0099] In the peripheral circuit area PCA, a contact plug CP may be disposed on the second active area AC2. To form the contact plug CP, a contact plug hole CPH extending (e.g., passing through or penetrating) in the upper cover layer 146B and the insulating filling layer 145 along the vertical direction Z may be disposed in the peripheral circuit area PCA. The contact plug CP may extend to the second active area AC2 of the substrate 110 along the contact plug hole CPH.

[0100] According to some embodiments, the outer protection layer OPL may extend (at least partially) along the inner protection layer 144B, and may be spaced apart from the contact plug CP in a manner that the insulating filling layer 145 is between the outer protection layer OPL and the contact plug CP. According to some embodiments, the thickness d1 of the outer protection layer OPL (in the first horizontal direction X) may be within 5 nanometers to 10 nanometers. Although the outer protection layer OPL is shown as extending conformally, the outer protection layer OPL is not limited to extending conformally. The inner protection layer 144B may be spaced apart from the contact plug CP in a manner that the outer protection layer OPL and the insulating filling layer 145 are between the inner protection layer 144B and the contact plug CP. The insulating spacer PGS may be spaced apart from the contact plug CP in a manner that the inner protection layer 144B, the outer protection layer OPL and / or the insulating filling layer 145 are between the insulating spacer PGS and the contact plug CP.

[0101] Fig. 6A is a cross-sectional view for explaining a semiconductor device according to some embodiments.

[0102] Figure 6B is a cross-sectional view for explaining a semiconductor device according to some embodiments.

[0103] Figure 6C yes Fig. 6A A magnified view of a portion of AR4.

[0104] refer to Fig. 6A , Figure 6B and Figure 6C , the semiconductor device 400 has the same Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 400 may include a structure similar to that of the semiconductor device 100 shown in FIG. 1 (almost the same structure). However, the semiconductor device 400 may include a spacer structure SP4 instead of the spacer structure SP1. Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C The semiconductor device 100 shown is the same FIG. 6A to FIG. 6C The description of the configuration of the semiconductor device 100 and the difference between the semiconductor device 400 will now be described in detail.

[0105] The semiconductor device 400 may include a cell array area MCA and a peripheral circuit area PCA, and a gate structure PGT may be formed on a second active area AC2 in the peripheral circuit area PCA. The gate structure PGT may include a gate dielectric layer 116, a gate electrode PG, and a gate capping pattern 142B sequentially stacked on the second active area AC2. The gate structure PGT may include a plurality of gate structures. The plurality of gate structures PGT may be spaced apart from each other in the first horizontal direction X.

[0106] The spacer structure SP4 may include an insulating spacer PGS, an inner protection layer 144B, and an outer protection layer OPL. The spacer structure SP4 may be disposed on each of two (eg, opposite) sidewalls of the plurality of gate structures PGT.

[0107] A plurality of insulating spacers PGS may be respectively located on (e.g., covering or overlapping) two (e.g., opposite) side walls of a plurality of gate structures PGT. According to some embodiments, each insulating spacer PGS may include, for example, an oxide layer, a nitride layer and / or a combination thereof. Although not shown in the drawings, the insulating spacer PGS may include a double layer. For example, the insulating spacer PGS may include a first insulating spacer (not shown) located on (e.g., covering or overlapping) two (e.g., opposite) side walls of the gate structure PGT and a second insulating spacer (not shown) located on (e.g., covering or overlapping) the first insulating spacer. According to some embodiments, the first insulating spacer may include, for example, a nitride layer, and the second insulating spacer may include, for example, an oxide layer.

[0108] The inner protection layer 144B may be disposed on the insulating spacer PGS. The inner protection layer 144B may be located on (e.g., covers or overlaps) the upper surface of each of the plurality of gate structures PGT. The inner protection layer 144B may be located on (e.g., covers or overlaps) the sidewalls of the plurality of insulating spacers PGS. According to some embodiments, the inner protection layer 144B may include, for example, a silicon nitride layer.

[0109] The outer protective layer OPL may be disposed on the inner protective layer 144B. The outer protective layer OPL may cover or overlap at least a portion of the inner protective layer 144B. For example, the outer protective layer OPL may be located on (e.g., covers or overlaps) the sidewall of the inner protective layer 144B. According to some embodiments, the outer protective layer OPL may not extend over the gate structure PGT, and may not be located on (e.g., does not cover or overlap) the inner protective layer 144B on the gate structure PGT. For example, the outer protective layer OPL may not be located on (does not cover or overlap) the upper surface of the inner protective layer 144B. According to some embodiments, the outer protective layer OPL may extend over the gate structure PGT to cover or overlap the inner protective layer 144B on the gate structure PGT. For example, the outer protective layer OPL may be located on (e.g., covers or overlaps) the upper surface of the inner protective layer 144B. The thickness of the extended portion of the outer protective layer OPL over the gate structure PGT may be adjusted by CMP on the outer protective layer OPL.

[0110] According to some embodiments, the outer protection layer OPL may extend (at least partially) along the inner protection layer 144B, and thus may be located on (e.g., covers or overlaps) a portion of the upper surface of the substrate 110. For example, the outer protection layer OPL may cover (or overlap) a portion of the upper surface of the substrate 110 that is not covered (or overlapped) by the gate structure PGT, the insulating spacer PGS, and the inner protection layer 144B. The outer protection layer OPL may be located on (e.g., covers or overlaps) an upper surface of the isolation layer 112. The outer protection layer OPL may contact a portion of the upper surface of the substrate 110 that is not covered (or overlapped) by the gate structure PGT, the insulating spacer PGS, and the inner protection layer 144B. The outer protection layer OPL may contact the upper surface of the isolation layer 112.

[0111] According to some embodiments, the outer protection layer OPL may have an etching rate different from that of the inner protection layer 144B. That is, the outer protection layer OPL and the inner protection layer 144B may have an etching selectivity. According to some embodiments, the outer protection layer OPL may include, for example, an oxide layer, a silicon oxide layer, SiOCN, SiON, SiOC, and / or a combination thereof.

[0112] On the spacer structure SP4, an insulating filling layer 145 may be provided. The insulating filling layer 145 may (at least partially) fill the (remaining) space in the space between the plurality of gate structures PGT (adjacent gate structures PGT therein) that is not filled by the spacer structure SP4. The outer protection layer OPL may extend around (e.g., at least partially surround) the insulating filling layer 145. The sidewall of the insulating filling layer 145 may be spaced apart from the inner protection layer 144B in a manner that the outer protection layer OPL is interposed between the sidewall of the insulating filling layer 145 and the inner protection layer 144B, and the lower end (e.g., the lower surface) of the insulating filling layer 145 may be spaced apart from the substrate 110 in a manner that the outer protection layer OPL is interposed between the lower end (e.g., the lower surface) of the insulating filling layer 145 and the substrate 110.

[0113] According to some embodiments, the insulating filling layer 145 may have an etching rate different from that of the outer protection layer OPL, and may have an etching rate the same as (e.g., substantially the same as) that of the inner protection layer 144B. According to some embodiments, the insulating filling layer 145 may include, for example, a nitride layer or a silicon nitride layer.

[0114] The upper cover layer 146B may be disposed on the insulating filling layer 145. The upper cover layer 146B may be located on (e.g., covers or overlaps) the upper surface of the insulating filling layer 145, and may be located on (e.g., covers or overlaps) a portion of the upper surface of the spacer structure SP4 that is not covered by the insulating filling layer 145. According to some embodiments, the outer protection layer OPL may not extend over the gate structure PGT, and the upper cover layer 146B may contact a portion (e.g., the upper surface) of the inner protection layer 144B that is not covered by the outer protection layer OPL. According to some embodiments, the outer protection layer OPL may extend over the gate structure PGT, and the upper cover layer 146B may be spaced apart from (the upper surface of) the inner protection layer 144B in a manner that the outer protection layer OPL is interposed between the upper cover layer 146B and the inner protection layer 144B.

[0115] According to some embodiments, the upper cover layer 146B may have an etch rate different from that of the outer protection layer OPL, and may have an etch rate the same as (eg, substantially the same as) that of the insulating filling layer 145. For example, the upper cover layer 146B may include a silicon nitride layer.

[0116] A contact plug hole CPH extending (e.g., passing through or penetrating) in the upper cover layer 146B and the insulating filling layer 145 in the vertical direction Z may be provided in the peripheral circuit area PCA. A contact plug CP may be provided in the contact plug hole CPH, and the contact plug CP may extend along the contact plug hole CPH to the second active area AC2 of the substrate 110.

[0117] According to some embodiments, the outer protective layer OPL may extend along the inner protective layer 144B and may contact the sidewall of the contact plug CP. According to some embodiments, the thickness d1 of the outer protective layer OPL (in the first horizontal direction X) may be within 5 nanometers to 20 nanometers. Although the outer protective layer OPL is shown as extending conformally, the outer protective layer OPL is not limited to extending conformally. The inner protective layer 144B may be spaced apart from the contact plug CP in a manner such that the outer protective layer OPL and the insulating filling layer 145 are between the inner protective layer 144B and the contact plug CP. The insulating spacer PGS may be spaced apart from the contact plug CP in a manner such that the outer protective layer OPL, the insulating filling layer 145 and the inner protective layer 144B are between the insulating spacer PGS and the contact plug CP. In some embodiments, the outer protective layer OPL, the inner protective layer 144B and the insulating spacer PGS may contact the upper surface of the substrate 110. The insulating filling layer 145 may be spaced apart from the upper surface of the substrate 110 in such a manner that the outer protection layer OPL is interposed between the insulating filling layer 145 and the substrate 110 .

[0118] 7A to 19A and FIG. 7B to FIG. 19B is a cross-sectional view for explaining a method of manufacturing a semiconductor device 100 according to some embodiments. Specifically, 7A to 19A According to the manufacturing process and along Figure 1A A cross-sectional view of some components of a partial area corresponding to a cross-sectional view taken along the line A1-A1', and FIG. 7B to FIG. 19B According to the manufacturing process and along Figure 1B The cross-section taken along the line B1 - B1 ′ corresponds to a cross-sectional view of some components of the portion.

[0119] refer to Fig. 7A and Figure 7B , a plurality of isolation trenches 112T and a plurality of isolation layers 112 may be formed in a substrate 110 having a cell array area MCA and a peripheral circuit area PCA to define a plurality of first active areas AC1 in the cell array area MCA of the substrate 110 and a second active area AC2 in the peripheral circuit area PCA of the substrate 110 .

[0120] In the cell array region MCA of the substrate 110, a plurality of linear word line trenches (not shown) extending parallel to each other in the first horizontal direction X and crossing (overlapping) the first active region AC1 may be formed to form Figure 1AIn order to form a plurality of word line trenches each having a step on its lower surface, the isolation layer 112 and the substrate 110 may be etched by separate etching processes, respectively, and thus have different etching depths. The resulting structure in which the plurality of word line trenches are formed may be cleaned, and then a dielectric material, a conductive material, and an insulating material may be formed in a prescribed order in each of the plurality of word line trenches. Before or after forming the plurality of word lines, an ion implantation process may be performed to form a plurality of source / drain regions above (in) the plurality of first active regions AC1.

[0121] refer to Fig. 8A and Figure 8B In the cell array area MCA, a buffer layer 114 including a first insulating layer 1141 and a second insulating layer 1142 may be formed on the substrate 110 , and in the peripheral circuit area PCA, a gate dielectric layer 116 may be formed on the substrate 110 .

[0122] Thereafter, a lower conductive layer 132 may be formed on the buffer layer 114 in the cell array area MCA and the gate dielectric layer 116 in the peripheral circuit area PCA. According to some embodiments, the lower conductive layer 132 may include, for example, Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, and / or combinations thereof. For example, the lower conductive layer 132 may include polysilicon.

[0123] refer to Fig.9A and Fig. 9B After forming a first mask pattern (not shown) on the lower conductive layer 132, the lower conductive layer 132 exposed by the opening (not shown) of the first mask pattern may be etched in the cell array region MCA. Thereafter, the exposed portion of the substrate 110 and the portion of the isolation layer 112 may be etched to form a direct contact plug hole DCH. A selected one of the first active regions AC1 (at least one first active region AC1) of the substrate 110 may be exposed through the direct contact plug hole DCH.

[0124] Thereafter, the first mask pattern may be removed, and a direct contact DC may be formed in the direct contact plug hole DCH. In an example of a process for forming a direct contact DC, a conductive layer having a thickness sufficient to fill the direct contact plug hole DCH may be formed in the direct contact plug hole DCH and on (the upper surface of) the lower conductive layer 132, and the conductive layer may be etched back so that the conductive layer remains only in the direct contact plug hole DCH. The conductive layer on (the upper surface of) the lower conductive layer 132 may be removed. The conductive layer may include, for example, polysilicon.

[0125] Then, in the cell array area MCA and the peripheral circuit area PCA, an intermediate conductive layer 134, an upper conductive layer 136, and a lower cover layer 142 may be formed on the lower conductive layer 132 and the direct contact DC in a prescribed order. According to some embodiments, each of the intermediate conductive layer 134 and the upper conductive layer 136 may include, for example, TiN, TiSiN, W, W silicide, and / or a combination thereof. The lower cover layer 142 may include, for example, a silicon nitride layer.

[0126] refer to Fig. 10A and Fig. 10B , in the case where the cell array area MCA is covered by a mask pattern (not shown), the gate dielectric layer 116, the lower conductive layer 132, the middle conductive layer 134, the upper conductive layer 136, and the lower cover layer 142 may be patterned in the peripheral circuit area PCA to form a gate electrode PG consisting of a lower conductive pattern 132B, an middle conductive pattern 134B, and an upper conductive pattern 136B located on the gate dielectric layer 116, and to form a gate cover pattern 142B located on (e.g., covering or overlapping) the gate electrode PG. Thereafter, an insulating spacer PGS may be formed on both (e.g., opposite) sidewalls of the gate structure PGT having the stacked structure of the gate dielectric layer 116, the gate electrode PG, and the gate cover pattern 142B, and an ion implantation process may be performed to form source / drain regions in the second active area AC2 on both (e.g., opposite) sides of (located on) the gate structure PGT.

[0127] Then, the mask pattern covering the cell array area MCA may be removed to expose the lower cover layer 142 in the cell array area MAC. An insulating layer 144 may be formed that covers or overlaps the lower cover layer 142 in the cell array area MCA and covers or overlaps the gate structure PGT, the insulating spacer PGS, and the exposed portion of the upper surface of the substrate 10 in the peripheral circuit area PCA. Thereafter, the insulating layer 144 may be patterned in the peripheral circuit area PCA by using a mask pattern (not shown) to form an inner protective layer 144B covering (or overlapping) the gate structure PGT, the insulating spacer PGS, and a portion of the upper surface of the substrate 110. According to some embodiments, the inner protective layer 144B may include a silicon nitride layer.

[0128] refer to Fig.11A and Fig. 11B , can be in (e.g., covering or overlapping) Fig. 10A and Fig. 10BAn outer protective layer OPL is formed on the resulting structure. An outer protective layer OPL of the cell array area MCA may be formed on the insulating layer 144 (e.g., covering or overlapping). An outer protective layer OPL of the peripheral circuit area PCA may be formed on (e.g., covering or overlapping) the inner protective layer 144B and the exposed portion of the upper surface of the substrate 110. According to some embodiments, the outer protective layer OPL may have an etching rate different from the etching rate of the inner protective layer 144B. That is, the outer protective layer OPL and the inner protective layer 144B may have etching selectivity. According to some embodiments, the outer protective layer OPL may include, for example, an oxide layer, a silicon oxide layer, SiOCN, SiON, SiOC and / or a combination thereof. The terms "SiOCN", "SiON" and "SiOC" used herein refer to materials composed of the elements respectively included in these terms, rather than chemical formulas representing stoichiometric relationships.

[0129] An insulating filling layer 145 may be formed on the outer protective layer OPL of the cell array area MCA and the outer protective layer OPL of the peripheral circuit area PCA. The insulating filling layer 145 of the cell array area MCA may be formed to cover or overlap the outer protective layer OPL. The insulating filling layer 145 in the peripheral circuit area PCA may cover or overlap the outer protective layer OPL, and may (at least partially) fill the (remaining) space between the (adjacent) gate structures PGT that is not filled by the insulating spacer PGS, the inner protective layer 144B, and the outer protective layer OPL. According to some embodiments, the insulating filling layer 145 may have an etching rate different from that of the outer protective layer OPL, and may have an etching rate the same as that of the inner protective layer 144B. According to some embodiments, the insulating filling layer 145 may include, for example, a nitride layer and / or a silicon nitride layer.

[0130] refer to Fig. 12A and Fig. 12B , CMP may be performed on the insulating filling layer 145 in the cell array area MCA and the peripheral circuit area PCA. The outer protection layer OPL may be exposed by CMP on the insulating filling layer 145 in the cell array area MCA, and a portion of the outer protection layer OPL above (on) the gate structure PGT may be exposed by CMP on the insulating filling layer 145 in the peripheral circuit area PCA. For example, at least a portion of the upper surface of the outer protection layer OPL may be exposed by CMP on the insulating filling layer 145.

[0131] Afterwards, CMP may be performed through the outer protective layer OPL of the cell array region MCA and the outer protective layer OPL above (on) the gate structure PGT in the peripheral circuit region PCA that are exposed by CMP. The insulating layer 144 may be exposed by CMP on the outer protective layer OPL in the cell array region MCA, and a portion of the inner protective layer 144B above the gate structure PGT may be exposed via CMP on the outer protective layer OPL above the gate structure PGT in the peripheral circuit region PCA. For example, at least a portion of the upper surface of the insulating layer 144 may be exposed by CMP on the outer protective layer OPL.

[0132] Because the insulating filling layer 145 has an etching rate different from that of the outer protection layer OPL, the outer protection layer OPL may be used as an etching stop layer during CMP with respect to the insulating filling layer 145. Because the outer protection layer OPL has an etching rate different from that of the inner protection layer 144B, the inner protection layer 144B may be used as an etching stop layer during CMP with respect to the outer protection layer OPL.

[0133] refer to Fig.13A and Fig. 13B , can be in (e.g., covering or overlapping) Fig. 12A and Fig. 12B An upper cap layer 146 is formed on the resulting structure after CMP.

[0134] Thereafter, a mask pattern (not shown) may be formed on the peripheral circuit area PCA, and the upper cover layer 146, the insulating layer 144, and the lower cover layer 142 may be patterned in the cell array area MCA, thereby forming a lower cover pattern 142A, an intermediate cover pattern 144A, and an upper cover pattern 146A sequentially stacked on the upper conductive layer 136. The lower cover pattern 142A, the intermediate cover pattern 144A, and the upper cover pattern 146A are referred to as an insulating cover structure 140.

[0135] refer to Fig.14A and Fig. 14B , the upper conductive layer 136, the middle conductive layer 134 and the lower conductive layer 132 can be etched using the lower covering pattern 142A, the middle covering pattern 144A and the upper covering pattern 146A as etching masks in the cell array area MCA to form a plurality of bit lines BL consisting of the lower conductive pattern 132A, the middle conductive pattern 134A and the upper conductive pattern 136A.

[0136] In the process of forming the plurality of bit lines BL, a portion directly contacting the sidewall of the DC may be removed, and a portion directly contacting the plug hole DCH may be exposed.

[0137] refer to Fig.15A and Fig. 15B, a first spacer 152 may be formed on the sidewalls of the plurality of bit lines BL and the sidewalls of the direct contacts DC. Thereafter, an insulating layer (not shown) may be formed on the sidewalls of the plurality of bit lines BL and the sidewalls of the direct contacts DC to have a thickness sufficient to fill the insides of the direct contact plug holes DCH, and then the insulating layer is anisotropically etched to leave a buried insulating layer 158 filling (at least partially filling) the insides of the direct contact plug holes DCH.

[0138] The second spacer 154 may be formed on the sidewalls of the plurality of bit lines BL to be located on (e.g., cover or overlap) the first spacer 152. The second spacer 154 may be used as an etching mask to remove a portion of the buffer layer 114 disposed between the plurality of bit lines BL, and may expose the upper surface of the substrate 110. At this time, a portion of the buried insulating layer 158 may also be removed.

[0139] Thereafter, a third spacer 156 may be formed on the sidewalls of the plurality of bit lines BL and the upper surface of the substrate 110 .

[0140] refer to Fig.16A and Fig. 16B ,exist Fig.15A and Fig. 15B In the resulting structure, the third spacer layer 156 defines Fig.15A and Fig. 15B A plurality of insulating barriers (not shown) spaced apart from each other in the line space LS in the cell may be formed between the plurality of bit lines BL in pairs adjacent to each other to separate the space defined by the third spacer layer 156 into a plurality of contact spaces CS. While forming the plurality of insulating barriers (not shown), the heights of the insulating capping structure 140 and the cell spacing structure 150 may be reduced.

[0141] Thereafter, the structure exposed by the plurality of contact spaces CS may be partially removed to form a plurality of recessed spaces RS exposing the first active area AC1 of the substrate 110 between the plurality of bit lines BL in pairs adjacent to each other. The plurality of recessed spaces RS may be formed via anisotropic etching or a combination of anisotropic etching and isotropic etching. For example, the third spacer 156 and respective portions of the substrate 110 below the third spacer 156 exposed by the plurality of contact spaces CS between the plurality of bit lines BL may be anisotropically etched, and portions of the first active area AC1 of the substrate 110 may be isotropically etched to form the plurality of recessed spaces RS. The plurality of recessed spaces RS may be connected to the contact spaces CS. When the etching process for forming the contact spaces CS is performed, respective portions of the cell spacing structure 150 and the buried insulating layer 158 may be (partially) consumed in an area adjacent to the upper surface of the substrate 110.

[0142] refer to Fig.17A and Fig. 17B In the cell array area MCA, a plurality of conductive plugs 166 may be formed to fill portions of the contact spaces CS between the plurality of bit lines BL while (at least partially) filling the plurality of recessed spaces RS between the plurality of bit lines BL.

[0143] Thereafter, a metal silicide layer 168A may be formed on the conductive plugs 166 exposed through the plurality of contact spaces CS in the cell array area MCA.

[0144] Thereafter, a plurality of contact plug holes CPH exposing the second active area AC2 of the substrate 110 may be formed in the peripheral circuit area PCA. According to some embodiments, the plurality of contact plug holes CPH may be formed by etching respective portions of the upper cover layer 146B, the insulating filling layer 145, and the outer protective layer OPL. The upper cover layer 146B, the insulating filling layer 145, and the outer protective layer OPL may be exposed through the plurality of contact plug holes CPH. For example, the sidewalls of the upper cover layer 146B, the sidewalls of the insulating filling layer 145, and the sidewalls of the outer protective layer OPL may be exposed through the plurality of contact plug holes CPH.

[0145] The process of forming the plurality of contact plug holes CPH may be performed earlier than the process of forming the metal silicide layer 168A in the cell array region MCA. In this case, the same metal silicide layer as the metal silicide layer 168A of the cell array region MCA may be formed along the inner wall of the contact plug holes CPH of the peripheral circuit region PCA.

[0146] According to the comparative example, in the process of etching the upper cover layer 146B and the insulating filling layer 145 to form a plurality of contact plug holes CPH, the insulating filling layer 145 may have an etching rate different from that of the upper cover layer 146B. Because the insulating filling layer 145 has an etching rate different from that of the upper cover layer 146B, the diameter of a portion of the contact plug hole CPH contacting the insulating filling layer 145 in the first horizontal direction X and the second horizontal direction Y may be greater than the diameter of a portion of the contact plug hole CPH contacting the upper cover layer 146B in the first horizontal direction X and the second horizontal direction Y. Because the diameter of a portion of the contact plug hole CPH contacting the insulating filling layer 145 is greater than the diameter of a portion of the contact plug hole CPH contacting the upper cover layer 146B, a void may be formed inside a portion of the contact plug CP connected to (contacting) the insulating filling layer 145.

[0147] According to some embodiments of the inventive concepts of the present disclosure, since the insulating filling layer 145 may have the same etching rate as that of the upper cover layer 146B, the diameter of the portion of the contact plug hole CPH contacting the insulating filling layer 145 in the first horizontal direction X and the second horizontal direction Y may be formed to be substantially the same as the diameter of the portion of the contact plug hole CPH contacting the upper cover layer 146B in the first horizontal direction X and the second horizontal direction Y. Therefore, the formation of a void inside the portion of the contact plug CP contacting the insulating filling layer 145 may be reduced (e.g., prevented), and ultimately the structural stability of the semiconductor device 100 may be improved.

[0148] refer to Fig.18A and Fig.18B , a conductive barrier layer 172 may be formed to conformally cover (or overlap) Fig.17A and Fig. 17B of the surface of the resulting structure. After forming the conductive barrier layer 172, a conductive layer 174 may be formed on (e.g., covering or overlapping) the conductive barrier layer 172. In the cell array area MCA, the conductive layer 174 may be formed to have a sufficient width and a sufficient height to (at least partially) fill a portion of the contact space CS between the plurality of bit lines BL. In the peripheral circuit area PCA, the conductive layer 174 may be formed to have a sufficient width and a sufficient height to (at least partially) fill a plurality of contact plug holes CPH. The conductive barrier layer 172B and the conductive layer 174B formed in the plurality of contact plug holes CPH may form a contact plug CP. The conductive layer 174B may be formed to have a sufficient width and a sufficient height to form a peripheral bit line, which will be described later.

[0149] refer to Fig.19A and Fig.19B , you can Fig.18A and Fig.18B The conductive layer 174 and the conductive barrier layer 172 are patterned in the cell array area MCA to form a plurality of landing pads LP. In order to form the plurality of landing pads LP, a mask pattern (not shown) for exposing a portion of the conductive layer 174 may be formed, and the mask pattern may be used as an etching mask to etch the conductive layer 174, the conductive barrier layer 172, and the insulating layer extending around (e.g., at least partially surrounding) the conductive layer 174 and the conductive barrier layer 172 to form an insulating space 180S. The mask pattern may be formed of a silicon nitride layer, but is not limited thereto.

[0150] 1 , the plurality of landing pads LP may have a plurality of island patterns. The plurality of landing pads LP may be formed on the metal silicide layer 168A to overlap portions of the plurality of bit lines BL in the vertical direction Z. As shown in FIG.

[0151] Thereafter, an insulating pattern 180A may be formed on the inner wall of the insulating space 180S in the cell array area MCA using an insulating material. The insulating pattern 180A may be formed by, for example, spin coating, chemical vapor deposition (CVD), or flowable CVD.

[0152] Thereafter, a capacitor lower electrode (not shown) may be formed on the plurality of landing pads LP in the cell array area MCA.

[0153] exist Fig.18A and Fig.18B In the peripheral circuit area PCA of the present invention, a plurality of peripheral bit lines 176B connected (e.g., electrically connected) to the plurality of contact plugs CP may be formed by patterning the conductive layer 174 and the conductive barrier layer 172. In order to form the plurality of peripheral bit lines 176B, a mask pattern (not shown) for exposing a portion of the conductive layer 174 may be formed, and the mask pattern may be used as an etching mask to etch the conductive layer 174, the conductive barrier layer 172, and the insulating layer extending around (e.g., at least partially surrounding) the conductive layer 174 and the conductive barrier layer 172 to form an insulating space 180S. The mask pattern may be formed of a silicon nitride layer, but is not limited thereto. The plurality of peripheral bit lines 176B may be spaced apart (e.g., insulated) from each other by the insulating pattern 180B formed in the insulating space 180S.

[0154] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device, comprising: substrate; a plurality of gate structures located on the substrate, wherein the plurality of gate structures include a first gate structure and a second gate structure adjacent to the first gate structure; a spacer structure, the spacer structure being located on opposite sidewalls of the first gate structure; Wherein, the spacing structure comprises: an insulating spacer located on opposite sidewalls of the first gate structure; an inner protection layer, the inner protection layer being located on an upper surface of the first gate structure and the insulating spacer; and an outer protective layer, the outer protective layer being located on at least a portion of the inner protective layer, an insulating filling layer being located on the spacer structure, wherein the insulating filling layer is located between the first gate structure and the second gate structure; and an upper covering layer, the upper covering layer being located on an upper surface of the insulating filling layer, Wherein, the upper covering layer comprises the same material as the insulating filling layer.

2. The semiconductor device according to claim 1, wherein The outer protection layer includes an oxide layer, a silicon oxide layer, SiOCN, SiON and / or SiOC.

3. The semiconductor device according to claim 1, wherein The inner protection layer includes a nitride layer and / or a silicon nitride layer.

4. The semiconductor device according to claim 1, wherein The insulating filling layer includes a nitride layer and / or a silicon nitride layer.

5. The semiconductor device according to claim 1, wherein The outer protective layer is located on the upper surface of the substrate, and The insulating filling layer has a side wall, and the side wall of the insulating filling layer is separated from the inner protective layer in a way that the outer protective layer is interposed between the side wall of the insulating filling layer and the inner protective layer, and the insulating filling layer has a lower surface, and the lower surface of the insulating filling layer is spaced from the upper surface of the substrate in a way that the outer protective layer is interposed between the lower surface of the insulating filling layer and the upper surface of the substrate.

6. The semiconductor device according to claim 5, further comprising: a contact plug extending in the upper cover layer and the insulating filling layer along a first direction perpendicular to the upper surface of the substrate, Wherein, the outer protective layer comprises: a side portion extending along the inner protective layer; and a lower portion extending from the side of the outer protection layer to the contact plug along the upper surface of the substrate, and The lower portion of the outer protective layer contacts a sidewall of the contact plug.

7. The semiconductor device according to claim 1, wherein The outer protective layer is located on the upper surface of the substrate, The outer protective layer extends along the inner protective layer onto the upper surface of the substrate, and The side walls of the insulating filling layer are spaced apart from the inner protective layer in a manner that the outer protective layer is interposed between the side walls of the insulating filling layer and the inner protective layer, and the lower surface of the insulating filling layer is spaced apart from the upper surface of the substrate in a manner that the outer protective layer and the inner protective layer are interposed between the lower surface of the insulating filling layer and the upper surface of the substrate.

8. The semiconductor device according to claim 7, further comprising: a contact plug extending in the upper cover layer and the insulating filling layer along a first direction perpendicular to the upper surface of the substrate, Wherein, the outer protective layer comprises: a side portion extending along the inner protective layer; and a lower portion extending from the side of the outer protection layer to the contact plug along the upper surface of the substrate, and The lower portion of the outer protective layer contacts a sidewall of the contact plug.

9. The semiconductor device according to claim 1, wherein: The insulating filling layer contacts an upper surface of the substrate.

10. The semiconductor device according to claim 9, further comprising: a contact plug extending in the insulating filling layer and the upper cover layer along a first direction perpendicular to the upper surface of the substrate, The sidewall of the contact plug is spaced apart from the outer protection layer in a manner that the insulating filling layer is interposed between the sidewall of the contact plug and the outer protection layer.

11. A semiconductor device, comprising: substrate; a plurality of gate structures located on the substrate; A spacing structure, wherein the spacing structures are respectively located on opposite side walls of each of the plurality of gate structures; Wherein, the spacing structure comprises: a plurality of insulating spacers, the plurality of insulating spacers being respectively located on opposite sidewalls of the plurality of gate structures; an inner protection layer, the inner protection layer being located on upper surfaces of the plurality of gate structures and the plurality of insulating spacers; and an outer protective layer, the outer protective layer being located on at least a portion of the inner protective layer, and an insulating filling layer, the insulating filling layer being located between adjacent gate structures among the plurality of gate structures, wherein the insulating filling layer is located on the spacer structure; an upper covering layer, the upper covering layer being located on an upper surface of the insulating filling layer, and a contact plug extending in the insulating filling layer and the upper cover layer along a first direction perpendicular to the upper surface of the substrate, Wherein, the outer protective layer includes an oxide layer, a silicon oxide layer, SiOCN, SiON and / or SiOC.

12. The semiconductor device according to claim 11, wherein The insulating filling layer includes the same material as the upper cover layer.

13. The semiconductor device according to claim 11, wherein The insulating filling layer includes a nitride layer and / or a silicon nitride layer.

14. The semiconductor device according to claim 11, wherein The contact plug includes: a conductive barrier layer extending along an inner wall of the contact plug hole; and A conductive layer at least partially fills a remaining space in the contact plug hole.

15. The semiconductor device according to claim 11, wherein The outer protective layer extends along the inner protective layer onto a portion of the upper surface of the substrate, and The side walls of the insulating filling layer are spaced apart from the inner protective layer in a manner that the outer protective layer is interposed between the side walls of the insulating filling layer and the inner protective layer, and the lower surface of the insulating filling layer is spaced apart from the upper surface of the substrate in a manner that the outer protective layer is interposed between the lower surface of the insulating filling layer and the upper surface of the substrate.

16. The semiconductor device according to claim 11, wherein The outer protective layer extends along the inner protective layer onto the upper surface of the substrate, and The side walls of the insulating filling layer are spaced apart from the inner protective layer in a manner that the outer protective layer is interposed between the side walls of the insulating filling layer and the inner protective layer, and the lower surface of the insulating filling layer is spaced apart from the upper surface of the substrate in a manner that the outer protective layer and the inner protective layer are interposed between the lower surface of the insulating filling layer and the upper surface of the substrate.

17. A semiconductor device, comprising: substrate; a plurality of gate structures located on the substrate; Spacer structures, each of which is located on opposite side walls of the plurality of gate structures; Wherein, the spacing structure comprises: a plurality of insulating spacers, the plurality of insulating spacers being respectively located on opposite sidewalls of the plurality of gate structures; an inner protection layer, the inner protection layer being located on upper surfaces of the plurality of gate structures and the plurality of insulating spacers; and an outer protective layer, the outer protective layer being located on at least a portion of the inner protective layer, and an insulating filling layer, the insulating filling layer being located between adjacent gate structures among the plurality of gate structures, wherein the insulating filling layer is located on the spacer structure; an upper covering layer, the upper covering layer being located on the insulating filling layer; and a contact plug extending in the insulating filling layer and the upper cover layer along a first direction perpendicular to the upper surface of the substrate, Wherein, the insulating filling layer comprises the same material as the upper covering layer, and The insulating filling layer includes a nitride layer and / or a silicon nitride layer.

18. The semiconductor device according to claim 17, wherein: The outer protection layer includes an oxide layer, a silicon oxide layer, SiOCN, SiON and / or SiOC.

19. The semiconductor device according to claim 17, wherein: The outer protective layer extends along the inner protective layer onto the upper surface of the substrate, and The side walls of the insulating filling layer are spaced apart from the inner protective layer in a manner that the outer protective layer is interposed between the side walls of the insulating filling layer and the inner protective layer, and the lower surface of the insulating filling layer is spaced apart from the upper surface of the substrate in a manner that the outer protective layer is interposed between the lower surface of the insulating filling layer and the upper surface of the substrate.

20. The semiconductor device according to claim 17, wherein The insulating filling layer contacts an upper surface of the substrate.

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