Semiconductor device and forming method thereof

Abstract

A semiconductor device includes: an interconnect substrate having a front side and a rear side, where the interconnect substrate includes an interconnect structure extending between the front side and the rear side thereof, and a bridge module embedded within the interconnect substrate and exposed from the rear side of the interconnect substrate; a front-side semiconductor component mounted on the front side of the interconnection substrate; two rear-side semiconductor components mounted on the rear side of the interconnect substrate, where the two rear-side semiconductor components are electrically coupled to each other through the bridge module and electrically coupled to the front-side semiconductor component through the interconnect structure; a rear-side sealing layer formed on the rear side of the interconnect substrate and sealing the two rear-side semiconductor components, where the rear-side sealing layer includes a plurality of sets of conductive pillars passing through the rear-side sealing layer; and a conductive bump mounted on a rear side of the rear side sealing layer and electrically coupled to the interconnect substrate through the plurality of sets of conductive pillars.

Description

Technical Field

[0001] The present application relates generally to semiconductor packaging technology, and more particularly, to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has been facing complex integration challenges as consumers want their electronic products to be smaller, faster, and higher performing, and to put more and more functions into a single device. One of the solutions is package-on-package (PoP). PoP is a packaging method that combines two or more integrated circuit (IC) packages together. In a typical PoP device, two or more packages are connected vertically. PoP devices can use space more efficiently and reduce the length of signal paths between packages. However, signal communication in conventional PoP devices is not satisfactory.

[0003] Therefore, there is a need to further improve existing semiconductor devices. Summary of the invention

[0004] An object of the present application is to provide a semiconductor device in which signal communication is improved and signal delay is reduced.

[0005] According to one aspect of the present application, a semiconductor device is provided. The semiconductor device includes: an interconnect substrate having a front side and a rear side, wherein the interconnect substrate includes an interconnect structure extending between the front side and the rear side thereof, and a bridge module embedded in the interconnect substrate and exposed from the rear side of the interconnect substrate; a front semiconductor component mounted on the front side of the interconnect substrate; two rear semiconductor components mounted on the rear side of the interconnect substrate, wherein the two rear semiconductor components are electrically coupled to each other through the bridge module and electrically coupled to the front semiconductor component through the interconnect structure; a rear sealing layer formed on the rear side of the interconnect substrate and sealing the two rear semiconductor components, wherein the rear sealing layer includes a plurality of groups of conductive pillars passing through the rear sealing layer; and a conductive bump mounted on the rear side of the rear sealing layer and electrically coupled to the interconnect substrate through the plurality of groups of conductive pillars.

[0006] According to another aspect of the present application, a method for forming a semiconductor device is provided. The method includes: providing an interconnect substrate, wherein the interconnect substrate includes an interconnect structure extending between its front side and rear side and a bridge module embedded therein and exposed from its rear side; mounting two rear-side semiconductor components on the rear side of the interconnect substrate, wherein the two rear-side semiconductor components each cover a portion of the bridge module, so that the two rear-side semiconductor components are electrically coupled to each other through the bridge module; forming a rear-side sealing layer on the rear side of the interconnect substrate to seal the two rear-side semiconductor components; forming multiple groups of conductive pillars on the rear side of the interconnect substrate, wherein the multiple groups of conductive pillars pass through the interconnect substrate; and mounting a front-side semiconductor component on the front side of the interconnect substrate, wherein the front-side semiconductor component is electrically coupled to the two rear-side semiconductor components through the interconnect structure.

[0007] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present invention. In addition, the accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate embodiments of the present invention and are used together with the description to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings referred to herein form part of the specification. Unless the detailed description explicitly indicates otherwise, the features shown in the drawings only illustrate some embodiments of the present application, not all embodiments of the present application, and readers of this specification should not make contrary inferences.

[0009] Figure 1A A semiconductor device according to an embodiment of the present application is shown.

[0010] Figure 1B Shows Figure 1A A portion of the semiconductor device.

[0011] Figures 2A to 2J A method for forming a semiconductor device according to an embodiment of the present application is shown.

[0012] Figure 3 A semiconductor device according to an embodiment of the present application is shown.

[0013] Figure 4 A semiconductor device according to an embodiment of the present application is shown.

[0014] Figure 5 A semiconductor device according to an embodiment of the present application is shown.

[0015] Figures 6A to 6E Part of the steps of a method for forming a semiconductor device according to an embodiment of the present application is shown.

[0016] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0017] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable those skilled in the art to practice the present application. Those skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret this specification in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0018] In this application, the use of the singular includes the plural unless otherwise specifically stated. In this application, the use of "or" means "and / or" unless otherwise specified. In addition, the use of the term "including" is not limiting. In addition, unless otherwise specifically stated, terms such as "element" or "component" encompass elements and components that include one unit and elements and components that include more than one subunit. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0019] As used herein, for ease of description, spatially relative terms such as "below", "below", "above", "up", "upper", "lower", "left", "right", "vertical", "horizontal", "side", etc. may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features), as shown in the figure. In addition to the orientation depicted in the drawings, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it may be directly connected to or coupled to the other element, or there may be intermediate elements.

[0020] Figure 1A A semiconductor device 100 according to an embodiment of the present application is shown. In some embodiments, the semiconductor device 100 can utilize a silicon-based interconnect structure to transmit signals between some of its semiconductor components, which can achieve a higher signal communication speed than conventional semiconductor devices.

[0021] like Figure 1AAs shown, the semiconductor device 100 includes an interconnect substrate 102, which can provide support and connection for electronic components mounted thereon. For example, the interconnect substrate 102 may include a printed circuit board (PCB), a carrier substrate, or a ceramic substrate. However, the interconnect substrate 102 is not limited to these examples. In some other examples, the interconnect substrate 102 may include a laminated interposer, a strip interposer, a lead frame, or other suitable substrates. The interconnect substrate 102 may include any structure on which or in which an integrated circuit system may be manufactured. For example, the interconnect substrate 102 may include one or more insulating layers or passivation layers, one or more conductive vias formed through the insulating layers, and one or more conductive layers formed on or between the insulating layers, as will be described in more detail below.

[0022] The interconnect substrate 102 has a front side and a back side, and generally divides the entire semiconductor device 100 into two parts, namely, a front portion on the front side and a back portion on the back side. In one embodiment, the interconnect substrate 102 includes a cavity formed on the back side thereof, and the bridge module 104 is embedded in the cavity. Figure 1A As shown, the bridge module 104 has a surface exposed from the rear side of the interconnect substrate 102 and is substantially flush with the rear surface of the interconnect substrate 102. In some embodiments, the bridge module 104 may be substantially formed of a silicon substrate, with various through silicon vias (TSVs) that pass through the silicon substrate to vertically transmit signals, that is, the bridge module 104 may be a silicon bridge. The bridge module 104 may also include one or more horizontal conductive material layers, such as wires, traces, or patterns, which may be electrically connected to the TSVs to allow horizontal connection across at least a portion of the bridge module 104. Since the conductive structure in the bridge module 104 may have a higher density and a shorter path than the conductive structure in a non-silicon-based substrate such as a printed circuit board, the bridge module 104 may provide a faster signal communication speed. It is understood that the bridge module 104 may also be formed of a printed circuit board, that is, substantially formed of a polymer compound material, which also has a plurality of horizontal and vertical conductive materials distributed therein. However, due to the high density and faster signal communication speed of the silicon substrate, a silicon substrate is preferably used for the bridge module.

[0023] In addition to the bridge module 104, the interconnect substrate 102 also includes an interconnect structure 106, such as a conductive via extending between the front side and the back side of the interconnect substrate. The interconnect structure 106 can provide a conductive path between the two sides of the interconnect substrate 102 to electrically couple the semiconductor components of the front of the semiconductor device 100 to other semiconductor components of the back. For example, the front semiconductor component 108 can be mounted on the front side of the interconnect substrate 102. The front semiconductor component 108 can be mounted on the interconnect substrate 102 directly or through a conductive bump (not shown). The front semiconductor component 108 can be a larger semiconductor chip or semiconductor package, and thus occupy a large portion of the interconnect substrate 102 on its front side. In addition, two back semiconductor components 110a and 110b can be mounted on the back side of the interconnect substrate 102. The size of the back semiconductor components 110a and 110b can be smaller than the front semiconductor component 108, so the back semiconductor component can be vertically aligned with a portion of the front semiconductor component 108. The backside semiconductor components 110a and 110b can be electrically coupled to the frontside semiconductor component 108 through the interconnection structure 106 in the interconnection substrate 102. Similar to the frontside semiconductor component 108, the backside semiconductor components 110a and 110b can be semiconductor chips or packages. In addition, each of the two backside semiconductor components 110a and 110b can overlap with a portion of the bridge module 104, so that the backside semiconductor components can contact the bridge module 104 for electrical connection (e.g., indirectly through solder bumps, or directly). In this way, the backside semiconductor components 110a and 110b can be electrically coupled to each other through the bridge module 104. That is, all semiconductor components on both sides of the interconnection substrate 102 can be electrically coupled together through the interconnection substrate 102, thereby forming a compact structure; and occupy a smaller area when the semiconductor device 100 is mounted on a carrier such as a printed circuit board. Specifically, the bridge module 104 may be connected to some interconnect structures 106 above it to form a vertical conductive path between the front semiconductor component 108 and the back semiconductor components 110a and 110b. In some embodiments, the interconnect substrate 102 may have a window filled with the bridge module 104, that is, the thickness of the bridge module 104 may be equal to the thickness of the interconnect substrate 102. However, in other embodiments, for example Figure 1A In the illustrated embodiment, the thickness of the bridge module 104 may be less than the thickness of the interconnect substrate 102. Then, the front-side semiconductor component 108 and the back-side semiconductor components 110a and 110b may be electrically coupled together through the bridge module 104. It can be seen that the bridge module 104 may be used as a "hub" for multiple semiconductor components of the semiconductor device 100, thereby achieving faster signal communication in the semiconductor device 100.

[0024] It is understood that more front-side semiconductor components and back-side semiconductor components can be mounted on either side of the interconnect substrate 102, and these semiconductor components can be electrically coupled together through the interconnect structure 106 or the bridge module 104. For example, in the case where the bridge module 104 is shaped as a square, four semiconductor components can be mounted on the back side of the interconnect substrate 102 and overlap with corresponding corners of the bridge module 104. In this way, all four semiconductor components can be coupled together through TSVs and other conductive structures within the bridge module 104. In addition, two or more bridge modules can be embedded in the interconnect substrate 102 on the front side or the back side or on both sides to connect at least some of the semiconductor components mounted on the same side as the corresponding bridge modules.

[0025] The backside sealing layer 112 is formed on the backside of the interconnect substrate 102 to seal the two backside semiconductor components 110a and 110b. The thickness of the backside sealing layer 112 can be greater than the thickness of the backside semiconductor components 110a and 110b to avoid the backside semiconductor components from being exposed from the sealing layer 112. The backside sealing layer 112 can be a polymer composite material, such as epoxy resin, epoxy acrylate, or any suitable polymer with or without filler. The backside sealing layer 112 can be non-conductive, provide structural support, and protect the semiconductor components 110a and 110b from external elements and contaminants in terms of environment.

[0026] The backside sealing layer 112 includes a plurality of groups of conductive pillars 114 that pass through the backside sealing layer 112 and are generally parallel to the backside semiconductor components 110a and 110b to electrically couple the interconnect substrate 102 with components or elements located further below the backside sealing layer 112. In some embodiments, the backside substrate 116 is mounted on the backside of the backside sealing layer 112 and is thus electrically coupled to the interconnect substrate 102 through the plurality of groups of conductive pillars 114. In addition, the conductive bumps 118 may be optionally mounted on the backside of the backside sealing layer 112 through the backside substrate 116 to electrically couple to the interconnect substrate 102 through the plurality of groups of conductive pillars 114 in the backside sealing layer 112 and optionally through the backside substrate 116. In some embodiments, the backside substrate 116 may include a redistribution layer 120 that may redistribute the layout and connection of the conductive bumps 118 and the conductive pillars 114. In some embodiments, at least one set of conductive pillars may be electrically connected to the interconnect structure 106 of the interconnect substrate 102 , and in some other embodiments, at least one set of conductive pillars 106 may be connected to the bridge module 104 to provide a fast conductive path between the semiconductor components 110 a and 110 b and the conductive bumps 118 .

[0027] The heat sink cover 122 may be mounted on the front side of the interconnect substrate 102 to cover the front side semiconductor component 108. The heat sink cover 122 may have a cavity to accommodate the front side semiconductor component 108, and a sidewall attached to the front surface of the interconnect substrate 102. In some embodiments, the heat sink cover 122 may be thermally coupled to the front side semiconductor component 108 through a thermal interface material layer 124 to form a better thermal conductive path between the heat sink cover 122 and the front side semiconductor component 108. It is understood that other structures may be formed on the front side of the interconnect substrate 102. For example, a front side sealing layer and an optional electromagnetic interference (EMI) shielding layer (not shown) may be formed instead to seal and protect the front side semiconductor component 108.

[0028] Figure 1B Shows Figure 1A A part 150 of the semiconductor component 100 is shown, in particular the bridge module 104 and its connections to other components of the semiconductor component 100 .

[0029] like Figure 1B As shown, two backside semiconductor components 110a and 110b are sealed in the backside sealing layer 112. In this embodiment, the backside semiconductor components 110a and 110b can be mounted on the interconnect substrate 102 by solder bumps 154, and then bottom-filled and sealed by the backside sealing layer 112. The solder bumps 154 can be aligned with the contact pads exposed to the interconnect substrate 102. In addition, a plurality of conductive pillars 114 can also be sealed by the backside sealing layer 112, and these conductive pillars 114 can pass through the entire sealing layer 112 in the thickness direction to allow electrical connection between the two surfaces of the sealing layer 112. For example, the conductive pillars 114 can take the form of conductive vias.

[0030] In this embodiment, the bridging module 104 may include a silicon substrate in which conductive wires are distributed. For example, a plurality of first conductive wires 152a may be formed in the silicon substrate to connect a solder bump 154 ​​attached to the back-side semiconductor component 110a with a solder bump 154 ​​attached to the back-side semiconductor component 110b. In this way, the two back-side semiconductor components 110a and 110b can be electrically coupled to each other to directly transmit signals therebetween. In addition, a plurality of second conductive wires 152b may be formed in the silicon substrate to connect a solder bump 154 ​​attached to one back-side semiconductor component to a conductive pillar 114. In this way, the back-side semiconductor components 110a and / or 110b can be electrically coupled to the back-side substrate 116 via the bridging module 104 and the conductive pillar 114. In addition, some conductive wires 152c (in Figure 1BThe conductive line 152c (only a portion of which is shown in the figure) can be electrically coupled between the conductive pillar 114 and the interconnect structure 106 in the interconnect substrate 102, so that other components mounted on the interconnect substrate 102 (for example, a front-side semiconductor component (not shown)) can be electrically coupled to the back-side substrate 116 through the interconnect structure 106, the conductive line 152c and the conductive pillar 114.

[0031] Depend on Figure 1B It can be seen that the conductive lines 152a, 152b, 152c in the bridge module provide flexibility for electrically connecting the various components of the semiconductor device. In other words, the bridge module can be used as an interposer in the semiconductor device. In some embodiments, the bridge module is formed by a silicon substrate. Due to the shorter conductive path in the silicon substrate, faster signal transmission can be achieved in the bridge module. It can be understood that Figure 1B The embodiments shown are merely exemplary and may be used for Figure 1B The bridge modules shown (particularly the conductive lines therein) are subject to various modifications.

[0032] Figures 2A to 2J The various steps of a method for forming a semiconductor device according to an embodiment of the present application are shown. For example, the method can be used to form Figure 1A A semiconductor device 100 is shown.

[0033] like Figure 2A As shown, an interconnect substrate 202 is provided. The interconnect substrate 202 includes a plurality of interconnect structures 206 extending between the front side and the back side thereof. In some embodiments, a portion of the interconnect structure 206 may be further connected to another portion of the interconnect structure 206 through a horizontal conductive structure in the interconnect substrate 202. A cavity 203 may be formed on the back side of the interconnect substrate 202 to accommodate a bridge module (not shown). The size and shape of the cavity 203 may depend on the location of the back side semiconductor component to be connected by the bridge module. Figure 2B As shown, the bridge module 204 is filled in the cavity, thereby being embedded in the interconnect substrate 202. For example, an adhesive material may be filled in the cavity to help the bridge module 204 to be firmly filled in the cavity. If the bridge module 204 is formed of a silicon substrate, it may be preformed using an integrated circuit manufacturing process.

[0034] Next, if Figure 2CAs shown, two backside semiconductor components 210a and 210b are mounted on the interconnect substrate 202. Each of the two backside semiconductor components 210a and 210b can overlap a portion of the bridge module 204 and thus be electrically connected to the bridge module 204. Due to the horizontal connection of the bridge module 204, the two backside semiconductor components 210a and 210b can also be electrically coupled to each other through the bridge module 204. In some embodiments, the backside semiconductor components 210a and 210b can also be electrically connected to the interconnect structure 206 of the interconnect substrate 202. For example, the backside semiconductor components 210a and 210b can have contact pads that can be bonded to contact pads on the rear surface of the interconnect substrate 202. In some optional embodiments, conductive bumps or similar structures can be formed between the backside semiconductor components 210 and 210b and the interconnect substrate 202.

[0035] Next, if Figure 2D As shown, a backside sealing layer 212 can be formed on the interconnect substrate 202 to cover the two backside semiconductor components 210a and 210b. For example, the backside sealing layer 212 can be formed using injection molding, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating or other suitable processes.

[0036] Next, if Figure 2E As shown, multiple groups of trenches 213 can be formed through the backside sealing layer 212 at locations where the backside semiconductor components 210a and 210b are not mounted. In some embodiments, the trenches 213 can be formed using laser ablation or etching. Then, a conductive material such as copper can be filled in the trenches to form multiple groups of conductive pillars 214, such as Figure 2F The conductive pillar 214 may pass through the interconnect substrate 202. If an excess portion of the conductive material is deposited in the trench and covers the rear surface of the sealing layer 212, an etching process may be performed to remove the excess conductive material.

[0037] Next, if Figure 2GAs shown, the interconnect substrate 202 is flipped over with its rear side facing downward. Then, the front side semiconductor component 208 can be mounted on the front side of the interconnect substrate 202. The front side semiconductor component 208 can be directly or indirectly mounted on the front surface of the interconnect substrate 202 via a conductive bump or similar structure (not shown). The front side semiconductor component 208 can be electrically connected to the interconnect substrate 202. In some embodiments, the front side semiconductor component 208 can be electrically coupled to the two rear side semiconductor components 210a and 210b through the interconnect structure 206. In some optional embodiments, the front side semiconductor component 208 can be further electrically coupled to the bridge module 204 through the interconnect structure 206, so that the semiconductor components on both sides of the interconnect substrate 202 can be mainly electrically coupled together through the bridge module 204.

[0038] Next, if Figure 2H As shown, a thermal interface material layer 224 can be formed on the front side of the front semiconductor component 208. For example, the thermal interface material can be dispensed onto the front surface of the front semiconductor component 208. The thermal interface material is used to enhance the thermal coupling between the front semiconductor component 208 and the heat sink cover to be attached. In some embodiments, the thermal interface material can be a thermally conductive, dispensable material, preferably a thermal grease, a thermal adhesive, a thermal gap filler, a liquid metal, and a solder paste. In an embodiment, the thermal interface material is an epoxy compound, which can be used to easily bond to metals, ceramics, most plastics, and a variety of other materials. In another embodiment, the thermal interface material includes a solder paste having a thermal conductivity superior to that of a typical thermal interface material. Preferably, the solder paste is an Ag-In solder alloy. Specifically, the thermal interface material can be a solder preform, that is, a solid, flat, manufactured shape of solder, and a flux can be applied to coat the solder preform. Then, the metal heat sink cover 222 can be attached to the interconnect substrate 202 to cover the front semiconductor component 208. The metal heat sink cover 222 is usually made of a high thermal conductivity metal material to effectively transfer heat from the front semiconductor components to the external space. In this embodiment, the metal heat sink cover 222 can be integrated with the thermal interface material layer 224 to better dissipate heat from the semiconductor components inside the semiconductor device. The metal heat sink cover 222 is preferably made of copper, aluminum, and copper-tungsten alloy. It is understood that other suitable materials can be used to form the metal heat sink cover 222.

[0039] Next, if Fig.2I As shown, a backside substrate 216 may be attached to the backside sealing layer 212 using, for example, a bonding process. The backside substrate 216 has a redistribution layer 220 that may be electrically connected to the respective groups of conductive pillars 214 passing through the backside sealing layer 212.

[0040] Next, if Figure 2JAs shown, the interconnect substrate 202 and the components mounted thereon are turned over, and the front side of the interconnect substrate faces downward. The conductive bumps 218 can be mounted on the rear side of the rear side sealing layer 212 using, for example, a surface mounting process. Thus, the conductive bumps 218 are electrically coupled to the interconnect substrate 202 through corresponding conductive pillars 216. In this way, a semiconductor device having various semiconductor components can be formed, and these semiconductor components are interconnected using a bridge module and / or an interconnect structure.

[0041] In some embodiments, the backside substrate 216 may be omitted. In this case, the conductive bumps 218 may be directly mounted on the back side of the backside sealing layer 212. However, the conductive bumps 218 need to be vertically aligned with the conductive pillars 214 in the backside sealing layer 212.

[0042] In some embodiments, the components on the back side of the interconnect substrate 202 may be arranged in a manner different from that of Figures 2B to 2F Formed in the manner shown. Figures 6A to 6E A part of the multiple steps of a method for forming a semiconductor device according to an embodiment of the present application is shown.

[0043] like Fig. 6A As shown, an interconnect substrate 602 is provided, in which a bridge module 604 is embedded. Figure 6B As shown, multiple sets of conductive pillars 614 can be attached to the interconnect substrate 602 on the same side as the bridge module 604. In some embodiments, a portion of the multiple sets of conductive pillars 614 can be connected to the bridge module 604 by, for example, solder bumps or by bonding to establish a conductive connection with the bridge module 604.

[0044] Then, if Figure 6C As shown, two backside semiconductor components 610a and 610b can be attached to the interconnect substrate 602, located on the same side as the conductive pillar 614. The backside semiconductor components 610a and 610b overlap with a corresponding portion of the bridge module 604, so that they can be electrically coupled to each other through the bridge module 604, thanks to the horizontal connection characteristics of the bridge module 604. In some embodiments, the backside semiconductor components 610a and 610b can also be electrically connected to other interconnect structures in the interconnect substrate 602 other than the bridge module 604, such as through conductive bumps or through bonding. It is understood that the backside semiconductor components 610a and 610b can have a thickness that is less than the height of the conductive pillar 614.

[0045] However, if Fig.6DAs shown, a backside sealing layer 612 can be formed on the interconnect substrate 602 to cover the two backside semiconductor components 610a and 610b and the plurality of conductive pillars 614. For example, the backside sealing layer 612 can be formed using injection molding, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable processes. In some embodiments, after the molding process, the backside sealing layer 612 can have a thickness equal to the height of the conductive pillars 614, so that no additional molding planarization or etching process is required. In some alternative embodiments, for example Fig.6D In the illustrated embodiment, the backside sealing layer 612 may have a thickness greater than the height of the conductive pillars 614, thereby requiring a mold planarization or etching process to remove excess molding material, as shown in FIG. Fig. 6E shown.

[0046] Figure 3 A semiconductor device 300 according to an embodiment of the present application is shown.

[0047] like Figure 3 As shown, different from Figure 1A As shown in the semiconductor device 100, the semiconductor device 300 does not include a heat sink cap. Alternatively, a front side sealing layer 328 is formed on the front side of the interconnect substrate 302 to seal the front side semiconductor component 308 mounted on the interconnect substrate 302. In addition, a bonding wire 326 can be attached between the front side of the front side semiconductor component 308 and the front side of the interconnect substrate 302 to electrically couple the front side semiconductor component and the interconnect substrate 302 together. In this way, the front side semiconductor component 308 can be electrically coupled to the back side semiconductor components 310a and 310b through the bonding wire 326 and the interconnect structure 306 inside the interconnect substrate 302. In some embodiments, the bonding wire 326 can be first formed on the interconnect substrate 302 and then sealed by the front side sealing layer 328 together with the front side semiconductor component 308.

[0048] In addition, Figure 1A Unlike the semiconductor device 100 including the backside substrate 116 shown, the semiconductor device 300 does not have a backside substrate, so that the conductive bumps 318 are respectively connected to the conductive pillars 314 inside the backside sealing layer 312, and the interconnect substrate 302 can be electrically coupled to the conductive bumps 318 under the entire semiconductor device 300.

[0049] Figure 4 A semiconductor device 400 according to an embodiment of the present application is shown.

[0050] like Figure 4 As shown, Figure 3Similar to the semiconductor device 300 shown, the semiconductor device 400 includes a front side sealing layer 428 that seals the front side semiconductor component 408 on the front side of the interconnect substrate 402. Specifically, the front side semiconductor component 408 is mounted on the interconnect substrate 402 through a set of conductive bumps 430, which facilitate the mounting of the front side semiconductor component 408. The conductive bumps 430 can be connected to contact pads exposed from the interconnect substrate 402 to electrically couple with the interconnect structure 406 in the interconnect substrate 402.

[0051] Figure 5 FIG. 5 shows a semiconductor device 500 according to an embodiment of the present application. Figure 1A , 3 Compared with the two-layer semiconductor components shown in FIG4 , the semiconductor device 500 includes more layers of semiconductor components. Therefore, more substrates can be stacked to provide connections between the semiconductor components.

[0052] like Figure 5 As shown, the semiconductor device 500 includes an interconnect substrate 502 mounted with a front side semiconductor component 508. The front side semiconductor component 508 is sealed by a front side sealing layer 528. A top substrate 532 is mounted on the front side of the front side sealing layer 528. A plurality of groups of top conductive pillars 536 can be mounted on the front side of the interconnect substrate 502, and the plurality of groups of top conductive pillars 536 pass through the front side sealing layer 528. In this way, the top conductive pillars 536 can electrically couple the top substrate 532 with the interconnect substrate 502, or specifically, electrically couple the top substrate 532 and the corresponding interconnect structures 506 and 538 within the interconnect substrate 502.

[0053] Similar to Figure 1A As shown in front side semiconductor component 508, top semiconductor component 540 can be mounted on the front side of top substrate 532. In addition, heat sink cover 542 can be mounted on the front side of top substrate 532 to cover top semiconductor component 540. Heat sink cover 542 can be thermally coupled to top semiconductor component 532 through thermal interface material layer 544.

[0054] In some embodiments, another semiconductor component 534 can be mounted on the back side of the top substrate 532, the semiconductor component 534 being opposite to the front semiconductor component 508. Both the semiconductor component 534 and the front semiconductor component 508 are sealed by the front sealing layer 528, and they do not contact each other. Due to the presence of the connected interconnect substrate 502 and the top substrate 532, all the various semiconductor components 540, 534, 508, 510a and 510b can be electrically coupled together to form a compact structure. It will be appreciated that if more substrates and conductive pillars are required, more semiconductor component layers can be integrated in the semiconductor device 500.

[0055] Although the exemplary semiconductor device of the present application has been described in conjunction with the corresponding drawings, those skilled in the art will appreciate that modifications and adaptations may be made to the method without departing from the scope of the present invention.

[0056] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes may be made to these embodiments, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. In addition, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the examples herein be considered exemplary only, with the true scope and spirit of the invention being indicated by the appended exemplary claim list.

Claims

1. A semiconductor device, characterized in that: include: an interconnect substrate having a front side and a back side, wherein the interconnect substrate includes an interconnect structure extending between the front side and the back side thereof, and a bridge module embedded in the interconnect substrate and exposed from the back side of the interconnect substrate; a front-side semiconductor component mounted on the front side of the interconnect substrate; two backside semiconductor components mounted on the backside of the interconnect substrate, wherein the two backside semiconductor components are electrically coupled to each other through the bridge module and to the frontside semiconductor component through the interconnect structure; a backside sealing layer formed on the backside of the interconnect substrate and sealing the two backside semiconductor components, wherein the backside sealing layer includes a plurality of groups of conductive pillars passing through the backside sealing layer; as well as A conductive bump is mounted on the rear side of the rear side sealing layer and is electrically coupled to the interconnect substrate through the plurality of groups of conductive pillars.

2. The semiconductor device according to claim 1, wherein: At least one set of conductive posts is connected to the bridge module.

3. The semiconductor device according to claim 1, wherein: The bridge module is further electrically coupled to the front-side semiconductor component.

4. The semiconductor device according to claim 1, wherein: The interconnect substrate includes a cavity at a rear side thereof, and the bridge module is embedded in the cavity.

5. The semiconductor device according to claim 1, wherein: Further included is a backside substrate mounted between the backside sealing layer and the conductive bumps.

6. The semiconductor device according to claim 1, wherein: Further included is a heat sink cover mounted on the front side of the interconnect substrate and covering the front side semiconductor component, wherein the heat sink cover is thermally coupled to the front side semiconductor component through a thermal interface material layer.

7. The semiconductor device according to claim 1, wherein: The front-side semiconductor components are mounted on the interconnect substrate directly or through conductive bumps.

8. The semiconductor device according to claim 1, wherein: Further included is bonding wires attached between a front side of the front side semiconductor component and the front side of the interconnect substrate.

9. The semiconductor device according to claim 1, wherein: Further included is a front side sealing layer on the front side of the interconnect substrate and sealing the front side semiconductor component.

10. The semiconductor device according to claim 9, characterized in that Further including: a plurality of groups of top conductive posts mounted on the front side of the interconnect substrate and extending through the front side sealing layer; a top substrate mounted on the front side of the front side sealing layer and electrically coupled to the plurality of groups of top conductive posts; as well as A top semiconductor component is mounted on the front side of the top substrate.

11. The semiconductor device according to claim 10, characterized in that Further included is a semiconductor component mounted on the rear side of the top substrate and opposite to the front side semiconductor component, and both the semiconductor component and the front side semiconductor component are sealed by the front side sealing layer.

12. The semiconductor device according to claim 10, characterized in that Further included is a heat sink cap mounted on the front side of the top substrate and covering the top semiconductor component, wherein the heat sink cap is thermally coupled to the top semiconductor component through a thermal interface material layer.

13. The semiconductor device according to claim 1, wherein: The bridge module is a silicon bridge.

14. A method for forming a semiconductor device, characterized in that: The method comprises: providing an interconnect substrate, wherein the interconnect substrate includes an interconnect structure extending between a front side and a rear side thereof and a bridge module embedded therein and exposed from the rear side thereof; mounting two backside semiconductor components on the backside of the interconnect substrate, wherein the two backside semiconductor components each cover a portion of the bridge module such that the two backside semiconductor components are electrically coupled to each other through the bridge module; forming a backside sealing layer on the backside of the interconnect substrate to seal the two backside semiconductor components; forming a plurality of groups of conductive pillars on the back side of the interconnect substrate, wherein the plurality of groups of conductive pillars pass through the interconnect substrate; and A front-side semiconductor component is mounted on the front side of the interconnect substrate, wherein the front-side semiconductor component is electrically coupled to the two back-side semiconductor components through the interconnect structure.

15. The method according to claim 14, characterized in that Providing an interconnect substrate further comprises: forming a cavity at the back side of the interconnect substrate; and The bridge module is filled in the cavity.

16. The method according to claim 14, characterized in that Further including: forming a thermal interface material layer on the front side of the front semiconductor component; attaching a heat sink cap on the interconnect substrate to cover the front side semiconductor component, wherein the front side semiconductor component is thermally coupled to the heat sink cap through the thermal interface material layer; attaching a rear substrate to the rear sealing layer; as well as Conductive bumps are formed on the back side of the back side sealing layer, wherein the conductive bumps are electrically coupled to the interconnect substrate through the plurality of groups of conductive pillars.

17. The method according to claim 14, characterized in that The bridge module is a silicon bridge.

Images