Semiconductor chip structure

Abstract

A semiconductor chip structure includes a plurality of semiconductor chips. Bonding electrodes included in each of the semiconductor chips are filled with nano-twin copper, and fine copper particles are disposed in at least a portion of the bonding electrodes.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor chip structure, and more particularly to a semiconductor chip structure including a pad structure. Background Art

[0002] With the high integration of semiconductor chips, research has been conducted on a semiconductor chip structure manufactured by bonding a first semiconductor chip to a second semiconductor chip. The semiconductor chip structure manufactured by bonding a first semiconductor chip to a second semiconductor chip should have high bonding reliability. When the bonding reliability during the manufacturing process is poor, the semiconductor chip structure formed by bonding the first semiconductor chip to the second semiconductor chip may not work properly. Summary of the invention

[0003] Embodiments of the inventive concept provide a semiconductor chip structure that can increase bonding reliability of a first semiconductor chip and a second semiconductor chip.

[0004] The objects of the inventive concept are not limited to the above contents, but other objects not described herein will be clearly understood by those of ordinary skill in the art through the following description.

[0005] According to an embodiment of the present invention, a semiconductor chip structure has a first semiconductor chip including a first chip region and a first scribe street region. The first semiconductor chip is bonded to a second semiconductor chip, and the second semiconductor chip includes a second chip region and a second scribe street region corresponding to the first chip region and the first scribe street region, respectively. The first semiconductor chip includes a first final wiring layer including a first final wiring pattern and a first passivation layer that insulates the first final wiring pattern. A first bonding wiring layer is disposed on the first final wiring layer. The first bonding wiring layer includes a first bonding insulating layer and a first bonding electrode disposed in the first bonding insulating layer. The second semiconductor chip includes a second final wiring layer, the second final wiring layer includes at least one second final wiring pattern, a polishing stop pattern disposed on the at least one second final wiring pattern, and a second passivation layer that insulates the at least one second final wiring pattern and the polishing stop pattern. A second bonding wiring layer is disposed on the second final wiring layer. The second bonding wiring layer includes a second bonding insulating layer and a second bonding electrode disposed in the second bonding insulating layer and the polishing stop pattern. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are respectively hybrid-bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer. At least a portion of a bonding interface between the first bonding insulating layer and the first bonding electrode of the first bonding wiring layer of the hybrid bonding and the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer includes fine-grained copper, and in the remaining portion of the bonding interface, an interior of each of the first bonding electrode and the second bonding electrode includes nano-twinned copper.

[0006] According to an embodiment of the present invention, a semiconductor chip structure has a first semiconductor chip including a first chip region and a first scribe street region. The first semiconductor chip is bonded to a second semiconductor chip including a second chip region and a second scribe street region. The first semiconductor chip includes a first circuit layer arranged in the first chip region and the first scribe street region. A first final wiring layer is arranged on the first circuit layer. The first final wiring layer includes a first final wiring pattern and a first passivation layer that insulates the first final wiring pattern. A first bonding wiring layer is arranged on the first final wiring layer. The first bonding wiring layer includes a first interlayer insulating layer, a first bonding insulating layer arranged on the first interlayer insulating layer, and a first bonding electrode arranged in the first interlayer insulating layer and the first bonding insulating layer. The second semiconductor chip includes a second circuit layer arranged in the second chip region and the second scribe street region. A second final wiring layer is arranged on the second circuit layer. The second final wiring layer includes at least one second final wiring pattern, a polishing stop pattern arranged on the at least one second final wiring pattern, and a second passivation layer that insulates the at least one second final wiring pattern and the polishing stop pattern. A second bonding wiring layer is arranged on the second final wiring layer. The second bonding wiring layer includes a second interlayer insulating layer, a second bonding insulating layer arranged on the second interlayer insulating layer, and a second bonding electrode arranged in the second bonding insulating layer, the second interlayer insulating layer and the polishing stop pattern. The first bonding electrode includes a first portion with a fine-grained copper plated on the uppermost surface and nano-twinned copper surrounding the side surface of the first portion and filling the inside of the first bonding electrode. The second bonding electrode includes a second portion with a fine-grained copper plated on the uppermost surface and nano-twinned copper surrounding the side surface of the second portion and filling the inside of the second bonding electrode. The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are mixedly bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer, respectively.

[0007] According to an embodiment of the present invention, a semiconductor chip structure includes a plurality of semiconductor chips, each of which includes a chip area and a scribe line area. Each of the plurality of semiconductor chips includes a circuit layer arranged in the chip area and the scribe line area. A final wiring layer is arranged on the circuit layer. The final wiring layer includes a final wiring pattern and a passivation layer that insulates the final wiring pattern. A bonding wiring layer is arranged on the final wiring layer. The bonding wiring layer includes an interlayer insulating layer, a bonding insulating layer arranged on the interlayer insulating layer, and a bonding electrode arranged in the interlayer insulating layer and the bonding insulating layer. The bonding electrode is filled with nano-twinned copper and fine-grained copper arranged in at least a portion of the uppermost surface of the bonding electrode. The grain size of the fine-grained copper is less than or equal to about 300nm, and the thickness ranges from about 1μm to about 1.5μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a cross-sectional view for describing the structure of a semiconductor chip according to an embodiment;

[0010] Figure 2 Is used to describe Figure 1 A partial cross-sectional view of a semiconductor chip structure;

[0011] FIG. 3A to FIG. 3C is a partial cross-sectional view for describing the structure of a semiconductor chip according to an embodiment;

[0012] Figures 4 to 13 Is used to describe Figure 1 and Figure 2 A cross-sectional view of a method of manufacturing a semiconductor chip structure according to the illustrated embodiment;

[0013] Fig.14 is a cross-sectional view for describing the structure of a semiconductor chip according to an embodiment;

[0014] Fig.15 and Fig.16 It is used to describe manufacturing Fig.14 A cross-sectional view of a method for a semiconductor chip structure;

[0015] Fig.17 is a block diagram schematically showing a memory card to which a semiconductor package including a semiconductor chip structure according to an embodiment is applied; and

[0016] Fig.18 is a block diagram schematically illustrating an electronic system to which a semiconductor package including a semiconductor chip structure according to an embodiment is applied. DETAILED DESCRIPTION

[0017] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals refer to the same elements in the drawings, and their repeated descriptions are omitted.

[0018] The embodiments of the inventive concept are provided so that the disclosure is comprehensive and complete, and the concept of the inventive concept is fully conveyed to those of ordinary skill in the art. However, the embodiments of the inventive concept are not limited to the described embodiments, and it should be understood that the inventive concept covers all changes, equivalent forms or alternative forms within the scope of the thought and technology of the inventive concept. When describing the inventive concept, detailed descriptions of known technologies associated with the inventive concept may be omitted, which may unnecessarily obscure the main points of the inventive concept.

[0019] Herein, a singular form of an element may include a plural form unless the context clearly specifies otherwise. In order to more clearly describe the inventive concept, some elements in the drawings may be exaggerated.

[0020] Figure 1 is a cross-sectional view for describing a semiconductor chip structure 1 according to an embodiment, and Figure 2 Is used to describe Figure 1 A partial cross-sectional view of a semiconductor chip structure 1 is shown.

[0021] In detail, Figure 1 and Figure 2 , the X direction and the Y direction may both be directions parallel to the surface 60a (e.g., upper surface) of the first substrate 60 and the surface 10a of the second substrate 10. In an embodiment, the Z direction may be a direction perpendicular to the surface 60a (e.g., upper surface) of the first substrate 60 and the surface 10a of the second substrate 10. Figure 2 Can be Figure 1 An enlarged cross-sectional view of a portion EN1 of the semiconductor chip structure 1 is shown.

[0022] The semiconductor chip structure 1 can be configured by bonding the second semiconductor chip 200 to the first semiconductor chip 100. In an embodiment, in the semiconductor chip structure 1, the first semiconductor chip 100 can be disposed in a lower portion (e.g., in the Z direction), and the second semiconductor chip 200 can be disposed in an upper portion (e.g., in the Z direction). However, the embodiments of the present inventive concept are not necessarily limited to this. For example, the first semiconductor chip 100 can be disposed in an upper portion of the semiconductor chip structure 1, and the second semiconductor chip 200 can be disposed in a lower portion of the semiconductor chip structure 1. Here, for convenience, the upper surface or upper portion of the first substrate 60 can be in the Z direction, and the upper surface or upper portion of the second substrate 10 can be in the Z direction.

[0023] The first semiconductor chip 100 may include a first chip region CHR1 and a first scribe lane region SLR1. The first chip region CHR1 may be a region where circuit elements (e.g., transistors, capacitors, resistors, etc.) configuring the first semiconductor chip 100 are provided. The first scribe lane region SLR1 may be a region formed secondarily when manufacturing the first chip region CHR1. The first scribe lane region SLR1 is spaced apart from the first chip region CHR1 (e.g., in the X direction). In an embodiment, the first scribe lane region SLR1 may be a region where no circuit elements are provided.

[0024] The second semiconductor chip 200 may include a second chip region CHR2 and a second scribe lane region SLR2. The second chip region CHR2 may be a region where circuit elements (e.g., memory cells) configuring the second semiconductor chip 200 are provided. The second scribe lane region SLR2 may be a region formed secondarily when manufacturing the second chip region CHR2. The second scribe lane region SLR2 is spaced apart from the second chip region CHR2 (e.g., in the X direction). In an embodiment, the second scribe lane region SLR2 may be a region where no circuit elements are provided.

[0025] The semiconductor chip structure 1 may be configured by bonding a first semiconductor chip 100 including a first chip region CHR1 and a first scribe street region SLR1 to a second semiconductor chip 200 including a second chip region CHR2 and a second scribe street region SLR2 respectively corresponding thereto.

[0026] First, elements of the first semiconductor chip 100 and the second semiconductor chip 200 will be described in more detail.

[0027] In more detail, the first semiconductor chip 100 may include a first substrate layer 100a, a first circuit layer 100b, a first final wiring layer 100c, and a first bonding wiring layer 100d that may be arranged along the Z direction. The first substrate layer 100a may include a first substrate 60. The first substrate 60 may include a surface 60a (e.g., an upper surface) and a back side 60b disposed on a side opposite to the surface 60a (e.g., in the Z direction). In an embodiment, the first substrate 60 may be a silicon substrate. For example, the first substrate 60 may be a silicon wafer. The first substrate 60 may include a first chip region CHR1 and a first scribe lane region SLR1.

[0028] The first circuit layer 100b may be disposed on a first substrate 60 including a first chip region CHR1 and a first scribe street region SLR1. The first circuit layer 100b may include a first circuit 62. The first circuit 62 may be disposed on a surface 60a of the first substrate 60 (e.g., directly thereon in the Z direction). In an embodiment, the first circuit 62 may be a peripheral circuit. The peripheral circuit may include a circuit element (e.g., a transistor).

[0029] The first final wiring layer 100c may be disposed on the first circuit layer 100b (e.g., directly disposed thereon in the Z direction). In an embodiment, the first final wiring layer 100c may include a first final wiring pattern 65, a first passivation layer 64 insulating the first final wiring pattern 65, and a first etch stop layer 66 disposed on the first passivation layer 64 and the first final wiring pattern 65 (e.g., directly disposed thereon).

[0030] The first final wiring pattern 65 may be electrically connected to the first circuit 62. Figure 1 , the first final wiring pattern 65 is shown as being directly connected to the first circuit 62. However, embodiments of the inventive concept are not necessarily limited thereto. For example, in an embodiment, the first final wiring pattern 65 may be electrically connected to the first circuit 62 through an intermediate wiring pattern. The first final wiring pattern 65 may include a metal material.

[0031] In some embodiments, the first final wiring pattern 65 may include a metal material different from the first bonding electrode 72. In some embodiments, the first final wiring pattern 65 may include aluminum, copper, tungsten, etc. In some embodiments, the first final wiring pattern 65 may include a base metal (e.g., aluminum and an impurity element), and may include, for example, a metal alloy containing silicon.

[0032] The first passivation layer 64 may insulate the first final wiring pattern 65. In an embodiment, the first passivation layer 64 may include silicon oxide. For example, the first passivation layer 64 may include silicon oxide formed by a high density plasma (HDP) process. The first etch barrier layer 66 may be formed to prevent the first final wiring pattern 65 from being damaged when the first bonding electrode 72 is formed. However, embodiments of the inventive concept are not necessarily limited thereto, and the first etch stop layer 66 may not be formed in some embodiments. In an embodiment, the first etch stop layer 66 may include silicon nitride.

[0033] The first bonding wiring layer 100d may be disposed on the first final wiring layer 100c (e.g., in the Z direction). In an embodiment, the first bonding wiring layer 100d may include a first interlayer insulating layer 68, a first bonding insulating layer 70, and a first bonding electrode 72. The first interlayer insulating layer 68 may be disposed on the first passivation layer 64, the first final wiring pattern 65, and the first etch stop layer 66 (e.g., in the Z direction). In an embodiment, the first interlayer insulating layer 68 may include silicon oxide. For example, the first interlayer insulating layer 68 may include silicon oxide formed by an HDP process.

[0034] The first bonding insulating layer 70 may be disposed on the first interlayer insulating layer 68 (e.g., directly thereon in the Z direction). In an embodiment, the first bonding insulating layer 70 may include at least one material selected from silicon carbide nitride (SiCN) and silicon oxide (SiO). The first bonding electrode 72 may be disposed in the first interlayer insulating layer 68 and the first bonding insulating layer 70.

[0035] The first bonding electrode 72 may include a metal material (e.g., copper, etc.). The first bonding electrode 72 may have an upper width and a lower width that are different along the Z direction. The first bonding electrode 72 may include nanotwin copper and fine grain copper. The detailed elements of the first bonding electrode 72 will be described below with reference to the accompanying drawings.

[0036] The second semiconductor chip 200 may include a second substrate layer 200a, a second circuit layer 200b, an intermediate wiring layer 200c, a second final wiring layer 200d, and a second bonding wiring layer 200e arranged in the Z direction. The second substrate layer 200a may include a second substrate 10. The second substrate 10 may include a surface 10a and a back side 10b disposed on a side opposite to the surface 10a (e.g., in the Z direction). In an embodiment, the second substrate 10 may be a silicon substrate. For example, the second substrate 10 may be a silicon wafer. The second substrate 10 may include a second chip region CHR2 and a second scribe road region SLR2.

[0037] The second circuit layer 200b may be disposed on the second substrate 10 including the second chip region CHR2 and the second scribing street region SLR2 (e.g., disposed directly thereon along the Z direction). In an embodiment, the second circuit layer 200b may include a second circuit 12. The second circuit 12 may be disposed on the surface 10a of the second substrate 10. The second circuit 12 may be driven by the first circuit 62.

[0038] In an embodiment, the second circuit 12 may include a memory cell. When the first circuit 62 and the second circuit 12 are separated from the semiconductor chip structure 1 , thermal stress applied when processes are performed on the first circuit 62 and the second circuit 12 may be optimized.

[0039] The intermediate wiring layer 200c may be disposed on the second circuit layer 200b (e.g., directly thereon in the Z direction). In an embodiment, the intermediate wiring layer 200c may include a first intermediate wiring insulating layer 14, an intermediate wiring pattern 15, a second etch stop layer 16, a second intermediate wiring insulating layer 18, and an intermediate wiring via 20. The intermediate wiring pattern 15 may be electrically connected to the second circuit 12.

[0040] The intermediate wiring pattern 15 may be insulated by the first intermediate wiring insulating layer 14. The intermediate wiring via 20 may be insulated by the second intermediate wiring insulating layer 18. In an embodiment, the intermediate wiring via 20 may be electrically connected to the intermediate wiring pattern 15 and may directly contact the intermediate wiring pattern 15. The intermediate wiring via 20 may include a plurality of via electrodes.

[0041] In an embodiment, the intermediate wiring pattern 15 and the intermediate wiring path 20 may include a metal material (e.g., aluminum, copper, tungsten, etc.). The first intermediate wiring insulation layer 14 and the second intermediate wiring insulation layer 18 may include silicon oxide. For example, the first intermediate wiring insulation layer 14 and the second intermediate wiring insulation layer 18 may include silicon oxide formed by an HDP process.

[0042] The second etch stop layer 16 may be formed to prevent the intermediate wiring pattern 15 from being damaged when forming the intermediate wiring via 20. However, embodiments of the inventive concept are not necessarily limited thereto, and in some embodiments, the second etch stop layer 16 may not be formed. In an embodiment, the second etch stop layer 16 may include silicon nitride.

[0043] The second final wiring layer 200d may be disposed on the intermediate circuit layer 200c (e.g., directly thereon in the Z direction). In an embodiment, the second final wiring layer 200d may include second final wiring patterns 22a and 22b, polishing stop patterns 28a and 28b, and second passivation layers 32a and 32b. The second final wiring patterns 22a and 22b may be electrically connected to the intermediate wiring pattern 15 through the intermediate wiring via 20.

[0044] The second final wiring patterns 22a and 22b may include a second final wiring pattern 22a formed in the second chip region CHR2 and a second final wiring pattern 22b formed in the second scribing street region SLR2. In an embodiment, in the X direction, the width of the second final wiring pattern 22a may be greater than the width of the second final wiring pattern 22b. The second final wiring patterns 22a and 22b may include a metal material.

[0045] In some embodiments, the second final wiring patterns 22a and 22b may include a different metal material from the second bonding electrode 52. In some embodiments, the second final wiring patterns 22a and 22b may include a base metal (eg, aluminum and an impurity element), and may include, for example, a metal alloy containing silicon.

[0046] Polishing stop patterns 28a and 28b may be disposed on the second final wiring layer 22b (eg, in the Z direction). The polishing stop patterns 28a and 28b may be formed to prevent the second final wiring patterns 22a and 22b from being damaged when a polishing process (eg, chemical mechanical polishing) is performed.

[0047] The polishing stop patterns 28a and 28b may have at least one of a metal pattern, an insulating pattern, and a combination thereof. In some embodiments, the polishing stop patterns 28a and 28b have a combined pattern of the metal patterns 24a and 24b and the insulating patterns 26a and 26b, or may be formed as a single pattern having the metal patterns 24a and 24b and the insulating patterns 26a and 26b. In some embodiments, the metal patterns 24a and 24b may include a single layer and a combined layer of titanium (Ti), tantalum (Ta), and titanium nitride (TiN). The insulating patterns 26a and 26b may include silicon nitride.

[0048] The polish stop patterns 28a and 28b may include a polish stop pattern 28a formed in the second chip region CHR2 and a polish stop pattern 28b formed in the second scribe street region SLR2. In the X direction, the width of the polish stop pattern 28a may be greater than that of the polish stop pattern 28b.

[0049] Due to the over-etching process, the second passivation layers 32a and 32b may be disposed in the first intermediate wiring insulation layer 14 or the second intermediate wiring insulation layer 18. In an embodiment, the second passivation layers 32a and 32b may include silicon oxide. For example, the second passivation layers 32a and 32b may include silicon oxide formed by an HDP process.

[0050] The second bonding wiring layer 200e may be disposed on the second final wiring layer 200d (e.g., disposed directly thereon in the Z direction). In an embodiment, the second bonding wiring layer 200e may include a second interlayer insulating layer 40, an adhesive layer 42, a second bonding insulating layer 44, and a second bonding electrode 52. The second interlayer insulating layer 40 may be disposed on the second passivation layers 32a and 32b and the polishing stop patterns 28a and 28b (e.g., disposed directly thereon in the Z direction).

[0051] In an embodiment, the second interlayer insulating layer 40 may include silicon nitride. The adhesive layer 42 may be formed to increase the adhesive properties between the second interlayer insulating layer 40 and the second bonding insulating layer 44. However, the embodiments of the present inventive concept are not necessarily limited thereto, and the adhesive layer 42 may not be formed in some embodiments. In an embodiment, the adhesive layer 42 may include silicon oxide.

[0052] The second bonding insulating layer 44 may be disposed on the second interlayer insulating layer 40 and the adhesive layer 42 (eg, directly thereon in the Z direction). In an embodiment, the second bonding insulating layer 44 may include at least one material selected from SiCN and SiO.

[0053] The second bonding electrode 52 may be disposed in the second interlayer insulating layer 40, the adhesive layer 42, the second bonding insulating layer 44, and the polishing stop pattern 28a of the second chip region CHR2. The second bonding electrode 52 may include a metal material (e.g., copper, etc.). In an embodiment, the second bonding electrode 52 may have an upper width and a lower width that are different along the Z direction. The second bonding electrode 52 may include nano-twinned copper and fine-grained copper. The detailed elements of the first bonding electrode 52 will be described below with reference to the accompanying drawings.

[0054] In an embodiment, each of the first bonding insulating layer 70 and the first bonding electrode 72 of the first bonding wiring layer 100d of the semiconductor chip structure 1 may be hybrid-bonded to the second bonding insulating layer 44 and the second bonding electrode 52 of the second bonding wiring layer 200e. Figure 2 The enlarged view of the cross section of the portion EN1 of the semiconductor chip structure 1 illustrates the bonding configuration of the first semiconductor chip 100 and the second semiconductor chip 200 in more detail. Figure 2 , for convenience, the upper and lower widths of the first bonding electrode 72 and the second bonding electrode 52 in the Z direction are illustrated as being equal to each other. However, embodiments of the inventive concept are not necessarily limited thereto.

[0055] In the first semiconductor chip 100, the upper surface of each of the first final wiring pattern 65 and the first passivation layer 64 of the first final wiring layer 100c may include a first flat surface PL1 having no step height between the first chip region CHR1 and the first scribing street region SLR1. In an embodiment, by polishing (e.g., chemical mechanical polishing) the surface of each of the first final wiring pattern 65 and the first passivation layer 64, the first flat surface PL1 may have no step height.

[0056] In the first semiconductor chip 100, the upper surface of each of the first bonding electrode 72 of the first bonding wiring layer 100d and the first bonding insulation layer 70 may include a first bonding surface b1 where there is no step height between the first chip region CHR1 and the first scribe street region SLR1. The first bonding surface b1 may be a first flat bonding surface. The first bonding electrode 72 may have a first width W1 (e.g., a length in the X direction). In an embodiment, the first bonding electrode 72 may include a first barrier metal layer 72a, a first via electrode 72b, a first internal electrode 72c, and a first upper electrode 72d.

[0057] In an embodiment, the first barrier metal layer 72a may include Ti, Ta, TiN or TaN. The first internal electrode 72c may be electrically connected to the first via electrode 72b, and thus may be provided as a whole. In some embodiments, the first internal electrode 72c and the first via electrode 72b may include nanotwinned copper. The first upper electrode 72d may include fine-grained copper located on the first internal electrode 72c. In an embodiment, the grain size (e.g., grain length) of the fine-grained copper filling the first upper electrode 72d may be approximately 300nm or less. The uppermost surface of the first upper electrode 72d may be coplanar with the uppermost surface of the first internal electrode 72c to configure a flat first bonding surface b1 without a step height. The first barrier metal layer 72a, the first via electrode 72b, the first internal electrode 72c and the first upper electrode 72d may be electrically connected to the first final wiring pattern 65.

[0058] In the second semiconductor chip 200 , an upper surface of each of the polish stop patterns 28 a and 28 b and the second passivation layers 32 a and 32 b of the second final wiring layer 200 d may include a second planar surface PL2 having no step height between the second chip region CHR2 and the second scribe street region SLR2 .

[0059] In the second semiconductor chip 200 , the upper surface of each of the second bonding electrode 52 and the second bonding insulation layer 44 of the second bonding wiring layer 200 e may include a second bonding surface b2 having no step height between the second chip region CHR2 and the second scribe street region SLR2 .

[0060] The second bonding surface b2 may be a second flat bonding surface. The upper portion of the second bonding electrode 52 may have a second width W2 (e.g., a length in the X direction). In an embodiment, the first width W1 of the upper portion of the first bonding electrode 72 and the second width W2 of the upper portion of the second bonding electrode 52 may be substantially equal to each other. In an embodiment, the second bonding electrode 52 may include a second barrier metal layer 52a, a second via electrode 52b, a second internal electrode 52c, and a second upper electrode 52d.

[0061] In an embodiment, the second barrier metal layer 52a may include Ti, Ta, TiN or TaN. The second internal electrode 52c may be electrically connected to the second via electrode 52b, and thus may be provided as a whole. In some embodiments, the second internal electrode 52c and the second via electrode 52b may include nano-twinned copper. The second upper electrode 52d may include fine-grained copper located on the second internal electrode 52c. In an embodiment, the grain size of the fine-grained copper filling the second upper electrode 52d may be about 300nm or less. The uppermost surface of the second upper electrode 52d may be coplanar with the uppermost surface of the second internal electrode 52c to configure a flat second bonding surface b2 without a step height. The second barrier metal layer 52a, the second via electrode 52b, the second internal electrode 52c and the second upper electrode 52d may be electrically connected to the second final wiring pattern 22a of the second chip region CHR2.

[0062] like Figure 2 As shown by the arrows, the first bonding electrode 72 of the first bonding wiring layer 100d and the first bonding surface b1 of the first bonding insulating layer 70 can be directly bonded to the second bonding electrode 52 of the second bonding wiring layer 200e and the second bonding surface b2 of the second bonding insulating layer 44. The simultaneous bonding of the bonding insulating layers 70 and 44 with the bonding electrodes 72 and 52 can be referred to as hybrid bonding.

[0063] In an embodiment, hybrid bonding can be performed by heat treatment in a state where the first bonding insulating layer 70 and the second interlayer insulating layer 40 are attached to the first bonding electrode 72 and the second bonding electrode 52. The first bonding surface b1 of the first bonding wiring layer 100d and the second bonding surface b2 of the second bonding wiring layer 200e can be a flat bonding surface. In this embodiment, in a bonding interface configured by a first upper electrode 72d and a second upper electrode 52d having a first bonding surface b1 and a second bonding surface b2, both of which have fine-grained copper, the mutual diffusion between copper and copper can be increased (e.g., maximized). Since the first bonding electrode 72 and the second bonding electrode 52 use a dual material including fine-grained copper and nano-twinned copper, the semiconductor chip structure 1 can improve the bonding reliability of bonding the first semiconductor chip 100 to the second semiconductor chip 200.

[0064] FIG. 3A to FIG. 3C is a partial cross-sectional view for describing a semiconductor chip structure according to an embodiment of the present disclosure.

[0065] In detail, FIG. 3A to FIG. 3C An enlarged cross-sectional view of portions EN2 to EN4 may be Figure 1 and Figure 2 FIG. 1 is a modified embodiment of an enlarged cross-sectional view of a portion EN1 of a semiconductor chip structure 1. FIG. 3A to FIG. 3C In, with Figure 1 and Figure 2 Like reference numerals denote like elements. FIG. 3A to FIG. 3C In order to facilitate the description, the Figure 1 and Figure 2 The same or similar description.

[0066] refer to Figure 3A , except that the first bonding electrode 72-1 of the first semiconductor chip 100 and the second bonding electrode 52-1 of the second semiconductor chip 200 are bonded to each other without matching (eg, completely overlapping) in the Z direction (eg, vertical direction), the semiconductor chip structure ( Figure 1 The enlarged cross-sectional view of part EN2 of 1) can be compared with Figure 2 Semiconductor chip structure ( Figure 1 The same as the enlarged cross-sectional view of part EN1 of 1).

[0067] The first bonding wiring layer 100d of the first semiconductor chip 100 may include a first bonding electrode 72-1 and a first bonding insulating layer 70. In an embodiment, as described above, the first bonding electrode 72-1 may include a first barrier metal layer 72a, a first via electrode 72b, a first internal electrode 72c, and a first upper electrode 72d. In an embodiment, the second bonding wiring layer 200e of the second semiconductor chip 200 may include a second bonding electrode 52-1 and a second bonding insulating layer 44. The second bonding electrode 52-1 may include a second barrier metal layer 52a, a second via electrode 52b, a second internal electrode 52c, and a second upper electrode 52d.

[0068] like Figure 3A As shown by the arrow, when the first bonding wiring layer 100d and the second bonding wiring layer 200e are mixed and bonded, the first bonding electrode 72-1 of the first semiconductor chip 100 and the second bonding electrode 52-1 of the second semiconductor chip 200 can be bonded to each other without matching in the Z direction (e.g., the vertical direction). For example, the first bonding surface b1 and the second bonding surface b2 may not completely overlap each other (e.g., in the Z direction). Although the first bonding electrode 72-1 and the second bonding electrode 52-1 are not bonded to each other in a completely matching manner in the vertical direction, in the bonding interface formed by bonding the first upper electrode 72d and the second upper electrode 52d both including fine-grained copper to each other, mutual diffusion between copper and copper can be easily performed.

[0069] refer to Figure 3B , except that the third width W3 (eg, the length in the X direction) of the first bonding electrode 72-2 and the shape of the first via electrode 72b-2 of the first bonding electrode 72-2 are changed, the semiconductor chip structure ( Figure 1 The enlarged cross-sectional view of part EN3 of 1) can be compared with Figure 3AAn enlarged cross-sectional view of portion EN2 is the same.

[0070] In an embodiment, the third width W3 (eg, the length in the X direction) of the first bonding electrode 72-2 may be greater than the first bonding electrode ( Figure 3A The first via electrode 72b-2 of the first bonding electrode 72-2 may be larger in the Z direction than the first width W1 (eg, length in the X direction). Figure 3A The second via electrode 52b-2 of the second bonding electrode 52-2 may be taller than the first via electrode 72b of the second bonding electrode 52-2 (for example, have a greater length). Figure 3A The second via electrode 52 b is taller (eg, has a greater length).

[0071] like Figure 3B As shown by the arrow, when the first bonding wiring layer 100d is mixed with the second bonding wiring layer 200e, the first bonding electrode 72-2 having a wide third width W3 of the first semiconductor chip 100 can be easily bonded to the second bonding electrode 52-2 having a narrower second width W2 of the second semiconductor chip 200. The second bonding surface b2 can completely overlap with the first bonding surface b1 (for example, in the Z direction). Although the third width W3 of the first semiconductor chip 100 is greater than the second width W2 of the second semiconductor chip 200, in the bonding interface formed by bonding the first upper electrode 72d and the second upper electrode 52d each including fine-grained copper to each other, mutual diffusion between copper and copper can be easily performed.

[0072] refer to Figure 3C , except that the shapes of the first bonding electrode 72-3 and the second bonding electrode 52-3 are changed, the semiconductor chip structure ( Figure 1 The enlarged cross-sectional view of part EN4 of 1) can be compared with Figure 3A An enlarged cross-sectional view of portion EN2 is the same.

[0073] In an embodiment, the first bonding electrode 72-3 may include a first barrier metal layer 72a, a first via electrode 72b-3, and a first upper electrode 72d. The first upper electrode 72d including fine-grained copper may be arranged to have a lateral side surface surrounded by the first via electrode 72b-3 including nanotwinned copper. The upper surface of the first bonding electrode 72-3 may have a width less than the first width ( Figure 3C The fourth width W4 of the first bonding electrode 72-3 may be substantially the same as or slightly smaller than the width of the first via electrode 72b-3.

[0074] In an embodiment, the second bonding electrode 52-3 may include a second barrier metal layer 52a, a second via electrode 52b-3, and a second upper electrode 72d. The second upper electrode 72d including fine-grained copper may be arranged to have a lateral side surface surrounded by the second via electrode 52b-3 including nanotwinned copper. The fifth width W5 (e.g., the length in the X direction) of the second bonding electrode 52-3 may be substantially the same as the width of the third via electrode 52b-3. The fifth width W5 of the second bonding electrode 52-3 may be substantially the same as or slightly smaller than the width W4 of the first bonding electrode 72-3.

[0075] like Figure 3C As shown by the arrows, when the first bonding wiring layer 100d and the second bonding wiring layer 200e are mixed-bonded, the first bonding electrode 72-3 having the fourth width W4 of the first semiconductor chip 100 can be easily bonded to the second bonding electrode 52-3 having the fifth width W5 of the second semiconductor chip 200. Interdiffusion between copper and copper can be easily performed in the bonding interface formed by bonding the first upper electrode 72d and the second upper electrode 52d each including fine grains to each other.

[0076] Figures 4 to 13 It is used to describe manufacturing Figure 1 and Figure 2 A cross-sectional view of a method of structuring a semiconductor chip 1.

[0077] In detail, Figures 4 to 12 It is used to describe manufacturing Figure 1 and Figure 2 FIG. 1 is a diagram of a method for manufacturing a second semiconductor chip 200. Figures 4 to 12 In, with Figure 1 and Figure 2 Like reference numerals denote like elements.

[0078] refer to Figure 4 , a second circuit 12 may be formed on a surface 10a of a second substrate 10 including a second chip region CHR2 and a second scribe lane region SLR2 spaced apart from each other (e.g., in the X direction) (e.g., formed directly thereon in the Z direction). The second substrate 10 may include a surface 10a and a back surface 10b opposite thereto. As described above, the second circuit 12 may include a memory cell. The memory cell may include a circuit element (e.g., a transistor).

[0079] An intermediate wiring pattern 15 insulated by the first intermediate wiring insulation layer 14 may be formed on the second circuit 12 (e.g., formed directly thereon in the Z direction). In an embodiment, the first intermediate wiring insulation layer 14 may include silicon oxide. For example, the first intermediate wiring insulation layer 14 may include silicon oxide formed by an HDP process. The intermediate wiring pattern 15 may be electrically connected to the second circuit 12. The intermediate wiring pattern 15 may include a metal material (e.g., aluminum, copper, tungsten, etc.).

[0080] A second etch stop layer 16 may be formed on the first intermediate wiring insulating layer 14 and the intermediate wiring pattern 15 (e.g., formed directly thereon in the Z direction). In an embodiment, the second etch stop layer 16 may include silicon nitride. An intermediate wiring via 20 electrically connected to the intermediate wiring pattern 15 and a second intermediate wiring insulating layer 18 insulating the intermediate wiring via 20 may be formed on the second etch stop layer 16 (e.g., formed directly thereon in the Z direction).

[0081] The intermediate wiring via 20 may include a metal material (eg, aluminum, copper, tungsten, etc.). In an embodiment, the second intermediate wiring insulating layer 18 may include silicon oxide. For example, the second intermediate wiring insulating layer 18 may include silicon oxide formed by a HDP process.

[0082] A second final wiring material layer 22 and a polishing stop material layer 28 may be sequentially formed (e.g., in the Z direction) on the second intermediate wiring insulation layer 18 and the intermediate wiring via 20. The second final wiring material layer 22 may include a metal material. For example, the second final wiring material layer 22 may include aluminum, copper, tungsten, and / or the like.

[0083] In some embodiments, the second final wiring material layer 22 may include a base metal (e.g., aluminum and impurity elements), and may include, for example, a metal alloy containing silicon. In an embodiment, the polishing stop material layer 28 may be configured by a combination of a metal material layer 24 and an insulating material layer 26. For example, the metal material layer 24 may include a single layer or a combination layer of Ti, Ta, and TiN. The second material layer 26 may include silicon nitride.

[0084] refer to Figure 5 In an embodiment, the polishing stop patterns 28a and 28b and the second final wiring patterns 22a and 22b may be formed by patterning the polishing stop material layer 28 and the second final wiring material layer 22 using a photolithography process.

[0085] The second final wiring patterns 22a and 22b may include a second final wiring pattern 22a formed in the second chip region CHR2 and a second final wiring pattern 22b formed in the second scribing street region SLR2. In an embodiment, the width of the second final wiring pattern 22a may be formed to be greater than the width of the second final wiring pattern 22b in the X direction. The second final wiring pattern 22b may be formed to be denser than the second final wiring pattern 22a in the X direction.

[0086] Polishing stop patterns 28a and 28b may be formed on the second final wiring patterns 22a and 22b (e.g., formed directly thereon in the Z direction). The polishing stop patterns 28a and 28b may be configured by a combination of the metal patterns 24a and 24b and the insulating patterns 26a and 26b. The polishing stop patterns 28a and 28b may include a polishing stop pattern 28a formed in the second chip region CHR2 and a polishing stop pattern 28b formed in the second scribing street region SLR2. In an embodiment, the width of the polishing stop pattern 28a in the X direction may be greater than the width of the polishing stop pattern 28b in the X direction.

[0087] Due to over-etching when forming the second final wiring patterns 22a and 22b and the polishing stop patterns 28a and 28b, the first to fourth trenches 30a to 30d may be formed in the second intermediate wiring insulation layer 18. In an embodiment, the depth of the fourth trench 30d formed in the second scribing street region SLR2 in the Z direction may be greater than the depth of each of the first to third trenches 30a to 30c in the Z direction.

[0088] Subsequently, a second passivation material layer 32 may be formed on the second final wiring patterns 22a and 22b and the polishing stop patterns 28a and 28b while burying the first to fourth trenches 30a to 30d. In an embodiment, the second passivation material layer 32 may include silicon oxide. For example, the second passivation material layer 32 may include silicon oxide formed by an HDP process.

[0089] The second passivation material layer 32 may include an upper surface 36 in the second chip region CHR2 and an upper surface 34 in the second scribe street region SLR2. The second passivation material layer 32 may have a step height between an uppermost surface 36H of the second chip region CHR2 and a lowermost surface 34L of the second scribe street region SLR2.

[0090] refer to Figure 6 , the second passivation material layer 32 may be polished (eg, chemical mechanical polishing) by using the polishing stop patterns 28a and 28b as a polishing stop layer. Thus, the second passivation layers 32a and 32b may be formed between the structure including the second final wiring patterns 22a and 22b and the polishing stop patterns 28a and 28b.

[0091] The second passivation layers 32a and 32b may include a second passivation layer 32a formed in the second chip region CHR2 and a second passivation layer 32b formed in the second scribing street region SLR2. In addition, by polishing the polishing stop patterns 28a and 28b and the upper surfaces of the second passivation layers 32a and 32b, a second flat surface PL2 having no step height may be formed between the second chip region CHR2 and the second scribing street region SLR2.

[0092] refer to Figure 7 and Figure 8 ,like Figure 7 As shown, a second interlayer insulating layer 40 may be formed on the polishing stop patterns 28a and 28b and the second passivation layers 32a and 32b (e.g., formed directly thereon in the Z direction). In an embodiment, the second interlayer insulating layer 40 may include silicon oxide. Subsequently, the resulting product formed with the second final wiring patterns 22a and 22b, the polishing stop patterns 28a and 28b, the second passivation layers 32a and 32b, and the second interlayer insulating layer 40 may be heat-treated. For example, in an embodiment, the second final wiring patterns 22a and 22b and the polishing stop patterns 28a and 28b may be alloyed by a heat treatment process.

[0093] Then, if Figure 8 As shown, an adhesive layer 42 and a bonding insulating layer 44 may be sequentially formed on the second interlayer insulating layer 40 (e.g., formed directly thereon in the Z direction). In an embodiment, the adhesive layer 42 may be formed to increase the adhesion performance between the second interlayer insulating layer 40 and the second bonding insulating layer 44. In an embodiment, the adhesive layer 42 may include silicon oxide. The second bonding insulating layer 44 may include at least one material of SiCN and SiO.

[0094] refer to Fig. 9 In an embodiment, a second through hole 50 may be formed by performing a photolithography process on the second bonding insulation layer 44, the adhesive layer 42, the second interlayer insulation layer 40, and the polishing stop pattern 28a of the second chip region CHR2. The second through hole 50 may be formed in the second bonding insulation layer 44, the adhesive layer 42, the second interlayer insulation layer 40, and the polishing stop pattern 28a. The second through hole 50 may expose a surface (e.g., an upper surface) of the second final wiring pattern 22a of the second chip region CHR2.

[0095] In an embodiment, the second via 50 may include a second lower via 46 formed in the second interlayer insulating layer 40 and the polish stop pattern 28a, and a second upper via 48 formed in the second bonding insulating layer 44, the adhesive layer 42, and the second interlayer insulating layer 40. In the X direction, the width of the second upper via 48 may be greater than the width of the second lower via 46. The second upper via 48 may be directly connected to the second lower via 46.

[0096] refer to Fig.10 In an embodiment, a preliminary second barrier metal layer 52a' may be conformally deposited on the sidewalls and lower walls of the second lower through hole 46 and the sidewalls of the second upper through hole 48, and a second internal electrode layer 52c' may be formed on (e.g., directly formed on) the preliminary second barrier metal layer 52a' and the second bonding insulating layer 44 by an electroplating process. The second internal electrode layer 52c' may include nano-twinned copper. In an embodiment, the second internal electrode layer 52c' may be formed to completely fill the second lower through hole 46 surrounded by the preliminary second barrier metal layer 52a', and to fill a portion of the second upper through hole 48. A second internal electrode layer 52c' having a certain thickness may be formed on the second bonding insulating layer 44. This process may be referred to as a first copper plating process.

[0097] refer to Fig.11 , can be electroplated Fig.10 A second upper electrode layer 52d' is formed on the resulting product. The second upper electrode layer 52d' may include fine-grained copper. In an embodiment, the grain size of the fine-grained copper filling the second upper electrode layer 52d' may be approximately 300nm or less. In the second upper through hole 48, a second upper electrode layer 52d' may be formed to cover other portions of the second internal electrode layer 52c' that are not filled. The second upper electrode layer 52d' may be formed on the second internal electrode layer 52c' to cover the second internal electrode layer 52c' formed on the second bonding insulating layer 44 with a certain thickness. This process may be referred to as a second copper plating process.

[0098] refer to Fig.12 In an embodiment, it can be achieved by Fig.11 The second upper electrode layer 52d' and the second internal electrode layer 52c' are polished by a chemical mechanical polishing process in. The chemical mechanical polishing process may be performed so that the uppermost surface of the second bonding insulating layer 44 is exposed. Fig.12In the resulting material, a second upper electrode 52d having a thickness in a range of about 1 μm to about 1.5 μm relative to the second bonding surface b2 may be formed. In an embodiment, the second barrier metal layer 52a, the second via electrode 52b, the second internal electrode 52c, and the second upper electrode 52d may constitute the second bonding electrode 52. The uppermost surface of the second bonding electrode 52 may be at the same vertical height (e.g., in the Z direction) as the second bonding surface b2. When the uppermost surface of the second bonding electrode 52 is observed in the vertical direction (e.g., the Z direction), the second upper electrode 52d may not directly contact the edge of the uppermost surface of the second bonding electrode 52. For example, the second internal electrode 52c may fill the edge of the uppermost surface of the second bonding electrode 52. In an embodiment, this may be the result of a first copper plating process and a second copper plating process (i.e., a copper plating process performed twice).

[0099] refer to Fig.13 , Fig.13 Can be used to describe Figure 1 and Figure 2 FIG. 1 is a diagram of a bonding process of a first semiconductor chip 100 and a second semiconductor chip 200. Figure 1 and Figure 2 The first semiconductor chip 100 is shown. Fig.13 In, with Figure 1 and Figure 2 Like reference numerals denote like elements. Fig.13 In the Figure 1 and Figure 2 The same or similar description.

[0100] In the first semiconductor chip 100, a first circuit 62 may be formed on (e.g., formed directly thereon in the Z direction) a first substrate 60, and then a first passivation layer 64 and a first final wiring pattern 65 may be formed on (e.g., formed directly thereon in the Z direction) the first circuit 62. A first etch stop layer 66 may be formed on (e.g., formed directly thereon in the Z direction) the first passivation layer 64 and the first final wiring pattern 65. A first interlayer insulating layer 68 and a first bonding insulating layer 70 may be formed on (e.g., formed directly thereon in the Z direction) the first etch stop layer 66.

[0101] A first bonding electrode 72 electrically connected to the first final wiring pattern 65 may be formed on the first etch stop layer 66 and in the first interlayer insulating layer 68 and the first bonding insulating layer 70. In an embodiment, the first bonding insulating layer 70 may include at least one material selected from SiCN and SiO. The first bonding electrode 72 may include a metal material (e.g., copper). In an embodiment, the first via electrode 72b and the first internal electrode 72c of the first bonding electrode 72 may include nanotwinned copper, and the first upper electrode 72d may include fine-grained copper.

[0102] The upper surface of each of the first bonding electrode 72 and the first bonding insulating layer 70 may be a first bonding surface b1 where there is no step height between the first chip region CHR1 and the first scribe street region SLR1. The first bonding surface b1 may be a first flat bonding surface. Through such a manufacturing process, the first semiconductor chip 100 may be manufactured.

[0103] like Fig.13 The second semiconductor chip 200 manufactured as shown can be reversed and arranged on the first semiconductor chip 100. The second bonding electrode 52 of the second bonding surface b2 and the second bonding insulating layer 44 can be mixed and bonded to the first bonding electrode 72 and the first bonding insulating layer 70 of the first bonding surface b1, respectively. In this embodiment, in the bonding interface configured by the first upper electrode 72d of the first bonding surface b1 and the second upper electrode 52d of the second bonding surface b2, both of which have fine-grained copper, the mutual diffusion between copper and copper can be increased. Since the first bonding electrode 72 and the second bonding electrode 52 use a dual material including fine-grained copper and nano-twinned copper, the semiconductor chip structure 1 can improve the bonding reliability of bonding the first semiconductor chip 100 to the second semiconductor chip 200.

[0104] Fig.14 is a cross-sectional view for describing a semiconductor chip structure 2 according to an embodiment.

[0105] In detail, Fig.14 , the X direction and the Y direction may both be directions parallel to the surface 60a (e.g., upper surface) of the first substrate 60 and the surface 10a of the second substrate 10. In an embodiment, the Z direction may be a direction perpendicular to the surface 60a (e.g., upper surface) of the first substrate 60 and the surface 10a of the second substrate 10.

[0106] The semiconductor chip structure 2 may be configured by bonding the second semiconductor chip 200 to the first semiconductor chip 100. The first semiconductor chip 100 may include a first chip region CHR1. The first chip region CHR1 may be a region where circuit elements (eg, transistors TR) configuring the first semiconductor chip 100 are disposed. The first chip region CHR1 may be a region where peripheral circuits are formed.

[0107] The second semiconductor chip 200 may include a second chip region CHR2. The second chip region CHR2 may be a region where circuit elements (eg, memory cells) configuring the second semiconductor chip 200 are disposed.

[0108] In an embodiment, the semiconductor chip structure 2 may be configured from a second semiconductor chip 200 including a second chip region CHR2 to a first semiconductor chip 100 including a first chip region CHR1. Fig.14 In, with Figure 1 Differently, for the sake of convenience, the semiconductor chip structure 2 may not include the first scribe street region SLR1 of the first semiconductor chip 100 and the second scribe street region SLR2 of the second semiconductor chip 200 .

[0109] First, elements of the first semiconductor chip 100 and the second semiconductor chip 200 will be described in more detail.

[0110] In an embodiment, the first semiconductor chip 100 may include a first substrate layer 100 a , a first circuit layer 100 b , a first final wiring layer 100 c , and a first bonding wiring layer 100 d . The first substrate layer 100 a may include a first substrate 60 .

[0111] The first substrate 60 may include a surface 60a and a back surface 60b disposed on a side opposite to the surface 60a (eg, in the Z direction). In an embodiment, the first substrate 60 may be a silicon substrate. The first substrate 60 may be a silicon wafer. The first substrate 60 may include a first chip region CHR1.

[0112] The first circuit layer 100b may be disposed on the first substrate layer 100a (e.g., directly disposed thereon in the Z direction). The first circuit layer 100b may be disposed on the first substrate 60 including the first chip region CHR1. In an embodiment, the first circuit layer 100b may include a first circuit 62 and a first circuit insulation layer 63 that insulates the first circuit 62. The first circuit 62 may be disposed on the surface 60a of the first substrate 60. The first circuit 62 may be a peripheral circuit. In an embodiment, the peripheral circuit may include a transistor TR and a contact plug 112.

[0113] The first final wiring layer 100c may be disposed on the first circuit layer 100b (eg, directly thereon in the Z direction). In an embodiment, the first final wiring layer 100c may include a first final wiring pattern 65-1, a first final wiring via 114, and a first passivation layer 64 insulating the first final wiring pattern 65-1.

[0114] The first final wiring pattern 65-1 may be electrically connected to the first circuit 62. Figure 2, the first final wiring pattern 65-1 is shown to be directly connected to the first circuit 62. However, embodiments of the inventive concept are not necessarily limited thereto, and the first final wiring pattern 65-1 may be electrically connected to the first circuit 62 through an intermediate wiring pattern. The first final wiring pattern 65-1 may include a metal material.

[0115] The first final wiring pattern 65-1 may be electrically connected to the first external connection terminal 118 disposed on the back surface 60b of the first substrate 60. In an embodiment, the first final wiring pattern 65-1 may be electrically connected to the first external connection terminal 118 through a via 116 passing through the first circuit insulation layer 63 and the first substrate 60. However, embodiments of the inventive concept are not necessarily limited thereto, and the first external connection terminal 118 may not be formed in some embodiments.

[0116] In some embodiments, the first final wiring pattern 65-1 may include a metal material different from the first bonding electrode 72-4. In some embodiments, the first final wiring pattern 65-1 may include aluminum, copper, tungsten, and / or the like. In some embodiments, the first final wiring pattern 65-1 may include a base metal (e.g., aluminum and an impurity element), and, for example, may include a metal alloy containing silicon.

[0117] The first passivation layer 64 may insulate the first final wiring pattern 65-1. In an embodiment, the first passivation layer 64 may include silicon oxide. For example, the first passivation layer 64 may include silicon oxide formed by an HDP process.

[0118] The first bonding wiring layer 100d may be disposed on the first final wiring layer 100c (e.g., disposed directly thereon in the Z direction). In an embodiment, the first bonding wiring layer 100d may include a first interlayer insulating layer 68, a first bonding insulating layer 70, and a first bonding electrode 72-4. The first bonding electrode 72-4 may include a first via electrode 72b, a first internal electrode 72c, and a first upper electrode 72d. The first interlayer insulating layer 68 may be disposed on the first passivation layer 64 and the first final wiring pattern 65-1. In an embodiment, the first interlayer insulating layer 68 may include silicon oxide. For example, the first interlayer insulating layer 68 may include silicon oxide formed by an HDP process.

[0119] The first bonding insulating layer 70 may be disposed on the first interlayer insulating layer 68 (e.g., directly thereon in the Z direction). In an embodiment, the first bonding insulating layer 70 may include at least one material selected from SiCN and SiO. The first via electrode 72b may be disposed in the first interlayer insulating layer 68. In an embodiment, the first internal electrode 72c may be electrically connected to the first via electrode 72b and may be disposed as a whole on the first via electrode 72b. The first internal electrode 72c may be disposed in the first bonding insulating layer 70.

[0120] The first via electrode 72b, the first internal electrode 72c and the first upper electrode 72d may include a metal material (eg, copper, etc.). The first via electrode 72b and the first internal electrode 72c may include nanotwinned copper. The first upper electrode 72d disposed on the first internal electrode 72c may include fine-grained copper.

[0121] In an embodiment, the second semiconductor chip 200 may include a second substrate layer 200a, a second circuit layer 200b, an intermediate wiring layer 200c, a second final wiring layer 200d, and a second bonding wiring layer 200e. The second substrate layer 200a may include a second substrate 10. The second substrate 10 may include a surface 10a and a back side 10b disposed on a side opposite to the surface 10a (e.g., in the Z direction). In an embodiment, the second substrate 10 may be a silicon substrate. The second substrate 10 may be a silicon wafer. The second substrate 10 may include a second chip region CHR2.

[0122] The second circuit layer 200b may be disposed on (e.g., directly disposed thereon along the Z direction) a second substrate 10 including a second chip region CHR2. The second circuit layer 200b may include a second circuit 12. The second circuit 12 may be disposed on a surface 10a of the second substrate 10. The second circuit 12 may be driven by the first circuit 62. A second external connection terminal 213 connected to the second circuit 12 may be disposed on a back side 10b of the second substrate 10. However, embodiments of the inventive concept are not necessarily limited thereto, and the second external connection terminal 213 may not be formed in some embodiments.

[0123] In an embodiment, the second circuit 12 may include a memory cell MC. In an embodiment, the memory cell MC may include conductive layers 212 and 214 disposed on the second substrate 10, and a stack structure 215 and a channel structure 217 both disposed on the conductive layers 212 and 214. The second circuit 12 may include a second circuit insulation layer 216, a contact plug 218, a pad 220, and a via plug 222.

[0124] The intermediate wiring layer 200c may be disposed on the second circuit layer 200b (e.g., directly thereon in the Z direction). In an embodiment, the intermediate wiring layer 200c may include an intermediate wiring insulation layer 228, an intermediate wiring pattern 224, and an intermediate wiring via 226. The intermediate wiring pattern 224 may be electrically connected to the via plug 222 of the second circuit 12.

[0125] The intermediate wiring pattern 224 and the intermediate wiring path 226 may be insulated by an intermediate wiring insulation layer 228. The intermediate wiring pattern 224 and the intermediate wiring path 226 may include a metal material (e.g., aluminum, copper, tungsten, etc.). In an embodiment, the intermediate wiring insulation layer 228 may include silicon oxide. The intermediate wiring insulation layer 228 may be silicon oxide.

[0126] The second final wiring layer 200d may be disposed on the intermediate circuit layer 200c (e.g., disposed directly thereon in the Z direction). The second final wiring layer 200d may include a second final wiring pattern 236, a second passivation layer 234, and a second final wiring via 232. The second final wiring pattern 236 may be electrically connected to the intermediate wiring pattern 224 through the second final wiring via 232.

[0127] In some embodiments, the second final wiring pattern 236 may include a metal material different from the second bonding electrode 52-4. For example, in some embodiments, the second final wiring pattern 236 may include aluminum, copper, tungsten, and / or the like. In some embodiments, the second final wiring pattern 236 may include a base metal (e.g., aluminum and an impurity element), and may include, for example, a metal alloy containing silicon.

[0128] In an embodiment, the second passivation layer 234 may include silicon oxide. The second passivation layer 234 may include silicon oxide.

[0129] The second bonding wiring layer 200e may be disposed on the second final wiring layer 200d (e.g., disposed directly thereon in the Z direction). In an embodiment, the second bonding wiring layer 200e may include a second interlayer insulating layer 40, a second bonding insulating layer 44, and a second bonding electrode 52-4. The second bonding electrode 52-4 may include a second via electrode 52b, a second internal electrode 52c, and a second upper electrode 52d. The second interlayer insulating layer 40 may be disposed on the second passivation layer 234 (e.g., disposed directly thereon in the Z direction).

[0130] In an embodiment, the second interlayer insulating layer 40 may include silicon nitride. The second bonding insulating layer 44 may be disposed on the second interlayer insulating layer 40. In an embodiment, the second bonding insulating layer 44 may include at least one material selected from SiCN and SiO.

[0131] The second bonding electrode 52-4 may be disposed in the second bonding insulating layer 44. The second via electrode 52b may be disposed in the second interlayer insulating layer 40. The second via electrode 52b, the second internal electrode 52c, and the second upper electrode 52d may include a metal material (e.g., copper, etc.). The second via electrode 52b and the second internal electrode 52c may include nanotwinned copper. The second upper electrode 52d disposed on the second internal electrode 52c may include fine-grained copper.

[0132] Fig.15 and Fig.16 is a cross-sectional view for describing a method of manufacturing a semiconductor chip structure according to an embodiment of the inventive concept.

[0133] In detail, Fig.15 It is used to describe manufacturing Fig.14 FIG. 1 is a diagram of a method for manufacturing a second semiconductor chip 200. Fig.15 In, with Fig.14 Like reference numerals denote like elements.

[0134] refer to Fig.15 , the second semiconductor chip 200 may include a second substrate layer 200a. The second substrate layer 200a may be formed on the second substrate 10 including the second chip region CHR2.

[0135] The second circuit layer 200b may be formed on (eg, directly thereon in the Z direction) the second substrate layer 200a. The second circuit layer 200b may include a second circuit 12. The second circuit 12 may be formed on a surface 10a (eg, upper surface) of the second substrate 10 including the second chip region CHR2.

[0136] In an embodiment, the second circuit 12 may include a memory cell MC. The memory cell MC may include conductive layers 212 and 214 disposed on the second substrate 10 and a stack structure 215 and a channel structure 217 both disposed on the conductive layers 212 and 214.

[0137] In an embodiment, the stacked structure 215 may include a gate pattern, a dielectric layer, and an insulating layer. The dielectric layer may cover the upper and lower surfaces of the gate pattern and may extend to a side surface. In an embodiment, the dielectric layer may include a high-k dielectric such as aluminum oxide. A plurality of gate patterns may be stacked to be spaced apart from each other by an insulating layer in a vertical direction (e.g., Z direction).

[0138] In an embodiment, the channel structure 217 may include a channel semiconductor layer, a vertical insulating layer formed inwardly from the channel semiconductor layer, and a gate dielectric structure disposed between the channel semiconductor layer and the stack structure 215. In an embodiment, the gate dielectric structure may include a tunnel dielectric layer, an information storage layer, and a blocking dielectric layer.

[0139] In an embodiment, the tunnel dielectric layer may include silicon oxide and / or silicon oxide doped with impurities. The blocking dielectric layer may include silicon oxide and / or a high-k dielectric. The information storage layer may include a material for storing information, and may include silicon nitride, for example.

[0140] Furthermore, in an embodiment, second circuit 12 may include contact plug 218 formed on conductive layers 212 and 214, pad 220 formed on channel structure 217 and contact plug 218, and via plug 222 formed on pad 220. Conductive layers 212 and 214, contact plug 218, pad 220, and via plug 222 may be insulated by second circuit insulation layer 216.

[0141] The intermediate wiring layer 200c may be formed on the second circuit layer 200b (e.g., formed directly thereon in the Z direction). In an embodiment, as described above, the intermediate wiring layer 200c may include an intermediate wiring insulation layer 228, an intermediate wiring pattern 224, and an intermediate wiring via 226. The intermediate wiring pattern 224 may be electrically connected to the via plug 222 of the second circuit 12.

[0142] The second final wiring layer 200d may be formed on the intermediate wiring layer 200c (e.g., formed directly thereon in the Z direction). In an embodiment, as described above, the second final wiring layer 200d may include a second final wiring pattern 236, a second passivation layer 234, and a second final wiring via 232. The second final wiring pattern 236 may be electrically connected to the intermediate wiring pattern 224 through the second final wiring via 232.

[0143] The second bonding wiring layer 200e may be formed on the second final wiring layer 200d (e.g., formed directly thereon in the Z direction). As described above, the second bonding wiring layer 200e may include a second interlayer insulating layer 40, a second bonding insulating layer 44, and a second bonding electrode 52-4. The second bonding electrode 52-4 may include a second via electrode 52b, a second internal electrode 52c, and a second upper electrode 52d.

[0144] The upper surface of each of the second bonding electrode 52-4 and the second bonding insulating layer 44 may be a second bonding surface b2. The second bonding surface b2 may be a second flat bonding surface. By such a manufacturing process, it is possible to manufacture Fig.14 The second semiconductor chip 200 is provided.

[0145] refer to Fig.16 , can be prepared Fig.14 The first semiconductor chip 100 is shown. Fig.16 In, with Fig.14 Like reference numerals denote like elements. Fig.16 In order to facilitate the description, the Figure 1 and Figure 2 The same or similar description.

[0146] The first semiconductor chip 100 may include a first substrate layer 100a. The first substrate layer 100a may include a first substrate 60. A first circuit layer 100b may be formed on the first substrate layer 100a (e.g., directly thereon in the Z direction). In an embodiment, the first circuit layer 100b may include a first circuit 62 and a first circuit insulation layer 63 that insulates the first circuit 62. The first circuit 62 may be a peripheral circuit. In an embodiment, the peripheral circuit may include a transistor TR and a contact plug 112.

[0147] The first final wiring layer 100c may be formed on the first circuit layer 100b (eg, formed directly thereon in the Z direction). In an embodiment, as described above, the first final wiring layer 100c may include the first passivation layer 64 and the first final wiring pattern 65 - 1 .

[0148] The first bonding wiring layer 100d may be formed on the first final wiring layer 100c (e.g., formed directly thereon in the Z direction). In an embodiment, as described above, the first bonding wiring layer 100d may include a first interlayer insulating layer 68, a first bonding insulating layer 70, and a first bonding electrode 72-4. The first bonding electrode 72-4 may include a first via electrode 72b, a first internal electrode 72c, and a first upper electrode 72d. The first via electrode 72b and the first internal electrode 72c may include nanotwinned copper. The first upper electrode 72d formed on the first internal electrode 72c may include fine-grained copper.

[0149] An upper surface of each of the first bonding electrode 72 - 4 and the first bonding insulating layer 70 may be a first bonding surface b1. The first bonding surface b1 may be a first flat bonding surface. Through such a manufacturing process, the first semiconductor chip 100 may be manufactured.

[0150] Then, the above-made Fig.15The second semiconductor chip 200 can be reversed and disposed on the first semiconductor chip 100. The second bonding electrode 52-4 and the second bonding insulating layer 44 of the second bonding surface b2 can be hybrid-bonded to the first bonding electrode 72-4 and the first bonding insulating layer 70 of the first bonding surface b1, respectively. In this embodiment, in the bonding interface formed by the first upper electrode 72d of the first bonding surface b1 and the second upper electrode 52d of the second bonding surface b2, both of which have fine-grained copper, the mutual diffusion between copper and copper can be increased. Since the first bonding electrode 72 and the second bonding electrode 52 use a dual material including fine-grained copper and nano-twinned copper, the semiconductor chip structure 2 can improve the bonding reliability of bonding the first semiconductor chip 100 to the second semiconductor chip 200.

[0151] Fig.17 is a block diagram schematically showing a memory card 700 to which a semiconductor package including a semiconductor chip structure according to an embodiment is applied.

[0152] Detailed reference Fig.17 , a controller 710 and a memory 720 may be provided in the memory card 700 to exchange electrical signals. For example, when the controller 710 issues an instruction, the memory 720 may transmit data. In an embodiment, the controller 710 and / or the memory 720 may include a semiconductor package to which a semiconductor chip structure according to one of the described embodiments is applied. Examples of semiconductor packages may be as described above with reference to Fig.14 and Fig.15 In an embodiment, the memory 720 may include a memory array or a memory array bank.

[0153] In an embodiment, the memory card 700 may be used for various cards such as a memory stick card, a smart media card (SM), a secure digital (SD), and a mini secure digital card (mini SD), or a storage device such as a multimedia card (MMC).

[0154] Fig.18 is a block diagram schematically illustrating an electronic system 800 to which a semiconductor package including a semiconductor chip structure according to an embodiment is applied.

[0155] Detailed reference Fig.18 In an embodiment, the electronic system 800 may include a controller 810, an input / output (I / O) device 820, a memory 830, and an interface 840. In an embodiment, the electronic system 800 may be a mobile system or a system for transmitting or receiving information. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card. However, embodiments of the inventive concept are not necessarily limited thereto.

[0156] The controller 810 may execute a program and may control the electronic system 800. In an embodiment, the controller 810 may be, for example, a microprocessor, a digital signal processor, a microcontroller, or a similar device. However, the embodiments of the inventive concept are not necessarily limited thereto. The I / O device 820 may be used to input or output data of the electronic system 800.

[0157] The electronic system 800 can be connected (e.g., electrically connected) to an external device (e.g., a personal computer or a network) by using an I / O device 820, and can exchange data with the external device. The I / O device 820 can be, for example, a keypad, a keyboard, or a display. The memory 830 can store code and / or data for the operation of the controller 810, and / or can store data obtained by processing by the controller 810.

[0158] The controller 810 and / or the memory 830 may include a semiconductor package to which the semiconductor chip structure according to one of the described embodiments is applied. Examples of the semiconductor package may be as described above with reference to Fig.14 and Fig.15 The interface 840 may be a data transmission path between the electronic system 800 and another external device. The controller 810 , the I / O device 820 , the memory 830 , and the interface 840 may communicate with each other through the bus 850 .

[0159] For example, in an embodiment, the electronic system 800 may be used in a mobile phone, an MP3 player, a navigation device, a portable multimedia player (PMP), a solid state drive (SSD), or a home appliance. However, embodiments of the inventive concept are not necessarily limited thereto.

[0160] Non-limiting embodiments have been described above in the drawings and the specification. The embodiments have been described using the terms described herein, but this is only used to describe the inventive concept and is not used to limit the meaning or scope of the inventive concept defined in the appended claims. Therefore, it can be understood by those of ordinary skill in the art that the embodiments of the inventive concept may include various modifications and other equivalent forms of the described embodiments.

[0161] While the inventive concept has been particularly shown and described with reference to non-limiting embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. A semiconductor chip structure, comprising a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip, wherein the first semiconductor chip comprises a first chip region and a first scribe street region, and the second semiconductor chip comprises a second chip region and a second scribe street region corresponding to the first chip region and the first scribe street region, respectively. in, The first semiconductor chip comprises: a first final wiring layer including a first final wiring pattern and a first passivation layer insulating the first final wiring pattern; and a first bonding wiring layer provided on the first final wiring layer, the first bonding wiring layer including a first bonding insulating layer and a first bonding electrode provided in the first bonding insulating layer, The second semiconductor chip comprises: a second final wiring layer including at least one second final wiring pattern, a polishing stop pattern disposed on the at least one second final wiring pattern, and a second passivation layer insulating the at least one second final wiring pattern and the polishing stop pattern; and a second bonding wiring layer provided on the second final wiring layer, the second bonding wiring layer including a second bonding insulating layer and a second bonding electrode provided in the second bonding insulating layer and the polishing stop pattern, wherein the first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are mixedly bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer, respectively, and At least a portion of a bonding interface between the first bonding insulating layer and the first bonding electrode of the first bonding wiring layer of the hybrid bonding and the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer includes fine-grained copper, and in the remaining portion of the bonding interface, an interior of each of the first bonding electrode and the second bonding electrode includes nano-twinned copper.

2. The semiconductor chip structure according to claim 1, wherein: The thickness of the fine-grained copper is in the range of 1 μm to 1.5 μm with respect to the bonding interface.

3. The semiconductor chip structure according to claim 1, wherein: The grain size of the fine-grained copper is less than or equal to 300 nm.

4. The semiconductor chip structure according to claim 1, wherein: The fine copper particles are not provided at the edge of the uppermost surface of the first bonding electrode and at the edge of the uppermost surface of the second bonding electrode.

5. The semiconductor chip structure according to claim 1, wherein: A surface of each of the first final wiring pattern and the first passivation layer is a first flat surface having no step height between the first chip region and the first scribe street region; and A surface of each of the second final wiring pattern and the second passivation layer is a second flat surface having no step height between the second chip region and the second scribe street region.

6. The semiconductor chip structure according to claim 1, wherein: The first bonding insulating layer and the second bonding insulating layer include at least one compound selected from silicon carbide nitride and silicon oxide.

7. The semiconductor chip structure according to claim 1, wherein: The first bonding electrode is electrically connected to the first final wiring pattern; and The second bonding electrode is electrically connected to the at least one second final wiring pattern.

8. The semiconductor chip structure according to claim 1, wherein: An etch stop layer is disposed on the first final wiring pattern and the first passivation layer.

9. The semiconductor chip structure according to claim 1, wherein: the first final wiring pattern and the first bonding electrode respectively include metal materials different from each other; and The at least one second final wiring pattern and the second bonding electrode respectively include metal materials different from each other.

10. The semiconductor chip structure according to claim 1, wherein: A width of the first bonding electrode and a width of the second bonding electrode are different from each other.

11. A semiconductor chip structure, comprising a first semiconductor chip and a second semiconductor chip bonded to the first semiconductor chip, wherein the first semiconductor chip comprises a first chip region and a first dicing street region, and the second semiconductor chip comprises a second chip region and a second dicing street region, in, The first semiconductor chip comprises: A first circuit layer, wherein the first circuit layer is disposed in the first chip region and the first scribe line region; a first final wiring layer disposed on the first circuit layer, the first final wiring layer including a first final wiring pattern and a first passivation layer insulating the first final wiring pattern; and a first bonding wiring layer, the first bonding wiring layer being disposed on the first final wiring layer, the first bonding wiring layer comprising a first interlayer insulating layer, a first bonding insulating layer disposed on the first interlayer insulating layer, and a first bonding electrode disposed in the first interlayer insulating layer and the first bonding insulating layer, The second semiconductor chip comprises: a second circuit layer, wherein the second circuit layer is disposed in the second chip region and the second scribe line region; a second final wiring layer disposed on the second circuit layer, the second final wiring layer including at least one second final wiring pattern, a polishing stop pattern disposed on the at least one second final wiring pattern, and a second passivation layer insulating the at least one second final wiring pattern from the polishing stop pattern; and a second bonding wiring layer, the second bonding wiring layer being disposed on the second final wiring layer, the second bonding wiring layer comprising a second interlayer insulating layer, a second bonding insulating layer disposed on the second interlayer insulating layer, and a second bonding electrode disposed in the second bonding insulating layer, the second interlayer insulating layer, and the polishing stop pattern, wherein The first bonding electrode includes a first portion whose uppermost surface is plated with fine-grained copper and nano-twinned copper surrounding a side surface of the first portion and filling an interior of the first bonding electrode. The second bonding electrode includes a second portion having an uppermost surface plated with fine-grained copper and nano-twinned copper surrounding a side surface of the second portion and filling an interior of the second bonding electrode, and The first bonding insulating layer and the first bonding electrode of the first bonding wiring layer are mixedly bonded to the second bonding insulating layer and the second bonding electrode of the second bonding wiring layer, respectively.

12. The semiconductor chip structure according to claim 11, wherein: At least a portion of the first portion is hybridly joined to at least a portion of the second portion.

13. The semiconductor chip structure according to claim 11, wherein: The fine-grained copper is formed to have a thickness ranging from 1 μm to 1.5 μm with respect to the uppermost surface of the first bonding electrode or the second bonding electrode.

14. The semiconductor chip structure according to claim 11, wherein: The grain size of the fine-grained copper is less than or equal to 300 nm.

15. The semiconductor chip structure according to claim 11, wherein: The first circuit layer includes peripheral circuits, and the second circuit layer includes memory cells.

16. The semiconductor chip structure according to claim 11, wherein: The first bonding electrode includes a first planar electrode and a plurality of first via electrodes electrically connected to the first planar electrode; and Each of the plurality of first via electrodes is electrically connected to the first final wiring pattern.

17. The semiconductor chip structure according to claim 11, wherein: A width of the first bonding electrode and a width of the second bonding electrode are different from each other.

18. The semiconductor chip structure according to claim 11, The semiconductor chip structure further includes an intermediate wiring pattern electrically connected to the second final wiring pattern and an intermediate wiring insulating layer disposed on the second circuit layer, the intermediate wiring insulating layer insulating the intermediate wiring pattern.

19. A semiconductor chip structure, comprising a plurality of semiconductor chips, each of the semiconductor chips comprising a chip region and a dicing street region, in, Each of the plurality of semiconductor chips comprises: A circuit layer, the circuit layer is arranged in the chip area and the scribe line area; a final wiring layer disposed on the circuit layer, the final wiring layer including a final wiring pattern and a passivation layer insulating the final wiring pattern; and a bonding wiring layer provided on the final wiring layer, the bonding wiring layer including an interlayer insulating layer, a bonding insulating layer provided on the interlayer insulating layer, and bonding electrodes provided in the interlayer insulating layer and the bonding insulating layer, and The bonding electrode is filled with nanotwinned copper, and fine-grained copper having a grain size of less than or equal to 300 nm and a thickness ranging from 1 μm to 1.5 μm is provided in at least a portion of an uppermost surface of the bonding electrode.

20. The semiconductor chip structure according to claim 19, wherein: The nano-twinned copper is disposed in an edge of an uppermost surface of the bonding electrode.

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