Semiconductor device including storage node and method of manufacturing the same

Abstract

The invention relates to a semiconductor device including a storage node and a method of manufacturing the semiconductor device. A method of manufacturing a semiconductor device including an array of conductive patterns is presented. The semiconductor device may include a first conductive pattern disposed over an insulating layer over a semiconductor substrate, a second conductive pattern disposed to extend longitudinally at a side edge of the first conductive pattern, and a third conductive pattern connected to the first conductive pattern and the second conductive pattern. The third conductive pattern may be a storage node of the capacitor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0102841 filed on August 7, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to integrated circuit devices, and in particular, to a semiconductor device including a storage node and a method of manufacturing the semiconductor device. Background Art

[0004] Integrated circuit devices can be integrated in semiconductor substrates to form semiconductor devices. As semiconductor devices have been miniaturized, the size, width or critical dimension of each conductive pattern in the conductive patterns constituting the integrated circuit device is reduced, and the space between the conductive patterns is rapidly reduced. Semiconductor devices may require capacitor elements as their data storage elements. As the width or critical dimension of each storage node in the storage nodes of the capacitor is reduced, the height of the storage node is increased to ensure capacitance. As a result, defects in which some storage nodes are lost in the storage nodes may occur at the edge portion of the area where the storage nodes have been arranged. Summary of the invention

[0005] The present invention overcomes the aforementioned limitations of the prior art.

[0006] According to a first aspect of the present invention, a semiconductor device is provided. The semiconductor device may include: a first conductive pattern disposed above an insulating layer above a semiconductor substrate, a second conductive pattern disposed above the insulating layer and extending longitudinally at a side of the first conductive pattern, and a third conductive pattern connected to the first conductive pattern and the second conductive pattern.

[0007] According to another aspect of the present invention, a method for manufacturing a semiconductor device of the present invention is provided. The method may include: forming a first insulating layer above a semiconductor substrate; forming a first conductive pattern and a second conductive pattern simultaneously above the first insulating layer, the second conductive pattern extending longitudinally at the side of the first conductive pattern; and forming a third conductive pattern connected to the first conductive pattern and the second conductive pattern.

[0008] These and other aspects, embodiments, features and advantages of the present invention will become apparent from the following detailed description of specific embodiments of the invention taken in conjunction with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 15is a simplified schematic diagram illustrating a semiconductor device and a method of manufacturing the semiconductor device according to one embodiment of the present invention.

[0010] Fig.16 is a simplified schematic plan view illustrating an array of conductive patterns of a semiconductor device according to an embodiment of the present invention.

[0011] Fig.17 is a simplified schematic plan view illustrating an array of conductive patterns of a semiconductor device according to an embodiment of the present invention.

[0012] Fig.18 is a simplified schematic plan view illustrating an array of conductive patterns of a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Any terms not specifically defined in the present specification may be interpreted according to their generally recognized or ordinary meanings understood by those skilled in the art.

[0014] Terms such as “first,” “second,” “third,” “fourth,” “fifth,” etc. are used to distinguish between elements and are not used to limit the elements themselves or to imply a specific order.

[0015] Embodiments of the present invention may be applied to various technical fields using semiconductors, including technical fields for implementing integrated circuit devices such as DRAM, PcRAM, and / or ReRAM devices. In addition, embodiments of the present invention may also be applied to technical fields for implementing memory devices for storing data or logic devices for performing logic operations. In addition, embodiments of the present invention may be applied to technical fields for implementing various products that require conductive patterns with fine sizes.

[0016] Note that in the various drawings, the same reference numerals denote the same components. Therefore, the same reference numerals or similar reference numerals may be described with reference to other drawings, even though they are not mentioned or described in the corresponding drawings. In addition, although reference numerals are not shown in the drawings, they may be described with reference to other drawings.

[0017] Figures 1 to 15 is a simplified schematic diagram illustrating a semiconductor device and a method of manufacturing the semiconductor device according to one embodiment.

[0018] Reference now Figure 1 , one lower conductive contact 310 or a plurality of lower conductive contacts 310 may be formed on the semiconductor substrate 100 . Figure 1 is along Figure 5. The semiconductor substrate 100 may include a cell region 100C and a peripheral region 100P. In a DRAM semiconductor device, the cell region 100C may indicate a cell array, and the peripheral region 100P may indicate a core region. The peripheral region 100P may be an area outside the cell region 100C or an area surrounding the cell region 100C. The cell region 100C of the semiconductor substrate 100 may include a first region 100R and a second region 100E. The second region 100E may be located outside the first region 100R and / or may surround the first region 100R. The second region 100E may be located at an edge region of the cell region 100C. The second region 100E may form a boundary between the first region 100R and the peripheral region 100P. A memory device or a memory element may be integrated in the cell region 100C. A circuit controlling the operation of the memory device may be provided in the peripheral region 100P. The memory device or the memory element may include a transistor and / or a capacitor. The control circuit may include a sense amplifier or a sub word line driver (SWD).

[0019] An isolation layer 150 may be formed in the semiconductor substrate 100, and the isolation layer 150 defines the active region 100A. The isolation layer 150 may include a field oxide layer. The isolation layer 150 may include a dielectric material (also referred to as an insulating material), such as silicon oxide (SiO2) or silicon nitride (Si3N4). The semiconductor substrate 100 may include a semiconductor material such as silicon (Si). The silicon substrate may further include a semiconductor material such as germanium (Ge). The semiconductor substrate 100 may include a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP). The semiconductor substrate 100 may have a wafer form.

[0020] Impurities may be doped into the active region 100A of the semiconductor substrate 100. The impurity-doped region may function as a source region or a drain region of a transistor.

[0021] A lower insulating layer 210 may be formed over the semiconductor substrate 100. A lower conductive contact 310 may be formed that substantially penetrates the lower insulating layer 210. The lower insulating layer 210 may cover and insulate the semiconductor substrate 100. The lower insulating layer 210 may include an insulating material. The lower insulating layer 210 may include a dielectric material such as silicon oxide (SiO2). One opening or a plurality of openings may be formed that penetrate the lower insulating layer 210. The one opening or each of the plurality of openings may be a through hole that exposes a portion of the semiconductor substrate 100 or a portion of the active region 100A of the semiconductor substrate 100.

[0022] A conductive layer filling the one or more openings may be formed on the lower insulating layer 210. The conductive layer may be separated into one lower conductive contact 310 or into multiple lower conductive contacts 310. The conductive layer or the lower conductive contact 310 may include a conductive material, such as polysilicon (polysilicon layer) into which impurities have been doped. The conductive layer may be etched back or subjected to chemical mechanical polishing (CMP) so that the surface of the lower insulating layer 210 is exposed. The lower insulating layer 210 may electrically isolate or insulate the lower conductive contact 310. Before forming the lower insulating layer 210, a gate or word line of a transistor may be further formed above the semiconductor substrate 100.

[0023] refer to Figure 2 , a lower conductive pattern 350 may be formed over the lower insulating layer 210. A conductive layer may be formed over the lower insulating layer 210. The conductive layer may be separated or patterned into the lower conductive patterns 350. By selectively removing some portions of the conductive layer, the conductive layer may be separated into the lower conductive patterns 350. One of the lower conductive patterns 350 may be formed to be connected to the lower conductive contact 310. The lower conductive contact 310 may electrically connect the lower conductive pattern 350 to the active region 100A of the semiconductor substrate 100.

[0024] One lower conductive pattern 350 or multiple lower conductive patterns 350 may form a bit line pattern. One lower conductive contact 310 or multiple lower conductive contacts 310 may form a bit line contact or a bit line plug. One lower conductive pattern 350 or each of the multiple lower conductive patterns 350 may include a metal layer, such as, for example, tungsten (W). One lower conductive pattern 350 or each of the multiple lower conductive patterns 350 may further include a barrier metal layer, such as titanium nitride (TiN), tungsten nitride (WN), titanium tungsten nitride (TiWN) or tungsten silicon nitride (WSiN), or a composite layer of titanium nitride (TiN), tungsten nitride (WN), titanium tungsten nitride (TiWN) or tungsten silicon nitride (WSiN).

[0025] refer to Figure 3 , a first insulating layer 230 covering the lower conductive pattern 350 may be formed over the lower insulating layer 210. The first insulating layer 230 may include an insulating material. The first insulating layer 230 may include a dielectric material such as silicon oxide (SiO2). An opening 230H or a plurality of openings 230H may be formed penetrating the first insulating layer 230 and the lower insulating layer 210. The one opening 230H or each of the plurality of openings 230H may be formed as a through hole exposing a portion of the semiconductor substrate 100 or exposing some of the active regions 100A of the semiconductor substrate 100.

[0026] refer to Figure 4 and Figure 5 , a conductive contact part 400 filling the opening 230H of the first insulating layer 230 may be formed. Figure 4 The diagram shows Figure 5 . A conductive layer filling the opening 230H may be formed on the first insulating layer 230. The conductive layer may be separated or patterned into conductive contacts 400. The conductive layer may be etched back or subjected to CMP so that the surface of the first insulating layer 230 is exposed. The first insulating layer 230 may electrically isolate or insulate the conductive contacts 400. The conductive contacts 400 may penetrate the first insulating layer 230 and the lower insulating layer 210 to electrically connect each conductive contact 400 to a corresponding one of the active regions 100A of the semiconductor substrate 100. The conductive contacts 400 may have a column form or a plug form. The conductive contacts 400 may each include: polysilicon into which impurities have been doped, or a conductive material, such as, for example, tungsten (W). The conductive contacts 400 may be formed in a pattern so that each of the conductive contacts 400 passes between a corresponding pair of adjacent conductive patterns 350.

[0027] like Figure 5 As presented in , the conductive contacts 400 may be formed in a pattern such that the conductive contacts 400 are spaced apart from each other and arranged at predetermined intervals. The conductive contacts 400 may be disposed in an array within a cell region 100C of the semiconductor substrate 100. The lower conductive contacts 310 may be disposed between the conductive contacts 400. The conductive contacts 400 may be divided into first conductive contacts 400R and second conductive contacts 400E. The first conductive contacts 400R (i.e., some of the conductive contacts 400) may be disposed within the first region 100R of the semiconductor substrate 100. The second conductive contacts 400E (i.e., some other of the conductive contacts 400) may be disposed within the second region 100E of the semiconductor substrate 100. The second conductive contacts 400E may be aligned to surround the first conductive contacts 400R. In Figure 5 In the embodiment, an example has been presented in which the second conductive contacts 400E have been arranged to form a first column along the second region 100E of the semiconductor substrate 100. However, the second conductive contacts 400E may be aligned into a plurality of columns, such as including a first column and a second column or a first column, a second column, and a third column.

[0028] refer to Figure 6 and Figure 7, a plurality of first conductive patterns 500R and second conductive patterns 500E may be formed over the first insulating layer 230. The first conductive patterns 500R may be patterned into patterns each having features different from the features of the second conductive patterns 500E. A conductive layer may be formed over the first insulating layer 230, and then some portions of the conductive layer may be removed by selectively etching the portions to form the first conductive patterns 500R and the second conductive patterns 500E. The first conductive patterns 500R and the second conductive patterns 500E may be formed simultaneously by this patterning process. The first conductive patterns 500R and the second conductive patterns 500E may each include a metal material, such as, for example, tungsten (W). The first conductive patterns 500R and the second conductive patterns 500E may each further include a barrier layer. The barrier layer may be made of any suitable material, including, for example, titanium (Ti), tungsten nitride (WN), or tungsten silicon nitride (WSiN). The barrier layer may block the diffusion or movement of metal ions.

[0029] The first conductive pattern 500R may be arranged in the first region 100R of the semiconductor substrate 100 while being spaced apart from each other at a predetermined interval. The first conductive pattern 500R may be formed to have island features, respectively, the island features being spaced apart from each other and arranged at a predetermined interval. The second conductive pattern 500E may be arranged to extend longitudinally on the side of the first conductive pattern 500R above the first insulating layer 230. The second conductive pattern 500E may have a linear shape feature or a strip shape extending longitudinally along the second region 100E of the semiconductor substrate 100. The linear shape feature of the second conductive pattern 500E may be formed to laterally face the island feature of the first conductive pattern 500R.

[0030] The second conductive pattern 500E may have a greater width than the first conductive pattern 500R. The width W2 of the second conductive pattern 500E may be greater than the width W1 of the first conductive pattern 500R. The second conductive pattern 500E may have an outer shape feature extending to surround the first conductive pattern 500R or to surround the outside of the array of the first conductive pattern 500R. The second conductive pattern 500E may surround the first conductive pattern 500R or to surround the outside of the array of the first conductive pattern 500R with an annular outer shape feature.

[0031] The conductive contact 400 may be coupled or connected to the first conductive pattern 500R and the second conductive pattern 500E. The conductive contact 400 may penetrate the first insulating layer 230, and may electrically connect the first conductive pattern 500R and the second conductive pattern 500E to the active region 100A of the semiconductor substrate 100. The first conductive contact 400R (i.e., some of the conductive contact 400) may be connected to the first conductive pattern 500R, respectively. The first conductive pattern 500R may be formed to overlap with the first conductive contact 400R, respectively, so that the first conductive contact 400R and the first conductive pattern 500R are connected in a one-to-one manner. The second conductive contact 400E (i.e., some of the other conductive contact 400) may be connected to the second conductive pattern 500E. A plurality of second conductive contacts 400E may be connected to one second conductive pattern 500E.

[0032] The first conductive pattern 500R and the second conductive pattern 500E may have widths W1 and W2, respectively. Each of the widths W1 and W2 is greater than the diameter or width W3 of the conductive contact 400. Therefore, even in the case where the first conductive pattern 500R and the second conductive pattern 500E are deviated from their original positions (at which the first conductive pattern 500R and the second conductive pattern 500E are in contact with the conductive contact 400), the possibility that the first conductive pattern 500R and the second conductive pattern 500E can be connected to the conductive contact 400 can be increased.

[0033] refer to Figure 8 , an etch stop layer 250 covering the first conductive pattern 500R and the second conductive pattern 500E may be formed. The etch stop layer 250 may be formed of a dielectric material or an insulating material. For example, the etch stop layer 250 may include silicon nitride (Si3N4). Before forming the etch stop layer 250, a second insulating layer 240 may be further formed over the first insulating layer 230 to isolate the first conductive pattern 500R and the second conductive pattern 500E from each other. The second insulating layer 240 may be formed of a dielectric material layer or an insulating material layer different from the dielectric material or insulating material of the etch stop layer 250. The second insulating layer 240 may include a dielectric material layer or an insulating material layer that may have an etching selectivity because the second insulating layer 240 has an etching rate different from the etching rate of the etch stop layer 250. For example, the second insulating layer 240 may be formed of silicon oxide (SiO2).

[0034] A first sacrificial layer 260 may be formed over the etch stop layer 250. The first sacrificial layer 260 may include a dielectric material layer or an insulating material layer different from that of the etch stop layer 250. The first sacrificial layer 260 may include a dielectric material layer or an insulating material layer that may have an etch selectivity because the first sacrificial layer 260 has an etch rate different from that of the etch stop layer 250. The first sacrificial layer 260 may include silicon oxide, such as, for example, borophosphosilicate glass (BPSG).

[0035] A first floating supporting layer 270 may be formed over the first sacrificial layer 260. The first floating supporting layer 270 may include a dielectric material layer or an insulating material layer different from that of the first sacrificial layer 260. The first floating supporting layer 270 may include a dielectric material layer or an insulating material layer that may have an etching selectivity because the first floating supporting layer 270 has an etching rate different from that of the first sacrificial layer 260. The first floating supporting layer 270 may include silicon nitride (Si3N4). The first floating supporting layer 270 may be formed of a layer having a smaller thickness than that of the first sacrificial layer 260.

[0036] A second sacrificial layer 280 may be formed over the first floating supporting layer 270. The second sacrificial layer 280 may include a dielectric material layer or an insulating material layer different from that of the first floating supporting layer 270. The second sacrificial layer 280 may include a dielectric material layer or an insulating material layer that may have an etching selectivity because the second sacrificial layer 280 has an etching rate different from that of the first floating supporting layer 270. The second sacrificial layer 280 may include a silicon oxide layer, such as, for example, a tetraethyl orthosilicate (TEOS) layer.

[0037] A second floating supporting layer 290 may be formed over the second sacrificial layer 280. The second floating supporting layer 290 may include a dielectric material layer or an insulating material layer different from that of the second sacrificial layer 280. The second floating supporting layer 290 may include a dielectric material layer or an insulating material layer that may have an etching selectivity because the second floating supporting layer 290 has an etching rate different from that of the second sacrificial layer 280. The second floating supporting layer 290 may include silicon nitride (Si3N4). The second floating supporting layer 290 may be formed of a layer having a smaller thickness than that of the second sacrificial layer 280.

[0038] The second sacrificial layer 280 and the second floating supporting layer 290 may be omitted. An additional sacrificial layer and an additional floating supporting layer may be further formed over the second floating supporting layer 290.

[0039] refer to Fig. 9, openings 260H may be formed that penetrate the second floating support layer 290, the second sacrificial layer 280, the first floating support layer 270, the first sacrificial layer 260, and the etch stop layer 250. Some portions of the second floating support layer 290, the second sacrificial layer 280, the first floating support layer 270, the first sacrificial layer 260, and the etch stop layer 250 may be selectively etched or removed by performing a photolithography process and a selective etching process. The openings 260H may each be formed in the form of a through hole that penetrates the second floating support layer 290, the second sacrificial layer 280, the first floating support layer 270, the first sacrificial layer 260, and the etch stop layer 250. Some of the openings 260H may be formed to be aligned with the first conductive pattern 500R, and some other of the openings 260H may be formed to be aligned with the second conductive pattern 500E. Some of the openings 260H may be formed to expose the first conductive patterns 500R, respectively, and some other of the openings 260H may be formed to expose some portions of the second conductive pattern 500E.

[0040] refer to Fig.10 and Fig.11 , a third conductive pattern 600 connected to the first conductive pattern 500R and the second conductive pattern 500E may be formed. A conductive layer may be formed by filling the opening 260H, the conductive layer being connected or bonded to some portions of the first conductive pattern 500R and some portions of the second conductive pattern 500E exposed to the opening 260H. By removing some portions of the conductive layer, the conductive layer may be separated into a third conductive pattern 600. The third conductive patterns 600 may each be separated into a form of filling each opening 260H in the opening 260H. The third conductive pattern 600 may be formed to have a conductive column feature that fills each opening 260H in the opening 260H. The third conductive pattern 600 may be formed to have a conductive column feature that extends along the contour of the opening 260H and has a concave form. The third conductive pattern 600 may include a layer including a metal such as titanium nitride (TiN). The third conductive pattern 600 may further include a conductive polysilicon layer formed above the titanium nitride (TiN). The third conductive pattern 600 may be formed in the form of an island feature or as an array of island features.

[0041] The third conductive pattern 600 may include a fourth conductive pattern 600R and a fifth conductive pattern 600E. The fourth conductive pattern 600R (i.e., some of the third conductive patterns 600 in the third conductive pattern 600) may be connected to the first conductive pattern 500R, respectively. The fifth conductive pattern 600E (i.e., some other third conductive patterns 600 in the third conductive pattern 600) may be connected to the second conductive pattern 500E. A plurality of fifth conductive patterns 600E may be connected to one second conductive pattern 500E. The fifth conductive pattern 600E may be arranged as an array around the fourth conductive pattern 600R or the fourth conductive pattern 600R. The fifth conductive pattern 600E may be formed to be arranged in the direction in which the second conductive pattern 500E extends.

[0042] The width W5 of the fifth conductive pattern 600E may be formed to be greater than the width W4 of the fourth conductive pattern 600R. The width W5 of the fifth conductive pattern 600E may be less than the width W2 of the second conductive pattern 500E taken along the line A-A'. The width W4 of the fourth conductive pattern 600R may be less than the width W1 of the first conductive pattern 500R. Therefore, since the width W1 of the first conductive pattern 500R is formed to be greater than the width W4 of the fourth conductive pattern 600R, the possibility that the fourth conductive pattern 600R can overlap and align with the first conductive pattern 500R can be increased.

[0043] Since the width W2 of the second conductive pattern 500E is formed to be greater than the width W5 of the fifth conductive pattern 600E, the possibility that the fifth conductive pattern 600E can be connected to the second conductive pattern 500E while overlapping with the second conductive pattern 500E without deviating from the second conductive pattern 500E can be increased. In addition, the possibility that the fifth conductive pattern 600E deviates from the second conductive pattern 500E and the fifth conductive pattern 600E is not connected to the second conductive pattern 500E can be reduced. Since the second conductive pattern 500E is formed to have a linear shape feature or an annular shape feature, the possibility that the fifth conductive pattern 600E deviates from its position (at which the fifth conductive pattern 600E is formed) can be reduced. Therefore, since the second conductive pattern 500E is formed to have a relatively large width W2 and also has a linear shape feature or an annular shape feature as described above, the fifth conductive pattern 600E can be more stably connected to the second conductive pattern 500E.

[0044] The third conductive pattern 600 may be formed to have a relatively large height H greater than the width W4 or W5. Since the first sacrificial layer 260 and / or the second sacrificial layer 280 are formed to have a relatively large thickness greater than the thickness of each of the first conductive pattern 500R and the second conductive pattern 500E, the third conductive pattern 600 may be formed to have a relatively large height H greater than the width W4 or W5.

[0045] refer to Fig.12 , an opening 290H or a plurality of openings 290H may be formed by selectively removing a portion or portions of the second floating supporting layer 290 , the opening 290H or the plurality of openings 290H exposing a portion or portions of the second sacrificial layer 280 thereunder.

[0046] refer to Fig.12 and Fig.13 , the second sacrificial layer 280 may be selectively removed through the opening 290H of the second floating supporting layer 290. As the second sacrificial layer 280 is removed, some portions of the side surfaces of the third conductive pattern 600 may be exposed. By supplying an etchant or chemical to the second sacrificial layer 280 through the opening 290H of the second floating supporting layer 290, the second sacrificial layer 280 may be removed by the etchant or chemical for etching.

[0047] refer to Fig.13 and Fig.14 , one opening 270H or a plurality of openings 270H may be formed by selectively removing a portion or portions of the first floating supporting layer 270 exposed as the second sacrificial layer 280 is removed through one opening 290H or a plurality of openings 290H of the second floating supporting layer 290, and the one opening 270H or a plurality of openings 270H may expose a portion or portions of the first sacrificial layer 260 thereunder. The first sacrificial layer 260 may be selectively removed through the opening 270H of the first floating supporting layer 270. As the first sacrificial layer 260 is removed, other portions of the side of the third conductive pattern 600 may be exposed. By providing an etchant or chemical to the first sacrificial layer 260 through the opening 270H of the first floating supporting layer 270, the first sacrificial layer 260 may be removed by the etchant or chemical for etching.

[0048] The remaining portion of the first floating supporting layer 270 and the remaining portion of the second floating supporting layer 290 may each function as a support member that supports the third conductive pattern 600 by holding the third conductive pattern 600 so that the third conductive pattern 600 does not collapse. The remaining portion of the first floating supporting layer 270 and the remaining portion of the second floating supporting layer 290 may each be represented as a nitride floating capacitor (NFC) structure.

[0049] refer to Fig.15 , a capacitor layer 710 covering the third conductive pattern 600 may be formed. The capacitor layer 710 may extend to cover the surface of the third conductive pattern 600, which is formed as the first sacrificial layer and the second sacrificial layer ( Fig.12260 and 280) have been exposed, and the capacitor layer 710 may extend to cover the first floating support layer 270 and the second floating support layer 290. The capacitor layer 710 may include a dielectric material constituting a capacitor. The capacitor layer 710 may include a high dielectric material layer having a high dielectric constant (k). The capacitor layer 710 may include zirconium oxide (ZrO2), aluminum oxide (Al2O3), or tantalum oxide (Ta2O5).

[0050] A plate node layer 720 may be formed covering the capacitor electrical layer 710. The plate node layer 720 may include various electrode materials. The plate node layer 720 may include a titanium nitride (TiN) layer. The plate node layer 720 may further include a conductive silicon layer, such as, for example, a silicon germanium (SiGe) layer covering the titanium nitride layer.

[0051] A capacitor structure including a third conductive pattern 600, a capacitor layer 710, and a plate node layer 720 may be constructed. The third conductive pattern 600 may be used as a storage node of the capacitor structure. The conductive contacts 400 electrically connected to the third conductive pattern 600 may each be used as a storage node contact (SNC) that connects the capacitor structure to each of the active regions 100A of the semiconductor substrate 100. The first conductive pattern 500R and the second conductive pattern 500E may each be used as a connection pad or a connection member that connects the capacitor structure or storage node to the storage node contact.

[0052] The first conductive contact 400R, the first conductive pattern 500R, and the fourth conductive pattern 600R disposed in the first region 100R of the semiconductor substrate 100 or disposed to overlap with the first region 100R may be elements that substantially construct a capacitor structure. In contrast, the second conductive contact 400E, the second conductive pattern 500E, and the fifth conductive pattern 600E disposed in the second region 100E of the semiconductor substrate 100 or disposed to overlap with the second region 100E may be dummy features that do not substantially operate as an integrated circuit. The dummy feature may be a feature that has been added so that the first conductive contact 400R, the first conductive pattern 500R, and the fourth conductive pattern 600R have stabilized features. The dummy feature may be a feature that has been added so that the first conductive contact 400R, the first conductive pattern 500R, and the fourth conductive pattern 600R are formed in accordance with the features expected in the design.

[0053] Fig.16 is a simplified schematic plan view illustrating an array of conductive patterns 500R and 500E-1 of a semiconductor device according to one embodiment. Fig.16 , is presented as having Figure 7 The components with the same reference numerals as in the reference numerals may indicate the same Figure 7 The components are the same as the components.

[0054] refer to Fig.16 , the plurality of second conductive patterns 500E-1 may be arranged around the first conductive pattern 500R or an array of the first conductive pattern 500R. The plurality of second conductive patterns 500E-1 may be arranged along the second region 100E of the semiconductor substrate 100. The second conductive pattern 500E-1 may be formed to have a linear shape or a strip shape extending along the second region 100E of the semiconductor substrate 100.

[0055] Fig.17 is a simplified schematic plan view illustrating an array of conductive patterns 500R, 500E-2, and 500E-3 of a semiconductor device according to one embodiment. Fig.17 , is presented as having Figure 7 The components with the same reference numerals as in the reference numerals may indicate the same Figure 7 The components are the same as the components.

[0056] refer to Fig.17 , a plurality of second conductive patterns 500E-2 may be disposed outside the first conductive pattern 500R or the array of the first conductive patterns 500R. A plurality of second conductive patterns 500E-2 may be formed to have a linear profile feature or a strip shape extending longitudinally along the second region 100E of the semiconductor substrate 100. The second conductive patterns 500E-2 may be disposed to face each other with the first conductive patterns 500R interposed between the second conductive patterns 500E-2, so that the second conductive patterns 500E-2 are spaced apart from each other. The sixth conductive pattern 500E-3 may be further disposed in the second region 100E of the semiconductor substrate 100 in the form of an island feature.

[0057] Fig.18 is a simplified schematic plan view illustrating an array of conductive patterns 500R, 500E, and 600E-1 of a semiconductor device according to one embodiment. Fig.18 , is presented as having Fig.11 The components with the same reference numerals as in the reference numerals may indicate the same Fig.11 The components are the same as the components.

[0058] refer to Fig.18, the third conductive pattern 600-1 may include a fourth conductive pattern 600R and a fifth conductive pattern 600E-1. A plurality of fifth conductive patterns 600E-1 may be formed as an array surrounding the fourth conductive pattern 600R or the fourth conductive pattern 600R. A plurality of fifth conductive patterns 600E-1 may be arranged along the second region 100E of the semiconductor substrate 100. The fifth conductive pattern 600E-1 may be formed to have a linear shape or a strip shape extending along the second region 100E of the semiconductor substrate 100. Because the fifth conductive patterns 600E-1 each have a linear shape or a strip shape, the fifth conductive pattern 600E-1 may be combined or connected to the second conductive pattern 500E with a larger area.

[0059] Return to reference Fig.11 and Fig.18 In the process of simultaneously forming the fourth conductive pattern 600R and the fifth conductive patterns 600E and 600E-1, since the second conductive pattern 500E has a linear shape feature or a ring shape feature, the possibility that the fourth conductive pattern and the fifth conductive pattern 600E and 600E-1 will be lost can be reduced. Fig.13 and Fig.14 As presented, the fifth conductive patterns 600E and 600E-1 may be unexpectedly lost during the removal of the sacrificial layers 260 and 280 because the fifth conductive patterns 600E and 600E-1 may be swept away by the etchant, chemical or cleaning agent. Since the fifth conductive patterns 600E and 600E-1 are disposed outside the edge of the outer portion of the fourth conductive pattern 600R, it is likely that the fifth conductive patterns 600E and 600E-1 will be lost more than the fourth conductive pattern 600R.

[0060] If the second conductive pattern has an island-like feature like the first conductive pattern 500R, the fifth conductive patterns 600E and 600E-1 may be misaligned with the second conductive pattern, so that the fifth conductive patterns 600E and 600E-1 may not be connected to the second conductive pattern. When the fifth conductive patterns 600E and 600E-1 are misaligned with the second conductive pattern, because the fifth conductive patterns 600E and 600E-1 are partially connected to the second conductive pattern, the bonding strength may be relatively small. Therefore, the possibility that the fifth conductive patterns 600E and 600E-1 will be lost more than the fourth conductive pattern 600R during the capacitor processing process may be increased.

[0061] Although the fifth conductive patterns 600E and 600E-1 are not aligned with the second conductive pattern 500E, because the second conductive pattern 500E has a linear shape feature or a ring shape feature, the possibility that the fifth conductive patterns 600E and 600E-1 will be connected or bonded to the second conductive pattern 500E is relatively large. Because the fifth conductive patterns 600E and 600E-1 can be connected to the second conductive pattern 500E relatively strongly or through a wide interface, the possibility that the fifth conductive patterns 600E and 600E-1 will be lost during the capacitor manufacturing process can be reduced.

[0062] Embodiments of the present disclosure have been described so far. Personnel with ordinary knowledge in the field to which the present invention belongs will understand that the present invention can be implemented in a modified form without departing from the inherent characteristics of the present disclosure. Therefore, the disclosed embodiments should be considered from a descriptive point of view and should not limit the scope of the present invention.

Claims

1. A semiconductor device comprising: A first conductive pattern is disposed on an insulating layer formed on a semiconductor substrate; A second conductive pattern is arranged to extend longitudinally above the insulating layer and on the side of the first conductive pattern; as well as The third conductive pattern is connected to the first conductive pattern and the second conductive pattern.

2. The semiconductor device according to claim 1, wherein: The first conductive pattern is formed to have island features that are spaced apart from each other and arranged at predetermined intervals, and The second conductive pattern is formed to have a linear profile feature laterally facing the island-shaped feature. 3 . The semiconductor device according to claim 1 , wherein the second conductive pattern is formed to have a larger width than each of the first conductive patterns. 4 . The semiconductor device according to claim 1 , wherein the second conductive pattern is formed to extend to surround an outside of the first conductive pattern. 5 . The semiconductor device according to claim 1 , wherein the second conductive pattern is formed to surround the outside of the first conductive pattern in a ring-shaped outer shape feature.

6. The semiconductor device according to claim 1, wherein: The semiconductor substrate includes a first region and a second region surrounding the first region, The first conductive pattern is disposed in the first region of the semiconductor substrate, and The second conductive pattern is disposed in the second region of the semiconductor substrate. 7 . The semiconductor device according to claim 1 , further comprising a conductive contact portion penetrating the insulating layer and electrically connecting the first conductive pattern and the second conductive pattern to the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein: The conductive contact portion includes a first conductive contact portion and a second conductive contact portion, The first conductive patterns are respectively connected to the first conductive contacts, and The second conductive patterns are connected to the second conductive contacts, respectively.

9. The semiconductor device according to claim 1, wherein: The third conductive pattern includes a fourth conductive pattern and a fifth conductive pattern, The fourth conductive patterns are connected to the first conductive patterns, respectively, and A plurality of the fifth conductive patterns are connected to the second conductive pattern. 10 . The semiconductor device according to claim 9 , wherein the fifth conductive pattern is formed to have a stripe shape extending in a longitudinal direction of the second conductive pattern. 11 . The semiconductor device according to claim 9 , wherein each of the fifth conductive patterns is formed to have a larger width than each of the fourth conductive patterns. 12 . The semiconductor device according to claim 1 , wherein the third conductive pattern is formed as a storage node of a capacitor. 13 . The semiconductor device of claim 1 , further comprising a floating supporting layer spaced apart from the insulating layer and supporting the third conductive pattern.

14. A method for manufacturing a semiconductor device, comprising: forming a first insulating layer over the semiconductor substrate; forming a first conductive pattern and a second conductive pattern simultaneously on the first insulating layer, wherein the second conductive pattern extends longitudinally on a side of the first conductive pattern; as well as A third conductive pattern is formed, the third conductive pattern being connected to the first conductive pattern and the second conductive pattern.

15. The method according to claim 14, wherein: The first conductive patterns are formed to respectively have island-shaped features, the island-shaped features are spaced apart from each other and arranged at predetermined intervals, and The second conductive pattern is formed to have a linear profile feature laterally facing the island-shaped feature. 16 . The method of claim 14 , wherein the second conductive pattern is formed to have a larger width than each of the first conductive patterns. 17 . The method of claim 14 , wherein the second conductive pattern is formed to extend in such a manner as to surround an outside of the first conductive pattern. 18 . The method of claim 14 , wherein the second conductive pattern is formed to surround an exterior of the first conductive pattern in the form of a ring-shaped feature.

19. The method of claim 14, wherein: The semiconductor substrate includes a first region and a second region surrounding the first region, The first conductive pattern is disposed in the first region of the semiconductor substrate, and The second conductive pattern is disposed in the second region of the semiconductor substrate.

20. The method of claim 14, further comprising: Before forming the first conductive pattern and the second conductive pattern, forming a conductive contact portion that penetrates the first insulating layer and is electrically connected to the semiconductor substrate, The first conductive pattern and the second conductive pattern are formed to be connected to the conductive contact portion.

21. The method of claim 20, wherein: The conductive contact portion includes a first conductive contact portion and a second conductive contact portion, The first conductive patterns are formed to be connected to the first conductive contacts, respectively, and The second conductive patterns are formed to be connected to the second conductive contact portions, respectively.

22. The method of claim 14, further comprising: A second insulating layer is formed over the first insulating layer, the second insulating layer isolating the first conductive pattern and the second conductive pattern from each other.

23. The method of claim 14, wherein: The third conductive pattern includes a fourth conductive pattern and a fifth conductive pattern, The fourth conductive patterns are formed to be connected to the first conductive patterns, respectively, and A plurality of the fifth conductive patterns are formed to be connected to the second conductive patterns. 24 . The method of claim 23 , wherein the fifth conductive pattern is formed to have a stripe shape extending in a longitudinal direction of the second conductive pattern. 25 . The method of claim 23 , wherein each of the fifth conductive patterns is formed to have a larger width than each of the fourth conductive patterns.

26. The method of claim 14, wherein the third conductive pattern is formed as a storage node of a capacitor.

27. The method according to claim 14, wherein forming the third conductive pattern comprises: forming an etch stop layer covering the first conductive pattern and the second conductive pattern; forming a sacrificial layer over the etch stop layer; forming an opening penetrating the sacrificial layer and the etch stop layer; forming a conductive layer in the opening; separating the conductive layer into the third conductive patterns; as well as The sacrificial layer is removed.

28. The method of claim 27, further comprising: forming a floating support layer above the sacrificial layer, The opening is formed to penetrate the floating supporting layer.

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