Semiconductor package

Abstract

A semiconductor package includes: a ceramic substrate having a cavity; a lower redistribution structure on a lower surface of the ceramic substrate and electrically connected to the ceramic substrate; an upper redistribution structure on an upper surface of the ceramic substrate and electrically connected to the ceramic substrate; a plurality of semiconductor chips arranged in a first direction on the upper redistribution structure; and a bridge chip structure in the cavity of the ceramic substrate and including a bridge chip electrically connecting the plurality of semiconductor chips to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0099831 filed on July 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a bridge chip. Background Art

[0004] In recent years, the demand for portable devices has increased rapidly in the electronic product market.

[0005] As a result, there is a continuous demand for miniaturization and weight reduction of electronic components mounted on these electronic products. In order to miniaturize and lighten electronic components, semiconductor packages mounted on electronic components are required to process a large amount of data while becoming smaller in size. Therefore, in order to achieve high performance and large capacity as well as miniaturization and weight reduction, research and development of semiconductor packages including bridge chips are continuously being conducted. Summary of the invention

[0006] The inventive concept provides a semiconductor package including a ceramic substrate having a cavity and a bridge chip located in the cavity.

[0007] Problems to be solved by the technical idea of ​​the present inventive concept are not limited to the problems to be solved by the above-mentioned present inventive concept, and other problems not mentioned are clearly understood by those skilled in the art from the following description.

[0008] According to an aspect of the inventive concept, there is provided a semiconductor package, comprising:

[0009] A ceramic substrate having a cavity, a lower redistribution structure located on a lower surface of the ceramic substrate and electrically connected to the ceramic substrate, an upper redistribution structure located on an upper surface of the ceramic substrate and electrically connected to the ceramic substrate, a plurality of semiconductor chips arranged along a first (e.g., horizontal) direction on the upper redistribution structure, and a bridge chip structure located in the cavity of the ceramic substrate and electrically connecting the plurality of semiconductor chips to each other.

[0010] In addition, according to another aspect of the present invention, a semiconductor package is provided, which includes: a ceramic substrate having a cavity, the ceramic substrate including a plurality of first insulating layers and a first circuit wiring layer between the plurality of first insulating layers; a lower redistribution structure on the lower surface of the ceramic substrate, the lower redistribution structure including a plurality of second insulating layers and a second circuit wiring layer between the plurality of second insulating layers and electrically connected to the first circuit wiring layer; an upper redistribution structure on the upper surface of the ceramic substrate, the upper redistribution structure including a plurality of third insulating layers and a third circuit wiring layer between the plurality of third insulating layers and electrically connected to the first circuit wiring layer; a plurality of semiconductor chips arranged along a first (e.g., horizontal) direction on the upper redistribution structure; a bridge chip structure in the cavity of the ceramic substrate, the bridge chip structure including a bridge chip electrically connecting the plurality of semiconductor chips to each other; and a packaging layer encapsulating the bridge chip structure in the cavity, wherein the packaging layer includes a ceramic material, a resin or a combination thereof.

[0011] In addition, according to another aspect of the inventive concept, there is provided a semiconductor package, comprising: a ceramic substrate having a cavity, a plurality of first insulating layers, and a first circuit wiring layer between the plurality of first insulating layers; a lower redistribution structure on a lower surface of the ceramic substrate, the lower redistribution structure comprising a plurality of second insulating layers and a second circuit wiring layer between the plurality of second insulating layers and electrically connected to the first circuit wiring layer; an upper redistribution structure on an upper surface of the ceramic substrate, the upper redistribution structure comprising a plurality of third insulating layers and a third circuit wiring layer between the plurality of third insulating layers and electrically connected to the first circuit wiring layer; and a first circuit wiring layer on the upper redistribution structure along the first A plurality of semiconductor chips arranged in a direction (e.g., horizontally), the plurality of semiconductor chips comprising logic semiconductor chips or high bandwidth memory (HBM) semiconductor chips; a bridge chip structure in a cavity of a ceramic substrate, the bridge chip structure comprising a bridge chip electrically connecting the plurality of semiconductor chips to each other; a packaging layer encapsulating the bridge chip structure in the cavity, wherein the packaging layer comprises a ceramic material, a resin, or a combination thereof; and a capacitor structure at an interface between the ceramic substrate and an upper redistribution structure, the capacitor structure comprising a lower electrode layer on an upper surface of the ceramic substrate, a dielectric layer on an upper surface of the lower electrode layer, and an upper electrode layer on an upper surface of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a cross-sectional view schematically showing a semiconductor package according to an embodiment;

[0014] Figure 2 yes Figure 1 An enlarged cross-sectional view of the EX1 portion;

[0015] Figure 3 is a cross-sectional view schematically showing a semiconductor package according to an embodiment;

[0016] Figure 4 yes Figure 3 An enlarged cross-sectional view of the EX2 portion;

[0017] Figures 5 to 11 is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor package according to an embodiment;

[0018] Fig.12 is a cross-sectional view schematically showing a semiconductor package according to an embodiment;

[0019] Fig.13 yes Fig.12 An enlarged cross-sectional view of the EX3 portion of FIG. 1 ; and

[0020] Fig.14 and Fig.15 is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the technical idea of ​​the inventive concept are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same components, and descriptions already given thereto are omitted.

[0022] Figure 1 is a cross-sectional view schematically showing a semiconductor package according to an embodiment.

[0023] Figure 2 yes Figure 1 An enlarged cross-sectional view of the EX1 portion.

[0024] Reference Figure 1 and Figure 2 , the semiconductor package 100 may include a ceramic substrate 110 , a lower redistribution structure 120 , an upper redistribution structure 130 , a first semiconductor chip ch1 , and a second semiconductor chip ch2 .

[0025] The ceramic substrate 110 may include a plurality of first insulating layers 112 and a first circuit wiring layer 114 disposed between the plurality of first insulating layers 112. In an embodiment, the plurality of first insulating layers 112 may include a low temperature sintered dielectric. For example, the plurality of first insulating layers 112 may include aluminum oxide (Al 2 O 3 ).

[0026] The first circuit wiring layer 114 may include a first wiring layer 114L, an upper wiring layer 114a, and a first via 114V. As shown in the figure, the first wiring layer 114L may extend in a horizontal direction between the plurality of first insulating layers 112, and may be arranged at a plurality of vertical levels. The first via 114V may be provided in a through hole (114VH, see Figure 5 ) inside, and the plurality of first wiring layers 114L disposed at different vertical levels may be connected to each other. In an embodiment, the first wiring layer 114L and the first via 114V may include silver (Ag) or tungsten (W). The upper wiring layer 114a may be formed in the cavity 110C. The bridge chip structure 140( Figure 2 ) may be disposed on the upper wiring layer 114a.

[0027] In an embodiment, the ceramic substrate 110 may be formed by forming a first wiring layer 114L and a first via 114V constituting a first circuit wiring layer 114 on each of a plurality of first insulating layers 112, stacking the plurality of first insulating layers 112, and then performing low-temperature co-sintering on the first insulating layers 112 and the first circuit wiring layers 114. For example, the co-sintering temperature may be in a range of about 700° C. to about 1100° C. The first wiring layer 114L may have a rounded side surface. In the process of forming the first circuit wiring layer 114 on the plurality of first insulating layers 112 and laminating and sintering the plurality of first insulating layers 112, the side surface of the first wiring layer 114L may be rounded, as shown in FIG. Figure 2 shown.

[0028] In an embodiment, the ceramic substrate 110 may include a cavity 110C. The cavity 110C may be formed at an upper end of the ceramic substrate 110. The cavity 110C may be formed to have a predetermined depth at an upper end of the ceramic substrate 110. For example, the vertical depth d of the cavity 110C may be 100 mm. 1 ( Figure 2 ) may be in the range of about 80 μm to about 200 μm. In the semiconductor package 100 of the present invention, by stacking and sintering a plurality of conductive sheets (P110, see Figure 5 ) to manufacture the ceramic substrate 110, thereby forming a deep vertical depth d of the cavity 110C 1 .

[0029] In an embodiment, the semiconductor package 100 may include a bridge chip structure 140. The bridge chip structure 140 may be accommodated in a cavity 110C of a ceramic substrate 110. The bridge chip structure 140 may be disposed on an upper wiring layer 114a of the ceramic substrate 110. The bridge chip structure 140 may be attached to the upper wiring layer 114a by an adhesive film 170 disposed between the bridge chip structure 140 and the upper wiring layer 114a. For example, the adhesive film 170 may include a die bonding film.

[0030] The bridge chip structure 140 may include a bridge chip 142, an upper bridge pad 144, and a bridge pillar 146. The bridge chip 142 may electrically connect a plurality of semiconductor chips. For example, the bridge chip 142 may electrically connect the first semiconductor chip ch1 and the second semiconductor chip ch2 to each other.

[0031] The upper bridge pad 144 and the bridge column 146 can electrically connect the bridge chip 142 to the plurality of semiconductor chips ch1 and ch2. For example, one or more upper bridge pads 144 and the bridge column 146 can electrically connect the bridge chip 142 and the first semiconductor chip ch1 to each other. In addition, one or more upper bridge pads 144 and the bridge column 146 can electrically connect the bridge chip 142 to the second semiconductor chip ch2. The upper bridge pad 144 and the bridge column 146 may include at least one of copper (Cu), nickel (Ni), gold (Au), platinum (Pt), titanium (Ti), chromium (Cr), and alloys thereof.

[0032] In an embodiment, the semiconductor package 100 may further include an encapsulation layer 160. The encapsulation layer 160 may fill the interior of the cavity 110C of the ceramic substrate 110. In detail, the encapsulation layer 160 may be formed to cover the bridge chip structure 140 accommodated in the cavity 110C of the ceramic substrate 110. The upper surface of the encapsulation layer 160 may be at the same level as the upper surface of the ceramic substrate 110 (i.e., the upper surface of the encapsulation layer 160 and the upper surface of the ceramic substrate 110 are coplanar).

[0033] In an embodiment, the encapsulation layer 160 may be made of a ceramic material, a resin, or a combination thereof. In addition, the encapsulation layer 160 may be formed of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a resin containing a reinforcing material such as an inorganic filler (in detail, Ajinomoto structured film (DBF), FR-4, BT, etc.), but is not limited thereto, and the encapsulation layer 160 may be formed of a molding material such as an epoxy molding compound (EMC) or a photosensitive material such as a photoimageable encapsulant (PIE).

[0034] In an embodiment, the bridge chip structure 140 may also include one or more structures selected from capacitors, inductors, and semiconductor switches (intelligent power devices (IPDs)). For example, the bridge chip structure 140 may also include Si capacitors. Capacitors, inductors, semiconductor switches, etc. may be accommodated in the cavity 110C of the ceramic substrate 110. Capacitors, inductors, semiconductor switches, etc. may be placed at the same vertical level as the bridge chip 142 in the cavity 110C.

[0035] The lower redistribution structure 120 may be disposed on the lower surface of the ceramic substrate 110. The lower redistribution structure 120 may include a plurality of second insulating layers 122 and a second circuit wiring layer 124 disposed between the plurality of second insulating layers 122. The lower redistribution structure 120 may be a redistribution substrate formed by a redistribution process. However, without being limited thereto, the lower redistribution structure 120 may correspond to any one of a printed circuit board (PCB), a metal core PCB (MCPCB), a metal PCB (MPCB), and a flexible PCB (FPCB).

[0036] In an embodiment, the plurality of second insulating layers 122 may include a polymer material, for example, a photo-imageable dielectric (PID), a photosensitive polyimide (PSPI), a glass-cured epoxy resin, a polyimide resin, a Teflon resin, or the like.

[0037] The second circuit wiring layer 124 may include a second wiring layer 124L and a second via 124V. The second wiring layer 124L may extend in a horizontal direction between a plurality of second insulating layers 122, and may be arranged at a plurality of vertical levels. The second via 124V may connect a plurality of second wiring layers 124L disposed at different vertical levels to each other. In an embodiment, the second wiring layer 124L and the second via 124V may include at least one of copper (Cu), nickel (Ni), gold (Au), platinum (Pt), titanium (Ti), chromium (Cr), and alloys thereof. The second circuit wiring layer 124 may be electrically connected to the first circuit wiring layer 114 of the ceramic substrate 110.

[0038] The upper redistribution structure 130 may be disposed on the ceramic substrate 110. The upper redistribution structure 130 may include a plurality of third insulating layers 132 and a third circuit wiring layer 134 disposed between the plurality of third insulating layers 132. The upper redistribution structure 130 may be a redistribution substrate formed by a redistribution process. However, not limited thereto, the upper redistribution structure 130 may correspond to any one of a PCB, an MCPCB, an MPCB, and an FPCB.

[0039] In an embodiment, the plurality of third insulating layers 132 may include a polymer material (eg, PID, PSP), glass fiber cured epoxy resin, polyimide resin, Teflon resin, or the like.

[0040] The third circuit wiring layer 134 may include a third wiring layer 134L and a third via 134V. The third wiring layer 134L may extend in a horizontal direction between a plurality of third insulating layers 132 and may be arranged at a plurality of vertical levels. The third via 134V may connect a plurality of third wiring layers 134L to each other between a plurality of third wiring layers 134L arranged at different vertical levels. In an embodiment, the third wiring layer 134L and the third via 134V may include at least one of copper (Cu), nickel (Ni), gold (Au), platinum (Pt), titanium (Ti), chromium (Cr) and alloys thereof. The third circuit wiring layer 134 may be electrically connected to the first circuit wiring layer 114 of the ceramic substrate 110.

[0041] In an embodiment, the upper redistribution structure 130 may further include a lower connection pad (not shown). The lower connection pad may be disposed at an interface between the upper redistribution structure 130 and the ceramic substrate 110. The lower connection pad may be electrically connected to the third via 134V of the upper redistribution structure 130.

[0042] In an embodiment, the semiconductor package 100 may include a first pad 152 disposed on a lower surface of the lower redistribution structure 120 and a second pad 154 disposed on an upper surface of the upper redistribution structure 130 .

[0043] The first pad 152 may be electrically connected to the second circuit wiring layer 124 of the lower redistribution structure 120. The first pad 152 may include a pad layer and a capping metal layer disposed on an outer surface of the pad layer. For example, the pad layer may include at least one of copper (Cu), nickel (Ni), gold (Au), platinum (Pt), titanium (Ti), chromium (Cr), and alloys thereof, and the capping metal layer may include at least one of nickel (Ni), gold (Au), platinum (Pt), and alloys thereof. An external connection terminal (such as a solder ball having a relatively large size) may be disposed on the capping metal layer of the first pad 152.

[0044] The second pad 154 may be electrically connected to the third circuit wiring layer 134 of the upper redistribution structure 130, and may include a pad layer and a capping metal layer disposed on an outer surface of the pad layer. For example, the pad layer may include at least one of copper (Cu), nickel (Ni), gold (Au), platinum (Pt), titanium (Ti), chromium (Cr), and alloys thereof, and the capping metal layer may include at least one of nickel (Ni), gold (Au), platinum (Pt), and alloys thereof.

[0045] The connection bump 156 may be disposed on the second pad 154. The connection bump 156 may be disposed to contact the second pad 154. The connection bump 156 may electrically connect the first semiconductor chip ch1 and the second semiconductor chip ch2 to the upper redistribution structure 130. Through the connection bump 156, at least one of a control signal, a power signal, and a ground signal for the operation of the first semiconductor chip ch1 and / or the second semiconductor chip ch2 may be provided from the outside (i.e., outside the semiconductor package 100), a data signal to be stored in the first semiconductor chip ch1 and / or the second semiconductor chip ch2 may be provided from the outside, or data stored in the first semiconductor chip ch1 and / or the second semiconductor chip ch2 may be provided to the outside. For example, the connection bump 156 may be made of a column structure, a ball structure, or a solder layer.

[0046] The first semiconductor chip ch1 and the second semiconductor chip ch2 may be mounted on the upper redistribution structure 130. For example, the first semiconductor chip ch1 and the second semiconductor chip ch2 may be mounted on the upper redistribution structure 130 through the connection bumps 156 using a flip chip method. Figure 1 Although not shown in the figure, in some embodiments, an underfill material layer surrounding the connection bumps 156 may be disposed between the plurality of semiconductor chips ch1 and ch2 and the upper redistribution structure 130. As shown in the figure, the first semiconductor chip ch1 and the second semiconductor chip ch2 may be arranged side by side. As shown in the figure, the first semiconductor chip ch1 and the second semiconductor chip ch2 may be arranged to be spaced apart in the horizontal direction. Figure 1 , the semiconductor package 100 is illustrated as including two semiconductor chips ch1 and ch2, but the inventive concept is not limited thereto. The semiconductor package 100 may include three or more semiconductor chips, and may include semiconductor chips having a stacked structure.

[0047] The first semiconductor chip ch1 may be a logic semiconductor chip. For example, the first semiconductor chip ch1 may include a logic semiconductor chip such as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), an application-specific integrated circuit (ASIC), or other processing chips. However, the first semiconductor chip ch1 is not limited thereto, and the first semiconductor chip ch1 may include a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) or a non-volatile memory semiconductor chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM).

[0048] The second semiconductor chip ch2 may be a memory semiconductor chip. For example, the second semiconductor chip ch2 may be a volatile memory semiconductor chip such as DRAM or SRAM, or a non-volatile memory semiconductor chip such as PRAM, MRAM, FeRAM, or RRAM. However, the second semiconductor chip ch2 is not limited thereto, and the second semiconductor chip ch2 may include a logic semiconductor chip such as a CPU, GPU, AP, ASIC, or other processing chip.

[0049] The ceramic substrate 110 has a low coefficient of thermal expansion (CTE) and effectively prevents warping of the semiconductor package 100 due to the material properties of the ceramic substrate 110. In addition, the manufacturing process time of the semiconductor package 100 including the ceramic substrate 110 of the present inventive concept can be shortened. In addition, due to the characteristics of the ceramic material, a high temperature process can be performed, and thus the functional characteristics of the semiconductor package 100 can be improved.

[0050] Figure 3 is a cross-sectional view schematically showing a semiconductor package according to an embodiment.

[0051] Figure 4 yes Figure 3 An enlarged cross-sectional view of the EX2 portion.

[0052] Reference Figure 3 and Figure 4 The semiconductor package 200 may include a ceramic substrate 110, a lower redistribution structure 120, an upper redistribution structure 130, a first semiconductor chip ch1, and a second semiconductor chip ch2. Figure 1 and Figure 2 Descriptions of the same or corresponding configurations of the described semiconductor package 100 may be omitted.

[0053] The ceramic substrate 110 may include a plurality of first insulating layers 112 and a first circuit wiring layer 114 disposed between the plurality of first insulating layers 112. In an embodiment, the plurality of first insulating layers 112 may include a low temperature sintered dielectric such as aluminum oxide (Al2O3). 2 O 3 ). The ceramic substrate 110 may include a cavity 110C. The cavity 110C may be formed at an upper end of the ceramic substrate 110. The cavity 110C may be formed to have a predetermined depth at an upper end of the ceramic substrate 110C.

[0054] The first circuit wiring layer 114 may include a first wiring layer 114L, an upper wiring layer 114b, and a first via 114V. The first wiring layer 114L may extend in a horizontal direction between the plurality of first insulating layers 112, and may be disposed at a plurality of vertical levels. The first via 114V may be disposed in a through hole (114VH, see FIG. 114H) penetrating the plurality of first insulating layers 112. Figure 5 ) inside, and multiple first wiring layers 114L may be connected to each other between multiple first wiring layers 114L disposed at different vertical levels. In an embodiment, the first wiring layer 114L and the first via 114V may include silver (Ag) or tungsten (W). The upper wiring layer 114b may be formed in the cavity 110C. The bridge chip structure 240 may be disposed on the upper wiring layer 114b.

[0055] In an embodiment, the ceramic substrate 110 may be formed by forming a first wiring layer 114L and a first via 114V constituting a first circuit wiring layer 114 on each of a plurality of first insulating layers 112, stacking the plurality of first insulating layers 112, and then performing low temperature co-sintering on the first insulating layers 112 and the first circuit wiring layers 114. For example, the co-sintering temperature may be in the range of about 700° C. to about 1100° C.

[0056] In an embodiment, the semiconductor package 200 may include a bridge chip structure 240. The bridge chip structure 240 may be accommodated in the cavity 110C of the ceramic substrate 110. The bridge chip structure 240 may be disposed on the upper wiring layer 114b of the ceramic substrate 110. The bridge chip structure 240 may be mounted on the upper wiring layer 114b by a connection pad 250 disposed between the bridge chip structure 240 and the upper wiring layer 114b. For example, the connection pad 250 may be formed by a column structure, a ball structure, or a solder layer.

[0057] The bridge chip structure 240 may include a bridge chip 242, an upper bridge pad 244, a bridge column 246, and a lower bridge pad 248. The bridge chip 242 may electrically connect a plurality of semiconductor chips. For example, the bridge chip 242 may electrically connect a first semiconductor chip ch1 and a second semiconductor chip ch2 to each other. The upper bridge pad 244 and the bridge column 246 may electrically connect the bridge chip 242 to a plurality of semiconductor chips ch1 and ch2. For example, one or more upper bridge pads 244 and bridge column 246 may electrically connect the bridge chip 242 to the first semiconductor chip ch1. In addition, one or more upper bridge pads 244 and bridge column 246 may electrically connect the bridge chip 242 to the second semiconductor chip ch2. The upper bridge pad 244, the lower bridge pad 248, and the bridge column 246 may include at least one of copper (Cu), nickel (Ni), gold (Au), platinum (Pt), titanium (Ti), chromium (Cr), and alloys thereof.

[0058] In an embodiment, the bridge chip 242 may include a through silicon via (TSV). The TSV may extend through the bridge chip 242 to the ceramic substrate 110. The TSV may electrically connect the upper bridge pad 244 and the lower bridge pad 248 to each other. Therefore, control signals (such as input / output data signals and command signals) may be transmitted between the first semiconductor chip ch1, the second semiconductor chip ch2, and the bridge chip 242 through the TSV, the upper bridge pad 244, the bridge column 246, and the lower bridge pad 248.

[0059] In an embodiment, the semiconductor package 200 may further include an encapsulation layer 160. The encapsulation layer 160 may fill the inside of the cavity 110C of the ceramic substrate 110. In detail, the encapsulation layer 160 may be formed to cover the bridge chip structure 240 accommodated inside the cavity 110C of the ceramic substrate 110. In detail, the encapsulation layer 160 may be formed to cover the upper wiring layer 114b, the bridge chip 242, and the connection pad 250. In detail, the encapsulation layer 160 may be formed to cover the upper wiring layer 114a, the bridge chip 242, and the adhesive film 170.

[0060] In an embodiment, an upper surface of encapsulation layer 160 may be at the same level (ie, coplanar) as a top surface of ceramic substrate 110. Encapsulation layer 160 may be made of a ceramic material, a resin, or a combination thereof.

[0061] The lower redistribution structure 120 may be disposed on the lower surface of the ceramic substrate 110. The lower redistribution structure 120 may include a plurality of second insulating layers 122 and a second circuit wiring layer 124 disposed between the plurality of second insulating layers 122. The lower redistribution structure 120 may be a redistribution substrate formed by a redistribution process. However, the inventive concept is not limited thereto, and the lower redistribution structure 120 may correspond to any one of a PCB, an MCPCB, an MPCB, and an FPCB.

[0062] The upper redistribution structure 130 may be disposed on the ceramic substrate 110. The upper redistribution structure 130 may include a plurality of third insulating layers 132 and a third circuit wiring layer 134 disposed between the plurality of third insulating layers 132. The upper redistribution structure 130 may be a redistribution substrate formed by a redistribution process. However, the inventive concept is not limited thereto, and the upper redistribution structure 130 may correspond to any one of a printed PCB, an MCPCB, an MPCB, and an FPCB.

[0063] In an embodiment, the semiconductor package 200 may include a first pad 152 disposed on a lower surface of the lower redistribution structure 120 and a second pad 154 disposed on an upper surface of the upper redistribution structure 130. A connection bump 156 may be disposed on the second pad 154. The connection bump 156 may be disposed to contact the second pad 154. The connection bump 156 may electrically connect the first semiconductor chip ch1 and the second semiconductor chip ch2 to the upper redistribution structure 130. For example, the connection bump 156 may be formed of a pillar structure, a ball structure, or a solder layer.

[0064] The first semiconductor chip ch1 and the second semiconductor chip ch2 may be mounted on the upper redistribution structure 130. For example, the first semiconductor chip ch1 and the second semiconductor chip ch2 may be mounted on the upper redistribution structure 130 through the connection bumps 156 using a flip chip method.

[0065] The first semiconductor chip ch1 may be a logic semiconductor chip. For example, the first semiconductor chip ch1 may include a logic semiconductor chip such as a CPU, a GPU, an AP, an ASIC, or other processing chips. However, the first semiconductor chip ch1 is not limited thereto and may include a memory semiconductor chip.

[0066] The second semiconductor chip ch2 may be a memory semiconductor chip. For example, the second semiconductor chip ch2 may be a volatile memory semiconductor chip such as DRAM or SRAM, or a nonvolatile memory semiconductor chip such as PRAM, MRAM, FeRAM, or RRAM. However, the second semiconductor chip ch2 is not limited thereto and may include a logic semiconductor chip.

[0067] In an embodiment, the bridge chip structure 240 may also include one or more structures selected from capacitors, inductors, and semiconductor switches. The capacitors, inductors, semiconductor switches, etc. may be accommodated in the cavity 110C. The capacitors, inductors, semiconductor switches, etc. may be placed at the same vertical level as the bridge chip 242 within the cavity 110C.

[0068] The ceramic substrate 110 has a low CTE and effectively prevents warping of the semiconductor package 200 due to the material properties of the ceramic substrate 110. In addition, the manufacturing process time of the semiconductor package 200 including the ceramic substrate 110 of the present inventive concept can be shortened. In addition, due to the characteristics of the ceramic material, a high temperature process can be performed, so the functional characteristics of the semiconductor package 200 can be improved.

[0069] Figures 5 to 11 is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0070] Reference Figure 5In an embodiment, each of the plurality of conductive sheets P110 may include a first insulating layer 112 , a first wiring layer 114L disposed on an upper surface of the first insulating layer 112 , and a first via 114V disposed in a through hole 114VH penetrating the first insulating layer 112 .

[0071] The uppermost conductive sheet P110_U may include a cavity hole 110CH. The conductive sheet P110 disposed below the uppermost conductive sheet P110_U may include an upper wiring layer 114 a.

[0072] In an embodiment, the first insulating layer 112 may be formed using a low temperature sintering dielectric and may include, for example, aluminum oxide (Al 2 O 3 In an embodiment, the first wiring layer 114L may be formed using a first conductive material, and the first conductive material may include silver or tungsten. In some embodiments, the first wiring layer 114L may be formed by applying or printing a silver paste on the first insulating layer 112.

[0073] Reference Figure 6 , the ceramic substrate 110 may be formed by sintering the plurality of conductive sheets P110. In an embodiment, the sintering temperature of the plurality of conductive sheets P110 may be about 700° C. to about 1100° C. In an embodiment, the first wiring layer 114L, the upper wiring layer 114a, and the first via 114V stacked in a vertical direction during the sintering process may constitute the first circuit wiring layer 114.

[0074] The cavity 110C may be formed in an upper portion of the ceramic substrate 110. The cavity 110C may be formed to have a predetermined depth at an upper end of the ceramic substrate 110C. For example, the vertical depth of the cavity 110C may be in the range of about 80 μm to about 200 μm.

[0075] Reference Figure 7 , a bridge chip structure 140 may be installed. The bridge chip structure 140 may be disposed in the cavity 110C of the ceramic substrate 110. The bridge chip structure 140 may be attached to the upper wiring layer 114a by an adhesive film 170 disposed between the bridge chip structure 140 and the upper wiring layer 114a. For example, the adhesive film 170 may include a die bonding film. The bridge chip structure 140 may include a bridge chip 142, an upper bridge pad 144, and a bridge column 146.

[0076] Reference Figure 8, an encapsulation layer 160 may be formed. The encapsulation layer 160 may fill the inside of the cavity 110C of the ceramic substrate 110. In detail, the encapsulation layer 160 may be formed to cover the bridge chip structure 140 accommodated inside the cavity 110C of the ceramic substrate 110. The encapsulation layer 160 may be made of a ceramic material, a resin, or a combination thereof.

[0077] Reference Fig. 9 , the upper surfaces of the ceramic substrate 110 and the encapsulation layer 160 may be polished. The upper surfaces of the ceramic substrate 110 and the encapsulation layer 160 may be formed at the same level (i.e., the upper surface of the ceramic substrate 110 and the upper surface of the encapsulation layer 160 are coplanar). The first via 114V of the ceramic substrate 110 may be exposed. The bridging pillar 146 of the bridge chip structure 140 may be exposed.

[0078] Reference Fig.10 , a lower redistribution structure 120 may be formed on a lower surface of the ceramic substrate 110. The lower redistribution structure 120 may include a second insulating layer 122 and a second circuit wiring layer 124.

[0079] In an embodiment, to form the lower redistribution structure 120 , the processes of forming a plurality of second insulating layers 122 and forming a plurality of second wiring layers 124L may be repeatedly performed.

[0080] In some embodiments, the second insulating layer 122 may be formed using a polymer material (e.g., a photoimageable dielectric (PID), a photosensitive polyimide (PSPI), a glass fiber cured epoxy resin, a polyimide resin, a Teflon resin, etc.). In some embodiments, the formation of the plurality of second wiring layers 124L may be performed using at least one of an electrolytic plating process, a chemical plating process, a sputtering process, and an evaporation process.

[0081] For example, in the process of forming the lower redistribution structure 120, the second via 124V may be formed to connect the second wiring layers 124L disposed at different vertical levels to each other in the process of forming the plurality of second wiring layers 124L. For example, a through hole may be formed in the second insulating layer 122, the second wiring layer 124L may be formed on the second insulating layer 122, and the portion of the second wiring layer 124L filling the inside of the through hole may be referred to as the second via 124V. Thereafter, the first pad 152 electrically connected to the second circuit wiring layer 124 may be formed on the bottom surface of the lower redistribution structure 120.

[0082] Reference Fig.11 , an upper redistribution structure 130 may be formed on an upper surface of the ceramic substrate 110. The upper redistribution structure 130 may include a third insulating layer 132 and a third circuit wiring layer 134.

[0083] In an embodiment, to form the upper redistribution structure 130 , the processes of forming a plurality of third insulating layers 132 and forming a plurality of third wiring layers 134L may be repeatedly performed.

[0084] In an embodiment, a polymer material (e.g., PID, PSPI, glass fiber cured epoxy resin, polyimide resin, The third insulating layer 132 is formed by using a 3D printing process, a brand resin, etc. In some embodiments, the formation of the plurality of third wiring layers 134L may be performed using at least one of an electrolytic plating process, a chemical plating process, a sputtering process, and an evaporation process.

[0085] For example, in the process of forming the upper redistribution structure 130, the third via 134V may be formed to connect the third wiring layers 134L disposed at different vertical levels to each other in the process of forming the plurality of third wiring layers 134L. For example, a through hole may be formed in the third insulating layer 132, the third wiring layer 134L may be formed on the third insulating layer 132, and the portion of the third wiring layer 134L filling the inside of the through hole may be referred to as the third via 134V. Thereafter, a second pad 154 electrically connected to the third circuit wiring layer 134 may be formed on the upper surface of the upper redistribution structure 130.

[0086] Afterwards, refer again to Figure 1 , the first semiconductor chip ch1 and the second semiconductor chip ch2 may be mounted on the upper redistribution structure 130 using connection bumps 156. The connection bumps 156 may electrically connect the first semiconductor chip ch1 and the second semiconductor chip ch2 to the upper redistribution structure 130.

[0087] Fig.12 is a cross-sectional view schematically showing a semiconductor package according to an embodiment.

[0088] Fig.13 yes Fig.12 An enlarged cross-sectional view of the EX3 portion.

[0089] Reference Fig.12 and Fig.13 The semiconductor package 300 may include a ceramic substrate 110, a lower redistribution structure 120, an upper redistribution structure 130, a first semiconductor chip ch1, a plurality of second semiconductor chips ch2, and a capacitor structure 380. Figure 1 and Figure 2 Descriptions of the same or corresponding configurations of the described semiconductor package 100 may be omitted.

[0090] The ceramic substrate 110 may include a plurality of first insulating layers 112 and a first circuit wiring layer 114 disposed between the plurality of first insulating layers 112. In an embodiment, the plurality of first insulating layers 112 may include a low temperature sintered dielectric such as aluminum oxide (Al2O3). 2 O 3 ). The ceramic substrate 110 may include a plurality of cavities 110C. Each cavity 110C may be formed at an upper end of the ceramic substrate 110. Each cavity 110C may be formed to have a predetermined depth at an upper end of the ceramic substrate 110. The plurality of cavities 110C may be formed at the same vertical level and may have the same depth, but is not limited thereto.

[0091] The first circuit wiring layer 114 may include a first wiring layer 114L, an upper wiring layer 114b, and a first via 114V. The first wiring layer 114L may extend along a first (e.g., horizontal) direction between the plurality of first insulating layers 112, and may be arranged at a plurality of vertical levels. The first via 114V may be provided in a through hole (114VH, see Figure 5 ) inside, and multiple first wiring layers 114L may be connected to each other between multiple first wiring layers 114L disposed at different vertical levels. In an embodiment, the first wiring layer 114L and the first via 114V may include silver (Ag) or tungsten (W). The upper wiring layer 114a may be formed in the cavity 110C. The bridge chip structure 140 may be disposed on the upper wiring layer 114a.

[0092] In an embodiment, the ceramic substrate 110 may be formed by forming a first wiring layer 114L and a first via 114V constituting a first circuit wiring layer 114 on each of a plurality of first insulating layers 112, stacking the plurality of first insulating layers 112, and then performing low temperature co-sintering on the first insulating layers 112 and the first circuit wiring layers 114. For example, the co-sintering temperature may be in the range of about 700° C. to about 1100° C.

[0093] In an embodiment, the semiconductor package 300 may include a bridge chip structure 140. A plurality of bridge chip structures 140 may be each accommodated in a plurality of cavities 110C of the ceramic substrate 110. Each bridge chip structure 140 may be disposed on an upper wiring layer 114a of the ceramic substrate 110. The description of the configuration and characteristics of the bridge chip structure 140 may be referred to in detail in the accompanying drawings. Figure 1 and Figure 2 The description given is used instead.

[0094] In an embodiment, the semiconductor package 300 may further include an encapsulation layer 160. The encapsulation layer 160 may fill the interior of the cavity 110C of the ceramic substrate 110. In detail, the encapsulation layer 160 may be formed to cover the bridge chip structure 140 accommodated inside the cavity 110C of the ceramic substrate 110. The upper surface of the encapsulation layer 160 may be at the same level as the upper surface of the ceramic substrate 110 (i.e., the upper surface of the encapsulation layer 160 and the upper surface of the ceramic substrate 110 are coplanar). The encapsulation layer 160 may be made of a ceramic material, a resin, or a combination thereof.

[0095] The lower redistribution structure 120 may be disposed on the lower surface of the ceramic substrate 110. The lower redistribution structure 120 may include a plurality of second insulating layers 122 and a second circuit wiring layer 124 disposed between the plurality of second insulating layers 122. The lower redistribution structure 120 may be a redistribution substrate formed by a redistribution process. However, not limited thereto, the lower redistribution structure 120 may correspond to any one of a PCB, an MCPCB, an MPCB, and an FPCB.

[0096] The upper redistribution structure 130 may be disposed on the ceramic substrate 110. The upper redistribution structure 130 may include a plurality of third insulating layers 132 and a third circuit wiring layer 134 disposed between the plurality of third insulating layers 132. The upper redistribution structure 130 may be a redistribution substrate formed by a redistribution process. However, not limited thereto, the upper redistribution structure 130 may correspond to any one of a PCB, an MCPCB, an MPCB, and an FPCB.

[0097] In an embodiment, the semiconductor package 300 may include a first pad 152 disposed on a lower surface of the lower redistribution structure 120 and a second pad 154 disposed on an upper surface of the upper redistribution structure 130. A connection bump 156 may be disposed on the second pad 154. The connection bump 156 may be disposed to contact the second pad 154. The connection bump 156 may electrically connect the first semiconductor chip ch1 and the second semiconductor chip ch2 to the upper redistribution structure 130. For example, the connection bump 156 may be formed of a pillar structure, a ball structure, or a solder layer.

[0098] The first semiconductor chip ch1 and the second semiconductor chip ch2 may be mounted on the upper redistribution structure 130. For example, the first semiconductor chip ch1 and the second semiconductor chip ch2 may be mounted on the upper redistribution structure 130 through the connection bumps 156 using a flip chip method. In some embodiments, an underfill material layer 390 surrounding the connection bumps 156 may be disposed between the first semiconductor chip ch1 and the second semiconductor chip ch2 and the upper redistribution structure 130. The underfill material layer 390 may be made of, for example, an epoxy resin formed using a capillary underfill method. In some embodiments, the underfill material layer 390 may be a non-conductive film (NCF).

[0099] The first semiconductor chip ch1 may be a logic semiconductor chip. For example, the first semiconductor chip ch1 may include a logic semiconductor chip such as a CPU, a GPU, an AP, an ASIC, or other processing chips. However, the first semiconductor chip ch1 is not limited thereto and may include a memory semiconductor chip.

[0100] The second semiconductor chip ch2 may be a memory semiconductor chip. For example, the second semiconductor chip ch2 may be a volatile memory semiconductor chip such as DRAM or SRAM, or a non-volatile memory semiconductor chip such as PRAM, MRAM, FeRAM, or RRAM. In some embodiments, the second semiconductor chip ch2 may be a high bandwidth memory (HBM) chip that increases bandwidth by stacking DRAM in multiple layers. However, the first semiconductor chip ch2 is not limited thereto, and may include a memory semiconductor chip.

[0101] The capacitor structure 380 may be disposed at an interface between the ceramic substrate 110 and the upper redistribution structure 130 . In addition, the capacitor structure 380 may be disposed adjacent to the first semiconductor chip ch1 . For example, the capacitor structure 380 may be disposed between the first semiconductor chip ch1 and the ceramic substrate 110 .

[0102] The capacitor structure 380 may include a lower electrode layer LE, a dielectric layer DL, and an upper electrode layer UE ( Fig.13 ), and may be a capacitor having a metal-insulator-metal (MIM) structure.

[0103] The lower electrode layer LE may be disposed on the upper surface of the ceramic substrate 110. For example, the lower electrode layer LE may be disposed at a higher vertical level than the plurality of first wiring layers 114L.

[0104] In an embodiment, the lower electrode layer LE may include a first conductive material, and the first conductive material may include silver (Ag) or tungsten (W). The lower electrode layer LE may include the same material as the material constituting the first circuit wiring layer 114. The lower electrode layer LE may be formed on the upper surface of the ceramic substrate 110 using an electroplating process or the like. The lower electrode layer LE may have a predetermined thickness. For example, the lower electrode layer LE may have a thickness ranging from about 1 μm to about 10 μm.

[0105] The dielectric layer DL may be disposed on the lower electrode layer LE on the ceramic substrate 110. In an embodiment, the dielectric layer DL may include a high-k dielectric material. The high-k dielectric material may refer to a material having a dielectric constant greater than that of silicon oxide. In an embodiment, the dielectric layer DL may include a material having a dielectric constant of about 5 or greater, or about 10 or greater. For example, the dielectric layer DL may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof, but the dielectric layer DL is not limited thereto.

[0106] The thickness of the dielectric layer DL may be, for example, about 1 μm to about 5 μm. Since the dielectric layer DL is formed of a high-k dielectric material and has a relatively thin thickness, the capacitor structure 380 may exhibit a relatively high capacitance.

[0107] The upper electrode layer UE may be disposed on the upper surface of the dielectric layer DL. The upper electrode layer UE may include a second conductive material, and the second conductive material may be different from the first conductive material. For example, the second conductive material may include at least one of copper (Cu), nickel (Ni), gold (Au), platinum (Pt), titanium (Ti), chromium (Cr), and alloys thereof. However, the second conductive material is not limited thereto, and the first conductive material may be the same as the second conductive material. The upper electrode layer UE may include the same material as the material constituting the third circuit wiring layer 134. The upper electrode layer UE may be formed on the upper surface of the dielectric layer DL using an electroplating process or the like. The upper electrode layer UE may have a predetermined thickness. For example, the upper electrode layer UE may have a thickness ranging from about 1 μm to about 10 μm.

[0108] In an embodiment, the lower electrode layer LE of the capacitor structure 380 may be electrically connected to the first via 114V of the ceramic substrate 110. The lower electrode layer LE may be electrically connected to the first wiring layer 114L through the first via 114V. The upper electrode layer UE of the capacitor structure 380 may be electrically connected to the third via 134V of the upper redistribution structure 130. The upper electrode layer UE may be electrically connected to the third wiring layer 134L through the third via 134V. The lower electrode layer LE may include the same material as the first wiring layer 114L, and the upper electrode layer UE may include the same material as the third wiring layer 134L.

[0109] The ceramic substrate 110 has a low CTE and effectively prevents warping of the semiconductor package 300 due to the material properties of the ceramic substrate 110. In addition, the manufacturing process time of the semiconductor package 300 including the ceramic substrate 110 of the present inventive concept can be shortened. In addition, due to the characteristics of the ceramic material, a high temperature process can be performed, so the functional characteristics of the semiconductor package 300 can be improved.

[0110] In addition, since a high temperature process is possible due to the characteristics of ceramic materials, the capacitor structure 380 may have a MIM structure. Therefore, by forming the capacitor structure 380 adjacent to the logic semiconductor chip, the power integrity (PI) characteristics of the logic semiconductor chip may be improved.

[0111] Fig.14 and Fig.15 is a cross-sectional view schematically illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0112] Reference Fig.14 , a capacitor structure 380 may be formed on the ceramic substrate 110. The method of forming the ceramic substrate 110 and the lower redistribution structure 120 may be the same as described above. Figures 5 to 10 The method of manufacturing a semiconductor package may be formed by sequentially stacking a lower electrode layer LE, a dielectric layer DL, and an upper electrode layer UE on a ceramic substrate 110.

[0113] In some embodiments, the lower electrode layer LE may be formed simultaneously in the process of forming the first circuit wiring layer 114. The dielectric layer DL may be formed on the lower electrode layer LE, and the upper electrode layer UE may be formed on the dielectric layer DL.

[0114] In embodiments, the dielectric layer DL may be formed using a high-k dielectric material by at least one of a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, and a spray coating process.

[0115] Therefore, a capacitor structure 380 having a MIM structure including the lower electrode layer LE, the dielectric layer DL, and the upper electrode layer UE may be formed.

[0116] Reference Fig.15 , an upper redistribution structure 130 may be formed on the upper surface of the ceramic substrate 110. The upper redistribution structure 130 may cover the capacitor structure 380. The upper redistribution structure 130 may include a third insulating layer 132 and a third circuit wiring layer 134. The method of forming the upper redistribution structure 130 may be the same as described above with reference to Fig.11 The method described is the same.

[0117] Refer again Fig.12 , the first semiconductor chip ch1 and the second semiconductor chip ch2 may be mounted on the upper redistribution structure 130 using connection bumps 156. The connection bumps 156 may electrically connect the first semiconductor chip ch1 and the second semiconductor chip ch2 to the upper redistribution structure 130.

[0118] An underfill material layer 390 surrounding the connection bumps 156 may be disposed between the first and second semiconductor chips ch1 and ch2 and the upper redistribution structure 130. The underfill material layer 390 may be made of, for example, epoxy resin formed using a capillary underfill method.

[0119] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor package, comprising: a ceramic substrate having a cavity; a lower redistribution structure located on a lower surface of the ceramic substrate and electrically connected to the ceramic substrate; an upper redistribution structure located on an upper surface of the ceramic substrate and electrically connected to the ceramic substrate; a plurality of semiconductor chips, the plurality of semiconductor chips being arranged on the upper redistribution structure along a first direction; as well as A bridge chip structure is located in the cavity of the ceramic substrate and includes a bridge chip electrically connecting the plurality of semiconductor chips to each other.

2. The semiconductor package according to claim 1, wherein: The bridge chip structure further includes a bridge column and an upper bridge pad that electrically connects the bridge chip and the plurality of semiconductor chips to each other.

3. The semiconductor package according to claim 2, wherein: The bridge chip includes a silicon through-via extending through the bridge chip to the ceramic substrate.

4. The semiconductor package according to claim 3, wherein: The bridge chip structure further includes a lower bridge pad connected to the through silicon via of the bridge chip. 5 . The semiconductor package of claim 1 , further comprising an encapsulation layer encapsulating the bridge chip structure within the cavity.

6. The semiconductor package according to claim 5, wherein: The encapsulation layer includes ceramic material, resin or a combination thereof.

7. The semiconductor package according to claim 1, wherein: The depth of the cavity into the ceramic substrate is in the range of 80 μm to 200 μm. 8 . The semiconductor package of claim 1 , further comprising a capacitor structure at an interface between the ceramic substrate and the upper redistribution structure, wherein the capacitor structure is between a first semiconductor chip among the plurality of semiconductor chips and the ceramic substrate.

9. The semiconductor package according to claim 1, wherein: The plurality of semiconductor chips include logic semiconductor chips or memory semiconductor chips.

10. The semiconductor package according to claim 1, wherein The bridge chip structure also includes one or more of a capacitor, an inductor, and a switch.

11. A semiconductor package, comprising: a ceramic substrate having a cavity, the ceramic substrate comprising a plurality of first insulating layers and a first circuit wiring layer between the plurality of first insulating layers; a lower redistribution structure on a lower surface of the ceramic substrate, the lower redistribution structure comprising a plurality of second insulating layers and a second circuit wiring layer between the plurality of second insulating layers and electrically connected to the first circuit wiring layer; an upper redistribution structure on an upper surface of the ceramic substrate, the upper redistribution structure comprising a plurality of third insulating layers and a third circuit wiring layer between the plurality of third insulating layers and electrically connected to the first circuit wiring layer; a plurality of semiconductor chips, the plurality of semiconductor chips being arranged on the upper redistribution structure along a first direction; a bridge chip structure located in the cavity of the ceramic substrate and including a bridge chip electrically connecting the plurality of semiconductor chips to each other; as well as A packaging layer is used to package the bridge chip structure in the cavity, wherein the packaging layer includes ceramic material, resin or a combination thereof.

12. The semiconductor package according to claim 11, wherein The depth of the cavity into the ceramic substrate is in the range of 80 μm to 200 μm.

13. The semiconductor package according to claim 11, Also included is a capacitor structure at an interface between the ceramic substrate and the upper redistribution structure, in, The capacitor structure includes a lower electrode layer on an upper surface of the ceramic substrate, a dielectric layer on an upper surface of the lower electrode layer, and an upper electrode layer on an upper surface of the dielectric layer.

14. The semiconductor package according to claim 13, wherein: The lower electrode layer is connected to the first circuit wiring layer, and the upper electrode layer is connected to the third circuit wiring layer.

15. The semiconductor package according to claim 13, wherein: The lower electrode layer includes the same material as the first circuit wiring layer, and the upper electrode layer includes the same material as the third circuit wiring layer.

16. The semiconductor package according to claim 15, wherein: The lower electrode layer includes silver or tungsten, and the upper electrode layer includes at least one of copper, nickel, gold, platinum, titanium, chromium, and alloys thereof.

17. The semiconductor package according to claim 11, wherein: An upper surface of the packaging layer is coplanar with an upper surface of the ceramic substrate.

18. A semiconductor package, comprising: a ceramic substrate having a cavity, the ceramic substrate comprising a plurality of first insulating layers and a first circuit wiring layer between the plurality of first insulating layers; a lower redistribution structure located on a lower surface of the ceramic substrate, the lower redistribution structure comprising a plurality of second insulating layers and a second circuit wiring layer between the plurality of second insulating layers and electrically connected to the first circuit wiring layer; an upper redistribution structure located on an upper surface of the ceramic substrate, the upper redistribution structure comprising a plurality of third insulating layers and a third circuit wiring layer between the plurality of third insulating layers and electrically connected to the first circuit wiring layer; a plurality of semiconductor chips arranged on the upper redistribution structure along a first direction and including logic semiconductor chips or high bandwidth memory semiconductor chips; a bridge chip structure located in the cavity of the ceramic substrate and including a bridge chip electrically connecting the plurality of semiconductor chips to each other; a packaging layer, which encapsulates the bridge chip structure in the cavity of the ceramic substrate, wherein the packaging layer comprises a ceramic material, a resin or a combination thereof; as well as A capacitor structure is provided at an interface between the ceramic substrate and the upper redistribution structure, the capacitor structure comprising a lower electrode layer on an upper surface of the ceramic substrate, a dielectric layer on an upper surface of the lower electrode layer, and an upper electrode layer on an upper surface of the dielectric layer.

19. The semiconductor package according to claim 18, wherein: The lower electrode layer is connected to the first circuit wiring layer, and the upper electrode layer is connected to the third circuit wiring layer.

20. The semiconductor package according to claim 18, wherein The vertical depth of the cavity into the ceramic substrate is in the range of 80 μm to 200 μm.

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