Method of manufacturing semiconductor device and semiconductor structure

Abstract

A method of manufacturing a semiconductor device includes forming a first multilayer interconnect structure over a first side of a device layer, the first multilayer interconnect structure including a patterned first metal layer disposed in a first dielectric layer, the device layer having a second side opposite the first side; forming a first portion of a second multilayer interconnect structure under a second side of the device layer, the first portion of the second multilayer interconnect structure including a patterned second metal layer disposed in a second dielectric layer; a trench extending through the second dielectric layer, the device layer, and the first dielectric layer is formed, a conductive structure is formed in the trench, and a second portion of the second multilayer interconnect structure is formed below the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes patterned third metal layers disposed in the third dielectric layer, and wherein one or more of the patterned third metal layers are electrically connected with the conductive structure. The embodiment of the invention also relates to a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to methods of manufacturing semiconductor devices and semiconductor structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Continuous advances in semiconductor manufacturing processes have resulted in integrated circuits ("ICs") having semiconductor devices with finer components and / or higher levels of integration. Functional density (i.e., the number of interconnected devices per IC chip area) has generally increased, while component size (i.e., the smallest component that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] Advanced IC packaging techniques have been developed to further reduce the density of ICs incorporated into many electronic devices and / or to improve the performance of ICs. For example, IC packaging has evolved so that multiple ICs can be stacked vertically in so-called three-dimensional ("3D") packages or 2.5D packages (using an interposer). A through-via (also known as a through-silicon via or through-substrate via (TSV)) is a technology for electrically and / or physically connecting stacked ICs. Although existing through-vias are generally adequate for their intended purpose, they are not completely satisfactory in all respects. Summary of the invention

[0004] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: forming a first multilayer interconnect structure above a first side of a device layer, wherein the first multilayer interconnect structure includes a patterned first metal layer disposed in a first dielectric layer, and the device layer has a second side opposite to the first side; forming a first portion of a second multilayer interconnect structure below the second side of the device layer, wherein the first portion of the second multilayer interconnect structure includes a patterned second metal layer disposed in the second dielectric layer; forming a groove extending through the second dielectric layer, the device layer and the first dielectric layer; forming a conductive structure in the groove; and forming a second portion of the second multilayer interconnect structure below the first portion of the second multilayer interconnect structure, wherein the second portion of the second multilayer interconnect structure includes a patterned third metal layer disposed in a third dielectric layer, and wherein one or more of the patterned third metal layers are electrically connected to the conductive structure.

[0005] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: receiving a first workpiece including a device layer; depositing a first dielectric layer on the front side of the device layer; forming a front portion of a guard ring in the first dielectric layer; depositing a second dielectric layer on the back side of the device layer; forming a back portion of the guard ring in the second dielectric layer; forming a groove extending through a portion of the first dielectric layer surrounded by the front portion of the guard ring and through a portion of the second dielectric layer surrounded by the back portion of the guard ring; forming a through hole in the groove; forming one or more metal layers in the second dielectric layer, wherein the one or more metal layers are located below and electrically connected to the through hole; and joining the second workpiece to the first workpiece, wherein the through hole is electrically connected to a conductive feature formed in the second workpiece.

[0006] Another embodiment of the present disclosure provides a semiconductor structure, which includes: a device layer having a first side and a second side; a first dielectric layer disposed above the first side of the device layer; a second dielectric layer disposed below the second side of the device layer; a guard ring having a front portion disposed in the first dielectric layer and a back portion disposed in the second dielectric layer; a metal line disposed in the second dielectric layer below the back portion of the guard ring; and a through hole extending through the first dielectric layer and the device layer and in physical contact with the metal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noteworthy that, in accordance with standard industry practice, the various components are not drawn to scale and are only used for illustration purposes. For clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a partial cross-sectional view of a semiconductor structure having front-side and back-side interconnect structures and through-vias according to various aspects of the present disclosure.

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D According to various aspects of the present disclosure Figure 1 An enlarged cross-sectional view of a portion of a semiconductor structure.

[0010] Figure 3 It is shown that various aspects of the present disclosure can be Figure 1 A top view of a partial or complete guard ring and a corresponding TSV implemented in a semiconductor structure.

[0011] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 are partial cross-sectional views of a portion or an entire workpiece at various fabrication stages of forming TSVs and corresponding guard rings according to various aspects of the present disclosure.

[0012] Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 A method of attaching a semiconductor structure to another semiconductor structure according to various aspects of the present disclosure is shown. Figure 1 Various embodiments of partial schematic cross-sectional views of a semiconductor arrangement of a portion or the entire semiconductor structure. DETAILED DESCRIPTION

[0013] The present disclosure relates generally to integrated circuit (IC) packaging, and more particularly, to an enhanced through via structure for a semiconductor device having a backside interconnect structure.

[0014] The following disclosure provides many different embodiments or examples of different components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] In addition, as understood by those of ordinary skill in the art, when "about," "approximately," and the like are used to describe a value or a range of values, the term is intended to encompass values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, a value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / -10% of the described value. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.5 nm to 5.5 nm, where, as known to those of ordinary skill in the art, the manufacturing tolerance associated with depositing material layers is known to be ±10%. In another example, two components described as having "substantially the same" size and / or being "substantially" oriented (e.g., "substantially parallel") in a particular direction and / or configuration encompass size differences between the two components and / or slight orientation differences of the two components from the precisely specified orientation, which may be inherent, but not intentional, caused by manufacturing tolerances associated with manufacturing the two components. Further, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0017] The interconnect structure electrically couples various components (e.g., transistors, resistors, capacitors, and / or inductors) fabricated on a substrate so that the various components can operate in a manner specified by design requirements. The interconnect structure includes a combination of a dielectric layer and a conductive layer configured to provide electrical signal routing. The conductive layer includes vias and contact components that provide vertical connections and wires that provide horizontal connections. In some embodiments, the interconnect structure may have a plurality of metal layers (or metallization layers) vertically interconnected by vias or contact components. During operation of the IC device, the interconnect structure routes signals between components of the IC device and / or distributes signals (e.g., clock signals, voltage signals, and / or ground signals) to components. The interconnect structure is formed in a back-end-of-line (BEOL) process, typically after a front-end-of-line (FEOL) process forms active devices (such as transistors) on a substrate and a middle-end-of-line (MEOL) process forms source / drain contact plugs and gate contact plugs.

[0018] In some embodiments, it is desirable to provide a vertical interconnect extending through an interconnect structure and / or a substrate to facilitate interconnection between various device structures, such as CMOS image sensors (CIS), three-dimensional integrated circuits (3DIC), MEMS devices, radio frequency (RF) devices, wafer-on-wafer (WoW) devices, etc. Such a vertical interconnect may be referred to as a through silicon via or through substrate via (TSV) because it extends in whole or in part through a semiconductor substrate. The term TSV in the present disclosure broadly encompasses a through-hole structure that provides direct power and / or signal routing from the front side of a substrate to the back side of a substrate or vice versa.

[0019] Guard rings are typically formed around TSVs to protect the TSVs, improve TSV performance, improve TSV structural stability, shield and / or reduce TSV-induced noise that may negatively affect signal integrity, or a combination thereof. Guard rings may be formed when forming the BEOL structure of a semiconductor device. TSVs may be formed after the BEOL structure is formed, for example by etching through a dielectric layer of the BEOL structure in an area defined by the guard ring and through a device layer to form a TSV trench, and filling the TSV trench with a conductive material. Such a TSV formation process is typically compatible with semiconductor devices having a front-side interconnect structure.

[0020] Traditionally, semiconductor devices are built in a stacked manner, with transistors at the lowest level and interconnect structures (contacts, vias, and metal lines) located on top of the transistors to provide connections to the transistors. Power rails (such as metal lines for voltage sources and ground planes) are also above the transistors and can be part of the interconnect structures. As integrated circuits continue to scale down, the power rails are also continuously scaled down. This inevitably leads to an increase in the voltage drop across the power rails, and an increase in the power consumption of the integrated circuit. In addition to the power rails, signal lines may also be affected by this scaling down, such as the ever-decreasing signal line spacing, which inevitably leads to an increase in parasitic capacitance and a decrease in circuit speed. Therefore, although existing methods in semiconductor manufacturing are generally sufficient to meet their intended purposes, they are not completely satisfactory in all aspects. One area of ​​interest is how to form a backside interconnect structure with reduced resistance and parasitic capacitance, including power rails and / or signal lines and vias on the back side of the IC. Implementing a backside interconnect structure in a semiconductor device poses new challenges to TSV formation. TSVs may extend through the device layers of a semiconductor device, but may be blocked by a backside interconnect structure.

[0021] The present disclosure provides a TSV with a guard ring, the guard ring comprising a combination of a front side component and a back side component, the front side component and the back side component are compatible with semiconductor manufacturing of devices with a front side interconnect structure and a back side interconnect structure as components. The details of the proposed TSV structure and its manufacture are described below. Different embodiments may have different advantages, and no embodiment requires a specific advantage.

[0022] Figure 1 is a partial cross-sectional view of a semiconductor structure 100 having an improved TSV design in part or in whole according to various aspects of the present disclosure. Figure 2A , Figure 2B , Figure 2C and Figure 2D According to various aspects of the present disclosure Figure 1 FIG. 1 is an enlarged cross-sectional view of a portion of the semiconductor structure 100 . Figure 3 According to various aspects of the present disclosure, Figure 1 FIG. 1 is a top view of a partial or complete guard ring and a corresponding TSV implemented in the semiconductor structure 100 . Figures 4 to 11 According to various aspects of the present disclosure, in forming part or whole Figure 1 FIG. 1 is a partial cross-sectional view of a workpiece at various manufacturing stages of the semiconductor structure 100 . Figures 12 to 17 According to various aspects of the present disclosure, Figure 1 The semiconductor structure 100 is a partial cross-sectional view of various semiconductor arrangements of a stacked IC, either partially or in its entirety.

[0023] For ease of description and understanding, this article also discusses Figure 1 and FIG. 2A to FIG. 2D . Figure 2A yes Figure 1 An enlarged view of a region I of the semiconductor structure 100, Figure 1 Region I of the semiconductor structure 100 includes a plurality of transistors formed in a device layer. Figure 2B yes Figure 1 An enlarged view of region II of the semiconductor structure 100, Figure 1 Region II of the semiconductor structure 100 includes TSVs and backside top metal features. Figure 2C yes Figure 1 An enlarged view of region III of the semiconductor structure 100, Figure 1 Region III of the semiconductor structure 100 is located in the active region, where the source / drain components are adjacent to the front side components and the back side components of the guard ring. The active region refers to the region where the source region, the drain region and the channel region of the transistor are formed. In this context, the active region is also referred to as the "oxide definition (OD) region". Figure 2D In an optional embodiment Figure 1FIG. 1 is an enlarged view of region III of semiconductor structure 100, region III being located in an isolation region (eg, a shallow trench isolation (STI) region), wherein a via passing through the isolation region abuts the front side component and the back side component of the guard ring. For clarity, Figure 1 and FIG. 2A to FIG. 2D It has been simplified for a better understanding of the inventive concepts of the present disclosure. Additional components may be added to the semiconductor structure 100 , and some of the components described below may be replaced, modified, or eliminated in other embodiments of the semiconductor structure 100 .

[0024] exist Figure 1 , the semiconductor structure 100 includes a device region 100a in which a device is formed and a TSV region 100b in which a TSV and a guard ring are formed. The semiconductor structure 100 includes a device layer 102, a front side multi-layer interconnect (FMLI) structure 110 disposed above the device layer 102, a back side multi-layer interconnect (BMLI) structure 112 disposed below the device layer 102, and a carrier wafer (e.g., a silicon wafer) 122 bonded to the FMLI structure 110, such as by a bonding layer 124.

[0025] Device layer 102 has a side 104 (e.g., a front side) and a side 106 (e.g., a back side) opposite side 104. Device layer 102 may include circuits fabricated on and / or over side 104 by front end of line (FEOL) processing. For example, device layer 102 may include various device components / parts, such as a semiconductor substrate, a doped well (e.g., an n-well and / or a p-well), an isolation component (e.g., a shallow trench isolation (STI) structure and / or other suitable isolation structures), a metal gate (e.g., a metal gate having a gate electrode and a gate dielectric), a gate spacer along a sidewall of the metal gate, a source / drain component (e.g., an epitaxial source / drain), other suitable device components / parts, or a combination thereof. In some embodiments, device layer 102 includes a planar transistor, wherein a channel of the planar transistor is formed in the semiconductor substrate between corresponding sources / drains, and a corresponding metal gate is disposed on the channel (e.g., on a portion of the semiconductor substrate where the channel is formed). In some embodiments, the device layer 102 includes a non-planar transistor having a channel formed in a semiconductor fin extending from a semiconductor substrate and between corresponding source / drain electrodes on / in the semiconductor fin, wherein a corresponding metal gate is disposed on the channel of the semiconductor fin and wraps around the channel of the semiconductor fin (i.e., the non-planar transistor is a fin field effect transistor (FinFET)). In some embodiments, the device layer 102 includes a non-planar transistor having a channel formed in a semiconductor layer suspended above a semiconductor substrate and extending between corresponding source / drain electrodes, wherein a corresponding metal gate is disposed on the channel and surrounds the channel (i.e., the non-planar transistor is a gate-all-around (GAA) transistor). Depending on design requirements, the various transistors of the device layer 102 may be configured as planar transistors and / or non-planar transistors.

[0026] The device layer 102 may include various passive microelectronic devices and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal oxide semiconductor (MOS) FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), lateral diffusion MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. The various microelectronic devices may be configured to provide functionally different regions of the IC, such as a logic region (i.e., a core region), a memory region, an analog region, a peripheral region (e.g., an input / output (I / O) region), a pseudo region, other suitable regions, or combinations thereof. The logic region may be configured with standard cells, each of which may provide a logic device and / or logic function, such as an inverter, an AND gate, a NAND gate, an OR gate, a NOR gate, a NOT gate, an XOR gate, an XNOR gate, other suitable logic devices, or combinations thereof. The memory region may be configured with memory cells, each of which may provide a memory device and / or storage function, such as flash memory, non-volatile random access memory (NVRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other volatile memory, other non-volatile memory, other suitable memory, or a combination thereof. In some embodiments, the memory cell and / or logic cell include transistors and interconnect structures that are combined to provide a memory device / function and a logic device / function, respectively.

[0027] Figure 2A yes Figure 1 FIG. 1 is an enlarged view of a region I of a semiconductor structure 100, wherein the region I includes a plurality of transistors formed in a device layer 102. Figure 2A, the device layer 102 includes a semiconductor substrate 202 and various transistors, such as transistor T1 and transistor T2. Transistors T1 and T2 each include a respective gate structure 208 (which may include a gate spacer disposed along a gate stack (e.g., a gate electrode disposed above a gate dielectric)) disposed between respective source / drain features 212 (e.g., epitaxial source / drain features), the gate structure 208 being disposed on, in, and / or above the semiconductor substrate 202 at locations where a channel extends between the respective source / drain features 212 in the semiconductor substrate 202. The device layer 102 may also include an isolation structure 214, such as a shallow trench isolation (STI) feature, which separates and / or electrically isolates the transistors in the device layer 102 from other transistors or devices. The device layer 102 also includes a dielectric layer 218. The dielectric layer 218 may include an interlayer dielectric (ILD) layer and / or a contact etch stop layer (CESL). Disposed over dielectric layer 218 is dielectric layer 222 , which may similarly include an ILD layer and an etch stop layer (ESL).

[0028] A gate contact (or gate via) 232 is disposed in the dielectric layer 222, a source / drain contact 234 is disposed in the dielectric layer 218, and a contact via 236 is disposed in the dielectric layer 222. The gate contact 232 electrically and physically connects the gate structure 208 (specifically, the gate electrode) to a metal line 240 in a metal zero interconnect layer (M0 level) of a front-side multi-layer interconnect (FMLI) structure 110, and the source / drain contact 234 and the contact via 236 electrically and physically connect the front side of the source / drain feature 212 to the metal line 240 in the M0 level of the FMLI structure 110. The dielectric layer 222, the gate contact 232, and the contact via 236 form a via zero interconnect layer (V0 level) of the FMLI structure 110. On the back side of the device layer 102, the back side dielectric layer 224 is disposed below the semiconductor substrate 202. The backside source / drain contact 242 extends through the semiconductor substrate 202, and the backside source / drain contact 242 electrically and physically connects the backside of the source / drain contact 234 to the metal line 244 in the backside metal zero interconnect layer (BM0 level) of the backside multi-layer interconnect (BMLI) structure 112. The front side and the back side of the source / drain feature 212 can each have a silicide layer 246 in physical contact with the source / drain contact 234 and the backside source / drain contact 242. The silicide layer 246 reduces the contact resistance. The semiconductor substrate 202 and the backside source / drain contact 242 form the backside via zero interconnect layer (BV0 level) of the BMLI structure 112.

[0029] Return to reference Figure 1, a front-side multi-layer interconnect (FMLI) structure 110 is disposed above the device layer 102, and a back-side multi-layer interconnect (BMLI) structure 112 is disposed below the device layer 102. Each of the FMLI structure 110 and the BMLI structure 112 may include one or more interconnect layers. In the device region 100a, the FMLI structure 110 and the BMLI structure 112 electrically couple various devices and / or components (such as Figure 2A In the TSV region 100b, the FMLI structure 110 and the first portion of the BMLI structure 112 form a TSV protection ring 150. In the TSV region 100b, the second portion of the BMLI structure 112 is physically and electrically connected to the TSV 132.

[0030] In the depicted embodiment, the FMLI structure 110 includes a via zero interconnect layer (V0 level), a metal zero interconnect layer (M0 level), a via one interconnect layer (V1 level), a metal one interconnect layer (M1 level), a via two interconnect layer (V2 level), a metal two interconnect layer (M2 level), a via three interconnect layer (V3 level), a metal three interconnect layer (M3 level), up to a via x interconnect layer (Vx level) and a metal x interconnect layer (Mx level), where x represents an integer (e.g., from 2 to 10).

[0031] Each of the V0 level, M0 level, V1 level, M1 level, V2 level, M2 level, V3 level, M3 level, ... Vx level, and Mx level may be referred to as a metal level. A metal line formed at the M0 level may be referred to as an M0 metal line. Similarly, vias or metal lines formed at the V1 level, M1 level, V2 level, M2 level, V3 level, M3 level, ... Vx level, and Mx level may be referred to as V1 vias, M1 metal lines, V2 vias, M2 metal lines, V3 vias, M3 metal lines, ... Vx vias, Mx metal lines, respectively. Each level of the FMLI structure 110 includes conductive features (e.g., metal lines 116, metal vias 118, and / or metal contacts) disposed in one or more dielectric layers (e.g., interlayer dielectric (ILD) layers and etch stop layers (ESL)). The dielectric layer (eg, Figure 2A 10) are collectively referred to as dielectric structures 115. In some embodiments, the conductive features at the same level (such as the M0 level) of the FMLI structure 110 are formed simultaneously. In some embodiments, the conductive features at the same level of the FMLI structure 110 have top surfaces that are substantially planar with each other and / or bottom surfaces that are substantially planar with each other.

[0032] As above combined Figure 2AAs discussed, the source / drain contacts may be formed on and in direct contact with a silicide layer disposed directly on the source / drain features. The V0 level includes a gate contact disposed on a gate structure and a contact via disposed on the source / drain contact, wherein the gate contact connects the gate structure to an M0 metal line and the contact via connects the source / drain contact to the M0 metal line. The V1 level includes a V1 via disposed in a dielectric structure 115, wherein the V1 via connects the M0 metal line to an M1 metal line. The M1 level includes an M1 metal line disposed in a dielectric structure 115. The V2 level includes a V2 via disposed in a dielectric structure 115, wherein the V2 via connects the M1 metal line to an M2 metal line. The M2 level includes an M2 metal line disposed in a dielectric structure 115. The V3 level includes a V3 via disposed in a dielectric structure 115, wherein the V3 via connects the M2 metal line to an M3 metal line. Similarly, the Vx level includes Vx vias disposed in the dielectric structure 115 , wherein the Vx vias connect the Mx- 1 metal line to the Mx metal line.

[0033] In the depicted embodiment, the BMLI structure 112 includes a backside via zero interconnect layer (BV0 level), a backside metal zero interconnect layer (BM0 level), a backside via one interconnect layer (BV1 level), a backside metal one interconnect layer (BM1 level), a backside via two interconnect layer (BV2 level), a backside metal two interconnect layer (BM2 level), up to a backside via y interconnect layer (BVy level) and a backside metal y interconnect layer (My level), where y represents an integer (e.g., from 2 to 10).

[0034] Each of the BV0 level, BM0 level, BV1 level, BM1 level, BV2 level, BM2 level, ... BVy level, and BMy level may be referred to as a metal level. A metal line formed at the BM0 level may be referred to as a BM0 metal line. Similarly, vias or metal lines formed at the BV1 level, BM1 level, BV2 level, BM2 level, ... BVy level, and BMy level may be referred to as BV1 vias, BM1 metal lines, BV2 vias, BM2 metal lines, ... BVy vias, BMy metal lines, respectively. Each level of the BMLI structure 112 includes conductive features (e.g., metal lines 116', metal vias 118', and / or metal contacts) disposed in one or more dielectric layers (e.g., interlayer dielectric (ILD) layers and etch stop layers (ESL)). The dielectric layers (e.g., Figure 2AThe backside dielectric layer 224 at the depicted BM0 level is collectively referred to as a dielectric layer (or dielectric structure) 115'. In some embodiments, the conductive features at the same level (such as the BM0 level) of the BMLI structure 112 are formed simultaneously. In some embodiments, the conductive features at the same level of the BMLI structure 112 have top surfaces that are substantially flat with each other and / or bottom surfaces that are substantially flat with each other.

[0035] As above combined Figure 2A As discussed, the back side source / drain contact can be formed on a silicide layer disposed directly below the source / drain component and in direct contact with the silicide layer. The back side contact at the BV0 level connects the source / drain component to the BM0 metal line. The BV1 level includes a BV1 via disposed in the dielectric structure 115', wherein the BV1 via connects the BM0 metal line to the BM1 metal line. The BM1 level includes a BM1 metal line disposed in the dielectric structure 115'. The BV2 level includes a BV2 via disposed in the dielectric structure 115', wherein the BV2 via connects the BM1 metal line to the BM2 metal line. The BM2 level includes a BM2 metal line disposed in the dielectric structure 115'. Similarly, the BVy level includes a BVy via disposed in the dielectric structure 115', wherein the BVy via connects the My-1 metal line to the BMy metal line.

[0036] In the depicted embodiment, the BMLI structure 112 also includes a semiconductor device 120 disposed below and electrically connected to the BMy metal line. In some embodiments, the semiconductor device 120 can be configured, for example, as a DRAM device, an MRAM device, another suitable memory device, a metal-insulator-metal (MIM) structure (e.g., a MIM capacitor), or other semiconductor devices. The present disclosure contemplates that the semiconductor device 120 is disposed between interconnect layers of the BMLI structure 112.

[0037] The contact layer 126 is disposed below the BMLI structure 112, and in the depicted embodiment, the contact layer 126 is disposed below the bottommost metallization layer (e.g., BMy level) of the BMLI structure 112. The contact layer 126 may include contacts 128 arranged in a desired pattern. The contact 128 may facilitate electrical connection of the circuit in the device layer 102 to an external circuit, and thus the contact 128 may be referred to as an external contact. In some embodiments, the contact 128 is an under-bump metallization (UBM) structure. In some embodiments, the contact 128 is a redistribution layer (RDL) structure. The contact 128 may be in physical and electrical contact with the bottom surface of the BMy metal line. Optionally, the contact 128 may be electrically connected to the BMy metal line through a via. In some embodiments, the contact layer 126 includes at least one passivation layer, such as a passivation layer 130 disposed below the dielectric structure 115'. In such an embodiment, the contact 128 is disposed in the passivation layer 130. The passivation layer 130 may include a material different from the dielectric material of the ILD layer in the dielectric structure 115'. In some embodiments, the passivation layer includes polyimide, undoped silicate glass (USG), silicon oxide, silicon nitride, other suitable passivation materials, or combinations thereof. In some embodiments, the dielectric constant of the dielectric material of the passivation layer is greater than the dielectric constant of the ILD layer in the dielectric structure 115'. The passivation layer 130 may have a multilayer structure having a plurality of dielectric materials. For example, the passivation layer 130 may include a silicon nitride layer and a USG layer.

[0038] The TSV 132 is disposed in the TSV region 100b. From the bottom up, the TSV 132 is physically positioned on one of the bottom metallization layers of the BMLI structure 112 and extends upward through the dielectric structure 115', the device layer 102, the dielectric structure 115 and partially through the carrier wafer 122. In the depicted embodiment, the TSV 132 is physically positioned on the BMy-1 (second from the bottom) metal line. In addition, in the depicted embodiment, the BMy-1 metal line 116' extends horizontally to a position directly below the guard ring 150. That is, in the depicted embodiment, the guard ring 150 does not extend downward into the bottom metallization layer (e.g., BVy-1, BMy-1, BVy, and BMy metal layers). The present disclosure contemplates that the TSV 132 is positioned on the metal line 116' in other metallization layers of the BMLI structure 112, such as the BMy metal line or the BMy-z metal line, where z is an integer less than y.

[0039] Figure 2B yes Figure 1FIG. 1 is an enlarged view of region II of semiconductor structure 100, wherein TSV 132 is physically positioned on metal line 116' in one of the bottom metallization layers of BMLI structure 112 located in TSV region 100b. TSV 132 and metal line 116' in region II are surrounded by dielectric structure 115'.

[0040] The dielectric structure 115' includes a dielectric material such as silicon oxide, tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), boron-doped silicate glass (BSG), boron-doped PSG (BPSG), a low-k dielectric material (e.g., having a dielectric constant less than that of silicon oxide (e.g., k < 3.9)), other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include fluorosilicate glass (FSG), carbon-doped oxide, Black (Applied Materials, Inc., Santa Clara, Calif.), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK (The Dow Chemical Company, Midland, Mich.), polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, the dielectric structure 115' includes a low-k dielectric material, such as a carbon-doped oxide, or an extremely low-k dielectric material (e.g., k≤2.5), such as a porous carbon-doped oxide.

[0041] The TSV 132 includes a conductive material, including, for example, aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or combinations thereof. In the depicted embodiment, the TSV 132 includes a body metal layer 134 (also referred to as a metal filling layer, a conductive plug, a metal plug, or a combination thereof), a barrier layer 136, and a liner 138. The barrier layer 136 is disposed between the body metal layer 134 and the liner 138. The barrier layer 136 may include titanium, a titanium alloy (e.g., TiN), tantalum, a tantalum alloy (e.g., TaN), other suitable barrier materials (e.g., materials that can prevent metal components from diffusing from the TSV 132 into the dielectric structure 115), or combinations thereof. In some embodiments, the body metal layer 134 is a copper plug or a tungsten plug, and the barrier layer 136 is a metal nitride layer (e.g., a TaN layer or a TiN layer). In some embodiments, the main metal layer 134 includes a seed layer located between the barrier layer 136 and the metal plug. The seed layer may include copper, tungsten, other suitable metals (such as those described herein), alloys thereof, or combinations thereof. In some embodiments, the liner 138 is a dielectric layer located between the barrier layer 136 and the dielectric structure 115'. The liner 138 includes silicon oxide, silicon nitride, other suitable dielectric materials, or combinations thereof. The main metal layer 134, the barrier layer 136, the liner 138, or a combination thereof may have a multilayer structure. In some embodiments, the TSV 132 includes polysilicon (e.g., the metal plug is a polysilicon plug).

[0042] In some embodiments, metal line 116' (as well as metal line 116, vias 118 and 118', contact 128) may include a main metal layer (also referred to as a metal filling layer, a conductive plug, a metal plug, or a combination thereof) 140 and a barrier layer 142. The main metal layer 140 may include a conductive material, including, for example, aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, silicides thereof, or a combination thereof. The barrier layer 142 may include titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other suitable barrier materials (e.g., materials that can prevent metal components from diffusing from the main metal layer 140 into the dielectric structure 115'). In some embodiments, the lower metal line 116' (and the lower metal line 116, the vias 118 and 118') closer to the device layer 102 may include tungsten, ruthenium, cobalt, or a combination thereof, while the upper metal line 116' (and the upper metal line 116, the vias 118 and 118') further away from the device layer 102 may include a different metal material, such as copper. In some embodiments, the metal lines 116 and 116', the vias 118 and 118', and the contact 128 include the same metal material.

[0043] Return to reference Figure 1 , the guard ring 150 surrounds the TSV 132 and is spaced apart from the TSV 132. In some embodiments, the guard ring 150 is electrically connected to a voltage. In some embodiments, the guard ring 150 is electrically connected to an electrical ground. In some embodiments, the guard ring 150 is configured to electrically insulate the TSV 132 from the device components (including the FMLI structure 110, the BMLI structure 112, and the device layer 102) in the device region 100a. In some embodiments, the guard ring 150 absorbs thermomechanical stress from the TSV 132, within the TSV 132, and / or around the TSV 132. In some embodiments, the guard ring 150 reduces thermomechanical stress from the TSV 132, within the TSV 132, and / or around the TSV 132. In some embodiments, the guard ring 150 reduces or eliminates cracks and / or delamination in the semiconductor structure 100. In some embodiments, the guard ring 150 provides structural support, integrity, enhancement, or a combination thereof for the TSV 132.

[0044] In the depicted embodiment, the guard ring 150 has a front side component disposed in the dielectric structure 115 and a back side component disposed in the dielectric structure 115'. The front side component of the guard ring 150 is formed by a portion of the FMLI structure 110 in the TSV area 100b. Each layer of the front side component of the guard ring 150 includes a corresponding metal line 116 and a corresponding via 118. The back side component of the guard ring 150 is formed by a first portion of the BMLI structure 112 in the TSV area 100b. Each layer of the back side component of the guard ring 150 includes a corresponding metal line 116' and a corresponding via 118'. Specifically, the back side component of the guard ring 150 is formed by a portion of the BMLI structure 112 above the metallization layer on which the TSV 132 is physically positioned. In the depicted embodiment, the TSV 132 is physically positioned on the BMy-1 metal line, and the guard ring 150 starts from the BMy-2 metal line. In the depicted embodiment, there is no BVy- 1 via in the TSV region 100 b such that the BMy- 2 metal line of the guard ring 150 has no electrical connection to the BMy- 1 metal line and, therefore, has no electrical connection to the TSV 132 .

[0045] Figure 2C yes Figure 11 is an enlarged view of region III of the semiconductor structure 100, wherein the guard ring 150 is formed in the active region. The bottom layer of the front side components of the guard ring 150 (e.g., the metal line 240 in the M0 level and the contact via 236 in the V0 level) is physically connected and / or electrically connected to the source / drain contact 234 and the front side of the source / drain component 212. The top layer of the back side components of the guard ring 150 (e.g., the metal line 244 in the BMO level and the back side source / drain contact 242) is physically and electrically connected to the back side of the source / drain component 212. The front side components of the guard ring 150 and the back side components of the guard ring 150 are electrically connected through the source / drain component 212 (and the silicide layer 246, if present).

[0046] Figure 2D In an optional embodiment Figure 1 1 is an enlarged view of region III of the semiconductor structure 100, wherein the guard ring 150 is formed in the STI region. Since there is no source / drain component in the STI region, unlike the active region, a through hole 250 is formed in the device layer 102. The through hole 250 extends through the semiconductor substrate 202, the STI component 214 and the dielectric layer 218. The through hole 250 connects the bottom layer of the front side component of the guard ring 150 (e.g., the metal line 240 in the M0 level and the contact through hole 236 in the V0 level) and the back side component of the guard ring 150 (e.g., the metal line 244 in the BMO level). The through hole 250 may include a main metal layer and a barrier layer. The main metal layer may include a conductive material, including, for example, aluminum, copper, titanium, tantalum, tungsten, ruthenium, cobalt, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, their alloys, their silicides, or combinations thereof. The barrier layer may include titanium, titanium alloys (e.g., TiN), tantalum, tantalum alloys (e.g., TaN), other suitable barrier materials. In some embodiments, via 250, metal line 240, contact via 236, and metal line 244 may include the same metal material. In alternative embodiments, via 250 may include a different metal material than metal line 240, contact via 236, and metal line 244.

[0047] Reference now Figure 3 , Figure 3 Top views of the guard ring 150 and corresponding TSV 132 in various configurations I-VII are provided. Figure 1 One or more of these configurations are simultaneously implemented in the semiconductor structure 100. In each of these depicted configurations I-VII, the TSV 132 exhibits a circular shape when viewed from the top. However, it is worth noting that the TSV 132 may also exhibit a variety of other shapes, including squares, diamonds, trapezoids, hexagons, octagons, or any other suitable shape.

[0048] In configuration I, when viewed from above, the guard ring 150 surrounds the TSV 132 in a continuous circular ring manner. Alternatively, the guard ring 150 can be in a discontinuous configuration consisting of discrete segments. In addition, in some cases, the guard ring 150 can have different shapes. For example, in configuration II, the guard ring 150 can have the form of a square ring. In configuration III, the guard ring 150 can have the form of an octagonal ring. Configuration IV shows a double square ring, in which the inner ring and the outer ring are concentric and electrically connected by conductive taps 152 distributed along the opposite edges of the two rings.

[0049] The guard rings 150 may also share one or more common edges when corresponding TSVs 132 are adjacent to each other. For example, configuration V shows two guard rings 150 that share a common edge between two adjacent TSVs 132. In configuration VI, four guard rings 150 are arranged in a 2×2 array, and the four guard rings 150 have a common edge between adjacent pairs of TSVs 132. In addition, in some scenarios, multiple TSVs 132 may share a single guard ring 150 in common. For example, configuration VII shows a single guard ring (150) around four TSVs 132 arranged in a 2×2 array.

[0050] In configurations I-VII, the guard ring 150 is formed by dielectric structures 115 and 115' ( Figure 1) is separated from the corresponding TSV 132. In some embodiments, the spacing between the guard ring 150 and the corresponding TSV 132 is about 0.2 μm to about 0.5 μm to maximize the protection and / or shielding provided by the guard ring 150 to the TSV 132. A spacing greater than 0.5 μm is too large and prevents the guard ring 150 from fully protecting the TSV 132. For example, when the guard ring 150 is too far away from the TSV 132 (e.g., greater than 0.5 μm), the guard ring 150 cannot fully absorb and / or reduce stress from the TSV 132, inside the TSV 132, and / or around the TSV 132. Then, the stress may be undesirably concentrated on the TSV 132, which may deteriorate the performance and / or structural integrity of the TSV 132. A spacing less than 0.2 μm is too small and may create a physical connection between the guard ring 150 and the TSV 132, which invalidates the purpose and / or function of the guard ring 150. For example, when the guard ring 150 is spaced too close to the TSV 132 (e.g., less than 0.2 μm), the guard ring 150 is essentially an extension of (and forms a portion of) the TSV 132 and may not protect the TSV 132 as intended. For example, the guard ring 150 may not provide electrical insulation; reduce or eliminate stress from, within, and / or around the TSV 132; reduce or eliminate cracks; provide structural integrity; or a combination thereof.

[0051] Reference now Figures 4 to 11 , Figures 4 to 11 According to various aspects of the present disclosure, Figure 1 A partial cross-sectional view of a workpiece 200 at various stages of fabrication of the TSV 132 and the guard ring 150 is depicted. For clarity, Figures 4 to 11 It has been simplified to provide a better understanding of the inventive concepts of the present disclosure. Additional components may be added to the workpiece 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the workpiece 200.

[0052] Steering Figure 4, after the workpiece 200 has undergone FEOL processing and MEOL processing, the workpiece 200 undergoes BEOL processing to form an FMLI structure 110 over the device region 100a of the device layer 102. The FMLI structure 110 can be physically connected and / or electrically connected to a semiconductor device, such as a transistor, formed in the device region 100a. While the FMLI structure 110 is formed, a front side component of a guard ring 150 is also formed over the TSV region 100b of the device layer 102. The front side component of the guard ring 150 can be physically connected and / or electrically connected to the device layer 102, such as to the source / drain components in the active region and / or the power via in the STI region. The guard ring 150 is a conductive ring (e.g., a metal ring) having an inner dimension of the dielectric region 210 that defines the dielectric structure 115. As further described below, the TSV 132 is formed to extend through the dielectric region 210.

[0053] In some embodiments, depositing a portion of the dielectric structure 115 includes depositing an ILD layer. In some embodiments, depositing a portion of the dielectric structure 115 includes depositing a CESL. The dielectric structure 115, the CESL, the ILD layer, or a combination thereof is formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), high density plasma CVD (HDPCVD), flowable CVD (FCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), remote plasma CVD (RPCVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable deposition methods, or combinations thereof.

[0054] In some embodiments, the metal lines 116 and vias 118 of the FMLI structure 110 and / or the guard ring 150 are formed by a dual damascene process, which may involve depositing conductive materials for the via / metal line pairs simultaneously. In such embodiments, the vias 118 and metal lines 116 may share a barrier layer and a conductive plug, rather than each having a corresponding and different barrier layer and conductive plug (e.g., where the barrier layer of the corresponding metal line 116 separates the conductive plug of the corresponding metal line 116 from the conductive plug of the corresponding via 118). In some embodiments, the dual damascene process includes performing a patterning process to form an interconnect opening extending through the dielectric structure 115 to expose the underlying conductive features. The patterning process may include a first photolithography step and a first etching step to form a trench opening of the interconnect opening in the dielectric structure 115 (which corresponds to and defines the metal line 116), and a second photolithography step and a second etching step to form a via opening of the interconnect opening in the dielectric structure 115 (which corresponds to and defines the via 118). The first photolithography / first etching step and the second photolithography / second etching step can be performed in any order (e.g., trench first and then via or via first and then trench). The first etching step and the second etching step are both configured to selectively remove the dielectric structure 115 relative to the patterned mask layer. The first etching step and the second etching step can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof.

[0055] After performing the patterning process, the dual damascene process may include performing a first deposition process to form a barrier material partially filling the interconnect opening over the dielectric structure 115, and performing a second deposition process to form a body conductive material over the barrier material, wherein the body conductive material fills the remaining portion of the interconnect opening. In such an embodiment, the barrier material and the body conductive material are disposed in the interconnect opening and over the top surface of the dielectric structure 115. The first deposition process and the second deposition process may include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, PEALD, electroplating, chemical plating, other suitable deposition methods, or combinations thereof. A CMP process and / or other planarization process is then performed to remove excess body conductive material and barrier material from over the top surface of the dielectric structure 115, thereby producing one of the interconnect layers of the FMLI structure 110 and a patterned via layer (e.g., via 118) and a patterned metal layer (e.g., metal line 116) of the corresponding interconnect structure of the guard ring 150. The CMP process planarizes the top surface of the dielectric structure 115 and the via 118 and / or the metal line 116. The barrier material and the bulk conductive material may fill the trench opening of the interconnect opening and the via opening without interruption, so that the barrier layer and the conductive plug of the metal line 116 and the via 118 may each extend continuously and without interruption from the metal line 116 to the corresponding via 118.

[0056] In some embodiments, for a given level interconnect layer, the metal lines 116 and vias 118 of the interconnect structure of the guard ring 150 at the given level interconnect layer are formed simultaneously with the metal lines 116 and vias 118 of the given level interconnect layer, respectively. In some embodiments, for a given level interconnect layer, the metal lines 116 and vias 118 of the interconnect structure of the guard ring 150 at the given level interconnect layer are at least partially formed simultaneously with the metal lines 116 and vias 118 of the given level interconnect layer, respectively. In some embodiments, for a given level interconnect layer, the metal lines 116 and vias 118 of the interconnect structure of the guard ring 150 at the given level interconnect layer are formed by different processes from the metal lines 116 and vias 118 of the given level interconnect layer, respectively. In some embodiments, for a given level interconnect layer, the metal lines 116 and / or vias 118 of the interconnect structure of the guard ring 150 at the given level interconnect layer are formed by the same single damascene process as the metal lines 116 and / or vias 118 at the given level interconnect layer, respectively. In some embodiments, for a given level of interconnection layer, the metal lines 116 and / or vias 118 of the interconnection structure of the guard ring 150 at the given level of interconnection layer are respectively formed by different single damascene processes from the metal lines 116 and / or vias 118 at the given level of interconnection layer. In some embodiments, for a given level of interconnection layer, the metal lines 116 and / or vias 118 of the interconnection structure of the guard ring 150 at the given level of interconnection layer are respectively formed by the same dual damascene process from the metal lines 116 and / or vias 118 at the given level of interconnection layer. In some embodiments, for a given level of interconnection layer, the metal lines 116 and / or vias 118 of the interconnection structure of the guard ring 150 at the given level of interconnection layer are respectively formed by different dual damascene processes from the metal lines 116 and / or vias 118 at the given level of interconnection layer.

[0057] refer to Figure 5 , the front side of the workpiece 200 is attached to the carrier 122, which allows the workpiece 200 to be turned upside down. This makes it possible to approach the workpiece 200 from the back side of the workpiece 200 for further processing. The carrier 122 can be attached to the workpiece 200 by any suitable attachment process, such as direct bonding, hybrid bonding, using an adhesive or other bonding method. In the depicted embodiment, a bonding layer 124 is applied between the top surface of the workpiece 200 and the carrier 122. The bonding process may also include alignment, annealing and / or other processes. In some embodiments, the carrier 122 may be a silicon wafer and is also referred to as a carrier wafer 122.

[0058] refer to Figure 6, the workpiece 200 is thinned from the back side of the workpiece 200 to remove a majority of the semiconductor substrate 202 of the device layer 102. The thinning process may include a mechanical grinding process and / or a chemical thinning process. During the mechanical grinding process, a large amount of the semiconductor substrate 202 may be first removed from the device layer 102. Then, the chemical thinning process may apply an etching chemical to the back side of the semiconductor substrate 202 to further thin the semiconductor substrate 202.

[0059] refer to Figure 7 , a first portion of the BMLI structure 112 is formed over the back side of the workpiece 200. The BMLI structure 112 may be physically and / or electrically connected to a semiconductor device, such as a transistor, formed in the device region 100a. While the BMLI structure 112 is being formed, a backside component of a guard ring 150 is also formed over the TSV region 100b of the device layer 102. The backside component of the guard ring 150 may be physically and / or electrically connected to the device layer 102, such as to source / drain components in an active region and / or power vias in an STI region. The guard ring 150 is a conductive ring (e.g., a metal ring) having an inner dimension of a dielectric region 210' that defines a dielectric structure 115'. As further described below, the TSV 132 is formed to extend through the dielectric region 210'. The formation of the dielectric structure 115', the BMLI structure 112, and / or the metal lines 116' and the vias 118' of the guard ring 150 are similar to the above description of the dielectric structure 115'. Figure 4 The formation of the dielectric structure 115, metal line 116 and via 118 described above is omitted here for the sake of simplicity. Figure 7 In the embodiment, the ILD layer of the dielectric structure 115' corresponding to the backside via layer is deposited as the bottommost layer of the BMLI structure 112 without forming a via therein.

[0060] refer to Figure 8, trenches 220 are formed in dielectric regions 210' of dielectric structure 115' and dielectric regions 210 of dielectric structure 115. The trenches 220 extend through dielectric structure 115', device layer 102, and dielectric structure 115, and partially into carrier wafer 122. In some embodiments, forming trenches 220 includes forming a patterned mask layer having openings therein exposing dielectric regions 210' of dielectric structure 115', and etching dielectric structure 115' and subsequently etching device layer 102 and dielectric structure 115 using the patterned mask layer as an etching mask. The patterned mask layer may be formed using a photolithography process, which may include resist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing resist, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. In some embodiments, the patterned mask layer is a patterned hard mask layer (e.g., a silicon nitride layer). In some embodiments, the patterned mask layer is a patterned resist layer. Etching can be a dry etching process, a wet etching process, other etching processes, or a combination thereof. In some embodiments, the etching process is an isotropic dry etching process. In some embodiments, a Bosch process is implemented to extend the groove 220 through the dielectric structure 115', the device layer 102, the dielectric structure 115, and partially into the carrier wafer 122. The Bosch process generally refers to a high aspect ratio plasma etching process, which involves alternating etching phases and deposition phases, wherein the cycle includes an etching phase and a deposition phase, and the cycle is repeated until the groove 220 has a desired depth.

[0061] exist Fig. 9 , fabrication continues by filling trench 220 with TSV 132. TSV 132 includes a conductive plug disposed over a barrier layer and a liner. In some embodiments, TSV 132 is formed by depositing a liner (e.g., silicon oxide, silicon nitride) and a barrier material (e.g., TiN or TaN) over workpiece 200 that partially fills trench 220, depositing a bulk conductive material (e.g., Cu) over workpiece 200 that fills the remainder of trench 220, and performing a planarization process (e.g., CMP) to remove excess barrier material and excess bulk conductive material from over workpiece 200 (e.g., over the top surface of dielectric structure 115').

[0062] exist Fig.10In the device region 100a, a second portion of the BMLI structure 112 is formed over the back side of the workpiece 200, wherein the metal layer is disposed in the dielectric layer added to the dielectric structure 115'. The newly added dielectric layer of the second portion of the BMLI structure 112 can be considered as an extension of the dielectric structure 115' in the vertical direction. Therefore, in the device region 100a, the BVy-1 via, the BMy-1 metal line, the BVy via, and the BMy metal line are formed in the dielectric structure 115' so that the first portion and the second portion of the BMLI structure 112 are physically and electrically connected. In comparison, the TSV region 100b does not have a BVy-1 via. Otherwise, the guard ring 150 would be short-circuited to the TSV 132 through the BMy-1 metal line. In the TSV region 100b, the BMy-1 metal line, the BVy via, and the BMy metal line are formed above the TSV 132. The BMy-1 metal line is physically and electrically connected to the TSV 132. In the depicted embodiment, the TSV 132 physically contacts the BMy-1 metal line. The present disclosure contemplates that the TSV 132 physically contacts metal lines 116' in other metallization layers of the BMLI structure 112, such as BMy metal lines or BMy-z metal lines, where z is an integer less than y.

[0063] Still reference Fig.10 , semiconductor device 120 is disposed above and electrically connected to the BMy metal line. In some embodiments, semiconductor device 120 may be configured, for example, as a DRAM device, an MRAM device, another suitable memory device, a metal-insulator-metal (MIM) structure (e.g., a MIM capacitor), or other semiconductor devices. The present disclosure contemplates that semiconductor device 120 is disposed between interconnect layers of BMLI structure 112. Contact layer 126 is disposed below BMLI structure 112. Contact layer 126 includes a contact 128 that facilitates electrical connection of the circuit in device layer 102 to an external circuit. In some embodiments, contact 128 is an under-bump metallization (UBM) structure. In some embodiments, contact 128 is a redistribution layer (RDL) structure. Contact 128 may be in physical and electrical contact with the bottom surface of the BMy metal line. Optionally, contact 128 may be electrically connected to the BMy metal line through a via. In some embodiments, contact layer 126 includes at least one passivation layer, such as a passivation layer 130 disposed below dielectric structure 115'. In such an embodiment, the contact 128 is disposed in the passivation layer 130. The passivation layer 130 may include a material different from the dielectric material of the ILD layer in the dielectric structure 115'. In some embodiments, the passivation layer includes polyimide, undoped silicate glass (USG), silicon oxide, silicon nitride, other suitable passivation materials, or combinations thereof.

[0064] exist Fig.11In the process, the manufacturing continues to form an ILD layer 133 over the contact 128 and to form one or more bonding pads 135 in the ILD layer 133. The bonding pads 135 are electrically connected to the TSVs 132 through the corresponding contacts 128. A planarization process (e.g., CMP) is performed to remove excess material of the carrier wafer 122 and to expose the TSVs 132 from the front side of the workpiece 200. After thinning the carrier wafer 122 and exposing the TSVs 132, a contact layer 137 is also formed on the front side of the workpiece 200. The contact layer 137 includes an interconnect structure 141 formed in a dielectric structure 139. The formation of the dielectric structure 139 can be similar to the dielectric structures 115 and 115'. In some embodiments, depositing a portion of the dielectric structure 139 includes depositing an ILD layer. In some embodiments, depositing a portion of the dielectric structure 139 includes depositing CESL. The interconnect structure 141 includes various conductive features distributed in multiple metal layers, and the various conductive features include various metal lines for horizontal wiring and vias for vertical wiring. The contact layer 137 may also include contacts 143 arranged in a desired pattern. The contacts 143 may facilitate electrical connection of the circuits in the device layer 102 to external circuits, and may therefore be referred to as external contacts. In some embodiments, the contacts 143 are under-bump metallization (UBM) structures. In some embodiments, the contacts 143 are redistribution layer (RDL) structures.

[0065] The semiconductor structure 100 may be attached (bonded) to another semiconductor structure to form an IC package or a portion of an IC package. Figures 12 to 17 In the embodiment, semiconductor structure 100 is attached to semiconductor structure 180, which may be similar to semiconductor structure 100. For example, Fig.12 As depicted, semiconductor structure 180 includes a respective device layer 102′, a respective FMLI structure 110′ disposed over a front side of the respective device layer 102′, and a respective contact layer 126′ disposed over the respective FMLI structure 110′, which are similar to their respective counterparts in semiconductor structure 100. In such an embodiment, circuits (e.g., transistors) formed in device layer 102′ of semiconductor structure 180 are electrically coupled to contacts 143 in contact layer 137 at a front side of semiconductor structure 180 via electrical routing through FMLI structure 110, contact layer 126′, contact layer 126, BMLI structure 112, TSV 132, and contact layer 137. Semiconductor structure 100 and semiconductor structure 180 may be bonded via dielectric-to-dielectric bonding (e.g., oxide-to-oxide bonding), metal-to-metal bonding (e.g., copper-to-copper bonding), metal-to-dielectric bonding (e.g., copper-to-oxide bonding), other types of bonding, or combinations thereof.

[0066] In some embodiments, semiconductor structure 100 and semiconductor structure 180 are chips including at least one functional IC, such as an IC configured to perform a logic function, a memory function, a digital function, an analog function, a mixed signal function, a radio frequency (RF) function, an input / output (I / O) function, a communication function, a power management function, other functions, or a combination thereof. In such an embodiment, TSV 132 physically and / or electrically connects the chips. In some embodiments, semiconductor structure 100 and semiconductor structure 180 are chips with the same function (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or a memory). In some embodiments, semiconductor structure 100 and semiconductor structure 180 are chips with different functions (e.g., a CPU and a GPU, respectively). In some embodiments, semiconductor structure 100 and semiconductor structure 180 are systems on a chip (SoC). In such an embodiment, TSV 132 physically and / or electrically connects the SoC. SoC generally refers to a single chip or a monolithic die (monolithic die) having multiple functions (e.g., a CPU, a GPU, a memory, other functions, or a combination thereof). In some embodiments, SoC is a single chip on which an entire system such as a computer system is manufactured. In some embodiments, semiconductor structure 100 is a chip and semiconductor structure 180 is a SoC, or vice versa. In such embodiments, TSV 132 physically and / or electrically connects the chip and the SoC.

[0067] In some embodiments, the semiconductor structure 100 is part of a chip-on-wafer-on-substrate (CoWoS) package, an integrated fan-out (InFO) package, a system-on-integrated-chip (SoIC) package, other three-dimensional integrated circuit (3DIC) packages, or a hybrid package implementing a combination of multi-chip packaging technologies. In some embodiments, the TSVs 132 of the semiconductor structure 100 are physically and / or electrically connected to a package substrate, an interposer, a redistribution layer (RDL), a printed circuit board (PCB), a printed wiring board, other packaging structures and / or substrates, or a combination thereof. In some embodiments, the TSVs 132 of the semiconductor structure 100 are physically and / or electrically connected to controlled collapse chip connections (C4 bonds) (e.g., solder bumps and / or solder balls) and / or microbumps (also referred to as microbonds, microbumps, and / or microbonding), which are physically and / or electrically connected to the packaging structure.

[0068] Figures 13 to 17 Many aspects of the embodiments in Fig.12 For the sake of brevity, similar aspects are not repeated below. Fig.13, the semiconductor structure 180 includes a corresponding FMLI structure 110' and a corresponding BMLI structure 112'. The contact layer 126' is disposed below the BMLI structure 112'. The carrier wafer 122' is disposed on the FMLI structure 110'. It is to bond the back side of the semiconductor structure 180 to the back side of the semiconductor structure 100. Fig.14 , the semiconductor structure 180 includes a corresponding device layer 102', a corresponding FMLI structure 110' disposed over the front side of the corresponding device layer 102', and a corresponding contact layer 126' disposed over the corresponding FMLI structure 110'. It is the front side of the semiconductor structure 180 that is bonded to the front side of the semiconductor structure 100. Fig.15 , the semiconductor structure 180 includes a corresponding FMLI structure 110' and a corresponding BMLI structure 112'. The contact layer 126' is disposed below the BMLI structure 112'. The carrier wafer 122' is disposed on the FMLI structure 110'. It is to bond the back side of the semiconductor structure 180 to the front side of the semiconductor structure 100. Fig.16 , the semiconductor structure 180 includes a corresponding device layer 102', a corresponding FMLI structure 110' disposed over the front side of the corresponding device layer 102', and a corresponding contact layer 126' disposed over the corresponding FMLI structure 110'. The redistribution layer 190 fans out the contacts at the front side of the semiconductor structure 180 and interconnects the front side of the semiconductor structure 180 with the front side of the semiconductor structure 100. Similarly, the redistribution layer 192 fans out the contacts at the back side of the semiconductor structure 100. Fig.16 The package shown is also known as an Integrated Fan-Out (InFO) package. Fig.17 , the semiconductor structure 180 includes a corresponding FMLI structure 110' and a corresponding BMLI structure 112'. The contact layer 126' is disposed below the BMLI structure 112'. The carrier wafer 122' is disposed on the FMLI structure 110'. The redistribution layer 190 fans out the contacts at the back side of the semiconductor structure 180 and interconnects the back side of the semiconductor structure 180 to the front side of the semiconductor structure 100. Similarly, the redistribution layer 192 fans out the contacts at the back side of the semiconductor structure 100. Fig.17 The package shown is also referred to as an Integrated Fan-Out (InFO) package.

[0069] The present disclosure provides many different embodiments. An exemplary semiconductor structure includes a device layer having a front side and a back side. An FMLI structure is disposed above the front side of the device layer, and a BMLI structure is disposed below the back side of the device layer. A through hole extends through the FMLI structure and a first portion of the BMLI structure and is electrically connected to a second portion of the BMLI structure. The through hole can electrically couple power or a signal from another semiconductor structure attached to the semiconductor structure.

[0070] In one exemplary aspect, the present disclosure provides an embodiment of a method for manufacturing a semiconductor device. The method includes forming a first multilayer interconnect structure above a first side of a device layer. The first multilayer interconnect structure includes a patterned first metal layer disposed in a first dielectric layer, the device layer having a second side opposite to the first side. The method also includes forming a first portion of a second multilayer interconnect structure below the second side of the device layer. The first portion of the second multilayer interconnect structure includes a patterned second metal layer disposed in the second dielectric layer. The method also includes forming a trench extending through the second dielectric layer, the device layer, and the first dielectric layer, forming a conductive structure in the trench, and forming a second portion of the second multilayer interconnect structure below the first portion of the second multilayer interconnect structure. The second portion of the second multilayer interconnect structure includes a patterned third metal layer disposed in a third dielectric layer, and one or more of the patterned third metal layers are electrically connected to the conductive structure. In some embodiments, forming the second portion of the second multilayer interconnect structure is after forming the conductive structure. In some embodiments, the one or more of the patterned third metal layers include metal lines in physical contact with the conductive structure. In some embodiments, the method also includes: before forming the first portion of the second multilayer interconnect structure, attaching a carrier to the semiconductor device, the carrier facing the first side of the device layer, and flipping the semiconductor device. In some embodiments, forming the groove includes extending the groove partially into the carrier. In some embodiments, the method further includes: before forming the first portion of the second multilayer interconnect structure, thinning the device layer from the second side. In some embodiments, the method further includes: forming a first stack of interconnect structures while forming the first multilayer interconnect structure. The first stack of interconnect structures forms a first ring defining an area of ​​the first dielectric layer, and the groove is formed in the area of ​​the first dielectric layer and extends through the area of ​​the first dielectric layer. In some embodiments, the method further includes: forming a second stack of interconnect structures while forming the first portion of the second multilayer interconnect structure. The second stack of interconnect structures forms a second ring defining an area of ​​the second dielectric layer, and the groove is formed in the area of ​​the second dielectric layer and extends through the area of ​​the second dielectric layer. In some embodiments, the first stack of interconnect structures and the second stack of interconnect structures are electrically connected by one or more source / drain components formed in the device layer. In some embodiments, the first stack of interconnect structures and the second stack of interconnect structures are electrically connected by one or more through holes formed in the isolation area of ​​the device layer.

[0071] In another exemplary aspect, the present disclosure provides an embodiment of a method, the method comprising receiving a first workpiece including a device layer; depositing a first dielectric layer on a front side of the device layer; forming a front portion of a guard ring in the first dielectric layer; depositing a second dielectric layer on a back side of the device layer; forming a back portion of the guard ring in the second dielectric layer; forming a trench extending through a portion of the first dielectric layer surrounded by the front portion of the guard ring and through a portion of the second dielectric layer surrounded by the back portion of the guard ring; forming a through hole in the trench; forming one or more metal layers in the second dielectric layer. The one or more metal layers are located below the through hole and are electrically connected to the through hole. The method also includes bonding the second workpiece to the first workpiece. The through hole is electrically connected to a conductive feature formed in the second workpiece. In some embodiments, after bonding, the second workpiece faces the front side of the device layer. In some embodiments, after bonding, the second workpiece faces the back side of the device layer. In some embodiments, the through hole couples a power supply to the second workpiece. In some embodiments, the through hole couples a signal to the second workpiece. In some embodiments, the guard ring is spaced apart from the through hole by a distance between about 0.2 μm and about 0.5 μm. In some embodiments, the method further includes attaching a carrier wafer to the first dielectric layer, wherein the through-vias extend partially through the carrier wafer, and prior to bonding, thinning the carrier wafer to expose the through-vias.

[0072] In yet another exemplary aspect, the present disclosure provides an embodiment of a semiconductor structure. The semiconductor structure includes: a device layer having a first side and a second side; a first dielectric layer, the first dielectric layer being disposed above the first side of the device layer; a second dielectric layer, the second dielectric layer being disposed below the second side of the device layer; a guard ring having a front portion disposed in the first dielectric layer and a back portion disposed in the second dielectric layer; a metal line disposed in the second dielectric layer below the back of the guard ring; and a through hole extending through the first dielectric layer and the device layer and in physical contact with the metal line. In some embodiments, the metal line is located directly below the back of the guard ring. In some embodiments, the semiconductor structure further includes: a redistribution layer disposed below the metal line. The redistribution layer includes a conductive component electrically connected to the through hole.

[0073] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first multi-layer interconnect structure over a first side of a device layer, wherein the first multi-layer interconnect structure comprises a patterned first metal layer disposed in a first dielectric layer, the device layer having a second side opposite the first side; forming a first portion of a second multilayer interconnect structure below the second side of the device layer, wherein the first portion of the second multilayer interconnect structure comprises a patterned second metal layer disposed in a second dielectric layer; forming a trench extending through the second dielectric layer, the device layer, and the first dielectric layer; forming a conductive structure in the trench; and A second portion of the second multilayer interconnect structure is formed below the first portion of the second multilayer interconnect structure, wherein the second portion of the second multilayer interconnect structure includes a patterned third metal layer disposed in a third dielectric layer, and wherein one or more of the patterned third metal layers are electrically connected to the conductive structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming the second portion of the second multi-layer interconnect structure is after forming the conductive structure.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The one or more of the patterned third metal layers include metal lines in physical contact with the conductive structures.

4. The method for manufacturing a semiconductor device according to claim 1, further comprising: before forming the first portion of the second multilayer interconnect structure, attaching a carrier to the semiconductor device, wherein the carrier faces the first side of the device layer; and The semiconductor device is turned over.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: Forming the trench includes extending the trench partially into the carrier.

6. The method for manufacturing a semiconductor device according to claim 1, further comprising: Prior to forming the first portion of the second multilayer interconnect structure, the device layer is thinned from the second side.

7. The method for manufacturing a semiconductor device according to claim 1, further comprising: A first stack of interconnect structures is formed simultaneously with the formation of the first multilayer interconnect structure, wherein the first stack of interconnect structures forms a first ring defining an area of ​​the first dielectric layer, and wherein the trench is formed in and extends through the area of ​​the first dielectric layer.

8. The method for manufacturing a semiconductor device according to claim 7, further comprising: A second stack of interconnect structures is formed simultaneously with forming the first portion of the second multilayer interconnect structure, wherein the second stack of interconnect structures forms a second ring defining an area of ​​the second dielectric layer, and wherein the trench is formed in and extends through the area of ​​the second dielectric layer.

9. A method for manufacturing a semiconductor device, comprising: receiving a first workpiece including a device layer; depositing a first dielectric layer on the front side of the device layer; forming a front portion of a guard ring in the first dielectric layer; depositing a second dielectric layer on the back side of the device layer; forming a back portion of the guard ring in the second dielectric layer; forming a trench extending through a portion of the first dielectric layer surrounded by the front portion of the guard ring and through a portion of the second dielectric layer surrounded by the back portion of the guard ring; forming a through hole in the groove; forming one or more metal layers in the second dielectric layer, wherein the one or more metal layers are located below the through-hole and electrically connected to the through-hole; and A second workpiece is joined to the first workpiece, wherein the through hole is electrically connected to a conductive member formed in the second workpiece.

10. A semiconductor structure comprising: a device layer having a first side and a second side; a first dielectric layer disposed over the first side of the device layer; a second dielectric layer disposed below the second side of the device layer; a guard ring having a front portion disposed in the first dielectric layer and a back portion disposed in the second dielectric layer; a metal line disposed in the second dielectric layer below the back portion of the guard ring; as well as A through-hole extends through the first dielectric layer and the device layer and is in physical contact with the metal line.

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