Semiconductor package

Abstract

The present disclosure provides a semiconductor package. The semiconductor package includes: a package plate; a first semiconductor chip disposed on the package board and having a first recess disposed at a first front surface of the first semiconductor chip facing the package board; a second semiconductor chip disposed on the package board side by side with the first semiconductor chip, and having a second recess disposed at a second front surface of the second semiconductor chip facing the package board; and an interconnection bridge disposed on the first front surface and the second front surface, and at least partially disposed in each of the first recess and the second recess. The interconnect bridge is connected to each of the first semiconductor chip and the second semiconductor chip.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0100614 filed on August 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package. Background Art

[0003] As the number of central processing unit (CPU) cores and graphics processing unit (GPU) cores in server products increases rapidly, die separation technology for effectively increasing the number of cores has become popular. In addition, with the growing demand for packages including high bandwidth memory (HBM), technology for die-to-die connection with fine circuit line width is needed. In order to meet this technical demand, technologies such as built-in silicon bridges or technologies using silicon interposers have been developed. However, the commercialization of this technology has limitations due to price issues, complex assembly processes, etc. Summary of the invention

[0004] An aspect of the present disclosure may provide a semiconductor package including an interconnection bridge, which has a high degree of freedom in design and may reduce the overall thickness of the semiconductor package.

[0005] Another aspect of the present disclosure may provide a semiconductor package including an interconnection bridge that may be manufactured with a simple process and at low cost.

[0006] According to an aspect of the present disclosure, there is provided a semiconductor package in which a recess is formed in each of a plurality of dies, a bridge for interconnecting the plurality of dies is provided in the recess, and the interconnection bridge and the plurality of dies in this state are mounted on a package board.

[0007] According to one aspect of the present disclosure, a semiconductor package may include: a package board; a first semiconductor chip disposed on the package board and having a first recess, the first recess being disposed at a first front surface of the first semiconductor chip facing the package board; a second semiconductor chip disposed on the package board side by side with the first semiconductor chip and having a second recess, the second recess being disposed at a second front surface of the second semiconductor chip facing the package board; and an interconnection bridge disposed on the first front surface and the second front surface and at least partially disposed in each of the first recess and the second recess. The interconnection bridge is connected to each of the first semiconductor chip and the second semiconductor chip.

[0008] According to another aspect of the present disclosure, a semiconductor package may include: a packaging board; a first semiconductor chip and a second semiconductor chip, which are arranged on the packaging board; a molding material, which is arranged on the packaging board and at least partially fills the space between the first semiconductor chip and the second semiconductor chip; a recess, which extends in a vertical direction from the lower surface of each of the first semiconductor chip and the second semiconductor chip and the molding material through a portion of each of the first semiconductor chip and the second semiconductor chip and the molding material; and an interconnect bridge, which is arranged in the recess and connected to each of the first semiconductor chip and the second semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically showing a state in which a ball grid array (BGA) package is mounted on a main board of an electronic device; Figure 4 is a cross-sectional view schematically showing a state in which a silicon interposer package is mounted on a main board; Figure 5 is a cross-sectional view schematically showing a state in which an organic interposer package is mounted on a main board; Figure 6 is a cross-sectional view schematically showing an example of a semiconductor package; Figure 7 It is schematically shown Figure 6 An enlarged cross-sectional view of an example of a region A; FIG. 8A to FIG. 8E is a schematic diagram showing the manufacturing Figure 6 An example process cross-sectional view of a semiconductor package; Fig. 9 is a cross-sectional view schematically showing another example of a semiconductor package; and Fig.10 It is schematically shown Fig. 9 An enlarged cross-sectional view of an example of region B. DETAILED DESCRIPTION

[0010] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0011] Electronic Devices Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0012] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically and / or electrically connected to the mainboard 1010. These electronic components may be connected to other electronic components described below via various signal lines 1090.

[0013] The chip-related components 1020 may include: a memory chip, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM) or a flash memory); an application processor chip, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor or a microcontroller; and a logic chip, such as an analog-to-digital converter (ADC) or an application-specific integrated circuit (ASIC). However, the chip-related components 1020 are not limited thereto and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be a package including the above-mentioned chips.

[0014] The network-related components 1030 may include components that are compatible with or communicate using protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) Protocol, Fourth Generation Mobile Communication Technology (4G) Protocol, and Fifth Generation Mobile Communication Technology (5G) Protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or communicating with various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0015] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, and in addition to these components, other components 1040 may also include passive elements in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0016] Based on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may be a camera 1050, an antenna 1060, a display 1070, a battery 1080, and the like. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, and the like. In addition, based on the type of the electronic device 1000, the electronic device 1000 may include other electronic components for various purposes.

[0017] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet personal computer (PC), a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may also be any other electronic device capable of processing data.

[0018] Figure 2 is a perspective view schematically illustrating an example of an electronic device.

[0019] Reference Figure 2, the electronic device may be, for example, a smart phone 1100. The smart phone 1100 may house a mainboard 1110, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, the smart phone 1100 may also house other electronic components (such as a camera module 1130 or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110. Some of the components 1120 may be chip-related components, for example, component packages 1121, and are not limited thereto. The component package 1121 may be in the form of a printed circuit board having electronic components (including active components and / or passive components) mounted on its upper surface. Alternatively, the component package 1121 may be in the form of a printed circuit board having active components and / or passive components embedded therein. In addition, the electronic device need not be limited to the smart phone 1100, and may be other electronic devices as described above.

[0020] Semiconductor package including an interposer Generally, many fine circuits are integrated in a semiconductor chip. However, the semiconductor chip itself may not be used as a finished semiconductor product and may be damaged due to external physical impact and / or chemical impact. Therefore, the semiconductor chip itself may not be used but may be packaged and used in an electronic device or the like in a packaged state.

[0021] Here, the reason why semiconductor packaging is needed is that in terms of electrical connection, there is a difference in circuit width between the semiconductor chip and the mainboard of the electronic device. In detail, the size of the contact pad of the semiconductor chip and the distance between the contact pads of the semiconductor chip are very fine. On the other hand, the size of the component mounting pad of the mainboard used in the electronic device and the distance between the component mounting pads of the mainboard are significantly larger than the size of the contact pad of the semiconductor chip and the distance between the contact pads of the semiconductor chip, respectively. Therefore, it may be difficult to mount the semiconductor chip directly on the mainboard, so a packaging technology for alleviating the difference in circuit width between the semiconductor chip and the mainboard is needed.

[0022] Hereinafter, a semiconductor package including an interposer manufactured by such a packaging technology will be described in more detail with reference to the accompanying drawings.

[0023] Figure 3 is a cross-sectional view schematically showing a state in which a ball grid array (BGA) package is mounted on a main board of an electronic device.

[0024] Semiconductor chips such as application specific integrated circuits (ASICs), graphic processing units (GPUs), etc. are very expensive, so it is very important to perform packaging of semiconductor chips such as ASICs, GPUs, etc. with a high yield. For this purpose, a ball grid array (BGA) board 2210 or the like, which can redistribute thousands to hundreds of thousands of contact pads, may be first prepared before mounting the semiconductor chip, and an expensive semiconductor chip such as a GPU 2220 may be mounted and packaged on the BGA board 2210 by using a surface mounting technology (SMT) or the like, and then finally mounted on the main board 2110.

[0025] In addition, the GPU 2220 may need to significantly reduce its signal path with a memory such as a high bandwidth memory (HBM). For this purpose, a product may be used in which a semiconductor chip such as the HBM 2240 is mounted on the interposer 2230, then packaged, and stacked in a package-on-package (POP) form on a package mounted with the GPU 2220. However, in this case, the device thickness may be excessively increased, and there is also a limitation in significantly reducing the signal path.

[0026] Figure 4 is a cross-sectional view schematically showing a state in which a silicon interposer package is mounted on a main board.

[0027] As a method for solving the above-mentioned problem, it may be considered to manufacture the semiconductor package 2310 including the silicon interposer by using the following interposer technology: the first semiconductor chip (such as the GPU 2220) and the second semiconductor chip (such as the HBM 2240) are surface mounted and then packaged side by side on the silicon interposer 2250. In this case, the GPU 2220 and the HBM 2240 having thousands to hundreds of thousands of contact pads may be redistributed through the silicon interposer 2250 and may be electrically connected to each other through the shortest path. In addition, when the semiconductor package 2310 including the silicon interposer is then mounted on the BGA board 2210 or the like and redistributed, the semiconductor package 2310 may be finally mounted on the main board 2110.

[0028] However, it is very difficult to form through silicon vias (TSVs) in the silicon interposer 2250 , and the cost required to manufacture the silicon interposer 2250 is significantly high, so the silicon interposer 2250 is disadvantageous in increasing area and reducing cost.

[0029] Figure 5 is a cross-sectional view schematically showing a state in which an organic interposer package is mounted on a main board.

[0030] As a method for solving the above-mentioned problem, it is conceivable to use an organic interposer 2260 instead of the silicon interposer 2250. For example, it is conceivable to manufacture a semiconductor package 2320 including an organic interposer by using the following interposer technology: a first semiconductor chip (such as a GPU 2220) and a second semiconductor chip (such as an HBM 2240) are surface-mounted and then packaged side by side on the organic interposer 2260. In this case, the GPU 2220 and the HBM 2240 having thousands to hundreds of thousands of contact pads can be redistributed through the organic interposer 2260, and can be electrically connected to each other through the shortest path. In addition, when the semiconductor package 2320 including the organic interposer is remounted on the BGA board 2210 or the like and redistributed, the semiconductor package 2320 can be finally mounted on the main board 2110. In addition, the organic interposer 2260 can be advantageous in increasing the area and reducing the cost.

[0031] However, when the organic interposer 2260 is used, the semiconductor chips 2220 and 2240 also need to be mounted on the organic interposer 2260 and then mounted on the BGA board 2210. Therefore, the manufacturing process of the semiconductor package may be somewhat complicated, and there is a risk of reduced packaging yield.

[0032] Semiconductor package including a bridge Figure 6 is a cross-sectional view schematically showing an example of a semiconductor package.

[0033] Figure 7 It is schematically shown Figure 6 An enlarged cross-sectional view of an example of region A.

[0034] Reference Figure 6 and Figure 7According to an exemplary embodiment, a semiconductor package 500A may include: a package board 100; a first semiconductor chip 210 and a second semiconductor chip 220, which are disposed on the package board 100; a molding material 410, which is disposed on the package board 100 and at least partially fills a space between the first semiconductor chip 210 and the second semiconductor chip 220; a recess R, which is formed in the first semiconductor chip 210 and the second semiconductor chip 220 and the molding material 410; an interconnection bridge 300, which is disposed in the recess R; a plurality of first contact members 430, which connect the package board 100 to the first semiconductor chip 210, the second semiconductor chip 220, and the interconnection bridge 300, respectively; a plurality of second contact members 440, which connect the interconnection bridge 300 to the first semiconductor chip 210 and the second semiconductor chip 220, respectively; and an insulating material 420, which has at least a portion disposed between the molding material 410, the first semiconductor chip 210, the second semiconductor chip 220, and the interconnection bridge 300 and the package board 100, and the plurality of first contact members 430 are embedded in the insulating material 420.

[0035] As described above, in the semiconductor package 500A according to the exemplary embodiment, the interconnection bridge 300 may be mounted above the package board 100, and the interconnection bridge 300 is attached to each of the first front surface of the first semiconductor chip 210 and the second front surface of the second semiconductor chip 220. Here, the first front surface may refer to the surface of the first semiconductor chip 210 facing the interconnection bridge 300 in the vertical direction, and the second front surface may be interpreted similarly. Compared with the case where the interconnection bridge 300 is embedded in the package board 100, the semiconductor package 500A has a superior design space to increase its design freedom, and can be manufactured with a simpler process and low cost. In addition, the recess R may be formed in the first semiconductor chip 210, the second semiconductor chip 220 and the molding material 410, and the interconnection bridge 300 may be arranged in the recess R, which can reduce the overall thickness of the package.

[0036] In addition, refer to Figure 6 Combined with Fig. 8A and Figure 8B , the recess R may include a first recess r1, a second recess r2, and a third recess r3. The first recess r1 may be provided at a first front surface of the first semiconductor chip 210 facing the package board 100. The second recess r2 may be provided at a second front surface of the second semiconductor chip 220 facing the package board 100. The third recess r3 may be provided in a bottom portion of the molding material 410 provided between the first semiconductor chip 210 and the second semiconductor chip 220. Fig. 8A and Figure 8B, the first recess r1 may extend from the first front surface through a portion of the first semiconductor chip 210 in the vertical direction, and the second recess r2 may extend from the second front surface through a portion of the second semiconductor chip 220 in the vertical direction. The first recess r1 and the second recess r2 may be recessed from surfaces of the first semiconductor chip 210 and the second semiconductor chip 220 facing each other in the horizontal direction, respectively. The first recess r1 and the second recess r2 may be connected to each other through the third recess r3. In this way, referring to Fig. 8A and Figure 8B , the recess R may include a first recess r1 formed in the first semiconductor chip 210, a second recess r2 formed in the second semiconductor chip 220, and a third recess r3 formed in the molding material 410. Therefore, the recess R may have: a bottom surface including the lower surface of a portion of each of the first semiconductor chip 210, the second semiconductor chip 220, and the molding material 410 that is recessed in the vertical direction; and a wall surface including surfaces of the first semiconductor chip 210 and the second semiconductor chip 220 that face each other in the horizontal direction. Here, the bottom surface of the recess R may be substantially flat. Therefore, the interconnection bridge 300 may be more easily disposed in the recess R, and may be more easily connected to each of the first semiconductor chip 210 and the second semiconductor chip 220.

[0037] In addition, the molding material 410 may cover the upper surface and / or outer surface of each of the first semiconductor chip 210 and the second semiconductor chip 220, and the lower surface of the molding material 410 may have a height difference due to the third recess r3. In more detail, the lower surface of the region of the molding material 410 covering the outer surface of each of the first semiconductor chip 210 and the second semiconductor chip 220 may be set at a height different from the height of the lower surface of the region of the molding material 410 disposed between the first semiconductor chip 210 and the second semiconductor chip 220. For example, the lower surface of the region of the molding material 410 covering the outer surface of each of the first semiconductor chip 210 and the second semiconductor chip 220 may be lower than the lower surface of the region of the molding material 410 disposed between the first semiconductor chip 210 and the second semiconductor chip 220. Therefore, the molding material 410 does not fill the recess R unnecessarily.

[0038] In addition, the interconnection bridge 300 may include: an organic insulating layer 310; a plurality of metal wiring layers 320, respectively disposed on or in the organic insulating layer 310; and at least one metal via layer 330, disposed in the organic insulating layer 310, and connecting the plurality of metal wiring layers 320 to each other. For example, the interconnection bridge 300 may be an organic bridge. For example, the interconnection bridge 300 may be a high-density printed circuit board including a microcircuit. Therefore, process simplification and cost reduction may be feasible compared to the case where the interconnection bridge 300 uses a silicon bridge. However, if necessary, the interconnection bridge 300 may use a silicon bridge instead of an organic bridge.

[0039] Hereinafter, components of a semiconductor package 500A according to exemplary embodiments will be described in more detail with reference to the accompanying drawings.

[0040] The package board 100 may be an organic board or a silicon board. The organic board may be a core-type printed circuit board, a coreless printed circuit board, etc., and is not limited thereto. The organic board may have any of various forms such as a rigid printed circuit board, a flexible printed circuit board, and a rigid-flexible printed circuit board. The organic board may include a plurality of insulating layers, a plurality of wiring layers respectively disposed on or in the plurality of insulating layers, and a plurality of via layers each extending through the plurality of insulating layers. The organic board may also include a solder resist layer disposed on the outermost side of the plurality of insulating layers.

[0041] Multiple insulating layers may include insulating materials. The insulating material may be a material prepared by impregnating a core material such as a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as a polyimide), or an inorganic filler (such as silica) and / or a core material such as glass fiber (such as glass fabric (such as glass cloth)) into a thermosetting resin or a thermoplastic resin, for example, a copper clad laminate (CCL), an Ajinomoto build-up film (ABF), a prepreg, etc., and is not limited thereto. Multiple insulating layers may have distinct boundaries, or may not have distinct boundaries if desired. For example, multiple insulating layers including substantially the same insulating material may have fuzzy boundaries. However, the boundaries of multiple insulating layers including different insulating materials can be easily distinguished from each other. However, the boundaries are not necessarily limited thereto, and may be clear regardless of the insulating material.

[0042] Multiple wiring layers may include metal materials. The metal material may use copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys. Multiple wiring layers may include electroless plating layers (e.g., chemical copper plating layers) and electrolytic plating layers (e.g., electrolytic copper plating layers). If necessary, each of the multiple wiring layers may also include copper foil. Multiple wiring layers may perform various functions based on various designs of the corresponding layers. For example, multiple wiring layers may include ground patterns, power patterns, signal patterns, etc. Here, the signal pattern may include various signal patterns other than the ground pattern and the power pattern, such as a data signal pattern. Each of these patterns may include a line pattern, a surface pattern and / or a pad pattern.

[0043] Multiple via layers may include metal materials. The metal material may use copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys. Multiple via layers may include electroless plating layers (e.g., chemical copper plating layers) and electrolytic plating layers (e.g., electrolytic copper plating layers). Multiple via layers may perform various functions based on various designs of corresponding layers. For example, multiple via layers may include ground vias, power vias, signal vias, etc. In multiple via layers, each via may be a filled via in which a metal material fills a via hole, but is not limited thereto, and may be a conformal via formed by a metal material along the wall surface of the via hole. In multiple via layers, each via may have various shapes (such as a cylindrical shape, an hourglass shape, and a tapered shape).

[0044] The solder resist layer can protect the internal components of the package board 100. The material of the solder resist layer is not particularly limited. For example, the solder resist layer can use an insulating material, in which case the insulating material can use a solder resist. However, the material of the solder resist layer is not limited thereto, and ABF or the like can be used.

[0045] A plurality of pads connected to the plurality of first contact members 430 may be provided on the top of the package board 100. The plurality of pads may be embedded in the upper surface of the package board 100, or may protrude from the upper surface of the package board 100. Each of the plurality of pads may include a metal material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The plurality of pads may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). If necessary, each of the plurality of pads may also include a copper foil. The plurality of pads may include a ground pad, a power pad, a signal pad, and the like.

[0046] Each of the first semiconductor chip 210 and the second semiconductor chip 220 may include an integrated circuit (IC) die in which hundreds to millions of elements or more are integrated into one chip. In this case, the IC may be, for example, an application processor (AP) chip, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc., or may be a logic chip, such as an analog-to-digital converter or an application-specific IC (ASIC), and is not limited thereto. The IC may be a memory chip, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM) or a flash memory), or a high-bandwidth memory (HBM), or may be another type of chip, such as a power management IC (PMIC).

[0047] The first semiconductor chip 210 and the second semiconductor chip 220 can both be formed based on an effective wafer. In this case, the base material of each body of the first semiconductor chip 210 and the second semiconductor chip 220 can be silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. Various circuits can be formed on the body. A contact pad can be formed on each body, and the contact pad can include a conductive material such as aluminum (Al) and / or copper (Cu). The first semiconductor chip 210 and the second semiconductor chip 220 can both be bare dies, in which case, if necessary, metal bumps can be set on the contact pads. The first semiconductor chip 210 and the second semiconductor chip 220 can both be packaged dies, in which case, an additional redistribution layer can be formed on the contact pads, and if necessary, metal bumps can be set on the redistribution layer.

[0048] The surface of the first semiconductor chip 210 where the first contact pad P is formed and the surface of the second semiconductor chip 220 where the second contact pad is formed may be an effective surface, for example, a front surface of the semiconductor chip, and the opposite surface thereof (for example, a rear surface of the semiconductor chip) may be an ineffective surface. The first recess r1 may be provided at the effective surface (for example, the front surface) of the first semiconductor chip 210, and / or the second recess r2 may be provided at the effective surface (for example, the front surface) of the second semiconductor chip 220.

[0049] For example, the first semiconductor chip 210 may include: a first semiconductor board 211; a plurality of first transistor elements 213 disposed on the first semiconductor board 211; a first insulating layer 212 disposed on the first semiconductor board 211; and a plurality of first metal layers 214 disposed on or in the first insulating layer 212. The plurality of first metal layers 214 may include a plurality of first contact pads P, each of which is at least partially exposed from a lower surface of the first insulating layer 212.

[0050] The first semiconductor plate 211 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon and / or germanium, for example, a silicon-germanium alloy. The first semiconductor plate 211 may be, for example, a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, and is not limited thereto.

[0051] The first transistor element 213 may include a gate insulating layer, a gate electrode, a capping layer, a spacer, etc. The source / drain regions may be provided on both sides of the first transistor element 213. The first transistor element 213 may be provided in the cell region, and may include, for example, a DRAM memory element, a flash memory element, or a complementary metal oxide semiconductor (CMOS) image sensor (CIS) element, but is not limited thereto, and may also include another logic element, a power element, etc.

[0052] The first insulating layer 212 may include a compound containing nitrogen and / or oxygen (such as oxide, nitride, etc.), for example, may include silicon oxide, silicon nitride, or silicon oxynitride, and is not limited thereto. The first insulating layer 212 may include a plurality of interlayer insulating layers, and the plurality of interlayer insulating layers may include the same material or different materials. If necessary, an interlayer insulating film may be provided between the interlayer insulating layers, and a protective layer may be provided on the interlayer insulating layer.

[0053] The first metal layer 214 may include, for example, a low resistance conductive material, such as copper (Cu), aluminum (Al), or tungsten (W). The first metal layer 214 may include a plurality of metal layers, and the plurality of metal layers may include the same material or different materials. Each layer in the first metal layer 214 may include a trace pattern, a via pattern, etc. The trace pattern may include a pad pattern connected to the via pattern. The first metal layer 214 may be surrounded by an anti-diffusion layer. The anti-diffusion layer may include at least one material selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), tungsten nitride (WN), nickel (Ni), and nickel boride (NiB). If necessary, the anti-diffusion layer may also include a plugging member, and the plugging member may be electrically connected to the first transistor element 213 and the first metal layer 214. The plugging member may include copper (Cu), tungsten (W), or a combination thereof.

[0054] The second semiconductor chip 220 may include: a second semiconductor board; a plurality of second transistor elements disposed on the second semiconductor board; a second insulating layer disposed on the second semiconductor board; and a plurality of second metal layers disposed on or in the second insulating layer, respectively. In addition, the plurality of second metal layers may include a plurality of second contact pads, each of the plurality of second contact pads being at least partially exposed from the lower surface of the second insulating layer. The detailed description of the second semiconductor chip 220 is substantially the same as the detailed description of the first semiconductor chip 210. In addition, although Figure 7 The second contact pad is not shown, but hereinafter, reference sign P may be applied to the first contact pad and the second contact pad.

[0055] The first semiconductor chip 210 and the second semiconductor chip 220 may be connected to the package board 100 and mounted on the package board 100 by using a plurality of first contact members 430. For example, some of the plurality of first contact pads P of the first semiconductor chip 210 and some of the plurality of second contact pads P of the second semiconductor chip 220 may each be connected to the package board 100 by using a plurality of first contact members 430. Each of the plurality of first contact members 430 may include a metal pillar (e.g., a copper pillar). Each of the plurality of first contact members 430 may also include a low melting point metal disposed on the metal pillar, for example, a solder including tin (Sn), aluminum (Al), copper (Cu), etc.

[0056] The interconnection bridge 300 may include a microcircuit for interconnection between the first semiconductor chip 210 and the second semiconductor chip 220, and more specifically, a microcircuit for die-to-die interconnection. For example, the interconnection bridge 300 may include: an organic insulating layer 310; a plurality of metal wiring layers 320, respectively disposed on or in the organic insulating layer 310; and at least one metal via layer 330, disposed in the organic insulating layer 310, and connecting the plurality of metal wiring layers 320 to each other. For example, the interconnection bridge 300 may be an organic bridge. For example, the interconnection bridge 300 may be a high-density printed circuit board including a microcircuit. However, if necessary, the interconnection bridge 300 may use a silicon bridge instead of an organic bridge.

[0057] The organic insulating layer 310 may include an organic insulating material. The organic insulating material may use a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating an inorganic filler (such as silica) and / or a core material into a thermosetting resin or a thermoplastic resin, such as a prepreg, ABF, FR-4, or bismaleimide triazine (BT), and is not limited thereto. The number of layers of the organic insulating layer 310 is not particularly limited and may be changed based on the design. The organic insulating layer 310 may have a distinct boundary, or may be integrated with each other to the extent that their boundaries are blurred.

[0058] The metal wiring layer 320 may include wiring for power transmission, wiring for signal transmission, wiring for grounding, etc. Each of these wirings may include a trace pattern, a pad pattern, etc. The metal wiring layer 320 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and in particular, may include copper (Cu). The metal wiring layer 320 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). The metal wiring layers 320 disposed on the uppermost side and the lowermost side of the metal wiring layer 320 may include a plurality of first connection pads 320P1 and a plurality of second connection pads 320P2, respectively.

[0059] The metal via layer 330 may include vias for power transmission, vias for signal transmission, vias for grounding, etc. Each of these vias may include a via pattern, etc. The metal via layer 330 may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. In detail, the metal via layer 330 may include a metal material. The metal via layer 330 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). The via pattern of the metal via layer 330 may taper toward the bottom based on its cross section, and is not limited thereto. The via pattern of the metal via layer 330 may include micro vias. The via pattern of the metal via layer 330 may include a filled via and / or a conformal via. The via pattern of the metal via layer 330 may include a stacked via and / or an alternating via.

[0060] The interconnection bridge 300 may be attached to the first semiconductor chip 210 and the second semiconductor chip 220 by using a plurality of second contact members 440. For example, other of the plurality of first contact pads P and other of the plurality of second contact pads P may be connected to the plurality of first connection pads 320P1 of the interconnection bridge 300 by using a plurality of second contact members 440, respectively. Each of the plurality of second contact members 440 may include a metal bump and / or a solder. For example, the second contact member 440 may include only a metal bump, may include only a solder, or may include both a metal bump and a solder. The metal bump may include copper (Cu), and is not limited thereto. The interconnection bridge 300 may be mounted on the package board 100 by using a plurality of first contact members 430. The plurality of second connection pads 320P2 of the interconnection bridge 300 may be connected to the package board 100 by using the plurality of first contact members 430 described above.

[0061] The molding material 410 may protect the first semiconductor chip 210 and the second semiconductor chip 220. The molding material 410 may fill the space between the first semiconductor chip 210 and the second semiconductor chip 220 and cover each of the upper surface and the outer surface of the first semiconductor chip 210 and the upper surface and the outer surface of the second semiconductor chip 220. The molding material 410 is not limited to any specific material, and, for example, epoxy molding compound (EMC) may be used.

[0062] The insulating material 420 may attach at least one of the first semiconductor chip 210, the second semiconductor chip 220, and the interconnection bridge 300 to the package board 100, and protect the plurality of first contact members 430. The insulating material 420 may at least partially fill the space between the molding material 410, at least one of the first semiconductor chip 210, the second semiconductor chip 220, and the interconnection bridge 300 and the package board 100, and embed and / or cover the plurality of first contact members 430. In one embodiment, some of the plurality of first contact pads P and some of the plurality of second contact pads P and the plurality of second connection pads 320P2 may be disposed on the same surface of the insulating material 420. The insulating material 420 is not limited to any specific material, and, for example, a non-conductive film (NCF) may be used.

[0063] FIG. 8A to FIG. 8E is a schematic diagram showing the manufacturing Figure 6 A process cross-sectional view of an example of a semiconductor package.

[0064] Reference Fig. 8A , the first semiconductor chip 210 and the second semiconductor chip 220 may be prepared, and then the first semiconductor chip 210 and the second semiconductor chip 220 may be covered with a molding material 410 .

[0065] Reference Figure 8B , a mask 450 may be used to form a recess R that passes through a portion of each of the first semiconductor chip 210 and the second semiconductor chip 220 and the molding material 410. The recess R may be formed by etching or laser processing. Alternatively, the recess R may be formed using a grinding process. If necessary, a barrier layer for forming the recess R may exist in the first semiconductor chip 210 and the second semiconductor chip 220. The recess R may include the first recess r1, the second recess r2, and the third recess r3 described above.

[0066] Reference Figure 8C , the interconnection bridge 300 may be manufactured in a separate process and then disposed in the recess R. Here, the interconnection bridge 300 may be connected to the first semiconductor chip 210 and the second semiconductor chip 220 by using a plurality of second contact members 440 .

[0067] Reference Fig.8D , a plurality of first contact members 430 may be formed on the first and second semiconductor chips 210 and 220 and the interconnection bridge 300 .

[0068] Reference Fig. 8EThe first semiconductor chip 210 and the second semiconductor chip 220 and the interconnection bridge 300 may be connected and mounted on the package board 100 using a plurality of first contact members 430 , and the first semiconductor chip 210 and the second semiconductor chip 220 and the interconnection bridge 300 may be attached and / or fixed to the package board 100 using an insulating material 420 .

[0069] The semiconductor package 500A according to the above exemplary embodiment may be manufactured through a series of processes, and other contents are substantially the same as those described above.

[0070] Fig. 9 is a cross-sectional view schematically showing another example of a semiconductor package.

[0071] Fig.10 It is schematically shown Fig. 9 An enlarged cross-sectional view of an example of region B.

[0072] Reference Fig. 9 and Fig.10 , compared to the semiconductor package 500A according to the above exemplary embodiment, in the semiconductor package 500B according to another exemplary embodiment, the interconnection bridge 300 may be directly connected to each of the first semiconductor chip 210 and the second semiconductor chip 220. The interconnection bridge 300 may contact the first semiconductor chip 210 and the second semiconductor chip 220 through the concave surface of the first recess r1 and the concave surface of the second recess r2, respectively. For example, the plurality of first connection pads 320P1 of the interconnection bridge 300 may be directly connected to some of the plurality of first contact pads P of the first semiconductor chip 210 and some of the plurality of second contact pads P of the second semiconductor chip 220, respectively. For example, the first connection pads 320P1 of the interconnection bridge 300 and the contact pads P of the semiconductor chip may be directly connected to each other by using pad-to-pad direct bonding, and is not limited thereto. In other words, some of the plurality of first contact pads P and some of the plurality of second contact pads P may contact the plurality of first connection pads 320P1 of the interconnection bridge 300, respectively. Processes other than the above process and reference FIG. 8A to FIG. 8E The process described is essentially the same.

[0073] As set forth above, the present disclosure can provide a semiconductor package including an interconnection bridge, which has a high degree of freedom in design and can reduce the package thickness.

[0074] The present disclosure may provide a semiconductor package including an interconnection bridge that can be manufactured with a simple process and at low cost.

[0075] In the present disclosure, the expression "covering" may include not only the case of completely covering an object but also the case of partially covering an object, and may also include indirect covering as well as direct covering. In addition, the expression "filling" may include not only completely filling an object but also substantially filling an object, for example, including the case where an object has some void spaces or gaps.

[0076] In the present disclosure, the expression “substantially” may be determined by including process errors occurring in the manufacturing process, positional deviations, measurement errors, etc. For example, the expression “substantially flat” may include not only completely flat but also approximately flat.

[0077] In the present disclosure, the expression "cross-sectional view" or "cross section" may indicate a diagram showing the cross-sectional shape of an object when the object is cut vertically or a diagram showing the shape of an object when the object is observed from the side. In addition, the expression "plan view" may indicate a diagram showing the shape of an object when the object is cut horizontally or a diagram showing the planar shape of an object when the object is observed from the top or bottom.

[0078] In the present disclosure, for convenience, the expression "vertical direction" indicates the up-down direction based on the cross section of the drawings, and for convenience, the expression "horizontal direction" indicates the left-right direction based on the cross section of the drawings. In addition, the terms "bottom", "lower part", "lower surface", etc. indicate the downward direction based on the cross section of the drawings, and the terms "top", "upper part", "upper surface", etc. indicate the direction opposite to the downward direction. However, these directions are defined for convenience of explanation, the claims are not particularly limited to the directions defined as above, and the concepts of up / down or left / right can be interchanged with each other.

[0079] In the present disclosure, the connection between two components conceptually includes their indirect connection through an adhesive layer, etc., as well as their direct connection. In addition, the expression "electrically connected" conceptually includes physical connection and physical disconnection. In addition, terms such as "first" or "second" are only used to distinguish an element from another element, and do not limit the order or importance of the elements. In some cases, without departing from the scope of the claims set forth herein, the first element may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0080] The expression "exemplary embodiment" or "example" used herein does not refer to the same exemplary embodiment or the same example, but is provided to emphasize each specific feature that is different from the feature of another exemplary embodiment or another example. The exemplary embodiments or examples provided herein may be implemented in combination with the features of another exemplary embodiment or another example. For example, unless an opposite or contradictory description is provided in another exemplary embodiment, the content described in a specific exemplary embodiment may be understood as a description related to another exemplary embodiment even if the content described in the specific exemplary embodiment is not described in another exemplary embodiment.

[0081] The terms used herein are only used to describe exemplary embodiments, rather than to limit the present disclosure.Here, unless otherwise clearly explained in the context, a singular term includes its plural form.

[0082] While exemplary embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: Package board; A first semiconductor chip is disposed on the package board and has a first recess, the first recess being disposed at a first front surface of the first semiconductor chip facing the package board; A second semiconductor chip is arranged on the package board side by side with the first semiconductor chip and has a second recess, the second recess being arranged at a second front surface of the second semiconductor chip facing the package board; as well as an interconnection bridge disposed on the first front surface and the second front surface and at least partially disposed in each of the first recess and the second recess, Wherein, the interconnection bridge is connected to each of the first semiconductor chip and the second semiconductor chip.

2. The semiconductor package according to claim 1, wherein: The first recess and the second recess extend from the first front surface and the second front surface in a vertical direction through a portion of the first semiconductor chip and a portion of the second semiconductor chip, respectively, and are respectively recessed from surfaces of the first semiconductor chip and the second semiconductor chip facing each other in a horizontal direction.

3. The semiconductor package according to claim 2, further comprising a molding material, the molding material at least partially filling a space between the first semiconductor chip and the second semiconductor chip, in, A third recess is provided at the bottom of the molding material, and The first recess and the second recess are connected to each other through the third recess.

4. The semiconductor package according to claim 3, wherein: The molding material covers an outer surface of each of the first semiconductor chip and the second semiconductor chip, and A lower surface of a portion of the molding material covering an outer surface of each of the first and second semiconductor chips and a lower surface of a portion of the molding material disposed in a region between the first and second semiconductor chips have a height difference due to the third recess.

5. The semiconductor package according to claim 3, further comprising: a plurality of first contact members, respectively connecting the first semiconductor chip, the second semiconductor chip and the interconnection bridge to the package board; as well as An insulating material is provided to fill a space between the molding material, at least one of the first semiconductor chip, the second semiconductor chip, and the interconnection bridge and the package board, and to embed the plurality of first contact members in the insulating material.

6. The semiconductor package according to claim 5, wherein: Each of the plurality of first contact members includes a metal pillar. 7 . The semiconductor package of claim 1 , further comprising a plurality of second contact members connecting the interconnection bridge to the first semiconductor chip and the second semiconductor chip, respectively.

8. The semiconductor package according to claim 7, wherein: Each of the plurality of second contact members includes at least one of a metal bump and a solder.

9. The semiconductor package according to claim 1, wherein: The interconnection bridge is directly connected to each of the first semiconductor chip and the second semiconductor chip.

10. The semiconductor package according to claim 1, wherein The interconnection bridge contacts the first semiconductor chip through a concave surface of the first concave portion, and / or the interconnection bridge contacts the second semiconductor chip through a concave surface of the second concave portion.

11. A semiconductor package, comprising: Package board; A first semiconductor chip and a second semiconductor chip are arranged on the packaging board; a molding material disposed on the package board and at least partially filling a space between the first semiconductor chip and the second semiconductor chip; a recess extending from a lower surface of each of the first and second semiconductor chips and the molding material in a vertical direction through a portion of each of the first and second semiconductor chips and the molding material; as well as An interconnection bridge is disposed in the recess and connected to each of the first semiconductor chip and the second semiconductor chip.

12. The semiconductor package according to claim 11, wherein The recess has a bottom surface including the lower surface of each of the first and second semiconductor chips and the molding material, and a wall surface including surfaces of the first and second semiconductor chips facing each other in a horizontal direction, and The bottom surface of the recess is substantially flat.

13. The semiconductor package according to claim 11, wherein: The first semiconductor chip comprises: a first semiconductor board; a plurality of first transistor elements arranged on the first semiconductor board; a first insulating layer arranged on the first semiconductor board; and a plurality of first metal layers arranged on or in the first insulating layer, respectively. The second semiconductor chip includes: a second semiconductor board; a plurality of second transistor elements arranged on the second semiconductor board; a second insulating layer arranged on the second semiconductor board; and a plurality of second metal layers respectively arranged on or in the second insulating layer, and The plurality of first metal layers include a plurality of first contact pads, and the plurality of second metal layers include a plurality of second contact pads, the plurality of first contact pads are at least partially exposed from a lower surface of the first insulating layer, and the plurality of second contact pads are at least partially exposed from a lower surface of the second insulating layer.

14. The semiconductor package according to claim 13, wherein: The interconnection bridge includes: an organic insulating layer; a plurality of metal wiring layers, respectively disposed on or in the organic insulating layer; and at least one metal via layer, disposed in the organic insulating layer and connecting the plurality of metal wiring layers to each other. The metal wiring layers disposed on the uppermost side and the lowermost side of the plurality of metal wiring layers include a plurality of first connection pads and a plurality of second connection pads, respectively, and Some of the plurality of first contact pads and some of the plurality of second contact pads are connected to the plurality of first connection pads, respectively.

15. The semiconductor package according to claim 14, wherein: Other ones of the plurality of first contact pads, other ones of the plurality of second contact pads, and the plurality of second connection pads are connected to the package board by using a plurality of first contact members, respectively, and The plurality of first contact members are embedded in an insulating material disposed to fill a space between the package board and at least one of the molding material, the first semiconductor chip, the second semiconductor chip, and the interconnection bridge.

16. The semiconductor package according to claim 15, wherein: The some of the plurality of first contact pads and the some of the plurality of second contact pads are connected to the plurality of first connection pads by using a plurality of second contact members, respectively.

17. The semiconductor package according to claim 15, wherein: The some of the plurality of first contact pads and the some of the plurality of second contact pads are directly connected to the plurality of first connection pads, respectively.

18. The semiconductor package according to claim 15, wherein: The some of the plurality of first contact pads and the some of the plurality of second contact pads are in contact with the plurality of first connecting pads, respectively.

19. The semiconductor package according to claim 15, wherein: The other ones of the plurality of first contact pads, the other ones of the plurality of second contact pads, and the plurality of second connection pads are disposed on a same surface of the insulating material.

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