Semiconductor structure with conductive bridge structure

Abstract

The invention provides a semiconductor structure. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is over the first surface of the substrate. The device layer comprises a plurality of passive element units. The metallization structure is over the device layer. The metallization structure comprises a conductive bridging part, and the conductive bridging part is electrically connected with two adjacent passive element units.

Description

Technical Field

[0001] The present application relates to a semiconductor structure, and in particular, the semiconductor structure includes a conductive bridge structure for electrically connecting two adjacent passive component units to electrically splice the two adjacent passive component units. Background Art

[0002] Integrated circuit (IC) manufacturers are adopting increasingly smaller geometries and corresponding technologies to create smaller, higher-speed semiconductor devices. With these advances, the challenges of maintaining yield and productivity are also increasing.

[0003] Generally, a semiconductor wafer includes die regions separated by dicing lanes. The dicing operation is performed on the active side of the semiconductor wafer, where the integrated circuits and the multi-layer wiring layers of the IC devices are formed, and the dicing lanes are defined between each individual IC device (such as the die region) in the semiconductor wafer region. Generally speaking, the dicing lane region is designed without any functional electrical wiring structure to prevent short circuits after the dicing operation. Summary of the invention

[0004] In an exemplary embodiment of the present application, a semiconductor structure is provided. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is located above the first surface of the substrate. The device layer includes a plurality of passive component units. The metallization structure is located above the device layer. The metallization structure includes a conductive bridging portion, which is electrically connected to two adjacent passive component units.

[0005] In another exemplary embodiment of the present application, a semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer, a plurality of first passive component units, a first type conductive terminal, and a second type conductive terminal. The plurality of first passive component units are concentrated in a first adjustable region of the semiconductor wafer in a top view.

[0006] The first type conductive terminal is located above the first adjustable area and does not overlap with the first passive component unit.

[0007] The second type conductive terminal is located above the first adjustable area and overlaps with the first passive component unit.

[0008] In another exemplary embodiment of the present application, a semiconductor structure is provided. The semiconductor structure includes a substrate, a passive device layer, a metallization structure, a first type conductive terminal, and a polymer layer. The substrate has a first surface. The passive device layer is located above the first surface of the substrate, and the passive device layer includes two separated passive component units. The metallization structure is located above the passive device layer, and the two passive component units in the passive device layer are electrically connected via a bridging portion of the metallization structure. The first type conductive terminal is projectively disposed above the bridging portion of the metallization structure. The polymer layer is located above the metallization structure and is configured to laterally surround the first type conductive terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The various aspects of the present disclosure can be best understood by reading the following embodiments and the accompanying drawings. It should be noted that the various features in the drawings are not drawn to scale, in accordance with standard operating practices in the art. In fact, the size of some features may be deliberately enlarged or reduced in order to be clearly described.

[0010] Figure 1 Cross-sectional views of semiconductor structures according to some comparative embodiments of the present application are shown.

[0011] Figure 2 A top view of a portion of a semiconductor wafer according to some comparative embodiments of the present application is shown.

[0012] Figure 3A A cross-sectional view of a semiconductor wafer according to some embodiments of the present application is shown.

[0013] Figure 3B A top view of a portion of a semiconductor wafer according to some embodiments of the present application is shown.

[0014] Figure 4A A top view of a portion of a semiconductor wafer according to some comparative embodiments of the present application is shown.

[0015] Figure 4B A top view of a portion of a semiconductor wafer according to some embodiments of the present application is shown.

[0016] Figure 5A A cross-sectional view of a semiconductor structure according to some embodiments of the present application is shown.

[0017] Figure 5B A cross-sectional view of a semiconductor structure according to some embodiments of the present application is shown.

[0018] Fig. 6A A top view of a portion of a semiconductor wafer according to some embodiments of the present application is shown.

[0019] Figure 6BA top view of a portion of a semiconductor wafer according to some embodiments of the present application is shown.

[0020] Figure 7 A cross-sectional view of a semiconductor structure according to some embodiments of the present application is shown.

[0021] Figure 8 A cross-sectional view of a semiconductor structure according to some embodiments of the present application is shown.

[0022] Figures 9A-9E A cross-sectional view of a semiconductor structure formed according to some embodiments of the present application is shown.

[0023] Figures 10A-10E A cross-sectional view of a semiconductor structure formed according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0024] This application claims priority to U.S. application No. 18 / 363,664, filed on August 1, 2023, the entirety of which is incorporated herein by reference.

[0025] The following disclosure provides many different embodiments or examples for implementing the different features of the present application. The following describes specific examples of components and configurations to simplify the present application. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first component is formed above a second component or a first component is formed on a second component, and an embodiment in which the first component and the second component are directly in contact may be included, and an embodiment in which an additional component is formed between the first component and the second component may be included, so that the first component and the second component may not be in direct contact. In addition, the disclosed content of the present application may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0026] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another element or components, as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0027] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, which should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another. When the terms "first," "second," and "third" are used herein, no order or sequence is implied unless clearly indicated by the context.

[0028] In conventional practice, memory dies or passive components of memory dies are usually manufactured in fixed-size units. For example, in wafer-level production, multiple device areas with the same size and repeating patterns (such as metallization layout and / or pin definition map (ball map)) are formed before the sawing operation. The location of the scribe line usually shows the boundary between adjacent device area units, and except for some test key patterns (each unit can then operate normally without these test key patterns), the electrical connections of each device area do not extend into the scribe line area to avoid short circuits after the sawing operation. Memory dies or passive components of memory dies with fixed-size units can be produced in a standardized manner, but this also limits the expansion flexibility between multiple units. From the packaging perspective, another IC chip or die of different size can be bonded to the memory die or passive component of the memory die. In order to comply with the bump map design of the unit such as the memory die or the passive component of the memory die, the bump map design of the IC chip or die is somewhat restricted. On the other hand, units such as memory dies or passive components of memory dies with fixed sizes lack the flexibility to expand. Each unit cut from the wafer has the same storage capacity or the same capacitance, and it is impossible to double or quadruple these values ​​by electrically combining multiple units.

[0029] In the present application, an elastic bump design for a memory die or a passive component of a memory die is disclosed. In some embodiments of the present application, the bump pattern on the memory die or the passive component of the memory die is designed to provide a more flexible bonding arrangement relative to another IC chip or die. The effective area of ​​the memory die or the passive component of the memory die that covers the conductive bump can be easily changed to conform to the bump pattern design of another IC chip or die so that they can be bonded together. On the other hand, the bump design described herein can also expand the storage capacity of the memory die or expand the capacitance of the capacitor structure.

[0030] Figure 1A semiconductor structure 90 of a comparative embodiment is disclosed, which includes a substrate 900. The substrate 900 has a first surface 901 and a second surface 902 opposite to the first surface 901. An active side of the substrate 900 is close to the first surface 901. A device layer 904 is formed on the first surface 901 of the substrate 900. The device layer 904 has a plurality of passive component units 906 formed therein, such as a plurality of capacitor structures. These passive component units 906 are arranged in an array in the device layer 904, and each two adjacent passive component units 906 are separated by a cutting line 908 (the cutting line may have a groove recessed from the top surface of the device layer 904 from a cross-sectional perspective, not shown in FIG. Figure 1 ). If a single passive component unit 906 is part of a memory die having a storage capacity of 128MB, then the final packaged product containing the memory die may have a storage capacity of 128MB. In other words, the layout of the passive component unit 906, after the dicing operation, will limit the scalability of the storage capacity of each memory die to some extent.

[0031] Figure 2 is a comparative embodiment from a top view angle. A plurality of passive component units 906 are formed on a semiconductor wafer 91 before cutting, and these passive component units 906 are arranged in an array and separated by cutting lanes 908. When a memory chip with a larger capacity is required (e.g., 256MB, 1024MB, etc.), the structure of each passive component unit 906 (e.g., having a storage capacity of 128MB / unit) must be changed, such as physically changing by increasing the density of transistors or capacitors, or electronically changing by increasing the number of bits stored in the cell, to meet such demand. However, these changes are technically fundamental, involving a large amount of research and development resources, and cannot be accomplished by utilizing the current layout of the passive component unit (e.g., having a storage capacity of 128MB / unit).

[0032] The present application provides a scalable semiconductor structure that provides flexibility in terms of storage capacity and bump map design by utilizing the current device layout. During the wafer-level production process, a bridging portion is manufactured to connect adjacent passive component areas. For example, the bridging portion can be electrically connected to 2, 4, 6, 8 or other numbers of passive component areas as required. The more passive component areas that are connected, the larger the effective area that can be obtained (i.e., the area of ​​the bump map allocated to other IC chips that are bonded thereto). By implementing a bridging portion in a semiconductor structure, not only can the storage capacity of a memory device or capacitor structure be expanded as required, but also the flexibility of the bump map design of other IC chips to be bonded to the memory device or capacitor structure can be achieved.

[0033] Reference Figure 3A In some embodiments, the scalable semiconductor structure 10 includes a substrate 100 having a first surface 101 and a second surface 102 opposite to the first surface 101. When the semiconductor structure 10 is a memory die, an active side of the substrate 100 is close to the first surface 101. When the semiconductor structure 10 is a capacitor structure, the substrate 100 can be a metal plate without active elements inside. A device layer 103 is formed on the first surface 101 of the substrate 100. The metallization structure 104 is formed on the device layer 103. In some embodiments, the substrate 100 is a semiconductor wafer made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or a combination thereof can also be used. In some embodiments, the substrate 100 is made of glass. In some embodiments, the substrate 100 is made of a conductive material such as a metal.

[0034] The device layer 103 includes a plurality of passive component units 105. In some embodiments, the substrate 100 includes a front-end-of-line (FEOL) structure. The FEOL structure is the first part of IC manufacturing, where active components such as transistors are formed in a semiconductor wafer. In some embodiments, the device layer 103 includes a middle-end-of-line (MOL / MEOL) structure and / or a back-end-of-line (BEOL) structure. Generally speaking, the MEOL structure is formed on the FEOL structure and is formed before the BEOL structure is formed. The specific definition of MEOL may vary, and in some embodiments of the present application, the MEOL structure refers to a region formed on the first surface 101 of the substrate 100 and located below the first metal layer (M1) 104A of the metallization structure 104. In some embodiments, the formation of the dielectric material in the MEOL structure is referred to as forming a pre-metal dielectric (PMD).

[0035] In some embodiments, the passive component unit 105 embedded in the device layer 103 is a passive component such as a capacitor structure. For example, the passive component unit 105 has a metal-insulator-metal (MIM) structure, a metal-oxide-metal (MOM) structure, etc. Generally speaking, a MIM capacitor includes an insulating layer sandwiched between two metal layers, while a MOM capacitor is composed of a plurality of parallel fingers or electrodes formed on a plurality of metal layers.

[0036] In some embodiments, the passive component units 105 are arranged in an array and separated by a plurality of cutting paths. In other words, each passive component unit 105 is separated from adjacent passive component units 105 by a cutting path area 106. In a conventional layout, these cutting path areas 106 originally only serve as cutting paths. However, for example, due to the implementation of the bridging portion described in the present application, the cutting path area 106 does not necessarily become a cutting point in the end. The cutting path area 106 can be closely surrounded by the passive component units 105 or the sealing ring structure 115. In some embodiments, such as Figure 3B As shown, a scribe line region 106 on a semiconductor wafer 11 includes a plurality of rows 106A and a plurality of columns 106B, and these columns 106B are perpendicular to the rows 106A, and each passive component unit 105 is surrounded by two adjacent rows 106A and two adjacent columns 106B. As mentioned above, in a conventional semiconductor wafer, the scribe line region is used to cut along the scribe line region (or simply the scribe line) to separate the passive component units from each other. However, in some embodiments of the present application, a portion of the scribe line region 106 is not necessarily used to separate the passive component units 105. On the contrary, the portion of the scribe line region 106 will be retained in the final product.

[0037] Reference Figure 4A , Figure 4A A top view of a portion of a semiconductor wafer having a plurality of passive component units 105 in a comparative embodiment is disclosed. Each passive component unit 105 is separated from each other by a scribe line region 106 (e.g., a plurality of rows 106A and columns 106B in a plurality of scribe lines). As shown, a plurality of conductive terminals 107 are formed in an area of ​​each passive component unit 105. In some embodiments, the conductive terminals 107 may be micro-bumps, C4 bumps, solder balls, or the like. It should be noted that for clarity of the description of the bump diagram, Figure 4A and Figure 4B Some conductive structures, such as the metallization structure 104 , are omitted.

[0038] Reference Figure 4B , Figure 4B A top view of a portion of a semiconductor wafer having a plurality of passive component units 105a-105d in some embodiments is disclosed. In some embodiments, a plurality of first-type conductive terminals 108 are formed in an area of ​​a first portion 110 of a scribe line region 106. The first portion 110 of the scribe line region 106 is Figure 4BThe area surrounded by the dotted line is referred to as an adjustable (scaled) area 111 described below in the present application, in which four passive component units 105a-105d are divided into a group. A plurality of second-type conductive terminals 107 are formed in an area or a projection area of ​​the passive component units 105a-105d. On the other hand, a second portion 109 of the cutting path area 106 refers to an area outside the individual spliced ​​areas, in which no conductive terminals are formed. However, in some embodiments, the second portion 109 of the cutting path area 106 may not include a conductive terminal but includes a bridging portion, which establishes an electrical connection between adjacent adjustable areas 111. The bridging portion can be implemented in any metallization layer, for example Figure 3A A first metal layer (M1) 104A is shown.

[0039] In some embodiments of the present application, these conductive terminals (i.e., the first type conductive terminals 108 and the second type conductive terminals 107) are substantially the same as each other. For example, both are made of solder material and have substantially the same size. The first type conductive terminals 108 and the second type conductive terminals 107 can be classified according to their relative positions. Figure 7 As shown, the first type conductive terminal 108 is located in an area of ​​the first portion 110 of the scribe line area 106, and the second type conductive terminal 107 is located in an area or a projection area of ​​the passive component unit 105a-105d. Figure 4B As shown, each conductive terminal is evenly distributed in a respective adjustable region 111. In other words, the first portion 110 of the scribe line region 106 is retained in the final product, while the second portion 109 of the scribe line region 106 is used as a cutting point during the singulation operation.

[0040] like Figure 4B As shown, in some examples, the passive component units 105a, 105b, 105c and 105d located in one of the adjustable regions 111 are electrically spliced ​​into a single unit and surrounded by the second portion 109 of the scribe line region 106 located on four sides thereof. The first type conductive terminals 108 can be arranged in parallel on one side of the adjustable region 111 and located between adjacent passive component units in the adjustable region 111, which means that in some embodiments, the arrangement of the first type conductive terminals 108 can be designed to correspond to the position of the passive component units below, rather than being randomly distributed on the metallization structure. A plurality of passive component units, such as Figure 4BThe passive component units 105a-105d disclosed in the present invention can be integrated into a single stitched semiconductor structure, and its storage capacity or capacitance is about four times that of a single passive component unit. For example, in the case where each passive component unit 105a-105d is a memory structure (such as a memory chip) with a storage capacity of 128MB, the stitched semiconductor structure including the stitched passive component units 105a-105d can have a storage capacity of 512MB. In other cases, the stitched semiconductor structure including two or more passive component units can have a storage capacity of 256MB, 768MB, 1024MB, etc., depending on the number of passive component units included therein.

[0041] The number of passive component units included in the spliced ​​semiconductor structure, or the number of the aforementioned adjustable areas, is customizable. For example, based on the requirements of a specific storage capacity or a specific effective area size, during wafer-level production, the passive component unit 105 and the first type conductive terminal 108 can be formed on the semiconductor wafer, and then packaged together with other IC chips or dies, and cut along the second portion 109 of the cutting path area 106. On the other hand, the number of adjustable areas 111 in each semiconductor package can be customized according to the required storage capacity. For example, as mentioned above, in an embodiment where the second portion 109 of the cutting path area 106 includes a bridging portion 116, it allows adjacent adjustable areas 111 to be electrically connected, so that they can be divided according to the specified storage capacity. Figure 4B and after a dicing operation, 2, 4 or 6 adjustable regions 111 are obtained in one semiconductor device package.

[0042] Still refer to Figure 4B Once the first type conductive terminals 108 are formed to meet specific packaging requirements, the first portion 110 of the scribe line region 106 having the first type conductive terminals 108 will remain in the final product. Compared to the second portion 109 of the scribe line region 106, the first portion 110 of the scribe line region 106 has a different morphology, which will be Figure 5A and Figure 5B Described in.

[0043] Reference Figure 5A , Figure 5A The semiconductor structure is along Figure 4B In some embodiments, the scribe line region 106 surrounds a plurality of passive component units 105. In some embodiments, the scribe line region 106 is located between two adjacent passive component units 105, or Figure 4BIn the embodiment shown, the scribe line region 106 is located between two adjacent adjustable regions 111 (for example, between a first adjustable region and a second adjustable region adjacent to the first adjustable region; for ease of understanding, the passive component units located in the first adjustable region and the second adjustable region can be respectively classified as the first passive component unit and the second passive component unit). In some embodiments, the second portion 109 of the scribe line region 106 includes a first trench 201 having a first depth D1. In some embodiments, the first depth D1 ranges from about 10 μm to about 15 μm. In some embodiments, the first depth D1 ranges from about 5 μm to about 10 μm. In some embodiments, the bottom of the first trench 201 is flush with the metallization structure 104. In some embodiments, one side of a passivation layer 112 on the metallization structure 104 is exposed to a sidewall of the first trench 201. In some embodiments, one side of a polymer layer 113 on the passivation layer 112 is exposed to the first trench 201. In some embodiments, the polymer layer includes a polyimide (PI) layer. Figure 5A The illustrated scribe line region 106 is a scribe point that will not remain in the final product, so the second portion 109 of the scribe line region 106 does not include the first-type conductive terminals 108 and the second-type conductive terminals 107 .

[0044] Reference Figure 5B , Figure 5B The semiconductor structure is along Figure 4B In some embodiments, the scribe line region 106 is located between two adjacent passive component units 105, such as Figure 4B In the embodiment shown, the scribe line region 106 is located in one of the adjustable regions 111 . Figure 5BThe scribe line region 106 in the embodiment is a first portion 110 of the scribe line region 106 that will be retained in the final product. In some embodiments, the first portion 110 of the scribe line region 106 includes a plurality of second trenches 114, each trench having a second depth D2. In some embodiments, the second depth D2 ranges from about 5 μm to about 10 μm. In some embodiments, the second depth D2 does not exceed about 5 μm. In some embodiments, the second depth D2 is less than the first depth D1. In some embodiments, a bottom of the second trench 114 is exposed to a top metal layer of the metallization structure 104. In some embodiments, one side of the passivation layer 112 on the metallization structure 104 is exposed to a sidewall of the second trench 114. In some embodiments, one side of the polymer layer 113 on the passivation layer 112 is exposed to the second trench 114. The second trench 114 is formed to provide an opening for a conductive bump (e.g., a second type conductive terminal) to contact the top metal layer of the metallization structure 104, or any conductive pad electrically connected to the metallization structure 104. Therefore, the depth of each second trench 114 is much smaller than the depth of the first trench 201 .

[0045] By constructing a bridge portion across the first portion 110 of the scribe line region 106, the conductive terminals (e.g., the first type conductive terminals 108) can be distributed on the area traditionally used as the scribe line, so that the passive component units 105 adjacent to the first portion 110 of the scribe line region 106 can be electrically spliced ​​together. By splicing the passive component units 105, the effective area of ​​the semiconductor die on these passive component units 105 (i.e., the area of ​​the contact bump layout) can be increased, so that the IC chip or die to be bonded to the semiconductor structure of the present application has better layout flexibility.

[0046] In a comparative example, referring to Fig. 6A , which discloses a semiconductor wafer having a first die region 801 and an adjacent second die region 802. One or more passive component units can be formed in each of the first die region 801 and the second die region 802 in the device layer on the semiconductor wafer. Generally speaking, each first bump region 811 or second bump region 812 (or active area) is smaller than the first die region 801 or the second die region 802. For example, Fig. 6A As shown, the first bump region 811 (indicated by a thick dashed line) is located in the first die region 801, and the second bump region 812 (indicated by a thick dashed line) is located in the second die region 802. An area of ​​each of the first bump region 811 and the second bump region 812 is 530μm*230μm, and an area of ​​each of the first die region 801 and the second die region 802 is 600μm*300μm. That is, in Fig. 6AIn the example shown, each bump area is 121,900 μm 2 , and the area of ​​each grain region is 180,000μm 2 , and the effective bump area (bump area / die area) is about 67.7%.

[0047] In some embodiments of the present application, the first grain region 801 and the second grain region 802 are Fig. 6A However, as previously described, since the first portion 110 of the scribe line region 106 is adjacent to the passive component unit 105, the passive component unit 105 can be connected to the passive component unit 105 by the bridge portion and the conductive terminal (such as previously shown in FIG. Figure 4B The first type conductive terminal 108 in the conductive bump is electrically connected, so a larger area can be calculated as the effective area of ​​the conductive bump layout. In some examples, such as Figure 6B FIG. 1 shows a semiconductor wafer 11 having a first grain region 401 and a second grain region 402 adjacent to each other. The first grain region 401 and the second grain region 402 may be Fig. 6A The first die region 801 and the second die region 802 shown previously in FIG. are substantially the same. Fig. 6A Compared with the comparative example shown, Figure 6B An area of ​​a splicing bump region 413 in the embodiment may be larger than Fig. 6A When the width W1 of the first portion 110 of the scribe line region 106 is about 80 μm, the area of ​​the spliced ​​bump region 413 may be 530 μm*610 μm, and the area of ​​the spliced ​​first die region 401 and the second die region 402 may be 600 μm*680 μm. Figure 6B In the example shown, the area of ​​the stitching bump region 413 is 323,300 μm 2 , while the area of ​​the grain region is 408,000μm 2 , and the effective area is about 79.2%. Therefore, the splicing of the die area not only increases the storage capacity of the passive component unit, but also expands the effective area of ​​the conductive bump layout, allowing the layout and bonding of more other IC chips or IC dies.

[0048] Reference Figure 7 In some embodiments, the semiconductor structure further includes a sealing ring structure 115 surrounding the periphery of the passive component unit 105. The sealing ring structure 115 is designed to protect the die area (such as previously shown in Figure 6BThe first die region 401 and the second die region 402 in the chip are separated to prevent electrostatic shock and avoid crack propagation or edge peeling during the singulation process, thereby eliminating the chip package interaction (CPI) reliability problem. Figure 7 As shown, each passive component unit 105 is laterally surrounded by a sealing ring structure 115, and the sealing ring structure 115 extends from the first surface 101 of the substrate 100 to the metallization structure 104. The metallization structure 104 also includes a bridge portion 116 electrically connected to two adjacent passive component units 105. The bridge portion 116 can be any conductive structure located in or adjacent to the first portion 110 of the scribe line area 106, and is used to electrically connect the passive component units 105 on opposite sides. Figure 3A The bridge portion 116 may be a conductive line or a through hole (not shown) located in or adjacent to the scribe line region 106. Figure 7 The bridge portion 116 may be a conductive line or a through hole (not shown) located in or adjacent to the first portion 110 of the scribe line region 106. Figure 7 , the first type conductive terminal 108 is projectedly disposed above the bridging portion 116 of the metallization structure 104. The term "projectedly" in this application refers to the spatial relationship of one item visible from a cross-sectional view being directly above or below another item. Directly above or below includes complete overlap or partial overlap, as long as a portion of each of the two items is vertically overlapped. The first type conductive terminal 108 can be electrically connected to the second type conductive terminal 107 through the bridging portion 116. The sealing ring structure 115 is at least partially located under a vertical projection of the bridging portion 116 of the metallization structure 104.

[0049] In some alternative embodiments, in order to obtain further anti-adjustable flexibility, the first portion 110 of the scribe line region 106 can be a dicing point during the singulation operation. The sealing ring structure 115 can be formed in each of the first portion 110 and the second portion 109 of the scribe line region 106, when the number of passive component units 105 in the adjustable region 111 is reduced based on demand (as disclosed in the aforementioned Figure 4B ), the party receiving the semiconductor wafer can separately cut the scribe line area 106 close to the sealing ring structure 115 and having the first type conductive terminals 108.

[0050] Still refer to Figure 7In some embodiments, the sealing ring structure 115 is located near the cutting line area 106, and the conductive bridging portion 116 crosses the cutting line area 106 to electrically connect two adjacent passive component units 105. In some embodiments, the metallization structure 104 includes one or more metal layers. In some embodiments, each passive component unit 105 is laterally separated in the device layer 103 by the sealing ring structure 115 and the cutting line area 106 between the sealing ring structures 115. In some embodiments, each second-type conductive terminal 107 is located at the same horizontal plane as the first-type conductive terminal 108. In some embodiments, a height of the sealing ring structure 115 is greater than a height of the passive component unit 105.

[0051] Reference Figure 7 and Figure 8 , Figure 8 A polymer layer 113 covering the metallization structure 104 is disclosed. In some embodiments, a plurality of conductive terminals (e.g., first-type conductive terminals 108 and second-type conductive terminals 107) protrude from the polymer layer 113 and contact the polymer layer 113 in the lateral direction. In some embodiments, the polymer layer 113 is configured to improve the mechanical strength of the conductive terminals and the mechanical strength of the semiconductor structure. The polymer layer 113 can also prevent particles from directly impacting the memory structure below. For example, compared to other dielectric materials such as silicon dioxide (SiO2), the polymer layer 113 (e.g., PI) exhibits stronger physical properties and chemical bonding. In particular, the tensile strength of the polymer layer 113 can reach about 230 MPa and the compressive strength can reach about 4 GPa, while the tensile strength of silicon dioxide is only about 155 MPa and the compressive strength is only about 1.6 GPa. In some embodiments, the thickness of the polymer layer 113 is about 10 μm. The thickness of the first-type conductive terminal (not shown) Figure 8 ) or the thickness of the second type conductive terminal 107 is greater than the thickness of the polymer layer 113. In addition, when the passive component unit 105 in the device layer 103 is a part of a memory die, the polymer layer 113 can be used to projectively cover the passive component unit 105 that is sensitive to space radiation (such as alpha particles).

[0052] 9A to 9E The process of forming the second portion 109 of the scribe line region 106 is disclosed. The manufacturing operation for forming the conductive bridge portion 116 across the first portion 110 of the scribe line region 106 to electrically connect the adjacent passive component units 105 is as follows. FIG. 10A to FIG. 10E drawn.

[0053] Reference Fig.9AIn some embodiments, a substrate 100 having a first surface 101 is provided. In some embodiments, a device layer 103 may be formed on the first surface 101 of the substrate 100, wherein the device layer 103 includes a plurality of passive component units 105 (e.g., a first passive component unit 1051 and a second passive component unit 1052). Each passive component unit 105 maintains a predetermined spacing 118 with adjacent passive component units in the device layer 103. In some embodiments, the predetermined spacing 118 is reserved for a seal ring structure and / or a scribe line area.

[0054] Reference Fig. 9B The sealing ring structure may be partially formed by a plurality of first through holes 121 that pass through the predetermined area 118 (see Fig.9A ) surrounds the entire periphery of the passive component unit 105. In some embodiments, the height of each first through hole 121 is greater than the thickness or height of the passive component unit 105. In some embodiments, one or more metal layers (such as metal layer 123 and metal layer 126) and one or more second through holes 122 can be formed on the first through hole 121 to form another part of the sealing ring structure. In some embodiments, the number of metal layers 123 and 126 can be two or three. For example, two metal layers can be implemented in a capacitor structure, and three metal layers can be implemented in a memory structure.

[0055] In some embodiments, the top of the first through hole 121 is flush with the top of the third through hole 124. The third through hole 124 is in contact with the top electrode of the passive component unit 105. Although not shown in FIG. FIG. 9B to FIG. 9E In some embodiments, the third through hole 124 and the first through hole 121 may be formed simultaneously in one operation, for example, an operation including forming a trench in the dielectric portion of the device layer 103, electroplating the first through hole 121 and the third through hole 124, and planarizing.

[0056] like Fig. 9B and 9C As shown, in some embodiments, after forming the metallization structure 104 on the device layer 103, and further forming the passivation layer 112 and the polymer layer 113 in sequence on the metallization structure 104, a plurality of openings 203 may be formed on the passivation layer 112 and the polymer layer 113 to expose the metal layer 126. In some embodiments, the metal layer 126 exposed in the openings 203 may be used as a conductive pad for receiving a signal transmitted through the top electrode of the passive component unit 105. Although not shown in FIG. Fig. 9C However, some openings 203 may be formed above the via structures electrically connected to the bottom electrodes of the passive component units 105. The scribe line region 106 includes a trench 201 recessed from the top surface of the dielectric layer of the metallization structure 104 to facilitate subsequent dicing operations.

[0057] Still refer to Fig.9D In some embodiments, the second type conductive terminal 107 may be formed in the opening 203. Each second type conductive terminal 107 protrudes from the polymer layer 113 and contacts the polymer layer 113 laterally. Since the area between the first passive component unit 1051 and the second passive component unit 1052 includes a scribe line, no conductive terminal is formed in the scribe line area 106. Fig.9E , a plurality of semiconductor devices can be mounted on the passive component unit 105 by a bumping operation. In some examples, a first semiconductor device 301 and a second semiconductor device 302 can be bonded to the first passive component unit 1051 and the second passive component unit 1052, respectively. Since no conductive terminals (or the first type conductive terminals 107 mentioned herein) are distributed in the scribe line region 106, the arranged bump pads of the first semiconductor device 301 and the second semiconductor device 302 can only be aligned with the bumps in the region where the second type conductive terminals 107 are located.

[0058] Reference Fig. 10A and 10B The passive component unit 105, the first through hole 121, the second through hole 122, the third through hole 124 and the metal layers 123 and 126 are formed with 9A to 9E The disclosure in is substantially the same. Fig. 10B In the embodiment, when the second metal layer 126 is formed on the first passive component unit 1051 and the second passive component unit 1052, a bridge portion 116 is also formed across the scribe line region 106. The bridge portion 116 may span the through-hole structure connected to the top electrode and the bottom electrode of the passive component unit 105, and in some embodiments, the bridge portion 116 may span the sealing ring structure to provide electrical connection between the first passive component unit 1051 and the second passive component unit 1052.

[0059] Next, refer to Fig. 10C , the passivation layer 112 and the polymer layer 113 may be subsequently formed on the metallization structure 104, and a plurality of openings 203 may be formed in the passivation layer 112 and the polymer layer 113 to expose the metal layer 126. Similar to the previous disclosure, the metal layer 126 exposed in the opening 203 may serve as a conductive pad for receiving a signal transmitted through the top electrode of the passive component unit 105. Although not shown in FIG. Fig. 10CIn some embodiments, the opening 114 has the same depth and size as the other openings 203. In other words, the opening 114 exposes the conductive bridge portion 116, but not as much as the other openings 203. Fig. 9C The trench 201 is shown extending deep into the dielectric layer of the metallization structure 104 .

[0060] Reference Fig. 10D In some embodiments, the second type conductive terminal 107 may be formed in the opening 203, and the first type conductive terminal 108 may be formed in the opening 114. Each conductive terminal (i.e., the second type conductive terminal 107 and the first type conductive terminal 108) protrudes from the polymer layer 113 and contacts the polymer layer 113 laterally. The scribe line area 106 shown in this embodiment will not be a scribe point, and therefore will remain in the final product. Fig. 10E , the semiconductor device can be mounted on the passive component unit by bonding operation. In some examples, a third semiconductor device 303 can be mounted on the first passive component unit 1051, the second passive component 1052 and the scribe line area 106 therebetween. In other words, the effective area of ​​the bump array is enlarged, and the bump pads arranged in the third semiconductor device 303 can be aligned with the bumps in the area where the first type conductive terminal 108 and the second type conductive terminal 107 are located. Although not shown in FIG. Fig. 10E However, two or more semiconductor devices may be mounted on the active area defined by the splicing of the first passive component unit 1051 and the second passive component unit 1052, as long as the bump arrangement of the two or more semiconductor devices is consistent with the spliced ​​passive component unit or the previously Figure 4B The flexible bump pattern matching provided by the adjustable region 111 discussed in the above can be used.

[0061] According to an embodiment of the present application, different passive component units can be connected to each other by a conductive bridging structure that spans an area traditionally used as a cutting path, and whether to use a conductive bridging structure to span this area to splice adjacent passive component units can be adjusted according to the needs of the semiconductor wafer buyer who will form the passive component unit on the semiconductor wafer. By using this adjustable semiconductor structure, the bump diagram of the passive component unit can be improved, thereby providing a more flexible semiconductor device installation tolerance. On the other hand, the electrical connection between the semiconductor device and the passive component unit can also be improved. For example, there can be more conductive terminals between the semiconductor device and the passive component unit, thereby increasing the bandwidth.

[0062] The foregoing content summarizes the structures of several embodiments so that those skilled in the art can better understand the aspects disclosed in this application. Those skilled in the art should understand that they can easily use this application as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced in this application. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this application, and they can make various changes, substitutions and modifications in this application without departing from the spirit and scope of this application.

[0063] Explanation of symbols

[0064] 10: Semiconductor structure

[0065] 100: substrate

[0066] 101: First surface

[0067] 102: Second surface

[0068] 103: Device layer

[0069] 104:Metalized structure

[0070] 104A: First metal layer

[0071] 105: Passive component unit

[0072] 105a-105d: Passive component unit

[0073] 1051: first passive component unit

[0074] 1052: Second passive component unit

[0075] 106: Cutting area

[0076] 106A: OK

[0077] 106B: Column

[0078] 107: (Type 2) Conductive terminal

[0079] 108: Type I conductive terminal

[0080] 109: Part 2

[0081] 110: Part 1

[0082] 11: Semiconductor wafer

[0083] 111: Adjustable area

[0084] 112: passivation layer

[0085] 113: polymer layer

[0086] 114: Second groove

[0087] 115: Sealing ring structure

[0088] 116: Bridge section

[0089] 118: Predetermined spacing

[0090] 121: first through hole

[0091] 122: Second through hole

[0092] 124: The third through hole

[0093] 123:Metal layer

[0094] 126:Metal layer

[0095] 201: (First) Groove

[0096] 203: Opening

[0097] 301: First semiconductor device

[0098] 302: Second semiconductor device

[0099] 303: Third semiconductor device

[0100] 401: first grain region

[0101] 402: Second grain region

[0102] 413: Splicing bump area

[0103] 801: first grain region

[0104] 802: Second grain region

[0105] 811: first bump area

[0106] 812: Second bump area

[0107] 90:Semiconductor structure

[0108] 900: substrate

[0109] 901: first surface

[0110] 902: Second surface

[0111] 904: Device layer

[0112] 906: Passive component unit

[0113] 908: Cutting Road

[0114] 91:Semiconductor wafer

[0115] A: Line segment

[0116] B: Line segment

[0117] D1: First Depth

[0118] D2: Second Depth

[0119] W1: Width

Claims

1. A semiconductor structure comprising: a substrate having a first surface; A device layer, located above the first surface of the substrate, wherein the device layer includes a plurality of passive component units; and The metallization structure is located above the device layer, and the metallization structure includes a conductive bridging portion, and the conductive bridging portion is electrically connected to two adjacent passive component units. 2 . The semiconductor structure of claim 1 , further comprising a first-type conductive terminal projectingly located above the conductive bridging portion of the metallization structure.

3. The semiconductor structure as claimed in claim 2, further comprising a second-type conductive terminal projectedly located above one of the passive component units, wherein the second-type conductive terminal is located at the same horizontal plane as the first-type conductive terminal. 4 . The semiconductor structure as claimed in claim 3 , wherein the conductive bridge portion comprises a horizontal metal line extending across the two adjacent passive device units. 5 . The semiconductor structure as claimed in claim 2 , wherein one of the passive device units comprises a silicon capacitor structure.

6. The semiconductor structure as claimed in claim 2 further comprises a sealing ring structure located in the device layer and between two adjacent passive component units, wherein the sealing ring structure is at least partially located below a vertical projection of the conductive bridging portion of the metallization structure. 7 . The semiconductor structure as claimed in claim 6 , wherein a height of the seal ring structure is greater than a height of one of the passive device units. 8 . The semiconductor structure as claimed in claim 1 , further comprising a scribe line region surrounding the passive device units, wherein the scribe line region comprises a recessed trench in the dielectric layer of the metallization structure.

9. The semiconductor structure of claim 1, wherein the metallization structure comprises two metal layers. 10 . The semiconductor structure as claimed in claim 2 , further comprising a polyimide layer located above the metallization structure, wherein the first-type conductive terminal protrudes and laterally contacts the polyimide layer.

11. A semiconductor structure comprising: Semiconductor wafers; A plurality of first passive component units, which are gathered in a first adjustable area of ​​the semiconductor wafer in a top-view angle; A first type conductive terminal, which is located above the first adjustable area and does not overlap with the first passive component units; and The second type conductive terminal is located above the first adjustable area and overlaps with the first passive component units.

12. The semiconductor structure of claim 11, further comprising: A plurality of second passive component units are gathered in the second adjustable area; and A cutting line region is formed between the first adjustable region and the second adjustable region. 13 . The semiconductor structure of claim 12 , wherein the scribe line region does not include the first-type conductive terminal and the second-type conductive terminal. 14 . The semiconductor structure according to claim 11 , wherein the first adjustable region comprises any even number of the first passive device units.

15. The semiconductor structure of claim 11, wherein the first-type conductive terminal is electrically connected to the second-type conductive terminal. 16 . The semiconductor structure as claimed in claim 11 , further comprising a plurality of first-type conductive terminals arranged parallel to one side of the first adjustable region and located between adjacent first passive device units.

17. A semiconductor structure comprising: a substrate having a first surface; A passive device layer, located above the first surface of the substrate, the passive device layer comprising two separated passive component units; A metallization structure located above the passive device layer, wherein the two passive component units in the passive device layer are electrically connected via a bridge portion of the metallization structure; A first type conductive terminal projectingly disposed above the bridging portion of the metallization structure; and The polymer layer is located above the metallization structure and is configured to laterally surround the first-type conductive terminals.

18. The semiconductor structure as claimed in claim 17, further comprising a second-type conductive terminal projectedly disposed above the passive component units and surrounded laterally by the polymer layer, wherein the second-type conductive terminal is located at the same level as the first-type conductive terminal. 19 . The semiconductor structure of claim 18 , wherein each of the first-type conductive terminal and the second-type conductive terminal has a thickness greater than a thickness of the polymer layer.

20. The semiconductor structure of claim 19, wherein the polymeric layer comprises a polyimide layer.

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