Semiconductor device

Abstract

The invention provides a semiconductor device. A semiconductor device (1, 201, 301, 401 or 501) comprises: a semiconductor chip (2) having a main face (3); an output region (6) formed on the main surface (3), in which an output element (20) is arranged; an inner element region (8, 208 or 308) surrounded by the output region (6) and insulated from the output region (6), in which inner element region a first element (9 or 309) different from the output element (20) is arranged; a first wiring layer (12), which is formed on the main surface (3) so as to cover the output region (6), and which includes first output wiring (98A) electrically connected to the output element (20); and a second wiring layer (13) formed on the first wiring layer (12) and including a second output wiring (98B) electrically connected to the first output wiring (98A) and a connection wiring (10 or 210) insulated from the second output wiring (98B), the connection wiring (10 or 210) extending from the inner element region (8, 208 or 308) across the output region (6) to an outer region (7) outside the output region (6).

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor chip having a main surface, an output region in which an output element is arranged, and a temperature sensing diode structure arranged in the output region.

[0003] [Prior art documents]

[0004] [Patent Document]

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-167338 Summary of the invention

[0006] Embodiments of the present disclosure provide a semiconductor device capable of improving mounting efficiency of output elements in an output region, thereby reducing a chip area.

[0007] According to an embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor chip having a main surface; an output region formed on the main surface, in which an output element is arranged; an inner element region, which is surrounded by the output region and insulated and isolated from the output region, in which a first element different from the output element is arranged; a first wiring layer, which is formed on the main surface in a manner covering the output region and comprises a first output wiring electrically connected to the output element; and a second wiring layer, which is formed on the first wiring layer and comprises a second output wiring electrically connected to the first output wiring and a connecting wiring insulated and isolated from the second output wiring, the connecting wiring extending from the inner element region across the output region to reach an outer region outside the output region, wherein the output element is arranged below the connecting wiring and comprises a trench electrode structure overlapping with the connecting wiring in the thickness direction of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure.

[0009] Figure 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure.

[0010] Figure 2 It is along Figure 1 A cross-sectional view taken along line II-II is shown.

[0011] Figure 3 It is shown Figure 1 A plan view of an example of a layout within a semiconductor chip is shown.

[0012] Figure 4is a schematic circuit diagram showing the electrical configuration of a semiconductor device.

[0013] Figure 5 It is shown Figure 3 The schematic circuit diagram of the output transistor is shown.

[0014] Figure 6 It is shown Figure 3 A plan view of the output area and inner component area is shown.

[0015] Figure 7 yes Figure 6 An enlarged view of region VII is shown.

[0016] Figure 8 This is a further enlarged view of region VII.

[0017] Fig. 9 It is along Figure 7 A cross-sectional view taken along line IX-IX is shown.

[0018] Fig.10 It is along Figure 7 A cross-sectional view taken along line XX is shown.

[0019] Fig.11 It is along Figure 7 A cross-sectional view taken along line XI-XI is shown.

[0020] Fig.12 It is along Figure 7 A cross-sectional view taken along line XII-XII is shown.

[0021] Fig.13 It is along Figure 7 A cross-sectional view taken along line XIII-XIII is shown.

[0022] Fig.14 is a plan view showing the inner element region, and is Figure 6 An enlarged view of region XIV is shown.

[0023] Fig.15 It is along Fig.14 A cross-sectional view taken along line XV-XV is shown.

[0024] Fig.16 It is along Fig.14 A cross-sectional view taken along line XVI-XVI is shown.

[0025] Fig.17 It is along Fig.14 A cross-sectional view taken along line XVII-XVII is shown.

[0026] Fig.18 It is along Fig.14A cross-sectional view taken along line XVIII-XVIII is shown.

[0027] Fig.19A It is along Fig.14 A cross-sectional view taken along line XIXA-XIXA is shown.

[0028] Fig.19B It is along Figure 6 A cross-sectional view taken along line XIXB-XIXB is shown.

[0029] Fig. 20 is a plan view showing an example of a layout in the semiconductor chip shown in the reference embodiment.

[0030] Fig.21 is a plan view showing an output region and an inner element region of a semiconductor device according to a second embodiment of the present disclosure, and is Figure 6 The corresponding view.

[0031] Fig. 22 is a plan view showing the inner element region, and is Fig.21 An enlarged view of region XXII is shown.

[0032] Fig.23 It is along Fig. 22 A cross-sectional view taken along line XXIII-XXIII is shown.

[0033] Fig.24 It is along Fig. 22 A cross-sectional view taken along line XXIV-XXIV is shown.

[0034] Fig.25 It is along Fig. 22 A cross-sectional view taken along line XXV-XXV is shown.

[0035] Fig.26A is a plan view showing an output region and an inner element region of a semiconductor device according to a third embodiment of the present disclosure, and is Figure 6 The corresponding view.

[0036] Fig.26B It is along Fig.26A A cross-sectional view taken along line XXVIB-XXVIB is shown.

[0037] Fig. 27 is a plan view showing a first modification example of the connection wiring according to the second embodiment, and is similar to Fig.25 The corresponding view.

[0038] Fig.28 is a cross-sectional view showing a second modification of the planar structure of the semiconductor device according to the first embodiment, and is similar to Fig.14The corresponding view. DETAILED DESCRIPTION

[0039] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams and are not strictly illustrated. The proportions and the like in the accompanying drawings do not necessarily match. In addition, corresponding structures in the accompanying drawings are represented by similar reference numerals, and their overlapping descriptions will be omitted or simplified.

[0040] Figure 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken along line II-II is shown. Figure 3 It is shown Figure 1 1 is a plan view of an example of a layout in the semiconductor chip 2 shown.

[0041] Reference Figures 1 to 3 , the semiconductor device 1 includes a semiconductor chip 2 formed in a rectangular parallelepiped shape. In the present embodiment, the semiconductor chip 2 is a Si chip including a Si single crystal. The semiconductor chip 2 may be composed of a wide bandgap semiconductor chip including a wide bandgap semiconductor single crystal. A wide bandgap semiconductor is a semiconductor having a bandgap greater than that of Si. GaN (gallium nitride), SiC (silicon carbide), C (diamond), etc. are exemplified as wide bandgap semiconductors. For example, the semiconductor chip 2 may be a SiC chip including a SiC single crystal.

[0042] Reference Figure 2 The semiconductor chip 2 has a first main surface (main surface) 3 on one side, a second main surface 4 on the other side, and a first side surface 5A to a fourth side surface 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed into a quadrilateral / square in a plan view when viewed from the normal direction Z thereof (hereinafter referred to as "top view"). The normal direction Z is also the thickness direction of the semiconductor chip 2.

[0043] The first main surface 3 is a circuit surface on which various circuit structures constituting an electronic circuit are formed. The second main surface 4 is a non-circuit surface having no circuit structure. The first side surface 5A and the second side surface 5B extend in a second direction Y intersecting (specifically, perpendicularly intersecting) the first direction X extending along the first main surface 3, and are opposite (opposite) to each other in the first direction X. The third side surface 5C and the fourth side surface 5D extend in the first direction X, and are opposite (opposite) to each other in the second direction Y.

[0044] Reference Figure 3 The semiconductor device 1 includes an output region 6 provided on the first main surface 3. The output region 6 is a region including an electronic circuit (circuit device) configured to generate an output signal to be output to the outside. An output transistor 20 (see FIG. 1 ) is formed in substantially the entire output region 6 except for its inner and outer peripheral portions. Figure 6 ). In the present embodiment, the output region 6 is defined in the region on the first side surface 5A side of the first main surface 3. The output region 6 has four sides parallel to the periphery of the first main surface 3 when viewed from above. The output region 6 is an annular (endless) region when viewed from above. In the present embodiment, the output region 6 is a substantially four-sided annular region.

[0045] The position, size, planar shape, etc. of the output region 6 are arbitrary and are not limited to a specific layout. The output region 6 may have a planar area of ​​25% or more and 80% or less of the planar area of ​​the first main surface 3. The planar area of ​​the output region 6 may be 30% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output region 6 may be 40% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output region 6 may be 50% or more of the planar area of ​​the first main surface 3. The planar area of ​​the output region 6 may be 75% or less of the planar area of ​​the first main surface 3.

[0046] Reference Figure 3 , the semiconductor device 1 includes a control region 7 provided in a region different from the output region 6 on the first main surface 3. The control region 7 is an example of an outer region located outside the output region 6. The control region 7 is a region including a plurality of types of electronic circuits (circuit devices) configured to generate control signals for controlling the output region 6. In the present embodiment, the control region 7 is defined in a region on the second side face 5B side relative to the output region 6 so as to be opposed to the output region 6 in the first direction X. In the present embodiment, the control region 7 is defined as a substantially quadrilateral shape having four sides parallel to the periphery of the first main surface 3 when viewed from above.

[0047] The position, size, planar shape, etc. of the control area 7 are arbitrary and are not limited to a specific layout. The planar area of ​​the control area 7 may be approximately equal to the planar area of ​​the output area 6. The planar area of ​​the control area 7 may be larger than the planar area of ​​the output area 6. The planar area of ​​the control area 7 may be smaller than the planar area of ​​the output area 6. The ratio of the planar area of ​​the control area 7 to the planar area of ​​the output area 6 may be greater than 0.1 and less than 4.

[0048] Reference Figure 3 The semiconductor device 1 includes an inner element region 8 surrounded by the output region 6 on the first main surface 3. The inner element region 8 is arranged at the center of the output region 6. The inner element region 8 is a region insulated and isolated from the output region 6. In the inner element region 8, no unit transistor 22 is formed (see Figure 6 ).

[0049] In a plan view, the inner element region 8 is adjacent to the output region 6 in four directions. In the present embodiment, the plane area of ​​the inner element region 8 is smaller than the plane area of ​​the output region 6. The ratio of the plane area of ​​the inner element region 8 to the plane area of ​​the output region 6 may be greater than 0.001 and less than 0.5. The ratio of the plane area of ​​the inner element region 8 to the plane area of ​​the output region 6 may be greater than 0.01 and less than 0.1.

[0050] In the present embodiment, the inner element region 8 is a region for arranging a temperature sensor element 9 as an example of a first element. The inner element region 8 is formed at a position corresponding to the center of the output region 6. Therefore, the temperature sensor element 9 arranged in the inner element region 8 is arranged at a position corresponding to the center of the output region 6. The temperature sensor element 9 is arranged adjacent to the output region 6. The temperature sensor element 9 detects the temperature of the output region 6.

[0051] Reference Figure 3 The output region 6 surrounds the entire circumference of the inner element region 8. The output region 6 is a quadrilateral ring (endless) region. In other words, the output region 6 surrounds the inner element region 8, so that the inner element region 8 is isolated from the control region 7.

[0052] Reference Figure 2 , the semiconductor device 1 includes an interlayer insulating layer 11 covering the first main surface 3. The interlayer insulating layer 11 covers the output region 6, the control region 7 and the inner element region 8 together. In the present embodiment, the interlayer insulating layer 11 has a stacked wiring structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked. Each insulating layer includes at least one selected from the group of SiO2 film and SiN film.

[0053] The interlayer insulating layer 11 includes a first wiring layer 12 arranged at any position on the first main surface 3 via an insulating layer, and a second wiring layer 13 arranged at any position on the first wiring layer 12 via an insulating layer. Each of the first wiring layer 12 and the second wiring layer 13 includes a plurality of output wirings. The plurality of wirings included in the first wiring layer 12 have the same height from the first main surface 3. The plurality of wirings included in the second wiring layer 13 have the same height from the first main surface 3. The heights of the first wiring layer 12 and the second wiring layer 13 from the first main surface 3 are different from each other.

[0054] The plurality of wirings included in the first wiring layer 12 and the second wiring layer 13 include a gate wiring 16 .

[0055] The semiconductor device 1 includes n gate wirings 16. The n gate wirings 16 are electrically connected to n main gates of the output transistor 20 and the control circuit 23, which will be described later. Specifically, the n gate wirings 16 are electrically connected to the n main gates (n system gates) of the output transistor 20 in a one-to-one correspondence, while being electrically independent of each other. Therefore, the n gate wirings 16 send n gate signals generated by the control circuit 23 individually to the n main gates of the output transistor 20. In other words, the n gate wirings 16 are electrically connected to the unit gates of one or more unit transistors 22 to be systemized as individual control objects in the collection composed of a plurality of unit transistors 22. The n gate wirings 16 may include one or more gate wirings 16 electrically connected to one unit transistor 22 to be systemized as an individual control object. In addition, the n gate wirings 16 may include one or more gate wirings 16 that connect in parallel a plurality of unit transistors 22 to be systemized as individual control objects.

[0056] Reference Figure 3 , the connection wiring 10 is connected to the temperature sensor element 9. The connection wiring 10 is one or more wirings. The connection wiring 10 extends from the inner element area 8 across the output area 6 to the control area 7 located outside the output area 6. The connection wiring 10 connects the temperature sensor element 9 and the control circuit 23 of the control area 7. The first temperature detection signal from the temperature sensor element 9 is applied to the overheat protection circuit 27 of the control circuit 23 via the connection wiring 10. As described later, the connection wiring 10 is included in the second wiring layer 13.

[0057] Reference Figure 1 and Figure 2 , the semiconductor device 1 includes a plurality of terminals 17 to 19. Figure 1 In FIG. 1 , the terminals 17 to 19 are indicated by hatching. The number, arrangement, and planar shape of the terminals 17 to 19 may be adjusted to any form according to the specifications of the output transistor 20 and the specifications of the control circuit 23, and are not limited to Figure 1 and Figure 2 In the present embodiment, the terminals 17 to 19 include a source terminal 17 , a plurality of control terminals 18 , and a drain terminal 19 .

[0058] In the present embodiment, the source terminal 17 is provided to be electrically connected to the output terminal of the load, and is arranged on a portion of the interlayer insulating layer 11 covering the output region 6. The source terminal 17 may cover the entire output region 6 when viewed from above. The source terminal 17 may include at least one selected from the group of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.

[0059] The plurality of control terminals 18 are terminals electrically connected to various electronic circuits within the control region 7, and are arranged on a portion of the interlayer insulating layer 11 that covers the control region 7. The planar area of ​​the plurality of control terminals 18 is smaller than the planar area of ​​the source terminal 17, and the plurality of control terminals 18 are arranged at intervals along the periphery of the control region 7 (the periphery of the first main surface 3).

[0060] Figure 4 It is shown Figure 1 Schematic circuit diagram of the electrical configuration of the semiconductor device 1 is shown. Figure 5 is a schematic circuit diagram showing the configuration of the output transistor 20. Figure 4 , in order to illustrate an example of the operation of the semiconductor device 1, an example in which an inductive load L as an example of a load is electrically connected to the source terminal 17 is shown. The inductive load L is not a component of the semiconductor device 1. Therefore, the configuration including the semiconductor device 1 and the inductive load L can be referred to as an "inductive load driving device" or an "inductive load control device". Examples of the inductive load L include relays, solenoids, lamps, motors, etc. The inductive load L can be a vehicle-mounted inductive load. That is, the semiconductor device 1 can be a vehicle-mounted semiconductor device.

[0061] Reference Figure 3 and Figure 4 The semiconductor device 1 includes an output transistor 20 formed in the output region 6. In the present embodiment, the output transistor 20 is composed of a split-gate transistor including a main drain, a main source and a plurality of main gates. The main drain is electrically connected to the drain terminal 19 (see Figure 2 ). The main source is electrically connected to the source terminal 17 (see Figure 2 ).

[0062] Reference Figure 4 , the multiple main gates of the output transistor 20 are configured so that multiple electrically independent gate signals (gate potentials) are individually input to the main gates. The output transistor 20 generates a single output current Io (output signal) in response to the multiple gate signals. In other words, the output transistor 20 is composed of a multi-input single-output switching device. The output current Io is a drain-source current flowing between the main drain and the main source. The output current Io is output to the outside of the semiconductor chip 2 (inductive load L) via the source terminal 17.

[0063] Reference Figure 4, the output transistor 20 includes a plurality of (two or more) system transistors 21, which are electrically independently controlled. In the present embodiment, the plurality of system transistors 21 include a first system transistor 21A and a second system transistor 21B. The plurality of system transistors 21 are formed together in the output region 6. The plurality of system transistors 21 are connected in parallel so that a plurality of gate signals are individually input to the system transistors 21, and are configured so that the system transistors 21 in the on state and the system crystal transistors 21 in the off state coexist.

[0064] The plurality of system transistors 21 respectively include a system drain, a system source and a system gate. The plurality of system drains are electrically connected to the main drain (drain terminal 19). The plurality of system sources are electrically connected to the main source (source terminal 17). Each system gate is electrically connected to each main gate. In other words, each system gate constitutes each main gate.

[0065] Each of the plurality of system transistors 21 generates a system current Is in response to a corresponding gate signal. Each system current Is is a drain-source current flowing between a system drain and a system source of each system transistor 21. The plurality of system currents Is may have different values, or may have substantially equal values. The plurality of system currents Is are added between a main drain and a main source. As a result, a single output current Io is generated from the sum of the plurality of system currents Is.

[0066] Reference Figure 5 , each of the plurality of system transistors 21 includes a single or a plurality of unit transistors 22 that are systemized (grouped) as individual control objects. Specifically, the plurality of system transistors 21 are composed of a single unit transistor 22 or a parallel circuit including a plurality of unit transistors 22. In the present embodiment, the plurality of unit transistors 22 are respectively composed of trench gate vertical transistors. The plurality of system transistors 21 may be composed of the same number of unit transistors 22, or may be composed of different numbers of unit transistors 22.

[0067] Reference Figure 5 Each unit transistor 22 includes a unit drain, a unit source, and a unit gate. The unit drain of each unit transistor 22 is electrically connected to the system drain of the corresponding system transistor 21. The unit source of each unit transistor 22 is electrically connected to the system source of the corresponding system transistor 21. The unit gate of each unit transistor 22 is electrically connected to the system gate of the corresponding system transistor 21.

[0068] Reference Figure 5, a plurality of unit transistors 22 generate unit currents Iu in response to corresponding gate signals, respectively. Each unit current Iu is a drain-source current flowing between a unit drain and a unit source of each unit transistor 22. The unit currents Iu may have different values, or may have substantially equal values. The unit currents Iu are added between the corresponding system drain and system source. As a result, a system current Is consisting of the sum of a plurality of unit currents Iu is generated.

[0069] As described above, the output transistor 20 is configured so that the first system transistor 21A and the second system transistor 21B are controlled to be turned on and off in a state where they are electrically independent of each other. That is, the output transistor 20 is configured so that both the first system transistor 21A and the second system transistor 21B are turned on at the same time. In addition, the output transistor 20 is configured so that one of the first system transistor 21A and the second system transistor 21B is turned on and the other is turned off.

[0070] Reference Figure 5 , when both the first system transistor 21A and the second system transistor 21B are turned on at the same time, the channel utilization of the output transistor 20 increases, and the on-resistance of the output transistor 20 decreases. When one of the first system transistor 21A and the second system transistor 21B is turned on and the other is turned off, the channel utilization of the output transistor 20 decreases, and the on-resistance of the output transistor 20 increases. In other words, the output transistor 20 is composed of a variable on-resistance switch device.

[0071] Reference Figure 3 and Figure 4 , the semiconductor device 1 includes a control circuit 23, which is formed in the control region 7 so that the control circuit 23 is electrically connected to the output transistor 20. The control circuit 23 may also be referred to as a "control IC". The control circuit 23 includes various functional circuits and constitutes an intelligent power device (IPD) together with the output transistor 20. The IPD may be referred to as an "intelligent power module (IPM)", "intelligent power switch (IPS)", "intelligent power driver", "intelligent MISFET (intelligent MOSFET)" or "protected MISFET (protected MOSFET)".

[0072] Reference Figure 3 and Figure 4 In this embodiment, the control circuit 23 includes a gate control circuit 24, a current monitoring circuit 25, an overcurrent protection circuit 26, an overheat protection circuit 27, a low voltage fault avoidance circuit 28, an open load detection circuit 29, an active clamping circuit 30, and a logic circuit 32. The control circuit 23 does not necessarily need to include all of these functional circuits at the same time, but only needs to include at least one of these functional circuits.

[0073] The current monitoring circuit 25 may be referred to as a CS circuit (current sensing circuit). The overcurrent protection circuit 26 may be referred to as an OCP circuit (overcurrent protection circuit). The overheat protection circuit 27 may be referred to as a TSD circuit (thermal shutdown circuit). The low voltage fault avoidance circuit 28 may be referred to as a UVLO circuit (undervoltage lockout circuit). The open load detection circuit 29 may be referred to as an OLD circuit (open load detection circuit).

[0074] The gate control circuit 24 is configured to generate a gate signal that controls the on / off operation of the output transistor 20. Specifically, the gate control circuit 24 generates a plurality of gate signals that individually control the on / off operation of the plurality of system transistors 21. In other words, in the present embodiment, the gate control circuit 24 generates a first gate signal that individually controls the on / off operation of the first system transistor 21A and a second gate signal that individually controls the on / off operation of the second system transistor 21B that is electrically independent of the first system transistor 21A.

[0075] The current monitoring circuit 25 generates a current Io (see Figure 4 ) and output the monitoring current to other circuits. For example, the monitoring circuit may include a transistor having the same configuration as the output transistor 20, and may be configured to generate a monitoring current linked to the output current Io by performing on / off control simultaneously with the output transistor 20. Of course, the current monitoring circuit 25 may be configured to generate a monitoring current linked to one or more system currents Is.

[0076] The overcurrent protection circuit 26 generates an electrical signal for controlling the gate control circuit 24 based on the monitoring current from the current monitoring circuit 25, and controls the on / off operation of the output transistor 20 in cooperation with the gate control circuit 24. For example, the overcurrent protection circuit 26 can be configured to determine that the output transistor 20 is in an overcurrent state when the monitoring current becomes above a predetermined threshold, and control a part or all of the output transistors 20 (a plurality of system transistors 21) to be turned off in cooperation with the gate control circuit 24. In addition, the overcurrent protection circuit 26 can be configured to transition the output transistor 20 to normal operation in cooperation with the gate control circuit 24 when the monitoring current becomes less than a predetermined threshold.

[0077] As described above, the overheat protection circuit 27 obtains the first temperature detection signal from the temperature sensor element 9 configured to detect the temperature of the output region 6. The overheat protection circuit 27 also includes a temperature sensing device (e.g., a temperature sensing diode) configured to detect the temperature of the control region 7. The overheat protection circuit 27 generates an electrical signal for controlling the gate control circuit 24 based on the first temperature detection signal from the temperature sensor element 9 and the second temperature detection signal from the temperature sensing device, and controls the on / off operation of the output transistor 20 in cooperation with the gate control circuit 24.

[0078] For example, the overheat protection circuit 27 may be configured to determine that the output region 6 is in an overheat state when the difference between the first temperature detection signal and the second temperature detection signal becomes greater than a predetermined threshold value, and control a portion or all of the output transistors 20 (a plurality of system transistors 21) to be turned off in cooperation with the gate control circuit 24. In addition, the overheat protection circuit 27 may be configured to transition the output transistor 20 to normal operation in cooperation with the gate control circuit 24 when the difference becomes less than a predetermined threshold value.

[0079] The low voltage fault avoidance circuit 28 is configured to prevent various functional circuits within the control circuit 23 from malfunctioning when the startup voltage for starting the control circuit 23 is less than a predetermined value. For example, the low voltage fault avoidance circuit 28 may be configured to start the control circuit 23 when the startup voltage becomes equal to or higher than a predetermined threshold voltage, and to stop the control circuit 23 when the startup voltage becomes lower than the threshold voltage. The threshold voltage may have a hysteresis characteristic.

[0080] The open load detection circuit 29 determines the electrical connection state of the inductive load L. For example, the open load detection circuit 29 may be configured to monitor the voltage between the terminals of the output transistor 20, and when the voltage between the terminals becomes equal to or higher than a predetermined threshold, determine that the inductive load L is in an open state. For example, the open load detection circuit 29 may be configured to determine that the inductive load L is in an open state when the monitor current becomes equal to or lower than a predetermined threshold.

[0081] The active clamp circuit 30 is electrically connected to the main drain and at least one main gate (e.g., the system gate of the first system transistor 21A) of the output transistor 20. The active clamp circuit 30 includes a Zener diode and a pn junction diode connected in series to the Zener diode in a reverse biased manner. The pn junction diode is a backflow prevention diode configured to prevent backflow from the output transistor 20.

[0082] The active clamp circuit 30 is configured to control a part or all of the output transistor 20 to be turned on in cooperation with the gate control circuit 24 when the back electromotive force voltage caused by the inductive load L is applied to the output transistor 20. Specifically, the output transistor 20 is controlled in multiple types of operation modes, including normal operation, first cut-off operation, active clamp operation, and second cut-off operation.

[0083] In normal operation, both the first system transistor 21A and the second system transistor 21B are controlled to be turned on at the same time. This increases the channel utilization of the output transistor 20 and reduces the on-resistance. In the first off operation, both the first system transistor 21A and the second system transistor 21B are controlled from the on state to the off state at the same time. As a result, the back electromotive force voltage caused by the inductive load L is applied to both the first system transistor 21A and the second system transistor 21B.

[0084] The active clamp operation is an operation in which the output transistor 20 absorbs (consumes) energy stored in the inductive load L, and is performed when the back electromotive force voltage caused by the inductive load L becomes equal to or higher than a predetermined threshold voltage. In the active clamp operation, the first system transistor 21A is controlled from the off state to the on state, and at the same time, the second system transistor 21B is controlled to (remained in) the off state.

[0085] The channel utilization rate of the output transistor 20 during the active clamp operation is less than the channel utilization rate of the output transistor 20 during the normal operation. The on-resistance of the output transistor 20 during the active clamp operation is greater than the on-impedance of the output transistor 20 during the normal operation. This suppresses a rapid increase in the temperature of the output transistor 20 during the active clamp operation and improves the durability of the active clamp.

[0086] When the back electromotive force voltage becomes less than a predetermined threshold voltage, a second cut-off operation is performed. In the second cut-off operation, the first system transistor 21A is controlled from the on state to the off state, and at the same time, the second system transistor 21B is controlled to (remained in) the off state. In this way, the back electromotive force voltage (energy) of the inductive load L is absorbed by a part of the output transistor 20 (here, the first system transistor 21A). Of course, during the active clamp operation, the first system transistor 21A can be controlled to (remain in) the off state, and at the same time, the second system transistor 21B can be controlled to be on.

[0087] The following will refer to Figures 6 to 13 The configuration of the output area 6 will be described. Figure 6 is a plan view showing the output region 6 and the inner element region 8 . Figure 7 yes Figure 6 An enlarged view of region VII is shown. Figure 8This is a further enlarged view of region VII. Fig. 9 It is along Figure 7 A cross-sectional view taken along line IX-IX is shown. Fig.10 It is along Figure 7 A cross-sectional view taken along line XX is shown. Fig.11 It is along Figure 7 A cross-sectional view taken along line XI-XI is shown. Fig.12 It is along Figure 7 A cross-sectional view taken along line XII-XII is shown. Fig.13 It is along Figure 7 A cross-sectional view taken along line XIII-XIII is shown.

[0088] The semiconductor device 1 includes an n-type (first conductivity type) first semiconductor region 51 formed on the surface of the second main surface 4 of the semiconductor chip 2. The first semiconductor region 51 forms the main drain of the output transistor 20 and the system drain of the system transistor 21. The first semiconductor region 51 can be called a "drain region". The first semiconductor region 51 is formed on the entire surface of the second main surface 4 and is exposed from the second main surface 4 and the first side surface 5A to the fourth side surface 5D (see FIG. 5A). Figure 1 wait).

[0089] The n-type impurity concentration of the first semiconductor region 51 may be 1×10 18 cm -3 Above and 1×10 21 cm -3 The thickness of the first semiconductor region 51 may be 10 μm or more and 450 μm or less. The thickness of the first semiconductor region 51 is preferably 50 μm or more and 150 μm or less. In the present embodiment, the first semiconductor region 51 is formed of an n-type semiconductor substrate (Si substrate).

[0090] The semiconductor device 1 includes an n-type second semiconductor region 52 formed on the surface of the first main surface 3 of the semiconductor chip 2. The second semiconductor region 52 forms the main drain of the output transistor 20 and the system drain of the system transistor 21 together with the first semiconductor region 51. The second semiconductor region 52 can be called a "drift region". The second semiconductor region 52 is formed on the entire surface of the first main surface 3 in a manner electrically connected to the first semiconductor region 51, and is exposed from the first main surface 3 and the first side surface 5A to the fourth side surface 5D (see FIG. 5A). Figure 1 wait).

[0091] The n-type impurity concentration of the second semiconductor region 52 is lower than the n-type impurity concentration of the first semiconductor region 51. The n-type impurity concentration of the second semiconductor region 52 may be 1×10 15 cm -3 Above and 1×10 18 cm-3 The thickness of the second semiconductor region 52 is less than that of the first semiconductor region 51. The thickness of the second semiconductor region 52 may be greater than 1 μm and less than 25 μm. The thickness of the second semiconductor region 52 is preferably greater than 5 μm and less than 15 μm. In the present embodiment, the second semiconductor region 52 is formed of an n-type epitaxial layer (Si epitaxial layer).

[0092] The semiconductor device 1 includes a first trench isolation structure 60 as an example of a region isolation structure defining an outer edge of the output region 6 at the first main surface 3. The first trench isolation structure 60 may be referred to as a "deep trench isolation (DTI) structure". The first trench isolation structure 60 may also be referred to as an "outer isolation structure".

[0093] Reference Figure 6 , the first trench isolation structure 60 is formed in a ring shape surrounding the outer periphery of the output region 6 when viewed from above. In the present embodiment, the first trench isolation structure 60 is formed in a substantially quadrilateral ring shape having four sides parallel to the periphery of the first main surface 3 when viewed from above. Strictly speaking, the first trench isolation structure 60 has a convex portion 60a, which is formed in a region opposite to the inner element region 8 across the output region 6 (a region opposite to the convex portion 8a described below in the first direction X), and is configured to protrude toward the inner element region 8 in the first direction X. The planar shape of the first trench isolation structure 60 is arbitrary, and may be formed in a polygonal ring shape.

[0094] Reference Figures 9 to 13 , the first trench isolation structure 60 includes a first isolation trench 61, a first isolation insulating film 62 and a first isolation electrode 63. That is, the first trench isolation structure 60 has a single electrode structure including a single electrode (first isolation electrode 63) buried in the first isolation trench 61 via an insulator (first isolation insulating film 62).

[0095] The first isolation trench 61 is dug downward from the first main surface 3 toward the second main surface 4. The first isolation trench 61 is formed at intervals from the bottom of the second semiconductor region 52 toward the first main surface 3. The first isolation insulating film 62 covers the wall surface of the first isolation trench 61. The first isolation insulating film 62 may include a silicon oxide film. The first isolation insulating film 62 may include a silicon oxide film composed of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method. The first isolation electrode 63 is buried in the first isolation trench 61 across the first isolation insulating film 62. The first isolation electrode 63 may include conductive polysilicon.

[0096] Reference Figure 7 and Figures 9 to 11, the first trench isolation structure 60 has a first isolation width W1 and a first isolation depth D1. The first isolation width W1 is the width in a direction perpendicular to the direction in which the first trench isolation structure 60 extends when viewed from above. The first isolation width W1 may be greater than 0.5 μm and less than 2.5 μm. The first isolation width W1 is preferably greater than 1.2 μm and less than 2 μm. The first isolation depth D1 may be greater than 1 μm and less than 10 μm. The first isolation depth D1 is preferably greater than 2 μm and less than 6 μm.

[0097] The aspect ratio D1 / W1 of the first trench isolation structure 60 may be greater than 1 and less than or equal to 5. The aspect ratio D1 / W1 is a ratio of the first isolation depth D1 to the first isolation width W1. The aspect ratio D1 / W1 is preferably greater than 2. The bottom wall of the first trench isolation structure 60 is preferably spaced from the bottom of the second semiconductor region 52 by 1 μm or more and 5 μm or less.

[0098] Reference Figure 6 and Figure 7 , the first trench isolation structure 60 has corners, each of which connects a portion extending in the first direction X and a portion extending in the second direction Y into an arc shape (curved shape). In the present embodiment, the four corners of the first trench isolation structure 60 are formed into an arc shape. That is, the output region 6 is defined as a rectangular shape having four corners, each of which extends in an arc shape. Preferably, the corners of the first trench isolation structure 60 have a constant first isolation width W1 along the arc direction.

[0099] Reference Figures 9 to 13 , the first isolation trench 61 includes a side wall and a bottom wall. The angle between the side wall of the first isolation trench 61 and the first main surface 3 in the semiconductor chip 2 can be greater than 90 degrees and less than 92 degrees. The first isolation trench 61 can be formed into a tapered shape in which the opening width decreases from the opening toward the bottom wall. The bottom wall corner of the first isolation trench 61 is preferably formed into a curved shape. The entire bottom wall of the first isolation trench 61 can be formed into a curved shape toward the second main surface 4.

[0100] The first isolation insulating film 62 is formed on the wall surface of the first isolation trench 61. Specifically, the first isolation insulating film 62 is formed in a film shape on the entire wall surface of the first isolation trench 61 to define a recessed space in the first isolation trench 61. Preferably, the first isolation insulating film 62 includes a silicon oxide film. More preferably, the first isolation insulating film 62 includes a silicon oxide film composed of an oxide of the semiconductor chip 2.

[0101] The first isolation electrode 63 is embedded in the first isolation trench 61 as an integral body through the first isolation insulating film 62. In the present embodiment, the first isolation electrode 63 comprises conductive polysilicon. A source potential is applied to the first isolation electrode 63. The first isolation electrode 63 has an electrode surface (isolation electrode surface) exposed from the first isolation trench 61. The electrode surface of the first isolation electrode 63 may be recessed in a curved shape toward the bottom wall of the first isolation trench 61. The electrode surface of the first isolation electrode 63 is preferably spaced apart from the first main surface 3 to the bottom wall of the first isolation trench 61 in the depth direction of the first isolation trench 61.

[0102] Reference Figures 7 to 13 The semiconductor device 1 includes a p-type (second conductivity type) first body region 67 formed on the surface of the first main surface 3 in the output region 6. The p-type impurity concentration of the first body region 67 may be 1×10 16 cm -3 Above and 1×10 18 cm -3 The first body region 67 is formed in the output region 6 on the entire surface of the first main surface 3 and is in contact with the side wall of the first trench isolation structure 60. The first body region 67 is formed in a region on the first main surface 3 side relative to the bottom wall of the first trench isolation structure 60. The first body region 67 is preferably formed in a region on the first main surface 3 side relative to the middle portion of the first trench isolation structure 60.

[0103] Reference Figure 6 As described above, the semiconductor device 1 includes an output transistor 20 formed on the first main surface 3 in the output region 6. The output transistor 20 is arranged in a ring shape surrounding the inner element region 8. The output transistor 20 includes a plurality of unit transistors 22 (see Figure 8 ), which are formed together on the first main surface 3 of the output region 6. The number of unit transistors 22 is arbitrary. The number of unit transistors 22 is preferably an even number. The unit transistors 22 are arranged in a row along the second direction Y when viewed from above, and are respectively formed into a strip shape extending in the first direction X. The unit transistors 22 are formed into a strip shape extending in the first direction X when viewed from above.

[0104] Reference Figure 8 , each unit transistor 22 includes a trench gate structure (trench electrode structure) 70 and a channel unit 78 controlled by the trench gate structure 70. Each trench gate structure 70 constitutes a unit gate of each unit transistor 22. The channel unit 78 is a region where the opening and closing of the current path is controlled by the trench gate structure 70. In the present embodiment, each unit transistor 22 includes a pair of channel units 78 formed on both sides of one trench gate structure 70.

[0105] Reference Figure 7 and Figure 8The trench gate structures 70 are arranged at intervals in the second direction Y in a plan view, and are respectively formed into a strip shape extending in the first direction X. That is, the trench gate structures 70 are formed into a strip shape extending in the first direction X in a plan view.

[0106] Reference Figures 7 to 10 , the trench gate structure 70 has a trench width W2 and a trench depth D2. The trench width W2 is the width in a direction (second direction Y) orthogonal to the direction in which the trench gate structure 70 extends. The trench width W2 is preferably smaller than the first isolation width W1 of the first trench isolation structure 60 (W2<W1). The trench width W2 may be greater than 0.5 μm and less than 2 μm. The trench width W2 is preferably greater than 0.5 μm and less than 1.5 μm. Of course, the trench width W2 may be approximately equal to the first isolation width W1 (W2≈W1).

[0107] The trench depth D2 is preferably less than the first isolation depth D1 of the first trench isolation structure 60 (D2<D1). The trench depth D2 may be greater than 1 μm and less than 10 μm. The trench depth D2 is preferably greater than 2 μm and less than 6 μm. Of course, the trench depth D2 may be approximately equal to the first isolation depth D1 (D2≈D1). The aspect ratio D2 / W2 of the trench gate structure 70 may be greater than 1 and less than or equal to 5. The aspect ratio D2 / W2 is the ratio of the trench depth D2 to the trench width W2. More preferably, the aspect ratio D2 / W2 is greater than 2. The bottom wall of the trench gate structure 70 is preferably spaced from the bottom of the second semiconductor region 52 by more than 1 μm and less than 5 μm.

[0108] Reference Figures 7 to 10 , the trench gate structures 70 are arranged in the second direction Y with a first interval I1. The first interval I1 is also the mesa width of the mesa portion defined in the region between two trench gate structures 70 adjacent to each other. The first interval I1 is preferably equal to or less than the first isolation width W1 of the first trench isolation structure 60. Preferably, the first interval I1 is equal to or less than the trench width W2. Particularly preferably, the first interval I1 is less than the trench width W2. The first interval I1 may be greater than 0.5 μm and less than 2 μm.

[0109] The internal structure of a trench gate structure 70 will be described below. Figures 9 to 13 , the trench gate structure 70 includes a gate trench 71, an insulating film 72, an upper electrode 73, a lower electrode 74 and an intermediate insulating film 75. In other words, the trench gate structure 70 has a multi-electrode structure including a plurality of electrodes (upper electrode 73 and lower electrode 74) buried in the gate trench 71 in the upper and lower directions via an insulator (insulating film 72 and intermediate insulating film 75).

[0110] The gate trench 71 is dug downward from the first main surface 3 toward the second main surface 4. The gate trench 71 penetrates the first body region 67 and is formed at intervals from the bottom of the second semiconductor region 52 toward the first main surface 3. The gate trench 71 includes a side wall and a bottom wall. The angle between the side wall of the gate trench 71 and the first main surface 3 in the semiconductor chip 2 can be greater than 90 degrees and less than 92 degrees. The gate trench 71 can be formed into a tapered shape in which the opening width decreases from the opening toward the bottom wall. Preferably, the bottom wall corner of the gate trench 71 is formed into a curved shape. The entire bottom wall of the gate trench 71 can be formed into a curved shape toward the second main surface 4. The insulating film 72 covers the wall surface of the gate trench 71. The insulating film 72 includes an upper insulating film 76 and a lower insulating film 77. The upper insulating film 76 covers the wall surface of the gate trench 71 on the opening side relative to the bottom of the first body region 67.

[0111] The upper insulating film 76 partially covers the wall surface of the gate trench 71 on the bottom wall side relative to the bottom of the first body region 67. The upper insulating film 76 is thinner than the first isolation insulating film 62. The upper insulating film 76 is formed as a gate insulating film. The upper insulating film 76 may include a silicon oxide film. Preferably, the upper insulating film 76 includes a silicon oxide film composed of an oxide of the semiconductor chip 2.

[0112] The lower insulating film 77 covers the wall surface of the gate trench 71 on the bottom wall side relative to the bottom of the first body region 67. The lower insulating film 77 is thicker than the upper insulating film 76. The thickness of the lower insulating film 77 may be approximately equal to the thickness of the first isolation insulating film 62. The lower insulating film 77 may include a silicon oxide film. The lower insulating film 77 may include a silicon oxide film composed of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method.

[0113] The upper electrode 73 is buried in the opening side of the gate trench 71 via the insulating film 72. Specifically, the upper electrode 73 is buried in the opening side of the gate trench 71 via the upper insulating film 76, and the upper electrode 73 faces the first body region 67 via the upper insulating film 76. The upper electrode 73 may be made of conductive polysilicon.

[0114] The lower electrode 74 is buried in the bottom wall side of the gate trench 71 via the insulating film 72. The upper end of the lower electrode 74 protrudes from the lower insulating film 77 toward the upper electrode 73 so as to be joined to the bottom of the upper electrode 73. The upper end of the lower electrode 74 is opposite to the upper insulating film 76 via the lower end of the upper electrode 73 in the lateral direction along the first main surface 3. The lower electrode 74 can be made of conductive polysilicon.

[0115] The intermediate insulating film 75 is interposed between the upper electrode 73 and the lower electrode 74, and electrically insulates the upper electrode 73 from the lower electrode 74 in the gate trench 71. The intermediate insulating film 75 is continuous with the upper insulating film 76 and the lower insulating film 77. The intermediate insulating film 75 is thinner than the lower insulating film 77. The intermediate insulating film 75 may include a silicon oxide film. The intermediate insulating film 75 preferably includes a silicon oxide film composed of an oxide of the lower electrode 74.

[0116] As described above, each unit transistor 22 includes a channel cell 78 controlled by a trench gate structure 70. In this embodiment, two channel cells 78 arranged on both sides of one trench gate structure 70 are controlled by one trench gate structure 70 and are not controlled by other trench gate structures 70.

[0117] Reference Figure 8 In the region along the interior of the trench gate structure 70, a plurality of channel units 78 are formed at intervals from both ends of the trench gate structure 70 in the longitudinal direction (first direction X) of the trench gate structure 70. The plurality of channel units 78 expose the first body region 67 from the region of the first main surface 3 sandwiched between both ends of the plurality of trench gate structures 70.

[0118] Reference Figure 8 Each channel unit 78 includes a plurality of n-type source regions 79 and a plurality of p-type contact regions 80. Figure 8 In the figure, the source region 79 is shaded for clarity. The contact region 80 may also be referred to as a “back gate region”. The n-type impurity concentration of each source region 79 may be 1×10 18 cm -3 Above and 1×10 21 cm -3 the following.

[0119] Reference Figure 8 and Fig. 9 , the source regions 79 are arranged at intervals along each trench gate structure 70. The source regions 79 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3, and are opposed to the upper electrode 73 via the insulating film 72 (upper insulating film 76). All the source regions 79 included in each unit transistor 22 form a unit source of each unit transistor 22.

[0120] Reference Figure 8 and Fig. 9 , each contact region 80 has a higher p-type impurity concentration than the first body region 67. The p-type impurity concentration of each contact region 80 may be 1×10 18 cm -3 Above and 1×10 21 cm -3The contact regions 80 are alternately arranged with the source regions 79 along each trench gate structure 70. The contact regions 80 are formed at intervals from the bottom of the first body region 67 toward the first main surface 3 and face the upper electrode 73 via the insulating film 72 (upper insulating film 76).

[0121] Reference Figure 8 Regarding the two channel units 78 formed on both sides of a trench gate structure 70, the source region 79 in one channel unit 78 is opposite to the source region 79 in the other channel unit 78 via the trench gate structure 70. In addition, the contact region 80 in one channel unit 78 is opposite to the contact region 80 in the other channel unit 78 via the trench gate structure 70.

[0122] Of course, the source region 79 in one channel unit 78 may be opposite to the contact region 80 in another channel unit 78 via the trench gate structure 70. In addition, the contact region 80 in one channel unit 78 may be opposite to the source region 79 in another channel unit 78 via the trench gate structure 70.

[0123] Regarding two channel cells 78 between two trench gate structures 70 , source region 79 in one channel cell 78 is connected to contact region 80 in another channel cell 78 in the second direction Y. In addition, contact region 80 of one channel cell 78 is connected to source region 79 of another channel cell 78 in the second direction Y.

[0124] Of course, the source region 79 in one channel cell 78 may be connected to the source region 79 in another channel cell 78 in the second direction Y. In addition, the contact region 80 of one channel cell 78 may be connected to the contact region 80 in another channel cell 78 in the second direction Y.

[0125] The inner channel unit 78 of the two channel units 78 formed on both sides of the outermost trench gate structure 70 is opposed to the second semiconductor region 52 in the thickness direction via a portion of the first body region 67. On the other hand, the outer channel unit 78 does not include the source region 79 but only includes the contact region 80. This suppresses the formation of a current path in the region between the first trench isolation structure 60 and the outermost trench gate structure 70.

[0126] Reference Figure 7 and Figure 8, the output transistor 20 includes a plurality of unit transistors 22. Each of the plurality of unit transistors 22 includes a trench gate structure 70 and two channel units 78 formed on both sides of the trench gate structure 70. With respect to each unit transistor 22, the trench gate structure 70 constitutes a unit gate, the source region 79 (two channel units 78) constitutes a unit source, and the first semiconductor region 51 constitutes a unit drain.

[0127] As described above, the output transistor 20 includes a first system transistor 21A (see Figure 5 ) and the second system transistor 21B (see Figure 6 The first system transistor 21A includes a plurality of unit transistors 22 systemized (grouped) from a plurality of unit transistors 22 as individual control targets. The second system transistor 21B includes a plurality of unit transistors 22 systemized (grouped) from a plurality of unit transistors 22 other than the first system transistor 21A as individual control targets.

[0128] Reference Figure 7 and Figure 8 In this embodiment, the output transistor 20 includes a plurality of blocks 81 arranged in the output region 6. The block 81 includes a plurality of first blocks 81A and a plurality of second blocks 81B. The first block 81A is respectively arranged with a plurality of first system transistors 21A (see Figure 5 ) of one or more (in this embodiment, a plurality of) unit transistors 22 (see Figure 5 The second block area 81B is an area where the second system transistor 21B (see Figure 5 ) of one or more (in this embodiment, a plurality of) unit transistors 22 (see Figure 5 ) area.

[0129] The first block areas 81A are arranged at intervals in the second direction Y. The number of unit transistors 22 in each first block area 81A is arbitrary. In the present embodiment, two unit transistors 22 are arranged in each first block area 81A. When the number of unit transistors 22 in each first block area 81A increases, the amount of heat generated in each first block area 81A increases. Therefore, the number of unit transistors 22 in each first block area 81A is preferably more than 2 and less than 5.

[0130] The second blocks 81B are alternately arranged with the first blocks 81A in a manner sandwiching one first block 81A along the second direction Y. As a result, heat generation sites attributed to the first blocks 81A can be thinned out by the second blocks 81B, and heat generation sites attributed to the second blocks 81B can be thinned out by the first blocks 81A.

[0131] The number of unit transistors 22 in each second block area 81B is arbitrary. In the present embodiment, two unit transistors 22 are arranged in each second block area 81B. When the number of unit transistors 22 in each second block area 81B increases, the amount of heat generated in each second block area 81B increases.

[0132] Therefore, the number of unit transistors 22 in each second block region 81B is preferably more than 2 and less than 5. Considering the in-plane temperature variation of the output region 6, the number of unit transistors 22 in the second block region 81B is preferably the same as the number of unit transistors 22 in the first block region 81A.

[0133] Reference Figure 6 and Figure 7 , the semiconductor device 1 includes a pair of trench connection structures 90 configured to connect both ends of a plurality of (two in this embodiment) trench gate structures 70 to be systematized (grouped) in each block region 81. That is, the pair of trench connection structures 90 connect both ends of the plurality of trench gate structures 70 to be systematized as the system transistor 21, respectively.

[0134] Reference Figure 6 The trench connection structure 90 on one side is connected to the first ends of multiple (two in this embodiment) corresponding trench gate structures 70 in an arch shape when viewed from above. The trench connection structure 90 on the other side is connected to the second ends of multiple (two in this embodiment) corresponding trench gate structures 70 in an arch shape when viewed from above.

[0135] Specifically, the trench connection structure 90 on one side has a first portion extending in the second direction Y and a plurality of (two in this embodiment) second portions extending in the first direction X. The first portion is opposite to the first ends of the plurality of trench gate structures 70 in a plan view. The second portion extends from the first portion toward the first end in a manner connected to the first end.

[0136] The trench connection structure 90 on the other side has a first portion extending in the second direction Y and a plurality of (two in this embodiment) second portions extending in the first direction X. The first portion is opposite to the second ends of the plurality of trench gate structures 70 in a plan view. The second portion extends from the first portion toward the second end in a manner connected to the second end. The trench connection structure 90 and the plurality of trench gate structures 70 in each block region 81 form a ring-shaped or ladder-shaped trench structure.

[0137] Reference Figure 6 The trench connection structure 90 is formed at a distance from the bottom of the first semiconductor region 51 toward the first main surface 3 , and is opposed to the first semiconductor region 51 via a portion of the second semiconductor region 52 .

[0138] Reference Figure 7 , the trench connection structure 90 can be formed to have approximately the same width and approximately the same depth as the trench gate structure 70. Of course, the first portion and the second portion of the trench connection structure 90 can have different widths. For example, the second portion of the trench connection structure 90 can be formed to have a narrower width than the first portion of the trench connection structure 90.

[0139] In this case, the width of the first portion may be approximately equal to the width of the first trench isolation structure 60, and the width of the second portion may be approximately equal to the width of the trench gate structure 70. In addition, in this case, the depth of the first portion may be approximately equal to the depth of the first trench isolation structure 60, and the depth of the second portion may be approximately equal to the depth of the trench gate structure 70.

[0140] Reference Figure 6 , the trench connection structure 90 on the other side has a structure similar to the trench connection structure 90 on one side, except that it is connected to the second end of the trench gate structure 70. Hereinafter, the configuration of the trench connection structure 90 on one side will be described, and the description of the configuration of the trench connection structure 90 on the other side will be omitted.

[0141] Reference Figure 7 and Figures 11 to 13 The trench connection structure 90 includes a connection trench 91, a connection insulating film 92, and a connection electrode 93. The connection trench 91 is formed in the first main surface 3 to define a wall surface of the trench connection structure 90. The connection trench 91 is connected to the plurality of gate trenches 71.

[0142] The connecting insulating film 92 covers the wall surface of the connecting groove 91. The connecting insulating film 92 is connected to the upper insulating film 76, the lower insulating film 77 and the intermediate insulating film 75 at the connecting groove 91 and the gate groove 71. The connecting insulating film 92 is thicker than the upper insulating film 76. The thickness of the connecting insulating film 92 can be approximately equal to the thickness of the lower insulating film 77. The connecting insulating film 92 may include a silicon oxide film. The connecting insulating film 92 may include a silicon oxide film composed of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method.

[0143] The connection electrode 93 is buried in the connection trench 91 via the connection insulating film 92, and is opposed to the second semiconductor region 52 and the first body region 67 via the connection insulating film 92. The connection electrode 93 is connected to the lower electrode 74 at the connecting portion between the connection trench 91 and the gate trench 71, and is electrically insulated from the upper electrode 73 by the intermediate insulating film 75. The connection electrode 93 is composed of a lead portion of the lower electrode 74 extending from the inside of the gate trench 71 to the inside of the connection trench 91. The connection electrode 93 may include conductive polysilicon.

[0144] Reference Fig. 9 and Fig.10 The semiconductor device 1 includes a main surface insulating film 94 selectively covering the first main surface 3 in the output region 6. The main surface insulating film 94 is connected to the insulating film 72 (upper insulating film 76) and the connecting insulating film 92, and exposes the first isolating electrode 63, the upper electrode 73 and the connecting electrode 93.

[0145] Reference Fig. 9 and Fig.10 , the main surface insulating film 94 is thinner than the first isolation insulating film 62. The main surface insulating film 94 is thinner than the lower insulating film 77. The main surface insulating film 94 is thinner than the connection insulating film 92. The thickness of the main surface insulating film 94 can be approximately the same as the thickness of the upper insulating film 76. The main surface insulating film 94 can include a silicon oxide film. The main surface insulating film 94 preferably includes a silicon oxide film composed of an oxide of the semiconductor chip 2.

[0146] Reference Figures 10 to 13 , the semiconductor device 1 includes a field insulating film 95 that selectively covers the first main surface 3 inside and outside the output region 6. The field insulating film 95 is thicker than the main surface insulating film 94. The field insulating film 95 is thicker than the upper insulating film 76. The thickness of the field insulating film 95 can be approximately the same as the thickness of the first isolation insulating film 62. The field insulating film 95 may include a silicon oxide film. The field insulating film 95 may include a silicon oxide film composed of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method.

[0147] The field insulating film 95 is formed in the output region 6 along the inner wall of the first trench isolation structure 60 and the outer wall of the second trench isolation structure 100 (see FIG. Fig.15 etc.) covers the first main surface 3 and is connected to the first isolation insulating film 62, the connection insulating film 92, the main surface insulating film 94 and the second isolation insulating film 102 (see Fig.15 The field insulating film 95 covers the first main surface 3 along the outer wall of the first trench isolation structure 60 outside the output region 6 and is connected to the first isolation insulating film 62 .

[0148] Reference Figures 9 to 13 The interlayer insulating layer 11 covers the first trench isolation structure 60 , the trench gate structure 70 , the trench connection structure 90 , the main surface insulating film 94 and the field insulating film 95 in the output region 6 .

[0149] Reference Figure 6 In this embodiment, in the output region 6, a plurality of blocks 81 are formed on both sides of the inner element region 8 in the first direction X. The block 81 formed on one side of the inner element region 8 in the first direction X is opposed to the block 81 formed on the other side of the inner element region 8 in the first direction X across the inner element region 8 in the first direction X. The block 81 opposing each other in the first direction X are electrically connected to each other.

[0150] Reference Figure 6 As described above, the semiconductor device 1 includes a plurality of gate wirings 16 arranged in the interlayer insulating layer 11. The gate wirings 16 are led to the output region 6 and the control region 7. The gate wirings 16 are electrically connected to the output transistors 20 in the output region 6, and are electrically connected to the control circuit 23 (gate control circuit 24) in the control region 7 (see Figure 4 ). The gate wiring 16 is individually controlled by the control circuit 23 (gate control circuit 24) (see Figure 4 ) generates multiple gate signals and sends them to the output transistor 20.

[0151] The gate wiring 16 includes a first system gate wiring 16A and a second system gate wiring 16B. The first system gate wiring 16A individually transmits a gate signal to the first system transistor 21A. The first system gate wiring 16A is electrically connected to the trench gate structure 70 for the first system transistor 21A via a plurality of through-hole electrodes 97 arranged in the interlayer insulating layer 11. Specifically, the first system gate wiring 16A is electrically connected to the corresponding upper electrode 73 and the corresponding connection electrode 93 via the through-hole electrode 97.

[0152] That is, the upper electrode 73 and the lower electrode 74 for the first system transistor 21A are simultaneously controlled to be turned on and off by the same gate signal. This suppresses the voltage drop between the upper electrode 73 and the lower electrode 74, and suppresses undesirable electric field concentration. As a result, the reduction in withstand voltage (breakdown voltage) otherwise caused by electric field concentration is suppressed.

[0153] The second system gate wiring 16B is electrically independent from the first system gate wiring 16A, and individually sends a gate signal to the second system transistor 21B. The second system gate wiring 16B is electrically connected to the trench gate structure 70 for the second system transistor 21B via a via electrode 97 arranged in the interlayer insulating layer 11. Specifically, the second system gate wiring 16B is electrically connected to the corresponding upper electrode 73 and the corresponding connection electrode 93 via the via electrode 97.

[0154] That is, the upper electrode 73 and the lower electrode 74 for the second system transistor 21B are simultaneously controlled to be turned on and off by the same gate signal. This suppresses the voltage drop between the upper electrode 73 and the lower electrode 74, and suppresses the undesired electric field concentration. As a result, the reduction in withstand voltage (breakdown voltage) otherwise caused by electric field concentration is suppressed.

[0155] Reference Figures 10 to 13The gate wiring 16 includes a first gate wiring 161 included in the first wiring layer 12 and a second gate wiring 162 included in the second wiring layer 13. The first gate wiring 161 may include a first system gate wiring 16A and a second system gate wiring 16B. The second gate wiring 162 may include a first system gate wiring 16A and a second system gate wiring 16B.

[0156] Reference Figures 9 to 13 , the semiconductor device 1 includes a source wiring 98 disposed in the interlayer insulating layer 11. The source wiring 98 is electrically connected to the source terminal 17, the first trench isolation structure 60, and the channel unit 78. Specifically, the source wiring 98 is electrically connected to the first trench isolation structure 60 and the channel unit 78 via a via electrode 97 disposed in the interlayer insulating layer 11.

[0157] Reference Figure 7 The through-hole electrode 97 for each channel unit 78 is arranged in a manner spanning two adjacent channel units 78, and is formed into a strip shape extending along each channel unit 78 when viewed from above. Therefore, the source terminal 17 is electrically connected to the system sources of all the system transistors 21 (the unit sources of the unit transistors 22).

[0158] Reference Figures 9 to 13 The source wiring 98 includes a first source wiring (first output wiring) 98A included in the first wiring layer 12 and a second source wiring (second output wiring) 98B included in the second wiring layer 13. The first source wiring 98A and the second source wiring 98B are electrically connected via a through-hole electrode (not shown). A plurality of first source wirings 98A and a plurality of second source wirings 98B are formed to overlap substantially the entire area of ​​the first main surface 3 where the output transistor 20 is formed when viewed from above.

[0159] Fig.14 is a plan view showing the inner element region 8, and is Figure 6 An enlarged view of region XIV is shown. Fig.15 It is along Fig.14 A cross-sectional view taken along line XV-XV is shown. Fig.16 It is along Fig.14 A cross-sectional view taken along line XVI-XVI is shown. Fig.17 It is along Fig.14 A cross-sectional view taken along line XVII-XVII is shown. Fig.18 It is along Fig.14 A cross-sectional view taken along line XVIII-XVIII is shown.

[0160] As described above, on the first main surface 3, the inner element region 8 surrounded by the output region 6 is formed in the central portion of the output region 6. Figure 6 , Fig.14 , Fig.15 and Fig.17 The configuration of the inner element region 8 will be described.

[0161] Reference Figure 6 and Fig.14 The inner element region 8 is an area insulated and isolated from the output region 6. In this embodiment, the inner element region 8 is defined as a polygon having four sides parallel to the periphery of the first main surface 3 when viewed from above. Figure 6 and Fig.14 In the example of FIG. 8 , the inner element region 8 has a substantially rectangular shape. The inner element region 8 has a convex portion 8 a protruding outward in the first direction X in a region facing the control region 7 across the output region 6 .

[0162] Reference Fig.14 The semiconductor device 1 includes a second trench isolation structure (isolation structure) 100 (trench separation structure) as an example of a regional isolation structure defining the periphery of the inner element region 8 on the first main surface 3. The second trench isolation structure 100 may be referred to as a "deep trench isolation (DTI) structure". The second trench isolation structure 100 may be referred to as an "inner isolation structure".

[0163] Reference Fig.14 , the second trench isolation structure 100 is formed in a ring shape surrounding the outer periphery of the inner element region 8 when viewed from above. In the present embodiment, the second trench isolation structure 100 is formed in a substantially quadrilateral ring shape having four sides parallel to the periphery of the first main surface 3 when viewed from above. The second trench isolation structure 100 has a convex portion 100a protruding outward in the first direction X in a region opposing the control region 7 across the output region 6. The planar shape of the second trench isolation structure 100 is arbitrary and can be formed in a polygonal ring shape.

[0164] Reference Fig.15 and Fig.17 , the second trench isolation structure 100 includes a second isolation trench (isolation trench) 101, a second isolation insulating film (isolation insulator) 102, and a second isolation electrode (isolation electrode) 103. That is, the second trench isolation structure 100 has a single electrode structure including a single electrode (second isolation electrode 103) buried in the second isolation trench 101 via an insulator (second isolation insulator film 102).

[0165] Reference Fig.15 and Fig.17, the second isolation trench 101 is dug downward from the first main surface 3 toward the second main surface 4. The second isolation trench 101 is formed at intervals from the bottom of the second semiconductor region 52 toward the first main surface 3. The second isolation insulating film 102 covers the wall surface of the second isolation trench 101. The second isolation insulating film 102 may include a silicon oxide film. The second isolation insulating film 102 may include a silicon oxide film composed of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method. The second isolation electrode 103 is buried in the second isolation trench 101 across the second isolation insulating film 102. The second isolation electrode 103 may include conductive polysilicon.

[0166] Reference Fig.15 and Fig.17 , the second trench isolation structure 100 has a second isolation width W3 and a second isolation depth D3. The second isolation depth D3 may be the same as the first isolation depth D1 (D3=D1). The second isolation depth D3 preferably exceeds the trench depth D2 (D3>D2). The second isolation width W3 is the width in a direction perpendicular to the direction in which the second trench isolation structure 100 extends when viewed from above. The second isolation width W3 may be the same as the first isolation width W1 (W3=W1).

[0167] The aspect ratio D3 / W3 of the second trench isolation structure 100 may be greater than 1 and less than or equal to 5. The aspect ratio D3 / W3 is a ratio of the second isolation depth D3 to the second isolation width W3. The aspect ratio D3 / W3 is preferably greater than 2. The bottom wall of the second trench isolation structure 100 is preferably spaced from the bottom of the second semiconductor region 52 by 1 μm or more and 5 μm or less.

[0168] Reference Fig.14 , the second trench isolation structure 100 has a corner portion, and the corner portion is connected in an arc shape (curved shape) to the portion extending in the first direction X and the second direction Y. In the present embodiment, the four corner portions of the second trench isolation structure 100 are formed in an arc shape. In other words, the inner element region 8 is defined as a substantially quadrilateral shape having four corner portions, each of which extends in an arc shape. Preferably, the corner portion of the second trench isolation structure 100 has a constant second isolation width W3 along the arc direction.

[0169] Reference Fig.15 and Fig.17 , the second isolation trench 101 includes a side wall and a bottom wall. The angle between the side wall of the second isolation trench 101 and the first main surface 3 in the semiconductor chip 2 can be greater than 90 degrees and less than 92 degrees. The second isolation trench 101 can be formed into a tapered shape with an opening width that decreases from the opening toward the bottom wall. The bottom wall corner of the second isolation trench 101 is preferably formed into a curved shape. The entire bottom wall of the second isolation trench 101 can be formed into a bulge toward the second main surface 4.

[0170] Reference Fig.15 and Fig.17 , a second isolation insulating film 102 is formed on the wall surface of the second isolation trench 101. Specifically, the second isolation insulating film 102 is formed in the form of a film on the entire wall surface of the second isolation trench 101, and defines a recessed space in the second isolation trench 101. The second isolation insulating film 102 preferably includes a silicon oxide film. Particularly preferably, the second isolation insulating film 102 includes a silicon oxide film composed of an oxide of the semiconductor chip 2.

[0171] Reference Fig.15 and Fig.17 , the second isolation electrode 103 is buried in the second isolation trench 101 as an integral body through the second isolation insulating film 102. In the present embodiment, the second isolation electrode 103 is made of conductive polysilicon. The source potential is applied to the second isolation electrode 103. The second isolation electrode 103 has an electrode surface (isolation electrode surface) exposed from the second isolation trench 101. The electrode surface of the second isolation electrode 103 may be recessed in a curved shape toward the bottom wall of the second isolation trench 101. The electrode surface of the second isolation electrode 103 is preferably spaced apart from the first main surface 3 to the bottom wall of the second isolation trench 101 in the depth direction of the second isolation trench 101.

[0172] Reference Fig.15 and Fig.17 The field insulating film 95 covers the first main surface 3 in the inner device region 8. The field insulating film 95 covers the first main surface 3 along the inner wall of the second trench isolation structure 100 in the inner device region 8 and is connected to the second isolation insulating film 102.

[0173] As described above, the temperature sensor element 9 is arranged in the inner element region 8. Fig.14 and Fig.15 The configuration of the temperature sensor element 9 will be described.

[0174] Reference Fig.14 and Fig.15 In the present embodiment, the temperature sensor element 9 is a temperature sensing diode 110. The temperature sensing diode 110 is, for example, a polysilicon diode. The temperature sensing diode 110 includes a plurality of temperature sensing diode elements 111. The temperature sensing diode 110 is in the form of a diode array in which a plurality of temperature sensing diode elements 111 are connected in series in a forward direction. Although not shown, in the temperature sensing diode 110, the temperature sensing diode elements 111 may be connected in parallel. In addition, the number of the temperature sensing diode elements 111 included in the temperature sensing diode 110 may be, for example, two to four (in Fig.14In the example of FIG. 1 , three are used). Furthermore, the number of the temperature sensing diode elements 111 included in the temperature sensing diode 110 is not limited to a plural number, but may be one.

[0175] Reference Fig.15 , each temperature sensing diode element 111 includes a polysilicon layer 113 formed on the first main surface 3 in the inner element region 8. More specifically, the polysilicon layer 113 is formed on the field insulating film 95. The polysilicon layer 113 is electrically insulated from the first main surface 3 by the field insulating film 95. The thickness of the polysilicon layer 113 can be 0.2μm or more and 1.0μm or less. The temperature sensing diode element 111 is formed by selectively introducing n-type impurities and p-type impurities into the polysilicon layer 113. The temperature sensing diode element 111 includes an anode region 114 formed in the polysilicon layer 113 and a cathode region 115 formed in the polysilicon film 113. The temperature sensing diode element 111 is a diode element having the anode region 114 as an anode and the cathode region 115 as a cathode.

[0176] Reference Fig.14 Each polysilicon layer 113 is formed to have a quadrilateral shape in a top view. A plurality of polysilicon layers 113 are arranged in the first direction X. A cathode region 115 is formed in a central portion of the polysilicon layer 113. In the present embodiment, the cathode region 115 is exposed from the first surface 113a and the second surface 113b of the polysilicon layer 113.

[0177] Reference Fig.14 , the anode region 114 is formed along the periphery of the cathode region 115. In the present embodiment, the anode region 114 is formed in a C-shape or a U-shape surrounding the cathode region 115 in a top view. The anode region 114 may be formed in a ring shape surrounding the entire circumference of the cathode region 115. The anode region 114 is electrically connected to the cathode region 115. In the present embodiment, the anode region 114 is exposed from the first surface 113a and the second surface 113b of the polysilicon layer 113. The anode region 114 is connected to the cathode region 115 over the entire thickness of the polysilicon layer 113. The anode region 114 forms a pn junction at the interface with the cathode region 115. In the present embodiment, since the anode region 114 surrounds the cathode region 115 in a C-shape or a U-shape, the pn junction also has a C-shape or a U-shape in a top view. The anode region 114 may surround the cathode region 115 in a ring shape. In this case, the pn junction has a ring shape in a top view.

[0178] Reference Fig.14 and Fig.16, the temperature sensing diode 110 includes a diode wiring 116. The diode wiring 116 has one end 116a and the other end 116b. The first connecting wiring 10A is electrically connected to the one end 116a of the diode wiring 116 via the through-hole electrode 117. The second connecting wiring 10B is electrically connected to the other end 116b of the diode wiring 116 via the through-hole electrode 117. Therefore, the temperature sensor element 9 (temperature sensing diode 110) is connected to the control circuit 23 (see FIG. 2 ) of the control region 7 via the first connecting wiring 10A and the second connecting wiring 10B. Figure 4 ).

[0179] Reference Fig.14 A pair of block regions 81 facing each other across the inner element region 8 in the first direction X are electrically connected to each other. The connection electrodes 93 (see Fig.17 and Fig.18 ) are connected by a gate connection wiring 120. The gate connection wiring 120 includes a first gate connection wiring 121 and a second gate connection wiring 122 which are opposed to each other in the first direction X.

[0180] Reference Fig.14 The first gate connection wiring 121 has a strip shape extending in the second direction Y. The first gate connection wiring 121 is connected to one side ( Fig.14 The block area 81 on the upper side of the block is formed by overlapping.

[0181] Reference Fig.17 The first gate connection wiring 121 is electrically connected to the connection electrode 93 of the block area 81 via the through-hole electrode 121A.

[0182] Reference Fig.14 The second gate connection wiring 122 has a strip shape extending in the second direction Y. The second gate connection wiring 122 is connected to the other side ( Fig.14 The block area 81 on the lower side of the block is formed by overlapping.

[0183] Reference Fig.18 The second gate connection wiring 122 is electrically connected to the connection electrode 93 of the block area 81 via the through-hole electrode 122A.

[0184] As described above, in this embodiment, the convex portion 8a is formed in the inner element region 8. Fig.14In order to avoid interference with the convex portion 8a, the trench connection structure 90 opposite to the convex portion 8a in the first direction X on the first main surface 3 is retracted / retreat further outward (toward the control region 7) than other trench connection structures 90 in the first direction X. The second gate connection wiring 122 is arranged so as to overlap with all the connection electrodes 93 (trench connection structure 90) of the block area 81 on the other side in the normal direction Z. The second gate connection wiring 122 crosses the convex portion 8a of the inner element region 8 in the second direction Y when viewed from above.

[0185] Reference Fig.14 , the gate connection wiring 120 also includes a third gate connection wiring 123. The third gate connection wiring 123 electrically connects the first gate connection wiring 121 and the second gate connection wiring 122. The third gate connection wiring 123 has a strip shape extending in the first direction X. In the present embodiment, the third gate connection wiring 123 has a pair of third gate connection wirings 123 that are opposite to each other in the second direction Y. The third gate connection wiring 123 crosses the inner element region 8 in the first direction X when viewed from above. The pair of third gate connection wirings 123 sandwich the temperature sensor element 9 in the second direction Y when viewed from above. The number of the third gate connection wirings 123 is not limited to a pair (two), and may be one.

[0186] Reference Fig.17 and Fig.18 The gate connection wiring 120 includes a lower wiring included in the first wiring layer 12 and an upper wiring included in the second wiring layer 13. Specifically, the first gate connection wiring 121 (see Fig.17 ) includes a first gate connection wiring 121 included in the first wiring layer 12 and a first gate connection wiring 121 included in the second wiring layer 13. The second gate connection wiring 122 (see Fig.18 ) includes the second gate connection wiring 122 included in the first wiring layer 12 and the second gate connection wiring 122 included in the second wiring layer 13. The third gate connection wiring 123 (see Fig.17 and Fig.18 ) includes a third gate connection wiring 123 included in the first wiring layer 12 and a third gate connection wiring 123 included in the second wiring layer 13. The first gate connection wiring 121, the second gate connection wiring 122, and the third gate connection wiring 123 included in the first wiring layer 12 are electrically connected to the first gate connection wiring 121, the second gate connection wiring 122, and the third gate connection wiring 123 included in the second wiring layer 13 via through holes (not shown), respectively.

[0187] Fig.19A It is along Fig.14 A cross-sectional view taken along line XIXA-XIXA is shown. Fig.19B It is along Figure 6 A cross-sectional view taken along line XIXB-XIXB is shown.

[0188] Reference Fig.19A , in the area between the control area 7 and the inner element area 8 in the output area 6, the first source wiring 98A and the second source wiring 98B are arranged above the first main surface 3. As described above, the first source wiring 98A is included in the first wiring layer 12, and the second source wiring 98B is included in the second wiring layer 13. In this area, the second wiring layer 13 includes the first connecting wiring 10A and the second connecting wiring 10B and the second source wiring 98B. In this area, the first connecting wiring 10A and the second connecting wiring 10B extend along the first direction X. The first connecting wiring 10A and the second connecting wiring 10B are sandwiched by multiple second source wirings 98B in the second direction Y. The first source wiring 98A overlaps with the first connecting wiring 10A and the second connecting wiring 10B in the normal direction Z.

[0189] The first connection wiring 10A and the second connection wiring 10B are not included in the first wiring layer 12. The first connection wiring 10A and the second connection wiring 10B are insulated and isolated from each other. The first connection wiring 10A and the second connection wiring 10B are insulated and isolated from the second source wiring 98B. The first connection wiring 10A and the second connection wiring 10B are also insulated and isolated from the first source wiring 98A included in the first wiring layer 12.

[0190] The first source wiring 98A is formed so as to overlap the entire region of the first main surface where the output transistor 20 is arranged when viewed from above. The second source wiring 98B is formed so as to overlap the entire region of the first main surface 3 where the output transistor 20 is formed when viewed from above, except for the region where the connection wiring 10 (the first connection wiring 10A and the second connection wiring 10B) is arranged.

[0191] A trench gate structure 70 is disposed below the first and second connection wirings 10A and 10B. That is, the trench gate structure 70 is formed below the first and second connection wirings 10A and 10B so as to overlap with the first and second connection wirings 10A and 10B in a plan view.

[0192] In the present embodiment, the first connection wiring 10A and the second connection wiring 10B are included in the wiring layer (second wiring layer 13). Therefore, even when the output transistor 20 is arranged in a manner overlapping with the first connection wiring 10A and the second connection wiring 10B when viewed from above, the output transistor 20 is not electrically connected to the connection wirings 10A and 10B. In this case, since the first connection wiring 10A and the second connection wiring 10B can be arranged above the trench gate structure 70, the output transistor 20 can be arranged in substantially the entire area of ​​the circumferential direction of the quadrilateral annular output region 6 surrounding the entire circumference of the inner element region 8.

[0193] Reference Fig.19B , in the area between the control area 7 and the inner element area 8 in the output area 6, the first gate wiring 161 and the second gate wiring 162 are arranged above the first main surface 3. As described above, the first gate wiring 161 is included in the first wiring layer 12, and the second gate wiring 162 is included in the second wiring layer 13. In this area, the second wiring layer 13 includes the second gate wiring 162, the first connecting wiring 10A and the second connecting wiring 10B. The first connecting wiring 10A and the second connecting wiring 10B are not included in the first wiring layer 12. In this area, the first connecting wiring 10A and the second connecting wiring 10B extend along the first direction X like the first gate wiring 161 and the second gate wiring 162.

[0194] The first connection wiring 10A and the second connection wiring 10B are insulated from each other. The first connection wiring 10A and the second connection wiring 10B are insulated from the second gate wiring 162 . The first connection wiring 10A and the second connection wiring 10B are also insulated from the first gate wiring 161 included in the first wiring layer 12 .

[0195] Reference Figure 3 , Figure 4 , Fig.19A and Fig.19B , the first temperature detection signal from the temperature sensor element 9 is provided to the overheat protection circuit 27 via the first connection wiring 10A and the second connection wiring 10B. The overheat protection circuit 27 controls the on / off operation of the output transistor 20 based on the first temperature detection signal from the temperature sensor element 9. When it is determined that the output region 6 is in an overheated state, the overheat protection circuit 27 controls a part or all of the output transistor 20 to be turned off. This prevents the semiconductor device 1 from being damaged.

[0196] Fig. 20 1 is a plan view showing an example of a layout within the semiconductor chip 2 of the semiconductor device 191 according to the reference embodiment. Fig. 20 In the embodiment, the output region 6 is formed in a manner surrounding the inner element region 8. However, in Fig. 20In the reference embodiment shown in FIG. 1 , the output transistor 20 is not arranged in the region 192 between the control region 7 and the inner element region 8 in the output region 6. Fig. 20 In the illustrated reference embodiment, the output transistor 20 is not arranged in the region of the output region 6 that overlaps with the connection wiring 10 in a plan view (the region below the connection wiring 10 in the output region 6 ).

[0197] In the semiconductor device 1 according to the first embodiment, as Fig.19A As shown in FIG. 1 , the transistor 20 is also formed in the entire region in the second direction Y between the control region 7 and the inner element region 8 in the output region 6. That is, the output transistor 20 is also formed in the region of the output region 6 that overlaps with the connection wiring 10 when viewed from above. By effectively using this region as the layout region for the output transistor 20, Fig. 20 Compared with the reference embodiment shown, the semiconductor device 1 can improve the mounting efficiency of the output transistor 20 on the first main surface 3. Therefore, in the semiconductor device 1, the chip area can be reduced.

[0198] In addition, the first connection wiring 10A and the second connection wiring 10B included in the first wiring layer 12 are not included in the first wiring layer 12, but are included in the second wiring layer 13 formed on the first wiring layer 12. Therefore, the routing of the first source wiring 98A in the first wiring layer 12 is not affected. Therefore, the source potential can be satisfactorily applied to the output transistor 20 (unit transistor 22). As a result, it is possible to improve the mounting efficiency of the output transistor 20 while satisfactorily applying the source potential to the output transistor 20.

[0199] Fig.21 is a plan view showing the output region 6 and the inner element region 208 of the semiconductor device 201 according to the second embodiment of the present disclosure, and is Figure 6 The corresponding view. Fig. 22 is a plan view showing the inner element region 208, and is Fig.21 An enlarged view of region XXII is shown. Fig.23 It is along Fig. 22 A cross-sectional view taken along line XXIII-XXIII is shown. Fig.24 It is along Fig. 22 A cross-sectional view taken along line XXIV-XXIV is shown. Fig.25 It is along Fig. 22 2. A cross-sectional view taken along line XXV-XXV shown in FIG. 2. In the second embodiment, only the parts different from the first embodiment will be mainly described. The same components as those described so far will be denoted by the same reference numerals, and description thereof will be omitted.

[0200] The difference between the second embodiment and the first embodiment is that not only the temperature sensor element 9 as the first element but also the current monitoring element 209 as the second element are arranged in the inner element region 208. Another difference between the second embodiment and the first embodiment is that a third trench isolation structure 140 (see FIG. 1 ) is formed inside the inner element region 208. Fig. 22 ).

[0201] Reference Fig.21 and Fig. 22 The size of the inner element region 208 in the second direction Y is larger than that of the inner element region 8 (see Figure 6 and Fig.14 ). Except for this, the inner device region 208 has the same structure as the inner device region 8. Like the inner device region 8, the outer periphery of the inner device region 208 is defined by the second trench isolation structure 100.

[0202] As described above, the temperature sensor element 9 and the current monitoring element 209 as examples of the second element are arranged in the inner element region 208. The inner element region 208 is arranged side by side with the temperature sensor element 9 in the second direction Y.

[0203] In the semiconductor device 201 according to the second embodiment, the current monitoring element 209 generates a monitoring current for monitoring the output current Io of the output transistor 20 (see Figure 4 The current monitoring element 209 includes a transistor having the same configuration as the output transistor 20, and is controlled to be turned on and off simultaneously with the output transistor 20 to generate a monitoring current linked to the output current Io.

[0204] The current monitoring element 209 is used to replace the current monitoring circuit 25 (see Figure 4 ). Overcurrent protection circuit 26 (see Figure 4 ) generates an electrical signal for controlling the gate control circuit 24 based on the monitoring current from the current monitoring element 209, and controls the on / off operation of the output transistor 20 in cooperation with the gate control circuit 24.

[0205] The following will refer to Figure 22 to Figure 25 The configuration of the current monitoring element 209 will be described.

[0206] Reference Fig. 22, the third trench isolation structure 140 defines a current detection region 209A in which a current monitoring element 209 is arranged in the inner element region 208. The third trench isolation structure 140 can be referred to as a "DTI structure". In the present embodiment, the third trench isolation structure 140 is formed into a quadrilateral ring having four sides parallel to the periphery of the first main surface 3 when viewed from above, and defines a current detection region 209A having a quadrilateral shape. According to the planar shape of the third trench isolation structure 140, the current detection region 209A can be defined as a polygonal shape. In this case, the planar shape of the third trench isolation structure 140 can be formed as a polygonal ring.

[0207] Reference Fig.23 The third trench isolation structure 140 includes a third isolation trench 141, a third isolation insulating film 142, and a third isolation electrode 143. That is, the third trench isolation structure 140 has a single electrode structure including a single electrode (third isolation electrode 143) buried in the third isolation trench 141 via an insulator (third isolation insulating film 142).

[0208] The third isolation trench 141 is dug downward from the first main surface 3 toward the second main surface 4. The third isolation trench 141 is formed at intervals from the bottom of the second semiconductor region 52 toward the first main surface 3. The third isolation insulating film 142 covers the wall surface of the third isolation trench 141. The third isolation insulating film 142 may include a silicon oxide film. The third isolation insulating film 142 may include a silicon oxide film composed of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method. The third isolation electrode 143 is buried in the third isolation trench 141 across the third isolation insulating film 142. The third isolation electrode 143 may include conductive polysilicon.

[0209] The aspect ratio D4 / W4 of the third trench isolation structure 140 may be greater than 1 and less than or equal to 5. The aspect ratio D4 / W4 is a ratio of the third isolation depth D4 to the third isolation width W4. The aspect ratio D4 / W4 is preferably greater than 2. The bottom wall of the third trench isolation structure 140 is preferably spaced from the bottom of the second semiconductor region 52 by 1 μm or more and 5 μm or less.

[0210] Reference Fig.23 , the third isolation trench 141 includes a side wall and a bottom wall. The angle between the side wall of the third isolation trench 141 and the first main surface 3 in the semiconductor chip 2 can be greater than 90 degrees and less than 92 degrees. The third isolation trench 141 can be formed into a cone shape in which the opening width decreases from the opening toward the bottom wall. The bottom wall corner of the third isolation trench 141 is preferably formed into a curved shape. The entire bottom wall of the third isolation trench 141 can be formed into a curved shape toward the second main surface 4.

[0211] Reference Fig.23A third isolation insulating film 142 is formed on the wall surface of the third isolation trench 141. Specifically, the third isolation insulating film 142 is formed in a film shape on the entire wall surface of the third isolation trench 141, and defines a recessed space in the third isolation trench 141. The third isolation insulating film 142 preferably includes a silicon oxide film. More preferably, the third isolation insulating film 142 includes a silicon oxide film composed of an oxide of the semiconductor chip 2.

[0212] Reference Fig.23 , the third isolation electrode 143 is buried in the third isolation trench 141 as an integral body through the third isolation insulating film 142. In the present embodiment, the third isolation electrode 143 comprises conductive polysilicon. The source potential is applied to the third isolation electrode 143. The third isolation electrode 143 has an electrode surface (isolation electrode surface) exposed from the third isolation trench 141. The electrode surface of the third isolation electrode 143 may be recessed in a curved shape toward the bottom wall of the third isolation trench 141. The electrode surface of the third isolation electrode 143 is preferably spaced apart from the first main surface 3 to the bottom wall of the third isolation trench 141 in the depth direction of the third isolation trench 141.

[0213] Reference Fig.23 The semiconductor device 201 includes a second body region 167 formed in the surface portion of the first main surface 3 in the current detection region 209A. The p-type impurity concentration of the second body region 167 may be 1×10 16 cm -3 Above and 1×10 18 cm -3 The p-type impurity concentration of the second body region 167 is preferably approximately equal to the p-type doping concentration of the first body region 67 (see Figure 7 Preferably, the second body region 167 has approximately the same thickness (depth) as the first body region 67. According to this structure, the second body region 167 can be formed simultaneously with the first body region 67.

[0214] In the current detection region 209A, the second body region 167 is formed on the entire surface of the first main surface 3. The second body region 167 is in contact with the inner peripheral wall of the third isolation trench 141 and is not in contact with the inner peripheral wall of the second isolation trench 101.

[0215] Reference Fig. 22 The semiconductor device 201 includes a monitoring transistor 220 formed on the first main surface 3 in the current detection region 209A. The monitoring transistor 220 includes a plurality of unit transistors 222 formed together on the first main surface 3 of the current detection region 209A. The unit transistor 222 is formed in a strip shape extending in the first direction X when viewed from above. In the monitoring transistor 220, the output current Io (see Figure 4 ) corresponds to the monitoring current.

[0216] Reference Fig.23 , each unit transistor 222 includes a trench gate structure 170 and a channel unit controlled by the trench gate structure 170. In the present embodiment, each unit transistor 222 includes a pair of channel units formed on both sides of a trench gate structure 170. Each channel unit includes a plurality of n-type source regions 179 and a plurality of p-type contact regions 180.

[0217] The trench gate structures 170 are arranged at intervals in the second direction Y in a plan view, and are each formed in a strip shape extending in the first direction X. That is, the trench gate structures 170 are formed in a strip shape extending in the first direction X in a plan view.

[0218] Reference Fig.23 , the trench gate structure 170 has a trench width W5 and a trench depth D5. The trench width W5 may be approximately equal to the trench width W2 (W5≈W2). The trench depth D5 may be approximately equal to the trench depth D2 (D5≈D2). The aspect ratio D5 / W5 of the trench gate structure 170 may be equal to the aspect ratio D2 / W2 of the trench gate structure 70.

[0219] The trench gate structure 170 includes a gate trench 171, an insulating film 172, an upper electrode 173, a lower electrode 174, and an intermediate insulating film 175. In other words, the trench gate structure 170 has a multi-electrode structure including a plurality of electrodes (upper electrode 173 and lower electrode 174) buried in the gate trench 171 in the upper and lower directions via an insulator (insulating film 172 and intermediate insulating film 175). The insulating film 172 includes an upper insulating film 176 and a lower insulating film 177. The gate trench 171, the insulating film 172, the upper electrode 173, the lower electrode 174, the intermediate insulating film 175, the upper insulating film 176, and the lower insulating film 177 have the same Fig. 9 The gate trench 71, insulating film 72, upper electrode 73, lower electrode 74, intermediate insulating film 75, upper insulating film 76 and lower insulating film 77 shown have the same structure.

[0220] The first end and the second end of each trench gate structure 170 are connected by a trench connection structure 190. The trench connection structure 190 is similar to the trench connection structure 90 (see Figure 7 Therefore, the description thereof will be omitted.

[0221] Reference Fig.23 The semiconductor device 201 includes a field insulating film 155 of the first main surface 3 selectively covering the inside and outside of the current detection region 209A. The thickness of the field insulating film 155 may be the same as the thickness of the field insulating film 95 (see Fig. 9The field insulating film 155 may include a silicon oxide film. The field insulating film 155 may include a silicon oxide film composed of an oxide of the semiconductor chip 2, or may include a silicon oxide film formed by a CVD method.

[0222] The monitoring transistor 220 is turned on and off controlled at the same timing as the output transistor 20. The monitoring transistor 220 generates an output current Io (see Figure 4 The monitoring current generated by the monitoring transistor 220 is supplied to the overcurrent protection circuit 26 (see FIG. 26 ) of the control circuit 23 in the control area 7 via the connection wiring 210. Figure 4 ).

[0223] The monitoring transistor 220 may include a first system monitoring transistor and a second system monitoring transistor corresponding to the first system transistor 21A and the second system transistor 21B, respectively. Each system monitoring transistor may be turned on and off at the same timing as the corresponding system transistor 21A or 21B, and may generate a system current Is (see Figure 4 ) increases and decreases in tandem with the system monitoring current.

[0224] like Fig. 22 As shown, one end of the connection wiring 210 is connected to the current monitoring element 209. The connection wiring 210 is, for example, a wire. The other end of the connection wiring 210 extends from the inner element region 208 across the output region 6 to the control region 7 outside the output region 6. The connection wiring 210 connects the current monitoring element 209 and the control circuit 23 of the control region 7 (see Figure 4 ).

[0225] like Fig.23 and Fig.24 As shown, the connection wiring 210 is included in the second wiring layer 13. The current signal from the current monitoring element 209 is applied to the overcurrent protection circuit 26 of the control circuit 23 via the connection wiring 210 (see Figure 4 ).

[0226] Reference Fig.25, in the area between the control area 7 and the inner element area 208 in the output area 6, the first source wiring 98A and the second source wiring 98B are arranged above the first main surface 3. As described above, the first source wiring 98A is included in the first wiring layer 12, and the second source wiring 98B is included in the second wiring layer 13. In this area, the second wiring layer 13 includes a connecting wiring 210 and a second source wiring 98B, a first connecting wiring 10A and a second connecting wiring 10B. In this area, the connecting wiring 210 extends along the first direction X. The connecting wiring 210 is sandwiched by multiple second source wirings 98B in the second direction Y. The wiring width WC1 of the connecting wiring 210 is the same as the wiring width WA of each of the first connecting wiring 10A and the second connecting wiring 10B. The first source wiring 98A overlaps with the connecting wiring 210 in the normal direction Z.

[0227] The connection wiring 210 is not included in the first wiring layer 12 . The connection wiring 210 is insulated from the first connection wiring 10A and the second connection wiring 10B. The connection wiring 210 is also insulated from the second source wiring 98B. The connection wiring 210 is also insulated from the first source wiring 98A included in the first wiring layer 12 .

[0228] From the current monitoring element 209 (see Fig. 22 ) is applied to the overcurrent protection circuit 26 of the control circuit 23 via the connection wiring 210 (see Figure 4 ). The overcurrent protection circuit 26 controls the on / off operation of the output transistor 20 based on the current signal. When it is determined that the output region 6 is in an overcurrent state, the overcurrent protection circuit 26 controls a part or all of the output transistor 20 to be turned off. This prevents the semiconductor device 201 from being damaged.

[0229] Fig.26A 3 is a plan view showing the output region 6 and the inner element region 308 of the semiconductor device 301 according to the third embodiment of the present disclosure, and is Figure 6 The corresponding view. Fig.26B It is along Fig.26A 2 is a cross-sectional view taken along line XXVIB-XXVIB shown in FIG. In the third embodiment, only the parts different from the first embodiment will be mainly described. The same configurations as those described above will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0230] The third embodiment is different from the first embodiment in that the current monitoring element 309 as the first element is provided in the inner element region 308. In addition, the inner element region 308 is not formed in a substantially quadrilateral shape but is formed in a polygonal shape (a hexadecagonal shape in the present embodiment) having four sides parallel to the periphery of the first main surface 3 when viewed from above.

[0231] The current monitoring element 309 according to the third embodiment has the same configuration as the current monitoring element 209 according to the second embodiment. Therefore, the description of the current monitoring element 309 will be omitted. The current monitoring element 309 and the control circuit 23 of the control area 7 (see Figure 4 ) are connected via connecting wiring 210.

[0232] Reference Fig.26B The connection wiring 210 is sandwiched by the plurality of second source wirings 98B in the second direction Y. The connection wiring 210 has a wiring width WC2. The first source wiring 98A overlaps the connection wiring 210 in the normal direction Z.

[0233] Although various embodiments of the present disclosure are described above, the present disclosure may be implemented in other forms.

[0234] A modified example of the second embodiment is Fig. 27 Shown in. Fig. 27 is with Fig.25 The corresponding view. Fig. 27 The semiconductor device 401 shown is different from that of the second embodiment in that the wiring width WC2 of the connection wiring 210 is larger than the wiring width WA of each of the first connection wiring 10A and the second connection wiring 10B.

[0235] also, Fig.28 A modification of the first embodiment is shown in FIG. Fig.28 is with Figure 6 The corresponding view. Fig.28 The semiconductor device 501 shown in the figure is different from the first embodiment in that no protrusion 8a is formed in the inner element region 8 (see FIG. Figure 6 In this modification, all trench connection structures 90 facing the inner element region 8 in the first direction X are aligned in the first direction X. In this case, the convex portion 60a may not be formed in the first trench isolation structure 60 (see Figure 6 ).

[0236] also, Fig.28 The illustrated modification examples can be combined not only with the semiconductor device 1 of the first embodiment but also with the semiconductor device 201 of the second embodiment and the semiconductor device 301 of the third embodiment.

[0237] In addition, in the first and second embodiments, other types of temperature sensor elements may be used instead of the temperature sensor element 9. For example, a temperature sensor element having the following structure may be used, wherein the temperature sensor element 9 is connected to the third trench isolation structure 140 (see FIG. Fig. 22) has an annular isolation structure equivalent to that of the present invention, a p-type diffusion region isolated from the surroundings is formed inside the inner element region 8 or 208, and a trench gate structure is formed in the diffusion region.

[0238] In addition, although the temperature sensor element 9, the current monitoring element 209 and the current monitoring element 309 are used as examples of elements (first element and second element) arranged in the inner element area 8, 208 or 308, elements other than the temperature sensor element and the current monitoring element may also be arranged in the inner element area 8, 208 or 308.

[0239] In addition, although the case where the connecting wiring 10A, 10B or 210 connects the elements (first element and second element) arranged in the inner element area 8, 208 or 308 and the control area 7 has been described as an example, the connecting wiring 10A, 10B or 210 can be connected to an area outside the control area 7.

[0240] Furthermore, in each of the above embodiments, an example has been described in which a wiring structure including the first wiring layer 12 and the second wiring layer 13 is employed. However, the wiring structure is not limited to a two-layer structure and may be a three-layer structure or a multilayer structure in which four or more layers are stacked.

[0241] In addition, in each of the above embodiments, an example in which the first conductivity type is n-type and the second conductivity type is p-type has been described. However, the first conductivity type may be p-type, and the second conductivity type may be n-type. The specific configuration in this case can be obtained by replacing the n-type region with a p-type region and replacing the p-type region with an n-type region in the above description and the accompanying drawings.

[0242] The above-described embodiments of the present disclosure are exemplary in all aspects and should not be construed as restrictive and are intended to include changes in all aspects.

[0243] Features described below as supplementary notes can be extracted from the description of the present disclosure and the drawings. Hereinafter, alphanumeric characters in brackets represent corresponding components in the above-described embodiments, but are not intended to limit the scope of each item (clause) to the embodiments.

[0244] [Additional Note 1-1]

[0245] A semiconductor device (1, 201, 301, 401 or 501), comprising:

[0246] A semiconductor chip (2) having a main surface (3);

[0247] an output region (6) formed on the main surface (3), wherein output elements are arranged in the output region;

[0248] an inner element region (8, 208 or 308), surrounded by the output region and insulated from the output region (6), wherein a first element (9 or 309) different from the output element (20) is arranged in the inner element region;

[0249] a first wiring layer (12) formed on the main surface (3) so as to cover the output region (6) and including a first output wiring (98A) electrically connected to the output element (20); and

[0250] a second wiring layer (13) formed on the first wiring layer (12) and comprising a second output wiring (98B) electrically connected to the first output wiring (98A) and a connecting wiring (10 or 210) insulated and isolated from the second output wiring (98B), wherein the connecting wiring (10 or 210) extends from the inner element region (8, 208 or 308) across the output region (6) to reach an outer region (7) outside the output region (6),

[0251] The output element (20) is arranged below the connection wiring (10 or 210) and includes a trench electrode structure (70) overlapping with the connection wiring (10 or 210) in the thickness direction (Z) of the semiconductor chip (2).

[0252] According to the above configuration, the connection wiring (10 or 210) is included in the second wiring layer (13). Therefore, the first element (9 or 309) can be arranged in the area below the connection wiring (10 or 210) of the main surface (3). By arranging the first element (9 or 309) below the connection wiring (10 or 210), the mounting efficiency of the first element (8 or 309) on the main surface can be increased. This makes it possible to reduce the chip area.

[0253] [Additional Notes 1-2]

[0254] A semiconductor device (1, 201, 301, 401 or 501) according to Note 1-1, wherein the connecting wiring (10 or 210) is sandwiched between the second output wirings (98B) in a second direction (Y) intersecting the first direction (X) extending the trench electrode structure (70).

[0255] [Notes 1-3]

[0256] A semiconductor device (1, 201, 301, 401 or 501) according to Note 1-1 or 1-2, wherein the first output wiring (98A) included in the first wiring layer (12) overlaps with the connecting wiring (10 or 210) in the thickness direction (Z) of the semiconductor chip (2).

[0257] [Notes 1-4]

[0258] The semiconductor device (1, 201, 301, 401 or 501) according to any one of Supplementary Notes 1-1 to 1-3, wherein the output element (20) includes an output transistor (20) formed on the main surface (3),

[0259] The semiconductor device further comprises an interlayer insulating layer (11) configured to cover the main surface (3).

[0260] wherein the first wiring layer (12) and the second wiring layer (13) are formed in the interlayer insulating layer (11), and

[0261] Each of the first output wiring (98A) and the second output wiring (98B) includes a source wiring (98A or 98B) connected to the output transistor (20).

[0262] [Notes 1-5]

[0263] A semiconductor device (1, 201, 301, 401 or 501) according to any one of Notes 1-1 to 1-4, wherein the trench electrode structure (70) is arranged in an area of ​​the output region (6) sandwiched between the outer region (7) and the inner component region (8, 208 or 308) in a first direction (X) in which the trench electrode structure (70) extends, so that the trench electrode structure is arranged in an entire area of ​​the output region (6) sandwiched between the outer region (7) and the inner component region (8, 208 or 308) in the first direction (X) and in a second direction intersecting the first direction.

[0264] [Appendix 1-6]

[0265] The semiconductor device (1, 201, 301, 401 or 501) according to Supplementary Notes 1 to 5, wherein the output region (6) is formed in a ring shape surrounding the inner element region (8, 208 or 308), and

[0266] Wherein, the output element (20) is arranged in a ring shape surrounding the inner element area (8, 208 or 308).

[0267] [Appendix 1-7]

[0268] The semiconductor device (1, 201, 301, 401 or 501) according to any one of Supplementary Notes 1-1 to 1-6, further comprising:

[0269] The annular isolation structure (100) is configured to surround the inner element region (8, 208 or 308) and insulate and isolate the inner element region (8, 208 or 308) from the output region (6).

[0270] [Appendix 1-8]

[0271] A semiconductor device (1, 201, 301, 401 or 501) according to Notes 1 to 7, wherein the isolation structure (100) includes an isolation electrode (103) buried in an isolation trench (101), and an isolation insulator (102) is inserted between the isolation electrode (101) and the isolation trench (103).

[0272] [Appendix 1-9]

[0273] The semiconductor device (201, 301 or 401) according to any one of Supplementary Notes 1-1 to 1-8, wherein the connection wiring (10 or 210) includes a plurality of connection wirings (10 or 210), and

[0274] The width (WC2) of at least one of the plurality of connecting wirings (10 or 210) is different from the width (WA) of the other connecting wirings (10).

[0275] [Notes 1-10]

[0276] The semiconductor device (1, 201, 401 or 501) according to any one of Supplementary Notes 1-1 to 1-9, wherein the first element (9) includes a temperature sensor element (9) configured to detect a temperature of the output region (6).

[0277] [Appendix 1-11]

[0278] The semiconductor device (1, 201, 401 or 501) according to Supplementary Notes 1 to 10, wherein the temperature sensor element (9) includes a temperature sensing diode (110) and a diode wiring (116), the diode wiring being configured to connect the temperature sensing diode (110) and the connection wiring (10), and

[0279] The diode wiring (116) is included in the first wiring layer (12).

[0280] [Appendix 1-12]

[0281] A semiconductor device (201401 or 501) according to any one of Notes 1-1 to 1-11, wherein a second element (209) different from the first element (9) is further arranged in the inner element region (208).

[0282] [Appendix 1-13]

[0283] A semiconductor device (201, 401 or 501) according to Supplementary Notes 1 to 12, wherein the second element (209) includes a current monitoring element (209) configured to detect an output current (Io) generated by the output element (20).

[0284] [Appendix 1-14]

[0285] A semiconductor device (301, 401 or 501) according to any one of Notes 1-1 to 1-9, wherein the first element (309) includes a current monitoring element (309) configured to detect an output current (Io) generated by the output element (20).

[0286] [Note 1-15]

[0287] The semiconductor device (1, 201, 301, 401 or 501) according to any one of Supplementary Notes 1-1 to 1-14, wherein the outer region (7) includes a control region (7) configured to generate a control signal.

[0288] Although certain embodiments have been described, these embodiments are presented only as examples and are not intended to limit the scope of the present disclosure. In fact, the embodiments described herein may be embodied in various other forms. In addition, various omissions, substitutions, and changes may be made to the forms of the embodiments described herein without departing from the spirit of the present disclosure. The attached claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present disclosure.

[0289] Explanation of Reference Symbols

[0290] 1: Semiconductor devices

[0291] 2: Semiconductor chips

[0292] 3: First main surface (main surface)

[0293] 4: Second main surface

[0294] 5A: First side

[0295] 5B: Second side

[0296] 5C: Third side

[0297] 5D: The fourth side

[0298] 6: Output area

[0299] 7: Control area (outer area)

[0300] 8: Inner component area

[0301] 8a: convex part

[0302] 9: Temperature sensor element (first element)

[0303] 10: Connect the wiring

[0304] 10A: First connection wiring

[0305] 10B: Second connection wiring

[0306] 11: Interlayer insulation layer

[0307] 12: First wiring layer

[0308] 13: Second wiring layer

[0309] 16: Gate wiring

[0310] 16A: First system gate wiring

[0311] 16B: Second system gate wiring

[0312] 17: Source terminal

[0313] 18: Control terminal

[0314] 19: Drain terminal

[0315] 20: Output transistor

[0316] 21: System transistor

[0317] 21A: First system transistor

[0318] 21B: Second system transistor

[0319] 22: Unit transistor

[0320] 23: Control circuit

[0321] 24: Gate control circuit

[0322] 25: Current monitoring circuit

[0323] 26: Overcurrent protection circuit

[0324] 27: Overheat protection circuit

[0325] 28: Low voltage fault avoidance circuit

[0326] 29: Open load detection circuit

[0327] 30: Active clamping circuit

[0328] 32: Logic Circuits

[0329] 51: First semiconductor region

[0330] 52: Second semiconductor region

[0331] 60: First trench isolation structure

[0332] 60a: convex part

[0333] 61: First isolation trench

[0334] 62: First isolation insulating film

[0335] 63: First isolation electrode

[0336] 67: First body area

[0337] 70: Trench gate structure (trench electrode structure)

[0338] 71: Gate trench

[0339] 72: Insulation film

[0340] 73: Upper electrode

[0341] 74: Lower electrode

[0342] 75: Intermediate insulating film

[0343] 76: Upper insulation film

[0344] 77: Lower insulation film

[0345] 78: Channel unit

[0346] 79: Source region

[0347] 80: Contact area

[0348] 81: Block

[0349] 81A: First Block

[0350] 81B: Second block

[0351] 90: Groove connection structure

[0352] 91: Connecting groove

[0353] 92: Connecting insulation film

[0354] 93: Connecting electrodes

[0355] 94: Main surface insulation film

[0356] 95: Field insulation film

[0357] 97: Through-hole electrode

[0358] 98: Source wiring

[0359] 98A: First source wiring (first output wiring)

[0360] 98B: Second source wiring (second output wiring)

[0361] 100: Second trench isolation structure (isolation structure)

[0362] 100a: convex part

[0363] 101: Second isolation trench (isolation trench)

[0364] 102: Second isolation insulating film (isolation insulator)

[0365] 103: Second isolation electrode (isolation electrode)

[0366] 110: Temperature sensing diode

[0367] 111: Temperature sensing diode element

[0368] 113: Polysilicon layer

[0369] 113a: First surface

[0370] 113b: Second surface

[0371] 114: Anode area

[0372] 115: Cathode area

[0373] 116: Diode wiring

[0374] 116b: The other end

[0375] 117: Through-hole electrode

[0376] 120: Gate connection wiring

[0377] 121: First gate connection wiring

[0378] 121A: Through-hole electrode

[0379] 122: Second gate connection wiring

[0380] 122A: Through-hole electrode

[0381] 123: Third gate connection wiring

[0382] 140: Third trench isolation structure

[0383] 141: The third isolation trench

[0384] 142: Third isolation insulating film

[0385] 143: Third isolation electrode

[0386] 155: Field insulation film

[0387] 161: First gate wiring

[0388] 162: Second gate wiring

[0389] 167: Second body area

[0390] 170: Trench gate structure

[0391] 171: Gate trench

[0392] 172: Insulation film

[0393] 173: Upper electrode

[0394] 174: Lower electrode

[0395] 175: Intermediate insulating film

[0396] 176: Upper insulation film

[0397] 177: Lower insulation film

[0398] 179: Source region

[0399] 180: Contact area

[0400] 190: Groove connection structure

[0401] 191: Semiconductor devices

[0402] 192: Area

[0403] 201: Semiconductor devices

[0404] 208: Inner component area

[0405] 209: Current monitoring element (second element)

[0406] 209A: Current detection area

[0407] 210: Connect the wiring

[0408] 301: Semiconductor devices

[0409] 308: Inner component area

[0410] 309: Current monitoring element (first element)

[0411] 401: Semiconductor devices

[0412] 501: Semiconductor devices

[0413] D1: First isolation depth

[0414] D2: Groove depth

[0415] D3: Second isolation depth

[0416] D4: Third isolation depth

[0417] D5: Groove depth

[0418] I1: First Interval

[0419] Io: output current

[0420] Is: system current

[0421] Iu: unit current

[0422] L: Inductive load

[0423] W1: First isolation width

[0424] W2: Groove width

[0425] W3: Second isolation width

[0426] W4: Third isolation width

[0427] W5: Groove width

[0428] WA: Wiring width

[0429] WC1: Wiring width

[0430] WC2: Wiring width

[0431] X: First direction

[0432] Y: Second direction

[0433] Z: Normal direction (thickness direction)

Claims

1. A semiconductor device, comprising: A semiconductor chip having a main surface; an output region formed on the main surface, wherein output elements are arranged in the output region; an inner element region, surrounded by the output region and insulated from the output region, wherein a first element different from the output element is arranged in the inner element region; A first wiring layer formed on the main surface in a manner covering the output region and including a first output wiring electrically connected to the output element; and a second wiring layer formed on the first wiring layer and comprising a second output wiring electrically connected to the first output wiring and a connecting wiring insulated and isolated from the second output wiring, the connecting wiring extending from the inner element region, across the output region, to an outer region outside the output region, The output element is arranged below the connection wiring and includes a trench electrode structure overlapping with the connection wiring in a thickness direction of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein The connection wiring is sandwiched between the second output wirings in a second direction intersecting the first direction in which the trench electrode structure extends.

3. The semiconductor device according to claim 1 or 2, wherein: The first output wiring included in the first wiring layer overlaps the connection wiring in the thickness direction of the semiconductor chip.

4. The semiconductor device according to claim 1 or 2, wherein: The output element includes an output transistor formed on the main surface, The semiconductor device further comprises an interlayer insulating layer configured to cover the main surface. wherein the first wiring layer and the second wiring layer are formed in the interlayer insulating layer, and Here, each of the first output wiring and the second output wiring includes a source wiring connected to the output transistor.

5. The semiconductor device according to claim 1 or 2, wherein: The trench electrode structure is arranged in an area of ​​the output region sandwiched between the outer area and the inner element region in a first direction in which the trench electrode structure extends, so that the trench electrode structure is arranged in the entire area of ​​the area of ​​the output region sandwiched between the outer area and the inner element region in the first direction and in a second direction intersecting the first direction.

6. The semiconductor device according to claim 5, wherein: The output region is formed in a ring shape surrounding the inner element region, and The output element is arranged in a ring shape surrounding the inner element area. 7 . The semiconductor device according to claim 1 , further comprising an annular isolation structure, wherein the annular isolation structure is configured to surround the inner element region and insulate and isolate the inner element region from the output region.

8. The semiconductor device according to claim 7, wherein: The isolation structure includes an isolation electrode buried in an isolation trench, and an isolation insulator is inserted between the isolation electrode and the isolation trench.

9. The semiconductor device according to claim 1 or 2, wherein: The connecting wiring includes a plurality of connecting wirings, and The width of at least one of the plurality of connection wirings is different from the widths of the other connection wirings.

10. The semiconductor device according to claim 1 or 2, wherein: The first element includes a temperature sensor element configured to detect a temperature of the output region.

11. The semiconductor device according to claim 10, wherein: The temperature sensor element includes a temperature sensing diode and a diode wiring configured to connect the temperature sensing diode and the connection wiring, and The diode wiring is included in the first wiring layer.

12. The semiconductor device according to claim 1 or 2, wherein: A second element different from the first element is also arranged in the inner element region.

13. The semiconductor device according to claim 12, wherein: The second element includes a current monitoring element configured to detect an output current generated by the output element.

14. The semiconductor device according to claim 1 or 2, wherein: The first element includes a current monitoring element configured to detect an output current generated by the output element.

15. The semiconductor device according to claim 1 or 2, wherein: The outer region includes a control region configured to generate a control signal.

Images