Display panel

Abstract

The invention discloses a display panel which comprises an array substrate and a light-emitting element. The array substrate comprises a base material, a plurality of connecting pad groups and a retaining wall structure. The base material is provided with a surface, the surface is provided with a corner, and the corner is provided with two connected edges. The connecting pad groups are arranged on the surface and comprise a first group of connecting pad groups located at the corners. The retaining wall structure is arranged on the surface and located at the corner, and is located between the first group of connecting pads and two edges of the corner. The retaining wall structure and at least one film layer of the connecting pad groups are formed by patterning the same film layer. The light-emitting elements are respectively arranged on the connecting pad groups.

Description

Technical Field

[0001] The invention relates to a display panel, and in particular to a display panel comprising a retaining wall structure arranged at a corner of an array substrate. Background Art

[0002] Micro-LED display panels have the advantages of power saving, high efficiency, high brightness and fast response time. However, in the current application of borderless panels, the uneven leveling of the photoresist at the corners of the panel can easily cause poor etching of the pads at the corners, resulting in a decrease in yield. Summary of the invention

[0003] The present invention provides a display panel, which can improve the uniformity of photoresist at the corner of the panel, reduce the probability of poor etching effect of the pad located at the corner, and thus improve the yield.

[0004] The display panel proposed in at least one embodiment of the present invention comprises an array substrate and a plurality of light-emitting elements. The array substrate comprises a substrate, a plurality of pad groups and a first retaining wall structure. The substrate has a surface, the surface has a first corner, and the first corner has a first edge and a second edge connected to each other. A plurality of pad groups are arranged on the surface, and these pad groups include a first group of pad groups located at the first corner. The first retaining wall structure is arranged on the surface and is located at the first corner, and is located between the first group of pad groups and the first edge and the second edge. The first retaining wall structure and at least one film layer of these pad groups are formed by patterning the same film layer. These light-emitting elements are respectively arranged on these pad groups.

[0005] In at least one embodiment of the present invention, the first retaining wall structure includes a first sub-wall and a second sub-wall, the first sub-wall is located between the first edge and the first group of pads, and the second sub-wall is located between the second edge and the first group of pads.

[0006] In at least one embodiment of the present invention, the first sub-wall is connected to the second sub-wall.

[0007] In at least one embodiment of the present invention, each pad group includes a first pad and a second pad, the first pad receives a first voltage, the second pad receives a second voltage, the first voltage is different from the second voltage, and the first retaining wall structure electrically connects the first pads.

[0008] In at least one embodiment of the present invention, the array substrate further includes a signal transmission layer and a pad layer. The signal transmission layer is disposed between the substrate and the pad group and is electrically connected to the second pad. The pad layer is disposed between the substrate and the first retaining wall structure and overlaps with the first retaining wall structure on the normal line of the substrate, and at least one film layer of the pad layer and the signal transmission layer is formed by patterning the same film layer.

[0009] In at least one embodiment of the present invention, the pad layer is electrically connected to the signal transmission layer.

[0010] In at least one embodiment of the present invention, the pad layer includes a plurality of electrically floating sections.

[0011] In at least one embodiment of the present invention, the pad layer is electrically connected to the first pad.

[0012] In at least one embodiment of the present invention, a distance between the first retaining wall structure and the first group of pads is no greater than 50 μm.

[0013] In at least one embodiment of the present invention, the surface further has a second corner, and the second corner has the second edge and the third edge connected to each other. The pad group further includes a second group of pads located at the second corner and a third group of pads located between the first group of pads and the second group of pads. The array substrate further includes a second retaining wall structure, which is disposed on the surface and located at the second corner, and is located between the second group of pads and the second edge and the third edge. The second retaining wall structure and at least one film layer of the pad group are formed by patterning the same film layer, and the first retaining wall structure and the second retaining wall structure do not extend between the third group of pads and the second edge.

[0014] The display device proposed in at least another embodiment of the present invention comprises an array substrate and a plurality of light-emitting elements. The array substrate comprises a substrate, a plurality of pad groups and a first retaining wall structure. The substrate has a surface, the surface has a first corner, and the first corner has a first edge and a second edge connected to each other. A plurality of pad groups are arranged on the surface, and these pad groups include a first group of pad groups located in the first corner, and each pad group includes a first pad and a second pad, the first pad receives a first voltage, and the second pad receives a second voltage, and the first voltage is different from the second voltage. The first retaining wall structure is arranged on the surface and is located in the first corner, and is located between the first group of pad groups and the first edge and the second edge. The first retaining wall structure is electrically connected to these first pads. These light-emitting elements are respectively arranged on these pad groups.

[0015] In at least another embodiment of the present invention, the array substrate further comprises a signal transmission layer and a pad layer. The signal transmission layer is disposed between the substrate and the pad group and is electrically connected to the second pad. The pad layer is disposed between the substrate and the first retaining wall structure and overlaps with the first retaining wall structure on the normal line of the substrate, and the pad layer is electrically connected to the first pad.

[0016] In at least another embodiment of the present invention, the first voltage is a reference potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1Ais a schematic top view of a display panel according to at least one embodiment of the present invention. Figure 1B yes Figure 1A Schematic diagram of the enlarged area A in the middle.

[0018] Figure 1C yes Figure 1B Schematic diagram of the cross section drawn along the section line a-a'.

[0019] Figure 2A is a schematic top view of a display panel according to at least another embodiment of the present invention. Figure 2B yes Figure 2A Schematic diagram of the enlarged area B in the middle.

[0020] Figure 2C yes Figure 2B Schematic diagram of the cross section drawn along the section line b-b'.

[0021] Figure 3A is a schematic top view of a display panel according to at least another embodiment of the present invention. Figure 3B yes Figure 3A Schematic diagram of the enlarged area C in the middle.

[0022] Figure 3C yes Figure 3B Schematic diagram of the cross section drawn along the section line c-c'.

[0023] Figure 4A is a schematic top view of a display panel according to at least another embodiment of the present invention. Figure 4B yes Figure 4A Schematic diagram of the enlarged area D in the middle.

[0024] Figure 4C yes Figure 4B Schematic diagram of the cross section drawn along the section line d-d'.

[0025] Wherein, the reference numerals are:

[0026] 1, 2, 3, 4: Display panel

[0027] 10: Array substrate

[0028] 100: Base material

[0029] 102: Switching element

[0030] 102a: Active layer

[0031] 102d: Drain

[0032] 102g: Gate

[0033] 102i: Gate insulation layer

[0034] 102m: Interlayer insulation layer

[0035] 102s: Source

[0036] 103: first insulating layer

[0037] 103a, 105a, 107a: organic sublayer

[0038] 103b, 105b, 107b: Inorganic sublayer

[0039] 104: routing layer

[0040] 105: Second insulation layer

[0041] 106:Signal transmission layer

[0042] 107: The third insulating layer

[0043] 108: pad protection layer

[0044] 110: pad group

[0045] 110a: first pad

[0046] 110b: second pad

[0047] 111: The first group of pads

[0048] 112: The second pad group

[0049] 113: The third group of pads

[0050] 121: First retaining wall structure

[0051] 121a: First sub-wall

[0052] 121b: Second sub-wall

[0053] 122: Second retaining wall structure

[0054] 123: The third retaining wall structure

[0055] 124: The fourth retaining wall structure

[0056] 20: Light-emitting element

[0057] 206, 306, 406: cushion layer

[0058] 206a, 406a: first sub-pad

[0059] 206b, 406b: second sub-pad

[0060] 306p: Segment

[0061] A, B, C, D: Area

[0062] a-a', b-b', c-c', d-d': section line

[0063] C1: First corner

[0064] C2: Second corner

[0065] C3: The third corner

[0066] C4: The fourth corner

[0067] E1: First Edge

[0068] E2: Second Edge

[0069] E3: The Third Edge

[0070] E4: The Fourth Edge

[0071] P: Spacing

[0072] S: Surface DETAILED DESCRIPTION

[0073] In the following text, in order to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions, etc.) in the drawings will be enlarged in unequal proportions, and the number of some elements will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings and the dimensions and shapes presented by the elements, but should cover the dimensions, shapes, and deviations thereof caused by the actual process and / or tolerances. For example, the flat surface shown in the drawings may have rough and / or nonlinear features, and the acute angles shown in the drawings may be rounded. Therefore, the elements presented in the drawings of the present invention are mainly for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they intended to limit the scope of the patent application of the present invention.

[0074] Secondly, the words "about", "approximately" or "substantially" used in the present invention not only cover the numerical values ​​and numerical ranges clearly recorded, but also cover the permissible deviation range that can be understood by a person with ordinary knowledge in the technical field to which the invention belongs, wherein the deviation range can be determined by the error generated during measurement, and the error is caused by the limitation of the measurement system or process conditions, for example. For example, two objects (such as the planes or traces of the substrate) are "substantially parallel" or "substantially perpendicular", wherein "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects may include the non-parallelism and non-perpendicularity caused by the permissible deviation range.

[0075] In addition, "approximately" may mean within one or more standard deviations of the above values, such as ±30%, ±20%, ±10% or ±5%. The words "approximately", "approximately" or "substantially" used in the present invention may be selected based on the optical properties, etching properties, mechanical properties or other properties to select an acceptable deviation range or standard deviation, rather than applying a single standard deviation to all properties such as the above optical properties, etching properties, mechanical properties and other properties.

[0076] The spatially relative terms used in the present invention, such as "below", "under", "above", "on", etc., are for the purpose of facilitating the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped up and down 180 degrees, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in the present invention should also be interpreted in the same way.

[0077] It should be understood that, although the present invention may use the terms "first", "second", "third" and the like to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another element, or one signal from another signal. In addition, the term "or" used in the present invention may include any one or more combinations of the associated listed items depending on the actual situation.

[0078] In addition, the present invention may be implemented or applied through other different specific embodiments, and the details of the present invention may also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

[0079] Figure 1A is a schematic top view of a display panel according to at least one embodiment of the present invention. Figure 1A , the display panel 1 includes an array substrate 10 and a plurality of light-emitting elements 20. The array substrate 10 includes a substrate 100, a plurality of pad groups 110 and a first retaining wall structure 121. The substrate 100 has a surface S, the surface S has a first corner C1, and the first corner C1 has a first edge E1 and a second edge E2 connected to each other. A plurality of pad groups 110 are arranged on the surface S, and these pad groups 110 include a first group of pad groups 111 located at the first corner C1. The first retaining wall structure 121 is arranged on the surface S and is located at the first corner C1, and is located between the first group of pad groups 111 and the first edge E1 and the second edge E2. The first retaining wall structure 121 and at least one film layer of these pad groups 110 are formed by patterning the same film layer. These light-emitting elements 20 are respectively arranged on these pad groups 110.

[0080] By setting a retaining wall structure (such as the first retaining wall structure 121) at the corner of the panel, and the retaining wall structure is located between the pad group at the corner of the panel and the two edges of the corner (such as the first edge E1 and the second edge E2 of the first corner C1), the uniformity of the photoresist at the corner of the panel can be improved to avoid the thickness of the photoresist at the corner of the panel being too thin, thereby reducing the probability of poor etching effect of the pad located at the corner, thereby improving the yield.

[0081] Please continue reading Figure 1A , the surface S further has a second corner C2, and the second corner C2 has a second edge E2 and a third edge E3 connected thereto. The pad group 110 further includes a second group pad group 112 located at the second corner C2 and a third group pad group 113 located between the first group pad group 111 and the second group pad group 112. The array substrate 10 further includes a second retaining wall structure 122, the second retaining wall structure 122 is disposed on the surface S and located at the second corner C2, and is located between the second group pad group 112 and the second edge E2 and the third edge E3. The second retaining wall structure 122 and at least one film layer of the pad group 110 are formed by patterning the same film layer, and the first retaining wall structure 121 and the second retaining wall structure 122 do not extend between the third group pad group 113 and the second edge E2. In some embodiments, no retaining wall structure is provided between the third group pad group 113 and the second edge E2.

[0082] Since the retaining wall structure does not extend between some pad groups and the edge of the panel, that is, the retaining wall structure is discontinuous, it can avoid the photoresist at the edge of the panel being too thick due to the retaining wall structure being completely closed, resulting in incomplete exposure and development and etching problems.

[0083] For example, see Figure 1A , the first retaining wall structure 121 extends from the first corner C1 along the direction parallel to the second edge E2 to a length of about two pixels wide, that is, a length of six sub-pixels wide, and the second retaining wall structure 122 extends from the second corner C2 along the direction parallel to the second edge E2 to a length of about two pixels wide, that is, a length of six sub-pixels wide. In some embodiments, the lengths of the first retaining wall structure 121 and the second retaining wall structure 122 in the direction parallel to the second edge E2 may be respectively between two and four pixels wide, that is, six to twelve sub-pixels wide.

[0084] In addition, the first retaining wall structure 121 extends from the first corner C1 along a direction parallel to the first edge E1 to a length of about two pixels, that is, a length of two sub-pixels, and the second retaining wall structure 122 extends from the second corner C2 along a direction parallel to the third edge E3 to a length of about two pixels, that is, a length of two sub-pixels. In some embodiments, the length of the first retaining wall structure 121 in the direction parallel to the first edge E1 and the length of the second retaining wall structure 122 in the direction parallel to the third edge E3 may be respectively between two and four pixels, that is, two to four sub-pixels.

[0085] Similarly, if Figure 1A As shown, the surface S further has a third corner C3 and a fourth corner C4, the third corner C3 has a third edge E3 and a fourth edge E4 connected thereto, and the fourth corner C4 has a fourth edge E4 and a first edge E1 connected thereto. The array substrate 10 further includes a third retaining wall structure 123 and a fourth retaining wall structure 124, the third retaining wall structure 123 and the fourth retaining wall structure 124 are disposed on the surface S and are located at the third corner C3 and the fourth corner C4, respectively. The third retaining wall structure 123 and the fourth retaining wall structure 124 and at least one film layer of the pad group 110 are formed by patterning the same film layer. The second retaining wall structure 122 and the third retaining wall structure 123 do not extend between a portion of the pad group 110 and the third edge E3, the third retaining wall structure 123 and the fourth retaining wall structure 124 do not extend between a portion of the pad group 110 and the fourth edge E4, and the first retaining wall structure 121 and the fourth retaining wall structure 124 do not extend between a portion of the pad group 110 and the first edge E1.

[0086] In addition, in some embodiments, the lengths of the third retaining wall structure 123 and the fourth retaining wall structure 124 in the direction parallel to the fourth edge E4 may be respectively between two and four pixel widths, i.e., six to twelve sub-pixel widths. In some embodiments, the lengths of the third retaining wall structure 123 in the direction parallel to the second edge E2 and the lengths of the fourth retaining wall structure 124 in the direction parallel to the first edge E1 may be respectively between two and four pixel lengths, i.e., two to four sub-pixel lengths.

[0087] Figure 1B yes Figure 1A Magnified schematic diagram of area A in the figure. Figure 1B , the first retaining wall structure 121 includes a first sub-wall 121a and a second sub-wall 121b, the first sub-wall 121a is located between the first edge E1 and the first group of pads 111, and the second sub-wall 121b is located between the second edge E2 and the first group of pads 111. In some embodiments, the first sub-wall 121a and the second sub-wall 121b are arranged in an L shape. In some embodiments, the first sub-wall 121a is connected to the second sub-wall 121b, that is, Figure 1BAs shown, the first sub-wall 121a is connected to the second sub-wall 121b at a position adjacent to the first corner C1. In other embodiments, the first sub-wall 121a may not be connected to the second sub-wall 121b, that is, there may be a disconnection between the first sub-wall 121a and the second sub-wall 121b. In some embodiments, the disconnection may be located adjacent to the first corner C1.

[0088] like Figure 1B As shown, the pad group 110 includes a first pad 110a and a second pad 110b, the first pad 110a receives a first voltage, the second pad 110b receives a second voltage, the first voltage is different from the second voltage, and the first retaining wall structure 121 is electrically connected to the first pad 110a. In some embodiments, the first voltage is a reference voltage (Vss), such as a ground voltage, and the second voltage is a working voltage (Vdd), such as a signal voltage obtained by electrically connecting the signal transmission layer 106.

[0089] Please continue reading Figure 1B There is a spacing P between the first retaining wall structure 121 and the first group of pads 111, and the spacing P is not greater than 50 μm. By designing the above spacing range, the uniformity of the photoresist at the panel corners can be effectively improved to prevent the thickness of the photoresist at the panel corners from being too thin, reduce the probability of poor etching effect of the pads at the corners, and thus improve the yield.

[0090] Figure 1C yes Figure 1B A schematic cross-sectional view of the section along the section line a-a' in FIG. Figure 1C , the array substrate 10 further includes a switch element 102, a first insulating layer 103, a routing layer 104, a second insulating layer 105, a signal transmission layer 106, a third insulating layer 107 and a pad protection layer 108. The switch element 102 is disposed on the substrate 100, and includes an active layer 102a, a gate insulating layer 102i, a gate 102g, an interlayer insulating layer 102m, a source 102s and a drain 102d. The active layer 102a is disposed on the substrate 100, the gate insulating layer 102i is disposed on the active layer 102a, and the gate 102g is disposed on the gate insulating layer 102i.

[0091] The interlayer insulating layer 102m is disposed on the gate 102g, and the source 102s and the drain 102d pass through the interlayer insulating layer 102m to connect the active layer 102a. In the present embodiment, the gate 102g is disposed above the active layer 102a to form a top-gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the gate 102g may also be disposed below the active layer 102a to form a bottom-gate thin film transistor. In some embodiments, a buffer layer (not shown) may be disposed between the substrate 100 and the active layer 102a.

[0092] The first insulating layer 103 is arranged on the source 102s and the drain 102d, the wiring layer 104 is arranged on the first insulating layer 103 and connected to the switching element 102 through the first insulating layer 103, the second insulating layer 105 is arranged on the wiring layer 104, the signal transmission layer 106 is arranged on the second insulating layer 105 and connected to the wiring layer 104 through the second insulating layer 105, the third insulating layer 107 is arranged on the signal transmission layer 106, the first pad 110a and the second pad 110b are arranged on the third insulating layer 107, and the second pad 110b is connected to the signal transmission layer 106 through the third insulating layer 107 to receive the second voltage, the pad protection layer 108 is arranged on the first pad 110a and the second pad 110b, and the light-emitting element 20 is arranged on the pad protection layer 108.

[0093] like Figure 1C As shown, the first retaining wall structure 121 and the first pad 110a and the second pad 110b of the pad group 110 are formed by patterning the same film layer. In other words, the first retaining wall structure 121 and the pad group 110 are located at a horizontal plane with approximately the same height, so the first retaining wall structure 121 can block the photoresist at the panel corner, thereby effectively improving the uniformity of the photoresist at the panel corner to prevent the thickness of the photoresist at the panel corner from being too thin, reducing the probability of poor etching effect of the pad group 110 located at the corner, thereby improving the yield.

[0094] Please continue reading Figure 1C , the first insulating layer 103, the second insulating layer 105 and the third insulating layer 107 respectively include organic sublayers 103a, 105a, 107a and inorganic sublayers 103b, 105b, 107b, and the inorganic sublayers 103b, 105b, 107b are respectively disposed on the organic sublayers 103a, 105a, 107a. In some embodiments, the inorganic sublayers 103b, 105b, 107b are respectively disposed on the organic sublayers 103a, 105a, 107a and cover the sidewalls of the organic sublayers 103a, 105a, 107a. The above-mentioned structural design can prevent or prevent moisture from penetrating into the display panel 1, thereby preventing the light-emitting element 20 and the array substrate 10 from being affected by moisture and failing.

[0095] The substrate 100 may be a transparent substrate or a non-transparent substrate, and the material of the substrate 100 may be quartz, glass, polymer material or other appropriate materials. In some embodiments, the switch element 102, the first insulating layer 103, the wiring layer 104, the second insulating layer 105, the signal transmission layer 106, the third insulating layer 107, the pad group 110, the first retaining wall structure 121 and the pad protection layer 108 may be formed on the substrate 100 by using a deposition process, an inkjet process, a printing process, a coating process and a photolithography process.

[0096] In some embodiments, the material of the active layer 102a of the switch element 102 may include a silicon semiconductor material (such as polycrystalline silicon, amorphous silicon, etc.), an oxide semiconductor material or an organic semiconductor material. The materials of the wiring layer 104, the signal transmission layer 106, and the gate 102g, the source 102s, and the drain 102d of the switch element 102 may include a metal with good conductivity, such as aluminum, molybdenum, titanium, copper, etc. The materials of the gate insulating layer 102i, the interlayer insulating layer 102m, the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107 may include a transparent insulating material, such as a transparent inorganic insulating material or an organic insulating material, the inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc., the organic insulating material such as poly(Methyl Methacrylate, PMMA, i.e., acrylic), siloxane, polyimide, epoxy, etc.

[0097] In some embodiments, the materials of the organic sublayer 103a of the first insulating layer 103, the organic sublayer 105a of the second insulating layer 105, and the organic sublayer 107a of the third insulating layer 107 may include transparent organic insulating materials, such as polymethyl methacrylate, siloxane, polyimide, epoxy resin, etc. The above-mentioned organic insulating materials are disposed between the metal layers of the switch element 102, the wiring layer 104, the signal transmission layer 106, and the pad group 110 to provide an insulating layer of a certain thickness, which can not only increase the flatness, but also reduce the capacitance between the metal layers, thereby reducing the circuit load of the array substrate 10.

[0098] The materials of the inorganic sublayer 103b of the first insulating layer 103, the inorganic sublayer 105b of the second insulating layer 105, and the inorganic sublayer 107b of the third insulating layer 107 may include transparent inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. By disposing the above-mentioned inorganic insulating materials on the organic sublayers 103a, 105a, 107a and covering the sidewalls of the organic sublayers 103a, 105a, 107a, it is possible to prevent or prevent the moisture absorbed by the organic sublayers 103a, 105a, 107a from penetrating into the display panel 1, thereby preventing the light-emitting element 20 and the array substrate 10 from being affected by the moisture and failing.

[0099] In some embodiments, the material of the pad protection layer 108 may include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum tin oxide (ATO), aluminum zinc oxide (AZO), indium germanium zinc oxide (IGZO) or other suitable materials. By disposing the pad protection layer 108 on the first pad 110a and the second pad 110b, the first pad 110a and the second pad 110b can be prevented from being exposed to the outside, causing metal diffusion or severe oxidation to cause abnormal resistance and affect display quality.

[0100] The light emitting element 20 may be a light emitting diode (LED), for example, a sub-millimeter light emitting diode (mini LED) or a micro LED (micro LED, μLED). The thickness of a micro LED is less than 10 microns, for example, 6 microns. Sub-millimeter LEDs can be divided into two types: one containing encapsulation glue and the other not containing encapsulation glue. The thickness of a sub-millimeter LED containing encapsulation glue may be less than 800 microns, while the thickness of a sub-millimeter LED without encapsulation glue may be less than 100 microns. In addition, the light emitting element 20 may also be a large-sized regular LED other than sub-millimeter LEDs and micro LEDs, so the light emitting element 20 is not limited to a smaller sub-millimeter LED or micro LED.

[0101] Figure 2A is a schematic top view of a display panel according to at least another embodiment of the present invention. Figure 2A , Figure 2A Examples and Figure 1A Most of the component structures, materials, processes and relative position relationships of the embodiments are the same, so the same technical features will not be repeated here. The differences between the two embodiments are Figure 2A The array substrate 10 of the display panel 2 further includes a pad layer 206 .

[0102] Figure 2B yes Figure 2A Schematic diagram of the enlarged area B in the middle. Figure 2C yes Figure 2B Schematic diagram of the cross section drawn along the section line b-b' in. Figure 2B and Figure 2CThe pad layer 206 is disposed between the substrate 100 and the first retaining wall structure 121 and overlaps with the first retaining wall structure 121 on the normal line of the substrate 100 . The pad layer 206 and at least one film layer of the signal transmission layer 106 are formed by patterning the same film layer.

[0103] like Figure 2B As shown, the pad layer 206 is electrically connected to the signal transmission layer 106. In addition, the pad layer 206 includes a first sub-pad 206a and a second sub-pad 206b. The first sub-pad 206a is located between the first edge E1 and the first group pad set 111, and the second sub-pad 206b is located between the second edge E2 and the first group pad set 111. In some embodiments, the first sub-pad 206a and the second sub-pad 206b are arranged in an L shape. In some embodiments, the first sub-pad 206a is connected to the second sub-pad 206b, that is, Figure 2B As shown, the first subpad 206a is connected to the second subpad 206b at a position adjacent to the first corner C1. In other embodiments, the first subpad 206a may not be connected to the second subpad 206b, that is, there may be a disconnection between the first subpad 206a and the second subpad 206b. In some embodiments, the disconnection may be located adjacent to the first corner C1.

[0104] like Figure 2C As shown, the pad layer 206 and the signal transmission layer 106 are formed by patterning the same film layer. In other words, the pad layer 206 and the signal transmission layer 106 are located at approximately the same level, so the pad layer 206 can block the photoresist at the panel corners, thereby effectively improving the uniformity of the photoresist at the panel corners to prevent the thickness of the photoresist at the panel corners from being too thin, reducing the probability of poor etching effect of the signal transmission layer 106 at the corners, thereby improving the yield.

[0105] Figure 3A is a schematic top view of a display panel according to at least another embodiment of the present invention. Figure 3A , Figure 3A Examples and Figure 2A Most of the component structures, materials, processes and relative position relationships of the embodiments are the same, so the same technical features will not be repeated here. The differences between the two embodiments are Figure 3A The pad layer 306 of the display panel 3 includes a plurality of electrically floating sections 306 p.

[0106] Figure 3B yes Figure 3A Schematic diagram of the enlarged area C in the middle. Figure 3C yes Figure 3B Schematic diagram of the cross section drawn along the section line c-c' in. Figure 3B and Figure 3C , the section 306p is not electrically connected to other layers, that is, the section 306p is an electrically floating conductive layer that does not receive any signal.

[0107] Figure 4A is a schematic top view of a display panel according to at least another embodiment of the present invention. Figure 4A Examples and Figure 2A Most of the component structures, materials, processes and relative position relationships of the embodiments are the same, so the same technical features will not be repeated here. Figure 4A Examples and Figure 2A The difference between the embodiments is Figure 4A The pad layer 406 of the display panel 4 is electrically connected to the first pad 110a.

[0108] Figure 4B yes Figure 4A Schematic diagram of the enlarged area D in the middle. Figure 4C yes Figure 4B Schematic diagram of the cross section drawn along the section line d-d' in . For details, please refer to Figure 4B and Figure 4C , the first retaining wall structure 121 is electrically connected to the first pad 110a, and the pad layer 406 is electrically connected to the first retaining wall structure 121, so the pad layer 406 is electrically connected to the first pad 110a. In addition, the pad layer 406 includes a first sub-pad 406a and a second sub-pad 406b, and their relative positions and connection relationships are the same as Figure 2B The above contents are similar, so the same technical features will not be repeated here.

[0109] Through the design of the above-mentioned electrical connection relationship, compared with the pad layer 206 of the display panel 2 being electrically connected to the signal transmission layer 106 with a different voltage from the first retaining wall structure 121, or the pad layer 306 of the display panel 3 being an electrically floating section 306p, the pad layer 406 of the display panel 4 is electrically connected to the first retaining wall structure 121, and is less likely to cause a short circuit between the overlapping pad layer and the retaining wall structure that receive different voltages due to process steps, such as laser cutting, or to generate unnecessary capacitance due to the pad layer that overlaps with the retaining wall structure but is electrically floating.

[0110] In summary, in the display panel of at least one embodiment of the present invention, a retaining wall structure is set at the corner of the panel, and the retaining wall structure is located between the pad group at the corner of the panel and the two edges of the corner. This can improve the uniformity of the photoresist at the corner of the panel, thereby avoiding the thickness of the photoresist at the corner of the panel being too thin, reducing the probability of poor etching effect of the pad located at the corner, and thereby improving the yield.

[0111] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person having ordinary knowledge in the technical field to which the present invention belongs may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A display panel, characterized in that: include: An array substrate, comprising: A substrate having a surface, wherein the surface has a first corner, wherein the first corner has a first edge and a second edge connected to each other; A plurality of pad groups are disposed on the surface, wherein the pad groups include a first group of pad groups located at the first corner; and a first retaining wall structure disposed on the surface and located at the first corner, and the first retaining wall structure is located between the first group of pads and the first edge and the second edge, wherein the first retaining wall structure and at least one film layer of the pads are formed by patterning the same film layer; and A plurality of light emitting elements are respectively disposed on the pad groups.

2. The display panel according to claim 1, wherein: The first retaining wall structure includes a first sub-wall and a second sub-wall. The first sub-wall is located between the first edge and the first group of pads, and the second sub-wall is located between the second edge and the first group of pads.

3. The display panel according to claim 2, wherein: The first sub-wall is connected to the second sub-wall.

4. The display panel according to claim 1, wherein: Each of the pad groups includes a first pad and a second pad. The first pad receives a first voltage, and the second pad receives a second voltage. The first voltage is different from the second voltage. The first retaining wall structure is electrically connected to the first pads.

5. The display panel according to claim 4, wherein: The array substrate further comprises: a signal transmission layer, disposed between the substrate and the pad groups, and electrically connected to the second pads; and A pad layer is disposed between the substrate and the first retaining wall structure and overlaps with the first retaining wall structure on a normal line of the substrate, wherein the pad layer and at least one film layer of the signal transmission layer are formed by patterning the same film layer.

6. The display panel according to claim 5, characterized in that: The pad layer is electrically connected to the signal transmission layer.

7. The display panel according to claim 5, wherein: The pad layer includes a plurality of electrically floating sections.

8. The display panel according to claim 5, wherein: The pad layer is electrically connected to the first pads.

9. The display panel according to claim 1, wherein: The distance between the first retaining wall structure and the first group of pads is no greater than 50 μm.

10. The display panel according to claim 1, wherein: The surface further has a second corner, the second corner has the second edge and a third edge connected to each other, the pad groups further include a second group pad group located at the second corner and a third group pad group located between the first group pad group and the second group pad group, the array substrate further includes a second retaining wall structure, which is arranged on the surface and located at the second corner, and the second retaining wall structure is located between the second group pad group and the second edge and the third edge, wherein the second retaining wall structure and at least one film layer of the pad groups are formed by patterning the same film layer, and the first retaining wall structure and the second retaining wall structure do not extend between the third group pad group and the second edge.

11. A display panel, characterized in that: include: An array substrate, comprising: A substrate having a surface, wherein the surface has a first corner, wherein the first corner has a first edge and a second edge connected to each other; A plurality of pad groups are disposed on the surface, wherein the pad groups include a first group of pad groups located at the first corner, and each of the pad groups includes a first pad and a second pad, the first pad receives a first voltage, the second pad receives a second voltage, and the first voltage is different from the second voltage; and a first retaining wall structure disposed on the surface and located at the first corner, and the first retaining wall structure is located between the first group of pads and the first edge and the second edge, wherein the first retaining wall structure is electrically connected to the first pads; and A plurality of light emitting elements are respectively disposed on the pad groups.

12. The display panel according to claim 11, wherein: The array substrate further comprises: a signal transmission layer, disposed between the substrate and the pad groups, and electrically connected to the second pads; and A pad layer is disposed between the substrate and the first retaining wall structure and overlaps with the first retaining wall structure on a normal line of the substrate, wherein the pad layer is electrically connected to the first pads.

13. The display panel according to claim 11, wherein: The first voltage is a reference potential.

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