Limit cycle oscillation suppression system and suppression method applied to particle accelerator power supply

Abstract

The invention discloses a limit cycle oscillation suppression system and suppression method applied to a particle accelerator power supply, and solves the problem of limit cycle oscillation caused by mismatching of the duty ratio resolution of a PWM wave output by a controller and the sampling resolution of an ADC in the control of the existing particle accelerator power supply. On the basis of a digital communication architecture formed by connecting a DSP and an FPGA, extra hardware facilities are not needed, an HRPWM module of the DSP is used for outputting high-precision digital PWM waves to be matched with a sigma-delta modulator and a modulation strategy, noise margin is separated, the duty ratio of the power supply of the particle accelerator is modulated in an error feedback mode, and the duty ratio of the power supply of the particle accelerator is adjusted. The problem of limit cycle oscillation caused by mismatching of the high-precision ADC sampling resolution and the PWM wave duty ratio resolution can be effectively suppressed, the power output quality of the particle accelerator is improved, and the hardware cost is reduced.

Description

Technical Field

[0001] The invention relates to an oscillation suppression method for a particle accelerator power supply, and in particular to a limit cycle oscillation suppression system and a suppression method applied to a particle accelerator power supply. Background Art

[0002] A particle accelerator is a device that uses a certain form of electromagnetic field to accelerate charged particles, such as electrons, protons, and heavy ions, to obtain high energy. Particle accelerators have a wide range of applications. One of them is basic scientific research. In high-energy physics experiments, particle accelerators are used to study the properties of elementary particles and explore the basic structure of the universe. In addition, particle accelerators are used in radiotherapy in the medical field, using high-energy particle beams to accurately destroy cancer cells, providing an effective treatment for cancer patients. This medical application can not only improve the treatment effect, but also reduce damage to the patient's healthy tissue. In industry, by precisely controlling the energy and intensity of the particle beam, particle accelerators can be used to change the properties of materials, perform fine processing on materials, etc., to improve production efficiency and product quality. At the same time, particle accelerators such as heavy ion accelerators are often used in nuclear fusion research to explore clean and sustainable energy solutions. In short, particle accelerators with multi-field applications have brought many important scientific, medical, and industrial technological advances to human society, and promoted innovation and development in various fields. At the same time, the development of these fields has also put forward higher requirements for accelerator technology.

[0003] The power supply and control system of a particle accelerator is a very important subsystem. Its output excitation current is used to control the magnetic field of the accelerator, form the trajectory and track of the beam, and achieve precise control of the beam. The power supply of a particle accelerator is a high-precision special power supply, including high-stability DC power supply, scanning power supply and pulse power supply.

[0004] The controller, as the core of the particle accelerator power supply, directly determines the final performance of the power supply. Many years ago, the particle accelerator power supply system, which was mainly based on analog power supply, usually used analog regulators to control the power supply system. This regulation method has fast response speed and simple control, but it requires the use of a large number of analog devices, and the analog circuit has aging and temperature drift problems. It is easy to reduce the accuracy and stability of the power supply after long-term operation, which is not conducive to maintenance.

[0005] In recent years, the industry's research on power supply controllers has gradually deepened, and the controller's hardware design, algorithms, control interfaces, and human-machine interfaces are all top priorities. With the development of semiconductor technology and computer science technology and the advancement of the digital transformation of particle accelerator power supplies, digital control technology has been more widely used. Domestic and foreign companies mostly use a combination of DSP, ARM, and FPGA to build an overall digital control architecture, and use an 18-bit ADC to increase the power supply output resolution from 10ppm to 3-5ppm. Figure 1 In the overall digital control architecture shown in the figure, the actual digital control also has the characteristics of amplitude quantization. Both the analog-to-digital converter ADC and the digital pulse width modulator PWM will perform amplitude quantization. The linear characteristics of the system are not retained during amplitude quantization. Such nonlinear behavior will cause changes in the movement of the state trajectory in the steady state, such as limit cycles. When the duty cycle resolution of the PWM wave is lower than the ADC sampling resolution, limit cycle oscillation will occur, such as Figure 2 As shown in , the emergence of limit cycles will potentially affect the regulation accuracy and performance of the digital controller. Figure 3 As shown in the figure, the steady-state oscillation of the output current occurs when the PWM resolution and duty cycle resolution are lower than the ADC sampling resolution. According to the measurement, the peak-to-peak value of the oscillation superimposed ripple reaches 8.2mA (under this topology, the peak-to-peak value of the ripple is 3mA). The output current in this case will seriously affect the use of the particle accelerator power supply. Summary of the invention

[0006] The purpose of the present invention is to solve the problem of limit cycle oscillation caused by the mismatch between the duty cycle resolution of the controller output PWM wave and the ADC sampling resolution in the control of the existing particle accelerator power supply, and to provide a limit cycle oscillation suppression system and suppression method applied to the particle accelerator power supply.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] A limit cycle oscillation suppression system applied to a particle accelerator power supply, which is special in that it includes an ADC sampling module, a PI current double closed-loop control module, a Σ-Δ modulator, a digital communication architecture formed by connecting a DSP and an FPGA, and a power driver;

[0009] The input end of the ADC sampling module is connected to the inductor of the particle accelerator power supply to collect the inductor current of the particle accelerator power supply, and the output end is connected to the first input end of the PI current double closed-loop control module;

[0010] The second input end of the PI current double closed-loop control module is connected to a given particle accelerator power supply current, and is used to perform PI control on the difference between the inductor current of the particle accelerator power supply and the given particle accelerator power supply current to obtain a PI control duty cycle. The output end of the PI current double closed-loop control module is connected to the input end of the Σ-Δ modulator;

[0011] The Σ-Δ modulator is used to load a residual accumulation term on the PI control duty cycle, and perform integer bit truncation to obtain an effective bit duty cycle and a noise margin, output the effective bit duty cycle through an output terminal, and feed back the noise margin as a residual accumulation term to an input terminal of the Σ-Δ modulator; the output terminal of the Σ-Δ modulator is connected to an input terminal of a digital communication architecture;

[0012] The output end of the digital communication architecture is connected to a particle accelerator power supply through a power driver.

[0013] Further, the Σ-Δ modulator includes an adder, a truncation module and a second subtractor;

[0014] The first input end of the adder is respectively connected to the output end of the PI current double closed-loop control module, and is used to accumulate the PI control duty cycle and the residual accumulation item to obtain an accumulated value; the output end of the adder is respectively connected to the input end of the truncation module and the first input end of the second subtractor;

[0015] The truncation module is used to perform integer bit truncation on the accumulated value according to the switching frequency of the particle accelerator power supply to obtain the effective bit duty cycle; the output end of the truncation module is respectively connected to the second input end of the second subtractor and the input end of the digital communication architecture;

[0016] The second subtractor is used to make a difference between the accumulated value and the effective bit duty cycle to obtain the noise margin as the margin accumulation item; the output end of the second subtractor is connected to the second input end of the adder.

[0017] Furthermore, in the truncation module, the calculation formula for performing integer digit truncation on the accumulated value output by the adder according to the switching frequency of the particle accelerator power supply is:

[0018]

[0019] Among them, n DPWM Indicates the accumulated value, n DPWM =u HR [k]+y[k];u HR [k] represents the PI control duty cycle, and y[k] represents the residual accumulation term;

[0020] u[k] represents the effective bit duty cycle, c represents the remainder, and P represents the minimum resolution duty cycle value of the HRPWM module in the digital communication architecture. THRPWM Represents the minimum resolution period of the HRPWM module in the digital communication architecture, T D represents the switching cycle of the particle accelerator power supply, f is the switching frequency of the particle accelerator power supply.

[0021] In the second subtractor, the noise margin is calculated as follows:

[0022] Δu[k]=n DPWM -u[k];

[0023] Wherein, Δu[k] represents the noise margin.

[0024] Further, the PI current double closed-loop control module includes a first subtractor and a PI current double closed-loop controller;

[0025] The two input ends of the first subtractor are respectively connected to the output end of the ADC sampling module and the given particle accelerator power supply current, the output end of the first subtractor is connected to the input end of the PI current double closed-loop controller, and the output end of the PI current double closed-loop controller is connected to the input end of the Σ-Δ modulator.

[0026] Furthermore, it also includes a power converter, wherein the input end of the power converter is connected to the output end of the power driver, and the output end of the power converter is connected to the particle accelerator power supply.

[0027] A limit cycle oscillation suppression method for a particle accelerator power supply is based on the limit cycle oscillation suppression system for a particle accelerator power supply, and is special in that it includes the following steps:

[0028] S1, collect the inductor current of the particle accelerator power supply through the ADC sampling module;

[0029] S2, subtracting the inductor current of the particle accelerator power supply from the given particle accelerator power supply current, performing PI control according to the obtained difference, and obtaining the PI control duty cycle;

[0030] S3, loading a margin accumulation item on the PI control duty cycle to obtain an accumulation value; truncating the accumulation value by integer bits according to the switching frequency of the particle accelerator power supply to obtain an effective bit duty cycle and a noise margin, outputting the effective bit duty cycle through an output terminal, and loading the noise margin as a margin accumulation item to the next PI control duty cycle;

[0031] S4, the digital communication architecture formed by connecting the effective bit duty cycle input DSP and FPGA outputs a high-resolution PWM wave, and controls the particle accelerator power supply through the power driver.

[0032] Furthermore, S3 is specifically:

[0033] S31, define the initial residual accumulation item as 0;

[0034] S32, add a margin accumulation item to the PI control duty cycle to obtain an accumulation value, and the calculation formula is:

[0035] u HR [k]+y[k]=n DPWM ;

[0036] Among them, u HR [k] represents the PI control duty cycle, y[k] represents the residual accumulation term, n DPWM Indicates the accumulated value;

[0037] S33, obtaining a switching period of the particle accelerator power supply according to the switching frequency of the particle accelerator power supply;

[0038]

[0039] Where, f represents the switching frequency of the particle accelerator power supply, T D represents the switching cycle of the particle accelerator power supply;

[0040] According to the switching cycle T of the particle accelerator power supply D The minimum resolution period T of the HRPWM module in the digital communication architecture HRPWM Calculate the minimum resolution duty cycle P of the HRPWM module in the digital communication architecture:

[0041]

[0042] The minimum resolution duty cycle of the HRPWM module in the digital communication architecture is used to truncate the accumulated value to obtain the effective duty cycle:

[0043]

[0044] Wherein, u[k] represents the effective bit duty cycle, and c represents the remainder;

[0045] S34. Calculate the noise margin based on the accumulated value and the effective bit duty cycle:

[0046] Δu[k]=n DPWM -u[k];

[0047] Where Δu[k] represents the noise margin;

[0048] S35, output the effective bit duty cycle through the output terminal, and use the noise margin as the margin accumulation item, return to S32, and load it into the next PI control duty cycle.

[0049] Further, in S4, driving and controlling the particle accelerator power supply through the power driver specifically includes: outputting a driving signal through the power driver, and the driving signal drives and controls the particle accelerator power supply after being low-pass filtered by the power converter.

[0050] Beneficial effects of the present invention:

[0051] The invention discloses a limit cycle oscillation suppression system and a suppression method for a particle accelerator power supply. Based on a digital communication architecture formed by connecting a DSP and an FPGA, no additional hardware facilities are required. The HRPWM module of the DSP itself is used to output a high-precision digital PWM wave in cooperation with a Σ-Δ modulator and a modulation strategy to separate the noise margin, and the duty cycle of the particle accelerator power supply is modulated by an error feedback method. The limit cycle oscillation problem caused by the mismatch between the high-precision ADC sampling resolution and the PWM wave duty cycle resolution can be effectively suppressed, thereby improving the output quality of the particle accelerator power supply and reducing the hardware cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a schematic diagram of the overall digital control architecture structure in the background technology of the present invention;

[0053] Figure 2 A diagram showing the limit cycle oscillation phenomenon occurring in the background technology of the present invention;

[0054] Figure 3 It is a waveform diagram of the steady-state oscillation phenomenon of the output current under the PWM resolution duty cycle in the background technology of the present invention;

[0055] Figure 4 It is a block diagram of the connection of various modules in an embodiment of a limit cycle oscillation suppression system applied to a particle accelerator power supply of the present invention;

[0056] Figure 5 It is a structural principle diagram of a Σ-Δ modulator in an embodiment of a limit cycle oscillation suppression system applied to a particle accelerator power supply of the present invention;

[0057] Figure 6 The waveform diagram of the output current ripple when the particle accelerator power supply is controlled by using the existing PWM wave modulation method;

[0058] Figure 7 The present invention is a waveform diagram of the output current ripple of a particle accelerator power supply controlled by a limit cycle oscillation suppression system and a suppression method for a particle accelerator power supply of the present invention. DETAILED DESCRIPTION

[0059] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0060] In this embodiment, a limit cycle oscillation suppression system is applied to a particle accelerator power supply. Figure 4 As shown, it includes an ADC sampling module, a PI current dual closed-loop control module, a Σ-Δ modulator, a digital communication architecture formed by connecting DSP and FPGA, and a power driver. This embodiment designs a Σ-Δ modulator based on the existing digital communication architecture formed by connecting DSP and FPGA, so as to suppress the limit cycle oscillation problem caused by the mismatch between the high-precision ADC sampling resolution and the PWM output resolution duty cycle, thereby improving the power output quality.

[0061] The input end of the ADC sampling module is connected to the inductor of the particle accelerator power supply to collect the inductor current of the particle accelerator power supply, and the output end is connected to the first input end of the PI current double closed-loop control module;

[0062] The second input end of the PI current double closed-loop control module is connected to the given particle accelerator power supply current, and is used to perform PI control on the difference between the inductor current of the particle accelerator power supply and the given particle accelerator power supply current to obtain a PI control duty cycle. The output end of the PI current double closed-loop control module is connected to the input end of the Σ-Δ modulator; the PI current double closed-loop control module includes a first subtractor and a PI current double closed-loop controller;

[0063] The two input ends of the first subtractor are respectively connected to the output end of the ADC sampling module and the given particle accelerator power supply current, the output end of the first subtractor is connected to the input end of the PI current double closed-loop controller, and the output end of the PI current double closed-loop controller is connected to the input end of the Σ-Δ modulator.

[0064] The Σ-Δ modulator is used to load the residual accumulation item to the PI control duty cycle, and perform integer bit truncation to obtain the effective bit duty cycle and the noise margin, output the effective bit duty cycle through the output end, and feed back the noise margin as the residual accumulation item to the input end of the Σ-Δ modulator; Figure 5 As shown, the output end of the Σ-Δ modulator is connected to the input end of the digital communication architecture; the Σ-Δ modulator includes an adder, a truncation module and a second subtractor;

[0065] The first input end of the adder is connected to the output end of the PI current double closed-loop control module, and is used to accumulate the PI control duty cycle and the residual accumulation item to obtain an accumulated value; the output end of the adder is respectively connected to the input end of the truncation module and the first input end of the second subtractor;

[0066] The truncation module is used to perform integer bit truncation on the accumulated value according to the switching frequency of the particle accelerator power supply to obtain the effective bit duty cycle; the output end of the truncation module is respectively connected to the second input end of the second subtractor and the input end of the digital communication architecture; in the truncation module, the calculation formula for performing integer bit truncation on the accumulated value output by the adder according to the switching frequency of the particle accelerator power supply is:

[0067]

[0068] Among them, n DPWM Indicates the accumulated value, n DPWM =u HR [k]+y[k];u HR [k] represents the PI control duty cycle, and y[k] represents the residual accumulation term;

[0069] u[k] represents the effective bit duty cycle, c represents the remainder, and P represents the minimum resolution duty cycle value of the HRPWM module in the digital communication architecture; T HRPWM Represents the minimum resolution period of the HRPWM module in the digital communication architecture, T D represents the switching cycle of the particle accelerator power supply;

[0070] f is the switching frequency of the particle accelerator power supply.

[0071] In the second subtractor, the noise margin is calculated as:

[0072] Δu[k]=n DPWM -u[k];

[0073] Wherein, Δu[k] represents the noise margin.

[0074] The second subtractor is used to make a difference between the accumulated value and the effective bit duty cycle to obtain the noise margin as the residual accumulation item; the output end of the second subtractor is connected to the second input end of the adder.

[0075] The Σ-Δ modulator of the present invention outputs the effective bit of the duty cycle calculated by closed loop to control the particle accelerator power supply, and the remaining noise is fed back to the accumulation item, accumulated multiple times until the minimum resolution of the duty cycle is reached and then output again.

[0076] The output of the digital communication architecture is connected to the particle accelerator power supply through a power driver.

[0077] In this embodiment, the effective bit duty cycle of the output, u[k] low frequency average value is equal to u HR [k], but noise will be generated at high frequencies, so jitter can be observed in the output of the power driver. Since the power converter has a low-pass filtering behavior, the jitter of the power driver output will be low-pass filtered and will basically not affect the output current or voltage of the power converter. At the same time, the average value of u[k] can be compared with u HR [k] is the same, which is equivalent to the average resolution of u[k] reaching u HR [k], thereby improving the effective resolution of the entire system. Based on this, the present embodiment also includes a power converter, the input end of the power converter is connected to the output end of the power driver, and the output end of the power converter is connected to the particle accelerator power supply.

[0078] A limit cycle oscillation suppression method for a particle accelerator power supply is based on a limit cycle oscillation suppression system for a particle accelerator power supply, and includes the following steps:

[0079] S1, collect the inductor current of the particle accelerator power supply through the ADC sampling module;

[0080] S2, subtracting the inductor current of the particle accelerator power supply from the given particle accelerator power supply current, performing PI control according to the obtained difference, and obtaining the PI control duty cycle;

[0081] S3, loading a margin accumulation item on the PI control duty cycle to obtain an accumulation value; truncating the accumulation value by integer bits according to the switching frequency of the particle accelerator power supply to obtain an effective bit duty cycle and a noise margin, outputting the effective bit duty cycle through the output terminal, and loading the noise margin as a margin accumulation item to the next PI control duty cycle; specifically:

[0082] S31, define the initial residual accumulation item as 0;

[0083] S32, add a margin accumulation item to the PI control duty cycle to obtain an accumulation value, and the calculation formula is:

[0084] u HR [k]+y[k]=n DPWM ;

[0085] Among them, u HR [k] represents the PI control duty cycle, y[k] represents the residual accumulation term, n DPWM Indicates the accumulated value;

[0086] S33, obtaining a switching period of the particle accelerator power supply according to the switching frequency of the particle accelerator power supply;

[0087]

[0088] Where, f represents the switching frequency of the particle accelerator power supply, T D represents the switching cycle of the particle accelerator power supply;

[0089] According to the switching cycle T of the particle accelerator power supply D The minimum resolution period T of the HRPWM module in the digital communication architecture HRPWM Calculate the minimum resolution duty cycle P of the HRPWM module in the digital communication architecture:

[0090]

[0091] Usually, the minimum resolution period of the HRPWM module in the digital communication architecture is T HRPWM Take it as 150ps.

[0092] The minimum resolution duty cycle of the HRPWM module in the digital communication architecture is used to truncate the accumulated value to obtain the effective duty cycle:

[0093]

[0094] Wherein, u[k] represents the effective bit duty cycle, and c represents the remainder;

[0095] S34. Calculate the noise margin based on the accumulated value and the effective bit duty cycle:

[0096] Δu[k]=n DPWM -u[k];

[0097] Where Δu[k] represents the noise margin;

[0098] S35, output the effective bit duty cycle through the output terminal, and use the noise margin as the margin accumulation item, return to S32, and load it into the next PI control duty cycle.

[0099] S4. Input the effective bit duty cycle into the digital communication architecture to output a high-resolution PWM wave, output a drive signal through the power driver, and drive the particle accelerator power supply after low-pass filtering by the power converter. The low-pass filtered signal drives the particle accelerator power supply.

[0100] The particle accelerator power supply is modulated using the existing PWM wave modulation method, and the output current is tested. The waveform is as follows Figure 6 As shown, the peak-to-peak value of the output current oscillation is 25.7 mA; the limit cycle oscillation suppression system and suppression method applied to the particle accelerator power supply of this embodiment are used to optimize the PWM effective resolution duty cycle, and the output current is further tested. The test output waveform is as follows Figure 7As shown, the peak-to-peak value of the output current oscillation is 8.9 mA respectively. By comparison, it can be seen that the limit cycle oscillation suppression system and suppression method applied to a particle accelerator power supply in this embodiment obtains that the PWM wave has almost no limit cycle oscillation in the control of the particle accelerator power supply, that is, the oscillation is suppressed.

[0101] The above description is only a specific embodiment of the present invention, and a comparison of the effects of the specific embodiments and the related comparative examples, but the protection scope of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A limit cycle oscillation suppression system for a particle accelerator power supply, characterized in that: It includes ADC sampling module, PI current double closed-loop control module, Σ-Δ modulator, digital communication architecture formed by connecting DSP and FPGA, and power driver; The input end of the ADC sampling module is connected to the inductor of the particle accelerator power supply to collect the inductor current of the particle accelerator power supply, and the output end is connected to the first input end of the PI current double closed-loop control module; The second input end of the PI current double closed-loop control module is connected to a given particle accelerator power supply current, and is used to perform PI control on the difference between the inductor current of the particle accelerator power supply and the given particle accelerator power supply current to obtain a PI control duty cycle. The output end of the PI current double closed-loop control module is connected to the input end of the Σ-Δ modulator; The Σ-Δ modulator is used to load a residual accumulation term on the PI control duty cycle, and perform integer bit truncation to obtain an effective bit duty cycle and a noise margin, output the effective bit duty cycle through an output terminal, and feed back the noise margin as a residual accumulation term to an input terminal of the Σ-Δ modulator; the output terminal of the Σ-Δ modulator is connected to an input terminal of a digital communication architecture; The output end of the digital communication architecture is connected to a particle accelerator power supply through a power driver.

2. A limit cycle oscillation suppression system for a particle accelerator power supply according to claim 1, characterized in that: The Σ-Δ modulator includes an adder, a truncation module and a second subtractor; The first input end of the adder is connected to the output end of the PI current double closed-loop control module, and is used to accumulate the PI control duty cycle and the residual accumulation item to obtain an accumulated value; the output end of the adder is respectively connected to the input end of the truncation module and the first input end of the second subtractor; The truncation module is used to perform integer bit truncation on the accumulated value according to the switching frequency of the particle accelerator power supply to obtain the effective bit duty cycle; the output end of the truncation module is respectively connected to the second input end of the second subtractor and the input end of the digital communication architecture; The second subtractor is used to make a difference between the accumulated value and the effective bit duty cycle to obtain the noise margin as the margin accumulation item; the output end of the second subtractor is connected to the second input end of the adder.

3. A limit cycle oscillation suppression system for a particle accelerator power supply according to claim 2, characterized in that: In the truncation module, the calculation formula for truncating the integer bit of the accumulated value output by the adder according to the switching frequency of the particle accelerator power supply is: Among them, n DPWM Indicates the accumulated value, n DPWM =u HR [k]+y[k];u HR [k] represents the PI control duty cycle, and y[k] represents the residual accumulation term; u[k] represents the effective bit duty cycle, c represents the remainder, and P represents the minimum resolution duty cycle value of the HRPWM module in the digital communication architecture. T HRPWM Represents the minimum resolution period of the HRPWM module in the digital communication architecture, T D represents the switching cycle of the particle accelerator power supply; f is the switching frequency of the particle accelerator power supply.

4. The limit cycle oscillation suppression system for a particle accelerator power supply according to claim 3, characterized in that: In the second subtractor, the noise margin is calculated as follows: Δu[k]=n DPWM -u[k]; Wherein, Δu[k] represents the noise margin.

5. The limit cycle oscillation suppression system for a particle accelerator power supply according to claim 1, characterized in that: The PI current double closed-loop control module includes a first subtractor and a PI current double closed-loop controller; The two input ends of the first subtractor are respectively connected to the output end of the ADC sampling module and the given particle accelerator power supply current, the output end of the first subtractor is connected to the input end of the PI current double closed-loop controller, and the output end of the PI current double closed-loop controller is connected to the input end of the Σ-Δ modulator.

6. The limit cycle oscillation suppression system for a particle accelerator power supply according to claim 1, characterized in that: It also includes a power converter, the input end of the power converter is connected to the output end of the power driver, and the output end of the power converter is connected to the particle accelerator power supply.

7. A limit cycle oscillation suppression method for a particle accelerator power supply, characterized in that: A limit cycle oscillation suppression system for a particle accelerator power supply according to any one of claims 1 to 6 comprises the following steps: S1, collect the inductor current of the particle accelerator power supply through the ADC sampling module; S2, subtracting the inductor current of the particle accelerator power supply from the given particle accelerator power supply current, performing PI control according to the obtained difference, and obtaining the PI control duty cycle; S3, loading a margin accumulation item on the PI control duty cycle to obtain an accumulation value; truncating the accumulation value by integer bits according to the switching frequency of the particle accelerator power supply to obtain an effective bit duty cycle and a noise margin, outputting the effective bit duty cycle through an output terminal, and loading the noise margin as a margin accumulation item to the next PI control duty cycle; S4, the digital communication architecture formed by connecting the effective bit duty cycle input DSP and FPGA outputs a high-resolution PWM wave, and controls the particle accelerator power supply through the power driver.

8. A limit cycle oscillation suppression method for a particle accelerator power supply according to claim 7, characterized in that: S3 is specifically: S31, define the initial residual accumulation item as 0; S32, add a margin accumulation item to the PI control duty cycle to obtain an accumulation value, and the calculation formula is: u HR [k]+y[k]=n DPWM ; Among them, u HR [k] represents the PI control duty cycle, y[k] represents the residual accumulation term, n DPWM Indicates the accumulated value; S33, obtaining a switching period of the particle accelerator power supply according to the switching frequency of the particle accelerator power supply; Where, f represents the switching frequency of the particle accelerator power supply, T D represents the switching cycle of the particle accelerator power supply; According to the switching cycle T of the particle accelerator power supply D The minimum resolution period T of the HRPWM module in the digital communication architecture HRPWM Calculate the minimum resolution duty cycle P of the HRPWM module in the digital communication architecture: The minimum resolution duty cycle of the HRPWM module in the digital communication architecture is used to truncate the accumulated value to obtain the effective duty cycle: Wherein, u[k] represents the effective bit duty cycle, and c represents the remainder; S34. Calculate the noise margin based on the accumulated value and the effective bit duty cycle: Δu[k]=n DPWM -u[k]; Where Δu[k] represents the noise margin; S35, output the effective bit duty cycle through the output terminal, and use the noise margin as the margin accumulation item, return to S32, and load it into the next PI control duty cycle.

9. The limit cycle oscillation suppression method for a particle accelerator power supply according to claim 7, characterized in that: In S4, driving and controlling the particle accelerator power supply through the power driver specifically includes: outputting a driving signal through the power driver, and the driving signal is driven and controlled by the particle accelerator power supply after being low-pass filtered by the power converter.

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