Digital controller

Abstract

A digital controller for a switching converter configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising a ripple cancellation signal generator configured to generate a ripple cancellation signal, the digital controller is configured to: receive a digitized current signal, the digitized current signal being a digital representation of a current flowing through the energy storage element; generating a filtered digital current error signal using the digitized current signal and a ripple cancellation signal arranged to reduce ripple from the digitized current signal when generating the filtered digital current error signal; and controlling the switching converter, the control of the switching converter depending on the filtered digital current error signal, in which, within each signal period, the ripple cancellation signal includes a rising slope having a first non-linear portion and / or a falling slope having a second non-linear portion.

Description

[0001] The present disclosure relates to a digital controller. In particular, the present disclosure relates to a digital controller for a switching converter.

[0002] background

[0003] 1(a) is a schematic diagram of a digital buck converter 100 having analog-to-digital converters (ADCs) 102, 104, 106 and a controller 108. Buck converter 100 includes switches 110, 112, an inductor 114, and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT.

[0004] When the power stage and passive components (inductor 114 and capacitor 116) remain the same as for the analog buck converter, ADC 102 converts the output voltage VOUT into a digital value. The conversion is performed in the time domain at a given rate: for example, the VOUT digital value is updated every 1 μs.

[0005] Optionally, the inductor current IL of the inductor 114 and the input voltage VIN may also be converted from analog to digital according to a digital control method.

[0006] We distinguish:

[0007] The switching frequency (FSW) of the buck converter 100, for example 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage.

[0008] The processing frequency (FS) of the digital controller 108 , for example, about 100 MHz. FS is equal to 1 / TS, where TS is the processing period of the controller 108 . Optionally, FS may also be the sampling frequency of the ADC 102 .

[0009] FIG. 1( b ) is a schematic diagram of a digital average current mode buck converter 118 and a control circuit 120 .

[0010] The operation of the circuit in Figure 1(b) is as follows:

[0011] The output voltage VOUT is digitized by the ADC 102 to provide a digitized output voltage signal DOUT.

[0012] The digitized output voltage signal DOUT is compared with a digital reference voltage DREF corresponding to a target voltage of the output voltage VOUT. The two digital DOUT and DREF can be, for example, 8-bit buses, where

[0013] The digital code [0; 255] corresponds to the analog range [0.50V; 1.50V].

[0014] The digital error voltage signal DVERR is equal to DREF-DOUT, which is provided to the digital loop control proportional-integral-derivative (PID) circuit 122 to convert the digitized error voltage DVERR into a digital target current DITARGET, which is a digital value that is a target setting for the analog inductor current IL. Therefore, if the output voltage VOUT decreases, the digitized output voltage signal DOUT decreases, the digital error voltage signal DVERR increases, and the digital target current DITARGET increases: the digital control PID 122 requests a larger inductor current IL to restore the output voltage VOUT.

[0015] The digital target current DITARGET may be encoded on more bits, such as 16 bits, and the following signal.

[0016] The inductor target current DITARGET enters the (digital current generating circuit 123; PIDI circuit 124;

[0017] The PWM circuit 126 and the power stage 100 form an “inner loop”. The inner loop adjusts the duty cycle MAG / DEMAG so that the analog inductor current IL matches its digital counterpart inductor current target DITARGET on average.

[0018] The digital current generation circuit 123 may be the ADC 104 as shown in FIG. 1( a ), or may be a “synthesizer” so that it can digitally reproduce the inductor current IL behavior based on the input voltage VIN, the output voltage VOUT, the duty cycle, and possibly other parameters.

[0019] The inner loop operates as follows: If the digital target current DITARGET is higher than the digital inductor current DIL, the digital current error DIERR increases. The digital current error DIERR passes through an integrator (PID 124) to generate a filtered and amplified version, the filtered digital current error DIERRF, which is added and enters the digital duty cycle converter (PWM circuit 126) to increase the duty cycle. This results in an increase in the inductor current IL.

[0020] The control circuit 120 also includes addition / subtraction circuits 128 , 130 , and logic and gate driver circuits 132 .

[0021] Once the inner loop settles to a steady state, the average digital target current is equal to the average digital inductor current, which can be expressed as follows:

[0022] <ditarget> ＝ <dil>(1)

[0023] Variables enclosed in "<>" are used to represent the mean value of the variable. For example, <x>Represents the mean value of the variable x.

[0024] FIG1(c) is a graph showing the transient response of the digital buck converter 100. Trace 134 shows the output voltage VOUT; trace 136 shows the digital target current DITARGET; trace 138 shows the digital inductor current DIL; trace 140 shows the digital current error DIERR; trace 142 shows the filtered digital current error; and trace 144 shows the duty cycle DUTY. The digital inductor current DIL is the digitized inductor current IL.

[0025] To simplify the explanation, Figure 1(c) is in the continuous time and data domain (as if it were analog rather than digital).

[0026] We imagine a load that reduces the output voltage VOUT at the end of the time slot T0.

[0027] • Regulation then increases the digital target current DITARGET to pull back the output voltage VOUT. This naturally increases the digital current error DIERR (the digital current error DIERR has a residual ripple inherited from DIL (because DIERR = DITARGET - DIL)).

[0028] The filtered digital current error DIERRF increases slowly after the transient. At one point, the duty cycle is readjusted for the next cycle (sampling effect) and it allows the inductor current IL (and therefore the digital inductor current DIL) to increase, thereby reducing the error digital current error DIERR until the average value of the digital inductor current DIL corresponds to the desired target digital inductor current DITARGET=2A (at the end of T2).

[0029] It can be observed that the filtered digital current error DIERRF takes a long time to change, so that the decision to adjust the duty cycle is delayed. This reduces the reaction time of the buck converter 100. In particular, the time T1 during which VOUT can be further reduced is not used.

[0030] Overview

[0031] It would be desirable to provide a digital controller that improves the reaction time of a switching converter, such as a digital buck converter, in response to load transients.

[0032] According to a first aspect of the present disclosure, there is provided a digital controller for a switching converter, the switching converter being configured to: receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller being configured to receive a digitized current signal, the digitized current signal being a digital representation of a current flowing through the energy storage element; generate a filtered digital current error signal using the digitized current signal and a ripple elimination signal, the ripple elimination signal being arranged to reduce ripple from the digital current signal when generating the filtered digital current error signal; and control the switching converter, the control of the switching converter depending on the filtered digital current error signal.

[0033] Optionally, the switching converter is a buck converter, a boost converter or a buck-boost converter.

[0034] Optionally, the energy storage element is an inductor.

[0035] Optionally, the one or more power switches include a first power switch and a second power switch.

[0036] Optionally, the digital current signal is received from a digitized current generating circuit.

[0037] Optionally, the digital current generating circuit includes a first analog-to-digital converter configured to sense current flowing through the energy storage element and digitize the sensed current to generate a digital current signal.

[0038] Optionally, the digital current generating circuit comprises a current synthesizer.

[0039] Optionally, the digital controller is configured to receive a digitized output voltage signal, the digitized output voltage signal being a digital representation of the output voltage of the switching converter.

[0040] Optionally, the digitized output voltage signal is received from a second analog-to-digital converter configured to receive the output voltage and digitize the output voltage to generate a digitized output voltage signal.

[0041] Optionally, the digital controller is configured to generate a digital target current signal using the digitized output voltage signal.

[0042] Optionally, the digital controller includes: a first voltage error generating circuit, which is configured to generate a digital error signal using a digitized output voltage signal and a digital voltage reference signal; and a proportional-integral-differential circuit, which is configured to convert the digital error signal into a digital target current signal.

[0043] Optionally, the first voltage error generating circuit is configured to generate a digital error signal by subtracting the digitized output voltage signal from a digital voltage reference signal.

[0044] Optionally, the digital controller includes: a first current error generating circuit, which is configured to generate an unfiltered digital current error signal using a digital target current signal and a digital current signal; and a ripple elimination circuit, which is configured to receive the unfiltered digital current error signal and a ripple elimination signal, and generate a filtered digital current error signal by reducing the ripple of the unfiltered digital current error signal using the ripple elimination signal.

[0045] Optionally, the first current error generating circuit is configured to generate an unfiltered digital current error signal by subtracting the digital target current signal from the digital current signal.

[0046] Optionally, the ripple cancellation circuit is configured to generate a filtered digital current error signal by adding an unfiltered digital current error signal to the ripple cancellation signal.

[0047] Optionally, the digital controller includes: a pulse width modulation circuit configured to generate a PWM signal using the filtered digital current error signal; and a logic and gate driver circuit configured to receive the PWM signal and generate a gate drive signal for each of the one or more power switches using the PWM signal.

[0048] Optionally, the pulse modulation circuit includes: a duty cycle signal generating circuit configured to generate a digital signal using a filtered digital current error signal and an offset signal; and a comparator configured to receive the digital signal and a ramp signal and output a PWM signal based on a comparison between the digital signal and the ramp signal.

[0049] Optionally, the comparator is configured to generate a PWM signal comprising a rising edge and a falling edge, the rising edge and the falling edge being dependent on the digital signal crossing the ramp signal.

[0050] Optionally, the offset signal depends on a duty cycle of the switching converter and a maximum value of the ramp signal.

[0051] According to a second aspect of the present disclosure, there is provided a method for controlling a switching converter using a digital controller, the switching converter being configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the method comprising: receiving a digitized current signal, the digitized current signal being a digital representation of a current flowing through the energy storage element; generating a filtered digital current error signal using the digitized current signal and a ripple elimination signal, the ripple elimination signal being arranged to reduce ripple from the digital current signal when generating the filtered digital current error signal; and controlling the switching converter, the control of the switching converter depending on the filtered digital current error signal.

[0052] It is to be understood that the method of the second aspect may include the features set out in the first aspect, and may be combined with other features as described herein.

[0053] According to a third aspect of the present disclosure, a digital controller for a switching converter is provided, the switching converter being configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising a ripple elimination signal generator, the ripple elimination signal generator being configured to generate a ripple elimination signal, the digital controller being configured to: receive a digitized current signal, the digitized current signal being a digital representation of a current flowing through the energy storage element; generate a filtered digital current error signal using the digitized current signal and the ripple elimination signal, the ripple elimination signal being arranged to reduce ripple from the digitized current signal when generating the filtered digital current error signal; and control the switching converter, the control of the switching converter depending on the filtered digital current error signal, wherein, within each signal cycle, the ripple elimination signal comprises a rising slope having a first nonlinear portion and / or a falling slope having a second nonlinear portion.

[0054] Optionally, the digital controller comprises a sampling circuit configured to sample the digital current signal, wherein the ripple cancellation signal generator is configured to generate the ripple cancellation signal using the sampled digital current signal.

[0055] Optionally, the ripple cancellation signal generator is configured to: receive a clock signal, which is a periodic digital signal having a switching frequency derived from a switching frequency of the switching converter; and generate a ripple cancellation signal using the clock signal, wherein a signal period of the ripple cancellation signal is equal to a period of the clock signal.

[0056] Optionally, the switching frequency of the switching converter is controlled by a clock signal.

[0057] Optionally, the ripple cancellation signal generator is configured to generate the ripple cancellation signal by setting the ripple cancellation signal to zero at each transition of the clock signal.

[0058] Optionally, the ripple cancellation signal includes a rising slope having a first linear portion and / or a falling slope having a second linear portion in each signal period.

[0059] Optionally, the rising slope includes a first linear portion linearly rising to zero and a first nonlinear portion nonlinearly rising from zero, and the falling slope includes a second linear portion linearly falling to zero and a second nonlinear portion nonlinearly falling from zero.

[0060] Optionally, the digital controller includes: a pulse width modulation circuit configured to generate a PWM signal using a filtered digital current error signal; and a logic and gate driver circuit configured to receive the PWM signal and generate a gate drive signal for each of the one or more power switches using the PWM signal, wherein the ripple cancellation signal generator is configured to generate the ripple cancellation signal using the PWM signal.

[0061] Optionally, the ripple cancellation signal generator is configured to generate the ripple cancellation signal using the PWM signal by switching alternately between a rising slope and a falling slope at each switching of the PWM signal.

[0062] Optionally, the PWM signal includes a magnetization state and a demagnetization state, and the ripple cancellation signal generator is configured to generate the ripple cancellation signal by generating a falling slope when the PWM signal is in the magnetization state and generating a rising slope when the PWM signal is in the demagnetization state.

[0063] Optionally, the energy storage element is an inductor having an inductance.

[0064] Optionally, the first linear portion of the rising slope is equal to the output voltage divided by the inductance, and the second linear portion of the falling slope is equal to the difference between the output voltage and the input voltage divided by the inductance.

[0065] Optionally, the first non-linear portion has an inverse exponential growth profile, and the second non-linear portion has an exponential decay profile.

[0066] Optionally, the ripple cancellation signal generator is configured to generate the ripple cancellation signal based on an operating state of the switching converter.

[0067] Optionally, the operating state of the switching converter is derived from a driving state of the switching converter and / or an actual state of the switching converter.

[0068] Optionally, the drive state depends on one or more PWM signals and / or the actual state depends on the switching state of one or more power switches.

[0069] Optionally, the switching converter is a buck-boost converter, and the driving state is dependent on two PWM signals.

[0070] Optionally, the digital controller includes: a pulse width modulation circuit configured to generate one or more PWM signals using the filtered digital current error signal; and a logic and gate driver circuit configured to receive the one or more PWM signals and generate a gate drive signal for each of the one or more power switches using the one or more PWM signals, wherein the ripple cancellation signal generator is configured to generate the ripple cancellation signal using the one or more PWM signals.

[0071] Optionally, the ripple cancellation signal generator is configured to generate the ripple cancellation signal using the one or more PWM signals by switching alternately between a rising slope and a falling slope at each switching of at least one PWM signal among the one or more PWM signals.

[0072] Optionally, each of the one or more PWM signals includes a magnetization state and a demagnetization state, and the ripple cancellation signal generator is configured to generate the ripple cancellation signal by generating a falling slope when at least one of the one or more PWM signals is in the magnetization state and generating a rising slope when at least one of the one or more PWM signals is in the demagnetization state.

[0073] According to a fourth aspect of the present disclosure, there is provided a method for controlling a switching converter using a digital controller, the switching converter being configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising a ripple elimination signal generator, the ripple elimination signal generator being configured to generate a ripple elimination signal, the method comprising: receiving a digitized current signal, the digitized current signal being a digital representation of a current flowing through the energy storage element; generating a filtered digital current error signal using the digitized current signal and the ripple elimination signal, the ripple elimination signal being arranged to reduce ripple from the digitized current signal when generating the filtered digital current error signal; and controlling the switching converter, the control of the switching converter depending on the filtered digital current error signal, wherein, within each signal cycle, the ripple elimination signal comprises a rising slope having a first nonlinear portion and / or a falling slope having a second nonlinear portion.

[0074] It will be appreciated that the method of the fourth aspect may include the features set out in the third aspect, and may be combined with other features as described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0077] FIG. 1( a ) is a schematic diagram of a digital buck converter, FIG. 1( b ) is a schematic diagram of a digital average current mode buck converter and a control circuit, and FIG. 1( c ) is a graph showing a transient response of the digital buck converter;

[0078] FIG. 2( a ) is a schematic diagram of a digital controller for a switching converter according to a first embodiment of the present disclosure, FIG. 2( b ) is a schematic diagram of a specific embodiment of the system shown in FIG. 2( a ), FIG. 2( c ) is a schematic diagram of another specific embodiment of the system shown in FIG. 2( a ), and FIG. 2( d ) is a schematic diagram of another specific embodiment of the system shown in FIG. 2( a );

[0079] FIG. 3( a ) is a schematic diagram of a specific embodiment of a controller according to a second embodiment of the present disclosure, and FIG. 3( b ) is a schematic diagram of a specific embodiment of a controller according to a third embodiment of the present disclosure;

[0080] Figure 4 is a schematic diagram of a specific embodiment of the system of the present disclosure according to a fourth embodiment of the present disclosure;

[0081] FIG5(a) shows Figure 4 FIG5( b ) is a time curve diagram of a simulation result of a practical implementation of the system shown in FIG5( b ). Figure 4 FIG5( c ) is another time curve diagram of a simulation result of a practical implementation of the system shown in FIG5( c ). Figure 4 FIG5( d ) is another time graph of a simulation result of a practical implementation of the system shown in FIG5( d ). Figure 4 FIG5( e) is a graph showing the cross over point of a digital signal and a ramp signal; FIG5( f) is a schematic diagram of an example of a local delay locked loop (DLL) that may be implemented in any of the described embodiments; and FIG5( g) is a graph showing the cross over point of a digital signal and a ramp signal;

[0082] Figure 6 It is shown Figure 4 A graph of simulation results for a practical implementation of the system;

[0083] FIG7(a) is a graph showing digitized inductor current versus time, FIG7(b) is a graph showing an unfiltered digital current error, a ripple cancellation signal, and a filtered digital current error, and FIG7(c) is a graph of a negative ideal ripple cancellation signal using a nonlinear slope;

[0084] FIG8( a ) is a schematic diagram of a specific embodiment of a digital controller according to a fifth embodiment of the present disclosure, and FIG8( b ) is a schematic diagram of a specific embodiment of a digital controller according to a sixth embodiment of the present disclosure;

[0085] FIG. 9( a ) is a graph showing a digitized inductor current for sampling, and FIG. 9( b ) is a graph showing the gain and phase relationship using the sampling method compared to an ideal ripple cancellation signal and a schematic diagram of a simulation circuit;

[0086] Fig.10 is a schematic diagram of a specific embodiment of a digital controller according to a seventh embodiment of the present disclosure;

[0087] Fig.11 is shown with Fig.10 A graph of a waveform associated with the operation of the system;

[0088] Fig.12 is a schematic diagram of a specific embodiment of a digital controller according to an eighth embodiment of the present disclosure;

[0089] Fig.13 is shown with Fig.12 A graph of a waveform associated with the operation of the system;

[0090] Fig.14 is a graph showing generation of a line slope that may be used for a line slope portion of a ripple cancellation signal;

[0091] Fig.15 is a schematic diagram of a specific embodiment of a digital controller and a buck converter according to a ninth embodiment of the present disclosure;

[0092] Fig.16 It is shown Fig.15 A graph of simulation results of a practical implementation of the system shown in ; and

[0093] FIG. 17( a ) is a schematic diagram of a specific example of a digital loop control proportional-integral-differential circuit, and FIG. 17( b ) is a schematic diagram of a specific example of a ripple cancellation signal generator.

[0094] Detailed Description

[0095] In FIG. 1( b ), PID 124 acts as a low pass filter and is used for the following reasons:

[0096] Preferably, the gain is applied by the PID 124. For example, assume we have a 50% duty cycle, we want the inductor current IL=1A, and the block PWM circuit 126 needs an input filtered digital current error DIERRF between 0 and 15 to generate / control a duty cycle within [0;1]. If the PID 124 has a gain of 1, this means that in order to obtain a 50% duty cycle, (DITARGET-DIL) will need to be 7. Therefore, for a digital inductor current DIL=1A, the target digital current DITARGET needs to be 8. We observe that the two values ​​DITARGET and DIL can be very different. This is not a fundamental issue in order for the buck converter 100 to work, but we lose the advantage of having DITARGET~DIL (which may be useful for current limiters, etc. applied on DITARGET). Applying the same calculation with a much larger PID 124 gain results in DITARGET being approximately equal to DIL, which is preferred.

[0097] • The PID 124 must also filter the difference (DITARGET-DIL): in effect, it allows to eliminate the ripple on the error inherited from the ripple on DIL.

[0098] Note that the buck converter 100 can tolerate this unfiltered ripple. However, there are two drawbacks:

[0099] 1. It may introduce subharmonic oscillations, which requires care when generating the duty cycle.

[0100] 2. We use DIERRF at one point in time to decide / set the duty cycle. So, this is equivalent to one sampling. At this point, due to this ripple, DIERFF can differ by 1A from the average DIERFF which is equal to zero. Therefore, the inner loop can set the inductor current IL on average 1A away from DITARGET. This leads to the same problem as the case where the gain of PID 124 is 1, and we get the additional problem in the multi-phase case with asymmetrical inductors.

[0101] Therefore, the average current mode controller uses PID 124 as an integrator to avoid these two problems.

[0102] However, PID 124, acting as an integrator, reacts slowly, leading to problems responding to load transients as previously described. In summary, the integral effect of PID 124 has an unfavorable consequence: DIERRF takes longer to change, and the decision to adjust the duty cycle is delayed. This reduces the reaction time of the buck converter 100.

[0103] FIG2( a) is a schematic diagram of a digital controller 200 for a switching converter 202 according to a first embodiment of the present disclosure. The switching converter is configured to receive an input voltage Vin and generate an output voltage Vout. The switching converter 202 includes one or more power switches 204 (shown as a single switch in this example) and an energy storage element 206. The digital controller 200 is configured to receive a digital current signal DI. The digital current signal DI is a digital representation of the current flowing through the energy storage element 206. The energy storage element 206 can be, for example, an inductor, so that the current flowing through the energy storage element 206 can correspond to the inductor current IL, and the digital current signal DI can correspond to the digital inductor current DIL, as previously described with respect to FIG1( b).

[0104] The digital controller 200 is further configured to generate a filtered digital current error signal DIERRF using the digital current signal DI and a ripple cancellation signal (RIPC). The ripple cancellation signal RIPC is arranged to reduce ripple from the digital current signal DI when generating the filtered digital current error signal DIERRF.

[0105] It is to be understood that in certain embodiments, the controller 200 may partially reduce the ripple such that some ripple still exists on the DIERRF. In alternative embodiments, the controller 200 may reduce the ripple sufficiently such that the ripple is removed when generating the DIERRF.

[0106] The ripple is caused by the periodic charging and discharging of the energy storage element 206 during the switching operation of the switching converter 202. For example, for a buck converter, the ripple may be as previously described with respect to the operation of the inductor 114, and as shown by the traces 138, 140. In the example shown in FIG1(c), the "ripple" refers to the periodic variation with a triangular distribution produced by the switching operation of the buck converter 100.

[0107] The digital controller 200 is further configured to control a switching converter 202 , the control of which depends on the filtered digital current error signal DIERRF.

[0108] In certain embodiments, the switching converter 202 may be, for example, a buck converter, a boost converter, or a buck-boost converter; and the energy storage element 206 may be an inductor.

[0109] The use of the ripple cancellation signal RIPC means that the ripple can be removed when generating the filtered digital current error signal DIERRF without the need for integration (as provided by PID 124 in FIG. 1( b)). Thus, the present disclosure provides a controller that overcomes the disadvantages of known systems having a slow response due to PID 124, while still maintaining the advantages of the average current control mode.

[0110] FIG2( b) is a schematic diagram of a specific embodiment of the system shown in FIG2( a). In this embodiment, the digital controller 200 is configured to receive a digitized output voltage DVout. The digitized output voltage signal DVout is a digital representation of the output voltage Vout of the switching converter 202. The digitized output voltage signal DVout is generated using an analog-to-digital converter (ADC) 208, which receives the output voltage Vout and digitizes the output voltage Vout to provide a digitized output voltage signal DVout. The digitized output voltage signal DVout can be used to generate a digital target current signal DITARGET (not shown).

[0111] FIG2(c) is a schematic diagram of another specific embodiment of the system shown in FIG2(a). In this embodiment, the digital current signal DI is received from the digital current generating circuit 210. The digital current generating circuit 210 may, for example, include an analog-to-digital converter configured to sense the current flowing through the energy storage element 206 and digitize the sensed current to generate the digital current signal DI. In another embodiment, the digital current generating circuit 210 may include a current synthesizer.

[0112] FIG. 2( d ) is a schematic diagram of another specific embodiment of the system shown in FIG. 2( a ) , which includes the features that have been previously described with reference to FIG. 2( b ) and FIG. 2( c ) .

[0113] FIG. 3( a ) is a schematic diagram of a specific embodiment of a controller 200 that may be used in any of the embodiments described herein, according to the understanding of a skilled person and according to a second embodiment of the present disclosure.

[0114] The controller 200 includes a voltage error generation circuit 300 configured to generate a digital error signal DVERR using a digitized output voltage signal DVout and a digitized voltage reference signal DREF.

[0115] The voltage error generation circuit 300 may be configured to generate a digital error signal DVERR by subtracting the digitized output voltage signal DVout from the digitized voltage reference signal DREF, which may be expressed as follows:

[0116] DVERR = DREF - DVout (2)

[0117] The controller 200 further includes a proportional-integral-derivative circuit (PID) 302 configured to convert the digitized voltage error signal DVERR into a digital target current signal DITARGET.

[0118] The controller 200 may further include a current error generation circuit 304 configured to generate an unfiltered digital current error signal DIERR using the digital target current signal DITARGET and the digitized current signal DI.

[0119] The current error generation circuit 304 may be configured to generate an unfiltered digital current error signal DIERR by subtracting the digital target current signal DITARGET from the digital current signal DI as follows:

[0120] DIERR = DI - DITARGET (3)

[0121] The controller 200 may further include a ripple cancellation circuit 306 configured to receive the unfiltered digital current error signal DIERR and the ripple cancellation signal RIPC and generate a filtered digital current error signal DIERRF by reducing the ripple of the unfiltered digital current error signal DIERR using the ripple cancellation signal RIPC.

[0122] The ripple cancellation circuit 306 may be configured to generate a filtered digital current error signal DIERRF by adding the unfiltered digital current error signal DIERR to the ripple cancellation signal RIPC as follows:

[0123] DIERRF = DIERR + RIPC (4)

[0124] FIG. 3( b ) is a schematic diagram of a specific embodiment of a controller 200 that may be used in any of the embodiments described herein, according to the understanding of a skilled artisan and in accordance with a third embodiment of the present disclosure.

[0125] In this example, the controller 200 includes a pulse width modulation (PWM) circuit 308 configured to generate a PWM signal (denoted as "PWM" in the figure) using the filtered digital current error signal DIERRF. According to the understanding of the technician, the digital current error signal DIERRF can be received from the components described with reference to the specific embodiment shown in Figure 3 (a).

[0126] The controller 200 also includes a logic and gate driver circuit 310 configured to receive the PWM signal and generate a gate drive signal GN for each of the one or more power switches 204 using the PWM signal.

[0127] It should be understood that the single gate drive signal GN is for illustration purposes. In fact, when applied to a switching converter having a high-side FET and a low-side FET, particularly when applied to the buck converter of this example, when PWM=0, the low-side FET is turned on by the gate drive signal; and when PWM=1, the high-side FET is turned on by the gate drive signal.

[0128] Additionally, the logic and gate driver circuit may include a driver component for generating a drive signal; and a logic component for providing a break-before-make operation to handle the switching between the high side and the low side.

[0129] The PWM circuit 308 may further include a duty cycle signal generation circuit 314 configured to generate a digital signal DCA using the filtered digital current error signal DIERRF and the offset signal PDSS.

[0130] In a specific embodiment, the digital signal DCA may be as follows:

[0131] DCA= DIERRF + PDSS (5)

[0132] The PWM circuit 308 may further include a comparator 316 configured to receive the digital signal DCA and the ramp signal RAMP and output a PWM signal based on a comparison between the digital signal DCA and the ramp signal RAMP.

[0133] The comparator 316 may be configured to generate the PWM signal such that the PWM signal includes a rising edge and a falling edge, the rising edge and the falling edge depending on the digital signal DCA crossing the ramp signal RAMP.

[0134] It is to be understood that comparator 316 is functionally a comparator, but uses one or more DLLs to increase its resolution in the time domain.

[0135] For example, if the clock frequency FS is 100 MHz in the case of using direct comparators, the time resolution of the PWM will be 10 ns, because in digital, the comparator will update the PWM every 10 ns. In practice, comparator 316 follows the scheme in FIG. 5( e ): compares the digital slopes on DCA and RAMP, and uses the DLL to generate the exact time of the PWM duration (much less than 10 ns). In other embodiments, the functionality of comparator 316 can be provided by more than one comparator.

[0136] The offset signal PDSS may depend on the duty cycle D of the switching converter 202 and the maximum value RMAX of the ramp signal. For example, if the ramp signal RAMP varies from 0 to RMAX, if we want the duty cycle D, PDSS may be calculated graphically as follows:

[0137] PDSS = (1-D).RMAX (6)

[0138] It will be appreciated that equation (6) is valid in the case of Figure 5(c) where RAMP is a triangular signal. In other embodiments where RAMP has a different profile, equation (6) will be different but easily derived graphically by the skilled person.

[0139] For embodiments in which the switching converter 202 is a buck converter, equation (6) may be rewritten as follows:

[0140] PDSS = (1-Vout / Vin). RMAX (7)

[0141] Figure 4 is a schematic diagram of a specific embodiment of the system of the present disclosure according to the fourth embodiment of the present disclosure, wherein the switching converter 202 includes a buck converter. The buck converter includes an inductor 400, two power switches 402, 404 and an output capacitor 406, and uses current mode control. The logic and gate driver circuit 310 outputs two gate drive signals GP, GN, each of which is provided to one of the power switches 402, 404. The logic and gate driver circuit 310 may also include a non-overlapping system provided by a logic circuit (such as the "break before make" discussed previously). According to the understanding of the technician, the components 300, 304, 306 can be adders and / or subtractors.

[0142] FIG5(a) shows Figure 4 1 is a time graph of simulation results for one actual implementation of the system shown in . A trace 500 of the digital target current signal DITARGET; a trace 502 of the digital inductor current DIL; and a trace 504 of the unfiltered digital current error DIERR are shown.

[0143] For clarity, FIG5(a), FIG5(b), and FIG5(c) use continuous time and continuous data domains for timing diagrams.

[0144] In this example, the energy storage element 206 is an inductor, and therefore the digital current signal DI is the digitized inductor current DIL.

[0145] It is desirable that the average digital target current equals the average digital inductor current, as described in equation (1). As can be observed in FIG. 5( a ), the system is currently in this desired steady state for a period of time (denoted by T SW ), as shown by trace 506 , which shows that the average value of the digital current error DIERR is 0 A during this period of time.

[0146] It can be observed that, assuming the digital current target DITARGET is constant, the unfiltered digital current error DIERR inherits all the ripple of the digital inductor current DIL.

[0147] S1 and S2 are the slopes of this ripple and come directly from the DIL. S1, S2 can be constant, typically (Vin-Vout) / L and -Vout / L for a buck converter, where "L" represents the inductance of the inductor 206. However, the slopes S1, S2 can be non-constant. In addition, the slopes S1, S2 can be exponential, for example due to series resistance and / or inductor de-rating in the power stage. In this disclosure, we assume that S1 and S2 are always known and can be compensated. S1 can follow IMAX(1-expt(-t / T)), where T=L / R and IMAX=(VIN-VOUT) / Rswitch.

[0148] FIG5(b) shows Figure 4 0046] Another time plot of simulation results of a practical implementation of the system shown in . A trace 507 of the ripple cancellation signal RIPC is shown; and a trace 508 of the filtered digital current error DIERRF is shown.

[0149] The ripple cancellation signal RIPC has an opposite slope to the digital current error DIERR and is centered around zero.

[0150] Since the digital current error DIERR is a digital slope and its value is assumed to be completely known within the time, a ripple cancellation signal RIPC of digital value with opposite polarity but the same absolute value can be generated.

[0151] Thus, the sum of DIERR and RIPC (as provided by equation (4)) results in the mathematical removal of the ripple. Thus, due to digital processing, we can achieve ripple removal without the need for PID 124.

[0152] FIG5(c) shows Figure 4 FIG. 5( c ) is another time plot of simulation results of a practical implementation of the system shown in FIG. 5( c ) shows a trace 510 of the offset signal PDSS; a trace 512 of the ramp signal RAMP; a trace 514 of the digital signal DCA; and a trace 516 of the PWM signal. PDSS represents the predicted offset to obtain a steady-state duty cycle (DSS). The relationship between the parameters shown in FIG. 5( c ) is given by equation (5).

[0153] Note that (DIL-DITARGET) is generated instead of (DITARGET-DIL) to satisfy the final modulation scheme (see FIG5(c)). Other embodiments may generate DITARGET-DIL according to the understanding of a skilled person.

[0154] As previously discussed with reference to FIG. 1( a ), average current mode provides a gain (infinite at 0 Hz because PID 124 is an integrator) to keep average DITARGET and average DIL substantially equal.

[0155] As provided in equation (4), generating DIERRF using the ripple cancellation signal RIPC is a gain-of-one operation.

[0156] The duty cycle D (shown by the PWM signal) is generated by the intersection of the digital signal DCA and the triangular ramp RAMP. In this example, this is achieved by a double leading edge / trailing edge: the rising edge of the PWM signal (which is magnetized) is not synchronized by the clock ("trailing edge modulation") or its falling edge is synchronized by the clock ("leading edge modulation"). Instead, the rising / falling edges of the PWM are all determined by the intersection of DCA and RAMP.

[0157] According to equation (7), the digitized versions of Vin and Vout can be used to create the offset signal PDSS. An analog-to-digital converter can be used to detect the input voltage Vin, to digitize Vin, and to generate a digital signal representing Vin. DVout can be generated as described above and according to the understanding of the technician.

[0158] The duty cycle control method using the offset signal PDSS means that the desired duty cycle D can be achieved within an acceptable tolerance for practical applicability while keeping the average value of the filtered digital current error DIERRF equal to zero, thereby making the average DITARGET equal to the average DIL.

[0159] This method may be referred to as DSS (steady state duty cycle), as referenced in the document "IEEE paper An Estimative Current Mode Controller for DC-DC Converters Operating in Continuous Conduction Mode by Mehdi Ferdowsi", which uses a different approach from the present disclosure and does not use leading / trailing edge operation.

[0160] The advantages of determining the rising / falling edge by the crossing of DCA and RAMP are:

[0161] When Vout changes, this will propagate to DITARGET which changes the DCA level (after removing the ripple). It can do this until the crossing of DCA / RAMP, so the sampling effect is no longer at the beginning of the cycle as it is for the DPWM described in Figures 1(a), 1(b), and 1(c). Any sudden change in Vout will change the PWM rise time until TS before this crossing.

[0162] · Re-evaluate the PWM falling edge until DCA intersects RAMP. Thus, we get two evaluations / samples within one TSW cycle. This results in bandwidth-related improvements compared to a system using only leading-edge modulation.

[0163] FIG5(d) shows Figure 4 518 is a graph of a practical implementation of a circuit and simulation results of the phase response and gain response of the circuit using only leading edge modulation. Figure 4 The phase response of the circuit; trace 520 is the phase response of the circuit using only leading edge modulation; trace 522 is Figure 4 and trace 524 is the gain response of the circuit using only leading edge modulation. As previously described, compared to the circuit using only leading edge modulation, Figure 4 The circuit shows an improvement in bandwidth.

[0164] The following discussion involves discrete time considerations. To meet the requirements of mobile communications, the duty cycle resolution is typically about 200ps. To achieve this resolution, a 5GHz clock is typically required, which will cause the digital control to consume too much power. There are two well-known solutions:

[0165] Dithering: Dithering is applied to the DPWM as shown in Figure 1(b), and the coarse duty cycle is sampled only once per TSW. Hence, we lose the benefit of DCA / RAMP crossover re-evaluation at each TS.

[0166] Local high clock domain for fine resolution. Although it is used in US9419627B2 and US9667260B2, the requirements of mobile communications have increased by 30 times, and the required 5GHz still results in too much consumption.

[0167] Embodiments of the present disclosure use a local delay locked loop (DLL) as fine resolution. It can be used for leading and trailing edges. The DLL can support leading / trailing edge intersection calculations based on slopes. More than one DLL can be used, such as resetting and locking one DLL while another DLL is in use. In specific embodiments where more modulators (multi-phase) are required, it is preferred that one or more dedicated DLLs be used per phase.

[0168] 5( e) is a graph 526 showing the intersection of the digital signal DCA and the ramp signal RAMP, where DCA is constant (“flat”); and a graph 528 of the digital signal DCA and the ramp signal RAMP, where DCA is inclined.

[0169] In Figure 5(e), DCA and RAMP are shown in the digital discrete time domain: they vary at rate TS, which is, for example, 10ns. The following two cases are shown:

[0170] • Graph 526. "Flat" Constant DCA: The ripple caused by DIL is completely eliminated, and the average digital current target itself is constant.

[0171] • Graph 528. Sloped DCA: Although the ripple caused by the DIL has been removed, the residual ripple of the average digital current target itself will still show up on the DCA.

[0172] In both cases, at each rising step of RAMP (or falling edge when RAMP is decreasing), the equivalent slope is calculated as if in continuous time (dashed line). Then, the time intersection of the two slopes is calculated (labeled 530a in graph 526 and 530b in graph 528). At a time point labeled "IRQ", the calculation shows that in the shaded interval [TS / 2, 3TS / 2], the continuous time slopes will cross, and the crossing time is known.

[0173] In this example, the DLL divides TS = 10ns into 64 segments and programs them to the desired values. For example, at "IRQ", the slope will cross after 8.3ns: the time interval from TS / 2 to 3TS / 2. This corresponds to 3.3ns from the beginning of TS / 2. The calculation method of the DLL code is (3.3ns / 10ns) multiplied by 64, which equals 21.

[0174] FIG. 5( f ) is a schematic diagram of an example of a DLL 540 that may be implemented in any of the embodiments described herein as would be appreciated by a skilled artisan.

[0175] DLL 540 injects a 100 MHz clock into a string of, for example, 64 delayed TDs. Control block 542 LCKCTRL compares the output of string "t64" with the next edge of the 100 MHz clock that occurs 10 ns later. If t64 occurs after the next edge, this means that 64xTD exceeds 10 ns.

[0176] Block 542LCKCTRL adjusts the control signal (analog or digital control signal) to make the delay TD faster. If t64 occurs before the next 100MHz edge, it means that 64xTD is shorter than 10 nanoseconds. In this case, block 542LCKCTRL makes the delay longer through DELREG. Finally, after several 100MHZ cycles, controller 542LCKCTRL ensures that 64xTD=10ns. DLL 540 is "locked" and TD~160ps=10ns / 64.

[0177] We now see that by using the MUX and the selection code sel<5:0> to select a tap, we get a signal crossing that is a fraction N / 64 of a 10ns clock. DELREG and more generally the system can be either analog or digital.

[0178] 5(g) is a graph 544 showing the intersection of the digital signal DCA 546 and the ramp signal RAMP 548. We use sel<5:0> and IRQ to perform the intersection of DCA and RAMP.

[0179] Some examples shown herein present DCA and RAMP, whose counterparts in the continuous time domain are SCA and SRAMP, respectively.

[0180] In digital, every clock cycle (e.g. 100MHz), we check DCA and RAMP: we calculate their continuous-time equivalents SCA and SRAMP and check if they will cross in the next cycle. If this is the case, the digital controller (equivalent to Figure 4 Block 316 in (which can provide additional functionality beyond a typical comparator) calculates the crossing point in the continuous time domain and digitizes it into the code sel<5:0>. In FIG5(g), the crossing is at 1 / 4 of TS=10ns, so the code will be 16 (64 / 4) and it is sent to DLL 540.

[0181] In addition, an interrupt IRQ is sent to indicate a crossing of the DLL 540 output signal. This fine-tuning will generate a crossing 2.5ns after the IRQ (which corresponds to 1 / 4 of the full Ts=10ns period). For example, in this case, the signal "crossing" starts the PWM through the RS latch.

[0182] In a particular embodiment, the crossing can be predicted even further ahead: instead of checking if the crossing is within the next cycle, we check within the next cycle plus half or a full clock cycle, as shown in Figure 5(e). In Figure 5(e), the IRQ is marked when the crossing occurs in the shaded area, not immediately after, but delayed by half a cycle. The reason for the delay is because we allocate this time to calculate the code in digital_sel<5:0> (propagation through the gate).

[0183] Figure 6 It is shown Figure 4 6 is a graph of simulation results for a practical implementation of a system of FIG. The labeling of the traces is consistent with the labeling applied previously. A trace 600 of the inductor current IL is shown.

[0184] The digital target current DITARGET and the digitized inductor current DIL are differentiated and the ripple is removed. A fixed offset PDSS is then added to give DCA.

[0185] Every time DCA is about to cross RAMP in the interval from TS / 2 to 3TS / 2 after evaluation, we see the DLL code is adjusted (marked with number 602). It is sent to the DLL and the signal PWM edges are triggered according to the DLL code. It can be observed that due to the fine-tuning, they are not aligned with the rising / falling edges but at the middle point.

[0186] As presented in embodiments of the present disclosure, the use of management of simultaneous leading / trailing edge modulation and discrete time quantization using local DLLs can be used to improve performance and accommodate the needs of mobile communications.

[0187] FIG. 7( a ) is a graph showing a trace 700 of the digitized inductor current DIL varying with time, where the slope is formed by a straight line, and a trace 702 of the digitized inductor current DIL varying with time, where the slope is non-linear.

[0188] Trace 700 shows the ideal shape of the digitized inductor current DIL used in US9419627B2 and US9667260B2. However, in reality, the digitized inductor current DIL will not show an ideal shape, but will have a rising slope and a falling slope in each cycle, with a nonlinear distribution. Specifically, the falling slope will show exponential decay, and the rising slope will show reverse exponential growth. Please note that the timing diagram shows continuous time and continuous data to help clarify the explanation.

[0189] The curvature of the slope is caused by the resistance contribution of the switching converter 202. For example, referring to Figure 4 In the buck converter example shown in FIG. 4 , the resistance of the inductor 400 and the on-resistance of the switches 402 , 404 form a non-linear distribution.

[0190] It is to be understood that other switching converters may also exhibit a non-linear slope profile of the digital inductor current DIL (or the digital current DI when different energy storage elements are used).

[0191] In the discrete time domain (timed as TS, which is the processing cycle of the controller 200), when the inductor is coupled to the input voltage Vin via the switch 402, the digitized inductor current DIL during the magnetization phase can be expressed as follows:

[0192] isynth[n] = isynth[n-1] - A(RHS).isynth[n-1] + B. (Vin-Vout) / L (8)

[0193] When the inductor is coupled to the ground PGND via the switch 404 , the digital inductor current DIL during the demagnetization phase can be expressed as follows:

[0194] isynth[n] = isynth[n-1] – A(RLS).isynth[n-1] – B. (VOUT) / L (9)

[0195] Therefore, the variable A term is the nonlinear correction to the ideal slope contributed by the B term.

[0196]

[0197] Where R is the sum of the DC resistance (DCR) and RHS (when magnetized) of the inductor 400; and R is the sum of DCR and RLS (when demagnetized); and the above case is for the buck converter. RHS is the on-resistance of the switch 402, and RHL is the on-resistance of the switch 404. B=TS, where TS is the processing period of the controller 200.

[0198] Preferably, the ripple cancellation signal RIPC is generated such that a filtered digital current error DIERRF can be generated without ripple. Note that the index (t), such as used for RIPC (t), can be used to represent continuous time, while the index [n] is used for discrete time.

[0199] 7( b ) is a graph showing the following traces: trace 706 of the unfiltered digital current error DIERR; trace 708 of the ripple cancellation signal RIPC; and trace 710 of the filtered digital current error DIERRF which can be obtained by applying equation (4). In this example, the ripple cancellation signal RIPC uses a straight line slope.

[0200] As shown in equation (3), the digital current error signal DIERR is equal to the digital current signal DI minus the digital current target DITARGET, so that when the energy storage element 206 is an inductor, DIERR=DIL-DITARGET.

[0201] As can be observed by trace 706, DIERR inherits the nonlinear ripple from DIL. A straight-line cancellation scheme using the ripple cancellation signal RIPC allows the filtered digital current error DIERRF to be centered around 0 A. Therefore, a ripple cancellation signal RIPC having a straight-line profile can be used with embodiments of the present disclosure to provide improvements over known systems (e.g., as presented in FIG. 1( b )).

[0202] However, as shown by trace 710, the difficulty in matching ΔIS and ΔIP (not equal as marked in FIG. 7(b)) and the residual DIERRF ripple can produce the slow subharmonic oscillations that have been observed in simulations.

[0203] Therefore, further improvement can be achieved by using a different ripple cancellation signal RIPC. FIG7(c) is a graph of a negative ideal ripple cancellation signal RIPC(t) using a nonlinear slope. RIPC(t) is the inverse of the ripple on the inductor current IL, and its negative value -RIPC is represented by the trace 712 shown in FIG7(c).

[0204] Preferred properties of RIPC(t) are:

[0205] It is centered around 0 A. This is beneficial because it is desirable to remove the ripple content while keeping the average value of the digital inductor current DIL constant.

[0206] • This cancels the recursive equation DIERR(t).

[0207] It is to be understood that FIG. 7( c ) shows an ideal representation and that in an actual system an improved or preferred characteristic of the ripple cancellation signal RIPC having a straight line slope may be obtained without exactly matching the trace 712 .

[0208] 8(a) is a schematic diagram of a specific embodiment of a digital controller 200 according to the fifth embodiment of the present disclosure, the digital controller 200 including a ripple cancellation signal generator 800. It is to be understood that the ripple cancellation signal generator 800 of this embodiment can be used to generate the ripple cancellation signal RIPC of any embodiment described herein according to the understanding of a skilled person.

[0209] The ripple cancellation signal RIPC includes a rising slope having a first non-linear portion and a falling slope having a second non-linear portion in each signal period.

[0210] For example, in certain embodiments, the ripple cancellation signal RIPC may have a distribution as shown by trace 712 in FIG. 7c .

[0211] In a specific embodiment, to cancel the recursive equation DIERR(t), we can perform the calculation "back in time" and calculate the digitized inductor current DIL at the previous time step and from the starting iteration, as shown in the equation:

[0212] I(STR) = isynth[n-1] - A(RHS).isynth[n-1] + B. (Vin-Vout) / L (11)

[0213] This can then be used to generate the ripple cancellation signal RIPC.

[0214] However, it may be difficult to generate the RIPC(t) curve prior to STR because the start of the magnetization of the inductor 400 may be difficult to detect since the calculation requires evaluating the digital inductor current DIL at a previous time step.

[0215] Feasibility studies have shown that it is possible to generate the ripple cancellation signal RIPC in this way, but it requires a computing clock of more than 5 GHz, which will result in a consumption of more than 100 mA and a 30% reduction in efficiency.

[0216] FIG8( b) is a schematic diagram of a specific embodiment of the digital controller 200 of FIG8( a) according to the sixth embodiment of the present disclosure. In the present disclosure, the digital controller also includes a sampling circuit 802 configured to sample the digital current signal DI. The ripple elimination signal generator 800 is configured to generate the ripple elimination signal RIPC using the sampled digital current signal DI. It should be noted that the following description involves the energy storage element 206 as an inductor 400, so that the digital current signal DI is a digitized inductor current DIL. It is to be understood that, according to the understanding of the technician, the ripple elimination signal generator 800 of this embodiment can be used to generate the ripple elimination signal RIPC of any embodiment described herein.

[0217] 9(a) is a graph showing a trace 900 of the digitized inductor current DIL sampled using the sampling circuit 802. To generate the ripple cancellation signal RIPC(t), at each switching cycle of the switching converter, DILPEAK and DILVALLEY (as marked in FIG. 9(a)) may be extracted, and the ripple cancellation signal RIPC may be generated using the following equation:

[0218] RIPC(t) = (DILPEAK+DILVALLEY) / 2 - DIL(t) (12)

[0219] 9( b ) is a graph 902 of the gain and phase relationship using the sampling method of the present embodiment (traces 904 , 906 ) compared to the ideal ripple cancellation signal RIPC (traces 908 , 910 ), and a schematic diagram 912 of an analog circuit of a practical implementation of the system involved in the present embodiment.

[0220] The sampling technique implies the presence of local loops (for sampling / extraction) that create resonance effects and lead to subharmonic oscillations. The Simplis POP simulation shows these resonances as depicted in Figure 9(b).

[0221] Fig.10 8 is a schematic diagram of a specific embodiment of a digital controller 200 according to the seventh embodiment of the present disclosure. It should be understood that, according to the understanding of a skilled person, the ripple elimination signal generator 800 of this embodiment can be used to generate the ripple elimination signal RIPC of any embodiment described herein.

[0222] The ripple cancellation signal generator 800 is configured to receive a clock signal. The clock signal FSW is a periodic digital signal having a switching frequency equal to the switching frequency FSW of the switching converter 202. Fig.10 It is represented by "FSW".

[0223] The ripple cancellation signal generator 800 operates to generate the ripple cancellation signal RIPC using the clock signal FSW. The ripple cancellation signal generator 800 may operate to generate the ripple cancellation signal RIPC using the clock signal FSW and the PWM signal. The signal period of the ripple cancellation signal RIPC is equal to the period of the clock signal FSW.

[0224] The switching frequency of the switching converter 202 may also be controlled by a clock signal FSW. The clock signal FSW may be provided by a clock circuit (not shown).

[0225] Fig.11 is shown with Fig.10 1 is a graph of waveforms associated with the operation of a system of FIG. 100 , a trace 1100 of a clock signal FSW, a trace 1102 of a digitized current error signal DIERR, a trace 1104 of a PWM signal, and a trace 1106 of a negative value of a ripple cancellation signal RIPC are shown.

[0226] In this graph, trace 1106 is discontinuous and shows a portion of the overall ripple cancellation signal RIPC. Trace 1106 includes a non-linear portion 1108 (also labeled S2P) of the rising slope and a non-linear portion 1110 (also labeled S1P) of the falling slope of the ripple cancellation signal RIPC. It should be noted that in the graph the falling slope is increasing and the rising slope is decreasing because -RIPC is shown.

[0227] The ripple cancellation signal generator 800 may be configured to generate the ripple cancellation signal RIPC by setting the ripple cancellation signal RIPC to zero at each transition of the clock signal FSW, such as Fig.11 shown.

[0228] As previously mentioned, the sampling technique enabled by the controller 200 of FIG8( b ) results in a resonant local loop. By avoiding the sampling effect, the resonant local loop can be removed. This is achieved by setting the ripple cancellation signal RIPC to a value of 0 at each transition of the clock signal FSW, which does not depend on the unfiltered digital current error DIERR.

[0229] The clock signal FSW clock edge is used to start the non-linear slopes S1P and S2P at a value of 0. S1P and S2P can be recalculated in the same way as the recursive equation DIL (which gives DIERR). Therefore, subtracting S1P and S2P from DIERR in the segments shown results in a mathematical cancellation of the ripple on the result DIERRF. The start / stop of these segments is chosen because this is where the start / stop signal PWM is determined.

[0230] In certain embodiments, within each signal period, a rising slope of the ripple cancellation signal RIPC may include a first linear portion, and a falling slope of the ripple cancellation signal RIPC may include a second linear portion.

[0231] In a specific embodiment, the rising slope includes a first linear portion that rises linearly to zero and a first nonlinear portion that rises nonlinearly from zero. In addition, the falling slope includes a second linear portion that falls linearly to zero and a second nonlinear portion that falls nonlinearly from zero.

[0232] Fig.12 8 is a schematic diagram of a specific embodiment of a digital controller 200 according to the eighth embodiment of the present disclosure. It should be understood that, according to the understanding of a skilled person, the ripple cancellation signal generator 800 of this embodiment can be used to generate the ripple cancellation signal RIPC of any embodiment described herein.

[0233] and Fig.10 Compared with the digital controller 200 of the embodiment, the digital controller 200 of the present embodiment further includes a PWM circuit 308 and a gate driver circuit 310 whose functions are as described above. In the present embodiment, the ripple cancellation signal generator is configured to generate the ripple cancellation signal RIPC using the PWM signal.

[0234] Fig.13 is shown with Fig.12 1 is a graph of waveforms related to the operation of the system. A trace 1300 of the PWM signal; a trace 1302 of the negative value of the ripple cancellation signal RIPC; a trace 1304 of the clock signal FSW; a trace 1306 of the unfiltered digital current error DIERR; and a trace 1308 of the filtered digital current error DIERRF are shown.

[0235] In each cycle, the rising slope of the ripple cancellation signal RIPC includes a nonlinear portion 1310 (also labeled as S2P) and a linear portion 1312 (also labeled as S2S). In each cycle, the falling slope of the ripple cancellation signal RIPC includes a nonlinear portion 1314 (also labeled as S1P) and a linear portion 1316 (also labeled as S1S).

[0236] In this embodiment, the nonlinear portion S1P has an exponential decay distribution, while the nonlinear portion S2P has an inverse exponential growth distribution. It should be understood that these distributions are Fig.13 is inverted because -RIPC is shown, whereas a graph of RIPC would show the distribution described.

[0237] In a specific embodiment, the ripple cancellation signal generator 800 can be configured to generate the ripple cancellation signal RIPC using the PWM signal by alternating between the rising slope and the falling slope of the ripple cancellation signal RIPC at each transition of the PWM signal. Fig.13 The locations where the edges of the PWM signal occur are marked with numbers 1318 and 1320.

[0238] The PWM signal includes a magnetization state and a demagnetization state. The ripple cancellation signal generator 800 may be configured to generate the ripple cancellation signal RIPC by generating a falling slope when the PWM signal is in the magnetization state and generating a rising slope when the PWM signal is in the demagnetization state.

[0239] For the embodiment where the energy storage element 206 is an inductor 400 , the first linear portion S2S of the rising slope is equal to the output voltage Vout divided by the inductance L, and the second linear portion S1S of the falling slope is equal to the difference between the output voltage Vout and the input voltage Vin divided by the inductance L.

[0240] Reference Fig.13 It can be observed that in Fig.12 The embodiment presented in generates a ripple cancellation signal RIPC by combining linear and nonlinear slopes, which provides the following advantages:

[0241] • True mathematical ripple cancellation is preferred when the resulting filtered digital current error DIERRF will cross the ramp signal RAMP. In this case, it is preferred to use S1P / S2P that accurately tracks the slope of the digital inductor current DIL.

[0242] · Once the DIERRF and RAMP crossing is completed as indicated by the PWM signal, DIERRF (and DCA) is preferably avoided

[0243] Large discontinuities in characteristics: Therefore S1S / S2S are used, as they are guaranteed to be 0 the next time they are swapped to S1P / S2P, without requiring large calculations.

[0244] Fig.13 The selection of S1P, S2P, S1S, S2S is shown in FIG, along with the filtered digital current error DIERRF provided by equation (4).

[0245] Note that using the leading / trailing edge modulation scheme provides advantages. Specifically, regardless of power stage delays, the clock signal FSW DCDC-Clock rising / falling edges are at the midpoint of magnetization / demagnetization, allowing: switching between slopes at a time when no decision is made.

[0246] Fig.13 This can be further summarized using the time stamps depicted over a complete TSW cycle:

[0247] 1. At the falling edge of the FSW clock, RIPC uses S2P to compensate for the ripple on DIERR. Since DIERR itself has the same slope S2P, we have a mathematical cancellation: DIERRF is flat.

[0248] 2. The crossing is detected, and PWM is now "1". We no longer need to eliminate it completely, but we'd better suppress any sampling effects and any dependence on DIERR itself. So, we use a straight line slope S1S. It introduces a moderate jump and residual curvature.

[0249] 3. On the rising edge of the FSW clock, the nature of the leading / trailing edge makes DCA (which is just a shifted version of DIERRF)

[0250] The crossover with RAMP occurs after this mark. Also, S1S reaches 0, so RIPC is swapped to S1P, and it starts at 0. From this point on, mathematical cancellation is ensured.

[0251] 4. A crossover DIERRF / DCA occurs and PWM returns to down. Complete elimination is no longer necessary, so we use S2S, which will guarantee that 0 is used at the next swap.

[0252] 5. The leading / trailing edge modulator ensures that the crossing will occur after this mark. Switch to S2P as in mark 1.

[0253] Fig.14 is a graph showing the slope of the generated straight line, which can be used, for example, to refer to Fig.12 and Fig.13 The linear slope portion of the ripple cancellation signal RIPC of the described embodiment is shown as follows: a trace 1400 for generating a first linear slope; and a trace 1402 for generating a second linear slope.

[0254] The result DIERRF of the correction (DIERR(t)+RIPC(t)) preferably shows minimal discontinuity. This is the slope of the signal DIERRF used to generate PWM (e.g., as described with reference to FIG. 5( c)). Sudden transitions in DIERRF can lead to erroneous slope calculations, which is partially solved by using a straight line slope of the ripple cancellation signal RIPC.

[0255] For negative values ​​of the ripple cancellation signal RIPC, the slope of the S1S straight line during magnetization is equal to (Vin-Vout) / L; the slope of the S2S straight line during demagnetization is equal to -Vout / L.

[0256] It will be appreciated that the slope of the ripple cancellation signal RIPC will be provided by the equation of the negative signal multiplied by negative one.

[0257] These slopes are started and reset so that they cross 0 on an edge of the DCDC clock FSW. They are therefore independent of DIERR. It is simple to calculate their starting point at the moment these slopes are reset (on one FSW edge) to ensure a 0 crossing on another FSW edge.

[0258] Fig.15 is a schematic diagram of a specific embodiment of a digital controller 200 and a buck converter 202 according to a ninth embodiment of the present disclosure, wherein the digital controller 200 includes a ripple cancellation signal generator 800, which may correspond to any of the embodiments described herein. In this specific example, the function of the ripple cancellation generator 800 is as follows: Fig.12 The presented embodiments work as described.

[0259] In summary, the controller 200 is used to cancel the nonlinear ripple of the digital inductor current signal DIL by using the ripple cancellation signal RIPC having a linear slope that can avoid any parasitic sampling effects and a nonlinear slope that allows mathematical cancellation at critical decision moments.

[0260] Fig.16 It is shown Fig.15 Graph of simulation results for a practical implementation of the presented system. Fig.16 is the discrete time analog. It should be noted that DCA is a shifted version of DIERRF, but has the same ripple.

[0261] Shown are a trace 1600 of the digital current target DITARGET; a trace 1602 of the digital inductor current DIL; a trace 1604 of the unfiltered digital current error DIERR; a trace 1606 of the clock signal FSW; a trace 1608 of the straight line slope S1S; a trace 1610 of the straight line slope S2S; a trace 1612 of the PWM signal; a trace 1614 of the ramp signal RAMP; and a trace 1616 of the digital signal DCA.

[0262] Fig. 17(a) is a schematic diagram of a specific example of a PID 302 that can be used with any of the embodiments described herein according to the understanding of a skilled person. D, P, I are gains used for adjustment.

[0263] 17( b ) is a schematic diagram of a specific example of a ripple cancellation signal generator 800 that can be used in any embodiment described herein according to the understanding of a skilled person. The signal generator 800 in this example includes synthesizers 1700 , 1702 ; step size extraction and accumulation units 1704 , 1706 ; and a selector circuit 1708 .

[0264] S1S and S2S are synthesizers 1700 and 1702 according to Fig.14 The slope of the straight line is created using the knowledge of the digitized VIN, VOUT, and L, so that the slopes in the digital domain are S1S = (VIN - VOUT) / L and S2S = (-VOUT) / L.

[0265] S1P and S2P are cumulative slopes: they are reset to 0 until they are selected (e.g. Fig.11 They are then constructed by accumulating the step sizes from DIERR. For example, S1P Fig.13 0 to time 3 in , and then builds up using the same numerical step size as DIERR.

[0266] Various improvements and modifications may be made to the above without departing from the scope of the present disclosure.< / x> < / dil> < / ditarget>

Claims

1. A digital controller for a switching converter, the switching converter being configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising a ripple cancellation signal generator configured to generate a ripple cancellation signal, the digital controller being configured to: receiving a digitized current signal, the digitized current signal being a digital representation of current flowing through the energy storage element; generating a filtered digital current error signal using the digitized current signal and the ripple cancellation signal, the ripple cancellation signal being arranged to reduce ripple from the digitized current signal when generating the filtered digital current error signal; and controlling the switching converter, the control of the switching converter being dependent on the filtered digital current error signal; in: In each signal cycle, the ripple elimination signal includes: having an increasing slope of the first non-linear portion; and / or The second non-linear portion has a decreasing slope.

2. The digital controller according to claim 1, comprising a sampling circuit configured to sample the digital current signal, wherein: The ripple cancellation signal generator is configured to generate the ripple cancellation signal using the sampled digital current signal.

3. The digital controller according to claim 1, wherein: The ripple cancellation signal generator is configured to: receiving a clock signal, the clock signal being a periodic digital signal having a switching frequency derived from a switching frequency of the switching converter; as well as generating the ripple cancellation signal using the clock signal; in: A signal period of the ripple elimination signal is equal to a period of the clock signal.

4. The digital controller according to claim 3, wherein: The switching frequency of the switching converter is controlled by the clock signal.

5. The digital controller according to claim 3, wherein: The ripple cancellation signal generator is configured to generate the ripple cancellation signal by setting the ripple cancellation signal to zero at each transition of the clock signal.

6. A digital controller according to any preceding claim, wherein: In each signal cycle, the ripple elimination signal includes: said rising slope having a first linear portion; and / or The decreasing slope has a second linear portion.

7. A digital controller according to claim 6, wherein: The rising slope includes: the first linear portion rising linearly to zero; and The first non-linear portion rises non-linearly from zero; and The descending slope includes: the second linear portion decreasing linearly to zero; and The second non-linear part starts with a non-linear decrease from zero.

8. The digital controller according to claim 7, comprising: a pulse width modulation circuit configured to generate a PWM signal using the filtered digital current error signal; as well as a logic and gate driver circuit configured to receive the PWM signal and generate a gate drive signal for each of the one or more power switches using the PWM signal; in: The ripple cancellation signal generator is configured to generate the ripple cancellation signal using the PWM signal.

9. The digital controller according to claim 8, wherein: The ripple cancellation signal generator is configured to generate the ripple cancellation signal using the PWM signal by alternately switching between the rising slope and the falling slope at each transition of the PWM signal.

10. A digital controller according to claim 9, wherein: The PWM signal includes a magnetization state and a demagnetization state; and The ripple cancellation signal generator is configured to generate the ripple cancellation signal by generating the falling slope when the PWM signal is in the magnetization state and generating the rising slope when the PWM signal is in the demagnetization state.

11. A method of controlling a switching converter using a digital controller, the switching converter being configured to receive an input voltage and generate an output voltage, the switching converter comprising one or more power switches and an energy storage element, the digital controller comprising a ripple cancellation signal generator configured to generate a ripple cancellation signal, the method comprising: receiving a digitized current signal, the digitized current signal being a digital representation of current flowing through the energy storage element; generating a filtered digital current error signal using the digitized current signal and the ripple cancellation signal, the ripple cancellation signal being arranged to reduce ripple from the digitized current signal when generating the filtered digital current error signal; and controlling the switching converter, the control of the switching converter being dependent on the filtered digital current error signal; in: In each signal cycle, the ripple elimination signal includes: having an increasing slope of the first non-linear portion; and / or The second non-linear portion has a decreasing slope.

Images