Modulation method and system for three-level split output inverter with common bridge arm of hybrid device

Abstract

The present invention belongs to the field of power electronics technology, and the present invention relates to a hybrid device common bridge arm three-level split output inverter modulation method and system, and the method steps are: according to the reference voltage vector generated by the three-phase original modulation wave, the mapping phase angle, the modulation degree and the area number are obtained; according to the size of the modulation degree, the mapping phase angle, the modulation degree, and the switching cycle, two vector action times are obtained; two modulation waves are generated according to the area number and the two vector action times; according to the area number, the first modulation wave, the forward and reverse carrier waves, the first pulse drive signal is generated; according to the area number, the forward and reverse carrier waves, the final carrier wave is generated, and the second pulse drive signal is generated according to the second modulation wave, the forward carrier wave, the forward carrier wave of the previous cycle, and the final carrier wave; the drive signal is selected from the above two pulse drive signals according to the area number. The present invention can maximize the modulation degree, generate drive pulses respectively under different modulation degree ranges, and the output current quality is high and the total harmonic distortion rate is low.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronics, and relates to inverter modulation technology, and in particular to a modulation method and system for a hybrid device common bridge arm three-level split output inverter. Background Art

[0002] Inverters are key equipment for renewable energy power generation and electric vehicles, and they have the core function of converting direct current into alternating current. High efficiency and high current quality are the two major goals that inverter research has long pursued. In the process of achieving these goals, the use of new power switching devices and optimized topology structures (for example:) three-level or multi-level topology structures have become the main technical development directions.

[0003] At present, silicon insulated gate bipolar transistors (hereinafter referred to as: Si IGBT) and silicon carbide metal oxide semiconductor field effect transistors (hereinafter referred to as: SiC MOSFET) are two power switching devices with different characteristics, each with its own characteristics. Si IGBT has significant advantages in on-state loss due to the conductivity modulation effect. SiC MOSFET has excellent performance in switching loss due to the use of new silicon carbide materials. In the hybrid device shared bridge arm three-level split output inverter, SiIGBT is used as the common bridge arm, and SiC MOSFET is used in the three-phase split output bridge arm, which can fully utilize the performance advantages of two different devices. This design allows the A, B, and C three-phase outputs to share the IGBT bridge arm, while improving efficiency and current quality, but its modulation method will be more complicated.

[0004] Traditional modulation methods include carrier comparison modulation method and space voltage vector modulation method. The carrier comparison modulation method is simple to implement. The drive pulse is obtained by directly comparing the modulation wave with the carrier. However, the linear modulation degree of this method cannot be maximized. It is necessary to continue to improve the linear modulation degree based on the traditional carrier comparison method. From the perspective of vector, the space voltage vector modulation method can maximize the linear modulation degree by fitting the reference vector of the basic vector of the inverter in segments, but it requires complex calculations and precise control strategies, which are complex and costly to implement, and have poor stability. The above two traditional modulation methods are applicable to traditional three-level inverters (containing 12 power switching devices). For the new common bridge arm three-level split output inverter (containing 10 power switching devices), since the number of power devices it contains is different from that of the traditional three-level inverter, the traditional carrier comparison modulation method and the space voltage vector modulation method are no longer applicable. It is urgent to propose a new modulation method to maximize the linear modulation degree and output high-quality three-phase current waveforms. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a hybrid device shared bridge arm three-level split output inverter modulation method and system, which can maximize the modulation index, generate drive pulses respectively under different modulation index ranges, have high output current quality and low total harmonic distortion rate.

[0006] In a first aspect, the present invention provides a modulation method for a hybrid device common bridge arm three-level split output inverter, the specific steps of which are:

[0007] Reference voltage generation step: generating a reference voltage vector according to the three-phase original modulation wave;

[0008] The steps for judging the large triangle area are as follows: Calculate the phase angle of the reference voltage based on the reference voltage vector, and add the phase angle of the reference voltage to the The actual phase angle is obtained by the offset, and the large triangle area number and the mapping phase angle are generated according to the actual phase angle;

[0009] Small triangle or trapezoidal area judgment steps: calculate the amplitude of the reference voltage according to the reference voltage vector, the amplitude of the reference voltage is the modulation degree, and generate the small triangle or trapezoidal area number according to the size of the modulation degree;

[0010] Time calculation step: calculate the first vector action time and the second vector action time according to the magnitude of the modulation index, the mapping phase angle, the modulation index, and the switching period;

[0011] The first modulation wave generating step: generating the first modulation wave according to the large triangle area number and the first vector action time;

[0012] The second modulation wave generating step: generating the second modulation wave according to the large triangle area number and the second vector action time;

[0013] The first pulse generating step: generating a first pulse driving signal according to the first modulation wave, the forward carrier wave and the reverse carrier wave;

[0014] The second pulse generating step: generating a final carrier wave according to the large triangle area number, the forward carrier wave, and the reverse carrier wave, and generating a second pulse driving signal according to the second modulation wave, the forward carrier wave, the forward carrier wave of the previous cycle, and the final carrier wave;

[0015] Pulse selection step: selecting a driving signal from the first pulse driving signal and the second pulse driving signal according to the small triangle or trapezoidal area number.

[0016] In some embodiments, in the reference voltage generation step, the method of generating the reference voltage vector according to the three-phase original modulation wave is: the original modulation wave of phase A u a Add B phase original modulation wave u b of After times, add the original adjustment wave of phase C u c of times the reference voltage vector U ref ,in, j Is an imaginary unit.

[0017] In some embodiments, in the large triangle area determination, the method of generating the large triangle area number and mapping the phase angle according to the actual phase angle is:

[0018] Control signal generation steps: actual phase angle divided by Then round up to get the control signal;

[0019] The steps of generating the area number and the mapped phase angle are as follows: when the control signal is 1, the area number of the large triangle is 4, and the actual phase angle is the mapped phase angle; when the control signal is 2, the area number of the large triangle is 5, and the actual phase angle is minus is the mapping phase angle; when the control signal is 3, the large triangle area number is 6, and the actual phase angle is reduced is the mapping phase angle; when the control signal is 4, the large triangle area number is 1, and the actual phase angle is reduced is the mapping phase angle; when the control signal is 5, the large triangle area number is 2, and the actual phase angle is reduced is the mapping phase angle; when the control signal is 6, the large triangle area number is 3, and the actual phase angle is reduced is the mapping phase angle.

[0020] In some embodiments, in the small triangle or trapezoidal area judgment step, the method of generating the small triangle or trapezoidal area number according to the size of the modulation degree is: when the modulation degree ≥ the set threshold, the small triangle or trapezoidal area number is 2; when the modulation degree < the set threshold, the small triangle or trapezoidal area number is 1.

[0021] In some embodiments, the time calculation step further comprises:

[0022] The first time calculation step: when the modulation index is less than the set threshold, the first vector action time is calculated according to the mapping phase angle, the modulation index, and the switching cycle; the first vector action time includes the action time , Action time , Action time , respectively expressed as:

[0023]

[0024]

[0025]

[0026] In the formula, is the switching cycle, To adjust the system, is the mapping phase angle;

[0027] The second time calculation step: when the modulation index is greater than or equal to the set threshold, the second vector action time is calculated according to the mapping phase angle, the modulation index, and the switching cycle; the second vector action time includes the action time , Action time , Action time , Action time , respectively expressed as:

[0028]

[0029]

[0030]

[0031] .

[0032] In some embodiments, in the first modulation wave generating step, the first modulation wave includes a modulation wave , Modulation Wave , Modulation Wave , Modulation Wave , Modulation Wave , the method of generating the first modulation wave according to the large triangle area number and the first vector action time is:

[0033] When the big triangle area number is 1, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave for , modulation wave is 0; when the large triangle area number is 2, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0; when the large triangle area number is 3, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1, the modulation wave for ; When the large triangle area number is 4, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave for , modulation wave is 1; when the large triangle area number is 5, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1; when the large triangle area number is 6, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0, the modulation wave for .

[0034] In some embodiments, in the first pulse generating step, the first pulse driving signal includes a driving signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , the method for generating the first pulse driving signal according to the first modulation wave, the forward carrier wave, and the reverse carrier wave is:

[0035] According to the modulation wave With reverse carrier u c2 The comparison result generates a driving signal and drive signal , according to the modulation wave With reverse carrier u c2 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal .

[0036] In some embodiments, in the second modulation wave generating step, the second modulation wave includes a modulation wave , Modulation Wave , Modulation Wave , Modulation Wave , Modulation Wave , the method of generating the second modulation wave according to the large triangle area number and the second vector action time is:

[0037] When the big triangle area number is 1, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave for , modulation wave is 0; when the large triangle area number is 2, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0; when the large triangle area number is 3, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1, the modulation wave for ; When the large triangle area number is 4, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave for , modulation wave is 1; when the large triangle area number is 5, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1; when the large triangle area number is 6, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0, the modulation wave for .

[0038] In some embodiments, in the second pulse generating step, the second pulse driving signal includes a driving signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , the method for generating the second pulse driving signal according to the second modulation wave, the positive carrier, the positive carrier of the previous cycle, and the final carrier is:

[0039] According to the difference between the positive carrier and the positive carrier of the previous cycle, the modulation wave With positive carrier u c1 The size comparison results of the modulation wave With positive carrier u c1 The comparison result generates a driving signal , drive signal , drive signal , drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal .

[0040] In a second aspect, the present invention provides a hybrid device common bridge arm three-level split output inverter modulation system, which is used to implement the hybrid device common bridge arm three-level split output inverter modulation method according to the first aspect of the present invention, comprising:

[0041] A reference voltage generation module generates a reference voltage vector according to the three-phase original modulation wave;

[0042] The large triangle area judgment module calculates the phase angle of the reference voltage based on the reference voltage vector. The phase angle of the reference voltage is added to The actual phase angle is obtained by the offset, and the large triangle area number and the mapping phase angle are generated according to the actual phase angle;

[0043] A small triangle or trapezoidal area judgment module calculates the amplitude of the reference voltage according to the reference voltage vector, the amplitude of the reference voltage is the modulation degree, and generates a small triangle or trapezoidal area number according to the size of the modulation degree;

[0044] A time calculation module, which calculates the first vector action time and the second vector action time according to the magnitude of the modulation index, the mapping phase angle, the modulation index, and the switching cycle;

[0045] A first modulation wave generating module, generating a first modulation wave according to the large triangle area number and the first vector action time;

[0046] A second modulation wave generating module generates a second modulation wave according to the large triangle area number and the second vector action time;

[0047] A first pulse generating module generates a first pulse driving signal according to a first modulation wave, a forward carrier wave, and a reverse carrier wave;

[0048] The second pulse generating module generates a final carrier according to the large triangle area number, the forward carrier and the reverse carrier, and generates a second pulse driving signal according to the second modulation wave, the forward carrier, the forward carrier of the previous cycle and the final carrier;

[0049] The pulse selection module selects a driving signal from the first pulse driving signal and the second pulse driving signal according to the small triangle or trapezoidal area number.

[0050] Compared with the prior art, the advantages and positive effects of the present invention are:

[0051] (1) The hybrid device shared bridge arm three-level split output inverter modulation method and system provided by the present invention, based on the space vector pulse width modulation (SVPWM) technology, generates a reference voltage vector according to the three-phase original modulation wave, generates a mapping phase angle and a modulation index, i.e., the region number where the reference voltage is located, according to the phase angle and amplitude obtained from the reference voltage vector, and subdivides the modulation region into a large triangle region and a small triangle or trapezoidal region, thereby improving the voltage utilization rate and control accuracy. Within different modulation index ranges, different vector action times are calculated based on the modulation index, the mapping phase angle, and the switching cycle, and the large triangle region number and the different vector action times are used to generate modulation waves and drive signals respectively, and the drive signal is selected from the first pulse drive signal and the second pulse drive signal according to the small triangle or trapezoidal region number to achieve precise control. At the same time, the drive signal is generated by alternating the use of forward and reverse carriers, thereby improving the dynamic response capability. The hybrid device shared bridge arm three-level split output inverter modulation method and system provided by the present invention can maximize the modulation index, and can output high-quality current waveforms within the modulation index range of 0~1.15, with low total harmonic distortion.

[0052] (2) The hybrid device common bridge arm three-level split output inverter modulation method and system provided by the present invention fully utilizes the advantages of different devices in the hybrid device common bridge arm three-level split output inverter to modulate the inverter, thereby improving the inverter modulation efficiency.

[0053] (3) The hybrid device shared bridge arm three-level split output inverter modulation method and system provided by the present invention reduces the number of power switching devices and drive circuits, and reduces the modulation complexity and cost, because the hybrid device shared bridge arm three-level split output inverter three-phase output shares the IGBT bridge arm. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A circuit diagram of a three-level split output inverter with a common bridge arm for hybrid devices according to an embodiment of the present invention;

[0055] Figure 2 It is a flow chart of a modulation method of a three-level split output inverter with a common bridge arm of a hybrid device according to an embodiment of the present invention;

[0056] Figure 3 This is a schematic diagram of a reference voltage generation link according to an embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram of the large triangle area determination process according to an embodiment of the present invention;

[0058] Figure 5 This is a schematic diagram of the small triangle or trapezoidal area determination process according to an embodiment of the present invention;

[0059] Figure 6This is a schematic diagram of the first vector action time calculation link in an embodiment of the present invention;

[0060] Figure 7 This is a schematic diagram of the second vector action time calculation link in an embodiment of the present invention;

[0061] Figure 8 This is a schematic diagram of the first modulation wave generation link in an embodiment of the present invention;

[0062] Fig. 9 This is a schematic diagram of the second modulation wave generating link in an embodiment of the present invention;

[0063] Fig.10 This is a schematic diagram of the first pulse generation link in an embodiment of the present invention;

[0064] Fig.11 This is a schematic diagram of the second pulse generating link in an embodiment of the present invention;

[0065] Fig.12 This is a schematic diagram of the pulse selection link described in an embodiment of the present invention;

[0066] Fig.13 This is a structural block diagram of a three-level split output inverter modulation system with a hybrid device sharing a bridge arm according to an embodiment of the present invention;

[0067] Fig.14 A schematic diagram of a three-phase output current waveform when the modulation method and system modulation of a three-level split output inverter with a common bridge arm of a hybrid device according to an embodiment of the present invention is used and the modulation index m=0.46 is reduced;

[0068] Fig.15 The figure is a schematic diagram of the three-phase output current waveform when the modulation method and system of the three-level split output inverter with a common bridge arm of the hybrid device described in the embodiment of the present invention is down-regulated to m=0.96.

[0069] In the figure, 1. reference voltage generating module, 2. large triangle area judging module, 3. small triangle or trapezoidal area judging module, 41. first time calculating module, 42. second time calculating module, 5. first modulation wave generating module, 6. second modulation wave generating module, 7. first pulse generating module, 8. second pulse generating module, 9. pulse selecting module. DETAILED DESCRIPTION

[0070] The present invention will be described in detail below by way of exemplary embodiments in conjunction with the accompanying drawings. However, it should be understood that, without further description, elements, structures and features in one embodiment may also be beneficially combined in other embodiments.

[0071] Figure 1The main topology circuit of the hybrid device shared bridge arm three-level split output inverter shown in the figure, wherein: V dc is a DC voltage source, C 1 , C 2 is the DC bus capacitance, S 1 ~ S 4 For IGBTs with a shared bridge arm, S 5 ~ S 10 For SiC MOSFET power switching devices, D a1 , D a2 , D b1 , D b2 , D c1 , D c2 For silicon carbide Schottky diode, L a1 , L a2 , L b1 , L b2 , L c1 , L c2 For the isolation inductor, L a , L b , L c is the load inductance, R a , R b , R c is the load resistance.

[0072] Continue to see Figure 1 , DC voltage source V DC Provide the overall voltage for the DC bus, and the DC bus capacitors are connected in series from top to bottom. C 1 , DC bus capacitor C 2 , C 1 and C 2 Connect at point O.S 1 The collector is connected to the positive pole of the DC bus at point P. S 1 Emitter and S 2 The collector is connected and intersects at point A; S 2 Emitter and S 3 The collector is connected and intersects at point O; S 3 Emitter and S 4 Collector connection, intersecting at point B, S 4 The emitter is connected to the negative pole N of the DC bus.

[0073] Continue to see Figure 1 , S 5 The drain terminal is connected to point A. S 5 Source terminal and D a2 Cathode terminal connection; S 6 Drain terminal and D a1 Anode terminal connection, S 6 The source terminal is connected to point B. S 7 The drain terminal is connected to point A. S 7 Source terminal and D b2 Cathode terminal connection; S 8 Drain terminal and D b1 Anode terminal connection, S 8 The source terminal is connected to point B; S 9 The drain terminal is connected to point A. S 9 Source terminal and D c2 Cathode terminal connection; S 10 Drain terminal and D c1 Anode terminal connection, S 10 The source terminal is connected to point B.

[0074] Continue to see Figure 1 , L a1 and La2 Connect in parallel S 5 Source terminal and D a1 The anode end and the common end on the other side are connected in series L a and R a ; L b1 and L b2 Connect in parallel S 7 Source terminal and D b1 The anode end and the common end on the other side are connected in series L b and R b ; L c1 and L c2 Connect in parallel S 9 Source terminal and D c1 The anode end and the common end on the other side are connected in series L c and R c Point N is the load resistance R a , R b , R c The neutral point.

[0075] For the above hybrid device shared bridge arm three-level split output inverter, the present invention provides a hybrid device shared bridge arm three-level split output inverter modulation method and system, which generates drive pulses in different modulation ranges, has high output current quality and low total harmonic distortion. The present invention can maximize the modulation degree and output high-quality current waveforms within the modulation degree range of 0~1.15.

[0076] The modulation method and system of the hybrid device common bridge arm three-level split output inverter of the present invention are described in detail below in conjunction with the accompanying drawings and embodiments.

[0077] See also Figure 2 The first aspect of the present invention provides a hybrid device common bridge arm three-level split output inverter modulation method, the specific steps of which are:

[0078] S1. Reference voltage generation step: Generate a reference voltage vector according to the three-phase original modulation wave.

[0079] Specifically, see Figure 3 The method of generating the reference voltage vector according to the three-phase original modulation wave is as follows: the original modulation wave of phase A u a Add B phase original modulation wave u b of After times, add the original adjustment wave of phase C u c of times the reference voltage vector U ref ,in, j Is an imaginary unit.

[0080] S2. Steps for judging the large triangle area: Calculate the phase angle of the reference voltage based on the reference voltage vector. Add the phase angle of the reference voltage to the The actual phase angle is obtained by adjusting the offset, and the large triangle area number and mapping phase angle are generated according to the actual phase angle.

[0081] Specifically, see Figure 4 , the phase angle of the reference voltage is calculated by the Complex-to-Angle module CA according to the reference voltage vector. The Complex-to-Angle module CA is introduced, and the Complex-to-Angle module CA directly decomposes the reference voltage vector into the phase angle, avoiding the error accumulation of redundant calculation.

[0082] Specifically, see Figure 4 , the method to generate the large triangle area number and the mapping phase angle according to the actual phase angle is:

[0083] S21, control signal generation step: actual phase angle divided by Then round up to get the control signal;

[0084] S22, area number and mapping phase angle generation step: when the control signal is 1, the large triangle area number N is 4, and the actual phase angle is the mapping phase angle ; When the control signal is 2, the large triangle area number N is 5, and the actual phase angle decreases The phase angle is mapped ; When the control signal is 3, the large triangle area number N is 6, and the actual phase angle is reduced The phase angle is mapped ; When the control signal is 4, the large triangle area number N is 1, and the actual phase angle decreases The phase angle is mapped ; When the control signal is 5, the large triangle area number N is 2, and the actual phase angle decreases The phase angle is mapped ; When the control signal is 6, the large triangle area number N is 3, and the actual phase angle is reduced The phase angle is mapped .

[0085] Specifically, in step S21, rounding up is performed by the Quantizer module Q.

[0086] S3, small triangle or trapezoidal area judgment step: calculate the amplitude of the reference voltage according to the reference voltage vector, the amplitude of the reference voltage is the modulation degree, and generate the small triangle or trapezoidal area number according to the size of the modulation degree.

[0087] Specifically, see Figure 5 , the amplitude of the reference voltage is calculated by the Complex-to-Magnitude module CM according to the reference voltage vector. The Complex-to-Magnitude module CM is introduced, and the Complex-to-Magnitude module CM directly decomposes the reference voltage vector into amplitudes, avoiding the error accumulation of redundant calculations.

[0088] Specifically, see Figure 5 The method of generating the small triangle or trapezoid area number according to the size of the modulation index is: when the modulation index ≥ the set threshold, the small triangle or trapezoid area number is 2; when the modulation index < the set threshold, the small triangle or trapezoid area number is 1.

[0089] S4, time calculation step: calculate the first vector action time and the second vector action time according to the magnitude of the modulation index, the mapping phase angle, the modulation index, and the switching period.

[0090] Specifically, the time step further includes:

[0091] S41, first time calculation step: see Figure 6 When the modulation index is less than the set threshold, the first vector action time is calculated according to the mapping phase angle, modulation index, and switching cycle; the first vector action time includes the action time , Action time , Action time , respectively expressed as:

[0092]

[0093]

[0094]

[0095] In the formula, is the switching cycle, To adjust the system, is the mapping phase angle.

[0096] S42, first time calculation step: see Figure 7 When the modulation index is greater than or equal to the set threshold, the second vector action time is calculated according to the mapping phase angle, modulation index, and switching cycle; the second vector action time includes the action time , Action time , Action time , Action time , respectively expressed as:

[0097]

[0098]

[0099]

[0100] .

[0101] S5, first modulation wave generating step: generating the first modulation wave according to the large triangle area number and the first vector action time.

[0102] Specifically, see Figure 8 , the first modulation wave includes a modulation wave , Modulation Wave , Modulation Wave , Modulation Wave , Modulation Wave , the method of generating the first modulation wave according to the large triangle area number and the first vector action time is:

[0103] When the triangle area number N is 1, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave for , modulation wave is 0;

[0104] When the triangle area number N is 2, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0;

[0105] When the triangle area number N is 3, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1, the modulation wave for ;

[0106] When the triangle area number N is 4, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave for , modulation wave is 1;

[0107] When the triangle area number N is 5, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1;

[0108] When the triangle area number N is 6, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0, the modulation wave for .

[0109] S6, second modulation wave generating step: generating a second modulation wave according to the large triangle area number and the second vector action time.

[0110] Specifically, see Fig. 9 , the second modulation wave includes a modulation wave , Modulation Wave , Modulation Wave , Modulation Wave , Modulation Wave , the method of generating the second modulation wave according to the large triangle area number and the second vector action time is:

[0111] When the triangle area number N is 1, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave for , modulation wave is 0;

[0112] When the triangle area number N is 2, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0;

[0113] When the triangle area number N is 3, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1, the modulation wave for ;

[0114] When the triangle area number N is 4, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave for , modulation wave is 1;

[0115] When the triangle area number N is 5, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1;

[0116] When the triangle area number N is 6, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0, the modulation wave for .

[0117] S7, first pulse generating step: generating a first pulse driving signal according to the first modulation wave, the forward carrier wave and the reverse carrier wave.

[0118] Specifically, see Fig.10 , the first pulse drive signal includes a drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal The method for generating the first pulse driving signal according to the first modulation wave, the forward carrier wave and the reverse carrier wave is as follows: With reverse carrier u c2 The comparison result generates a driving signal and drive signal , according to the modulation wave With reverse carrier u c2 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal .

[0119] Specifically, in some embodiments, continue to see Fig.10 , according to the modulation wave With reverse carrier u c2 The comparison result generates a driving signal and drive signal The method is: when the modulation wave ≥Reverse carrier u c2 When the drive signal High level, driving signal is low level; when the modulation wave <Reverse Carrier u c2 When the drive signal is low level, driving signal is high level.

[0120] Specifically, in some embodiments, continue to see Fig.10 , according to the modulation wave With reverse carrier u c2 The comparison result generates a driving signal and drive signal The method is: when the modulation wave ≥Reverse carrier u c2 When the drive signal High level, driving signal is low level; when the modulation wave <Reverse Carrier u c2 When the drive signal is low level, driving signal is high level.

[0121] Specifically, in some embodiments, continue to see Fig.10 , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal The method is: when the modulation wave ≥Forward carrier u c1 When the drive signal High level, driving signal is low level; when the modulation wave <Forward Carrier u c1 When the drive signal is low level, driving signal is high level.

[0122] Specifically, in some embodiments, continue to see Fig.10 , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal The method is: when the modulation wave ≥Forward carrier u c1 When the drive signal High level, driving signal is low level; when the modulation wave <Forward Carrier u c1 When the drive signal is low level, driving signal is high level.

[0123] Specifically, in some embodiments, continue to see Fig.10 , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal The method is: when the modulation wave ≥Forward carrier u c1 When the drive signal High level, driving signal is low level; when the modulation wave <Forward Carrier u c1 When the drive signal is low level, driving signal is high level.

[0124] S8, second pulse generating step: generating a final carrier according to the large triangle area number, the forward carrier and the reverse carrier, generating a second pulse driving signal according to the second modulation wave, the forward carrier, the forward carrier of the previous cycle and the final carrier.

[0125] Specifically, see Fig.11 The method of generating the final carrier according to the large triangle area number, forward carrier and reverse carrier is: when the large triangle area number N is 1, 3, or 5, the final carrier is the reverse carrier; when the large triangle area number N is 2, 4, or 6, the final carrier is the forward carrier.

[0126] Specifically, see Fig.11 , the second pulse drive signal includes a drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal The method of generating the second pulse drive signal according to the second modulation wave, the positive carrier wave, the positive carrier wave of the previous cycle, and the final carrier wave is as follows: according to the difference between the positive carrier wave and the positive carrier wave of the previous cycle, the modulation wave With positive carrier u c1 The size comparison results of the modulation wave With positive carrier u c1 The comparison result generates a driving signal , drive signal , drive signal , drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal .

[0127] Specifically, in some embodiments, continue to see Fig.11 , according to the difference between the positive carrier and the positive carrier of the previous cycle, the modulation wave With positive carrier u c1 The size comparison results of the modulation wave With positive carrier u c1 The comparison result generates a driving signal , drive signal , drive signal , drive signal The method is:

[0128] When (positive carrier u c1 - Positive carrier wave of the previous cycle u c1—M )≥0 and the modulation wave ≥Forward carrier u c1 And the modulation wave <Forward Carrier u c1 When the drive signal is low level, driving signal is high level; under other conditions, the driving signal is low level, driving signal is high level;

[0129] When (positive carrier u c1 - Positive carrier wave of the previous cycle u c1—M )<0 and the modulation wave ≥Forward carrier uc1 And the modulation wave <Forward Carrier u c1 When the drive signal High level, driving signal is low level; under other conditions, the driving signal is low level, driving signal is high level.

[0130] Specifically, in some embodiments, continue to see Fig.11 , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal The method is: when the modulation wave ≥ Final Carrier u m When the drive signal High level, driving signal is low level; when the modulation wave < Final Carrier u m When the drive signal is low level, driving signal is high level.

[0131] Specifically, in some embodiments, continue to see Fig.11 , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal The method is: when the modulation wave ≥ Final Carrier u m When the drive signal High level, driving signal is low level; when the modulation wave < Final Carrier u m When the drive signal is low level, driving signal is high level.

[0132] Specifically, in some embodiments, continue to see Fig.11 , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal The method is: when the modulation wave ≥ Final Carrier u m When the drive signal High level, driving signal is low level; when the modulation wave < Final Carrier u m When the drive signal is low level, driving signal is high level.

[0133] Specifically, the positive carrier wave of the previous cycle is obtained from the storage module M.

[0134] S9, pulse selection step: select a driving signal from the first pulse driving signal and the second pulse driving signal according to the small triangle or trapezoidal area number.

[0135] Specifically, see Fig.12 , the method of selecting a driving signal from the first pulse driving signal and the second pulse driving signal according to the small triangle or trapezoidal area number is:

[0136] When the small triangle or trapezoid area number n>1, the drive signal To drive signal For the driving signal To drive signal ; When the small triangle or trapezoid area number n≤1, the drive signal To drive signal For the driving signal To drive signal .

[0137] In the large triangle area judgment link, the first modulation wave generation link, the second modulation wave generation link, and the second pulse generation link, different input signals are selected for output according to the control signal through the Multiport Switch module MS. The Multiport Switch module MS realizes the dynamic selection and output of the input signal through the allocation of the control signal. Each control signal corresponds to a specific input mode, ensuring that the appropriate input signal can be adapted in different areas or conditions, ensuring the accuracy and real-time performance of the signal selection.

[0138] In the small triangle or trapezoidal area judgment link, the second pulse generation link and the pulse selection link, the selection switch SK is used to judge and select the signal. The selection switch SK is divided into an input side and an output side. In the input side, there are three signal inputs, the terminals "+" and "-" are signal input terminals, the terminal I is the comparison signal input terminal, and the terminal O is the signal output terminal. When the signal of the comparison signal terminal I is greater than or equal to 0.5, the O terminal outputs the signal received by the "+" terminal; when the comparison signal received by the I terminal is less than 0.5, the O terminal outputs the signal received by the "-" terminal.

[0139] See also Fig.13 The second aspect of the present invention provides a hybrid device common bridge arm three-level split output inverter modulation system, which is used to implement the hybrid device common bridge arm three-level split output inverter modulation method described in the first aspect of the present invention, including:

[0140] A reference voltage generating module 1 generates a reference voltage vector according to the three-phase original modulation wave;

[0141] The large triangle area judgment module 2 calculates the phase angle of the reference voltage according to the reference voltage vector, and the phase angle of the reference voltage is added The actual phase angle is obtained by the offset, and the large triangle area number and the mapping phase angle are generated according to the actual phase angle;

[0142] A small triangle or trapezoidal area judgment module 3 calculates the amplitude of the reference voltage according to the reference voltage vector, the amplitude of the reference voltage is the modulation degree, and generates a small triangle or trapezoidal area number according to the size of the modulation degree;

[0143] A time calculation module 4 calculates the first vector action time and the second vector action time according to the magnitude of the modulation degree, the mapping phase angle, the modulation degree, and the switching period;

[0144] A first modulation wave generating module 5 generates a first modulation wave according to the large triangle area number and the first vector action time;

[0145] A second modulation wave generating module 6 generates a second modulation wave according to the large triangle area number and the second vector action time;

[0146] A first pulse generating module 7, generating a first pulse driving signal according to a first modulation wave, a forward carrier wave and a reverse carrier wave;

[0147] The second pulse generating module 8 generates a final carrier according to the large triangle area number, the forward carrier and the reverse carrier, and generates a second pulse driving signal according to the second modulation wave, the forward carrier, the forward carrier of the previous cycle and the final carrier;

[0148] The pulse selection module 9 selects a driving signal from the first pulse driving signal and the second pulse driving signal according to the small triangle or trapezoidal area number.

[0149] In some embodiments, see Fig.13 , the time calculation module includes:

[0150] A first time calculation module 41, when the modulation index is less than a set threshold, calculates the first vector action time according to the mapping phase angle, the modulation index, and the switching period;

[0151] The second time calculation module 42 calculates the second vector action time according to the mapping phase angle, the modulation degree and the switching period when the modulation degree is greater than or equal to the set threshold.

[0152] In order to verify the effectiveness of the hybrid device shared bridge arm three-level split output inverter modulation method and system of the present invention, simulation verification is carried out in MATLAB / Simulink. The DC bus voltage is 600V, the load resistance is 10Ω, and the load inductance is 2mH. When the modulation index m=0.46 and the modulation index m=0.96, the inverter three-phase output current waveforms under the modulation of the hybrid device shared bridge arm three-level split output inverter modulation method and system of the present invention are as follows: Fig.13 and Fig.14 As shown. Through Fourier analysis, it can be seen that when the modulation index m=0.46, the total harmonic distortion rates of the three-phase currents of A, B, and C are 1.67%, 1.69%, and 1.67% respectively; when the modulation index m=0.96, the total harmonic distortion rates of the three-phase currents of A, B, and C are 1.15%, 1.15%, and 1.15% respectively. The three-phase output current distortion rate is low, and the output current waveform quality is high. It can effectively illustrate the effectiveness of the hybrid device shared bridge arm three-level split output inverter modulation method and system proposed in the present invention.

[0153] It should be noted that the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the hybrid device common bridge arm three-level split output inverter modulation method and system according to multiple embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of an instruction, and the module, a program segment or a part of an instruction contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0154] The above embodiments are used to explain the present invention rather than to limit the present invention. Any modification and change made to the present invention within the spirit of the present invention and the protection scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A modulation method for a three-level split output inverter with a hybrid device sharing a bridge arm, characterized in that: The specific steps are: Reference voltage generation step: generating a reference voltage vector according to the three-phase original modulation wave; The steps for judging the large triangle area are as follows: Calculate the phase angle of the reference voltage based on the reference voltage vector, and add the phase angle of the reference voltage to the The actual phase angle is obtained by using the offset of , and the large triangle area number and the mapped phase angle mapped back to the first large sector are generated according to the actual phase angle; Small triangle or trapezoidal area judgment steps: calculate the amplitude of the reference voltage according to the reference voltage vector, the amplitude of the reference voltage is the modulation degree, and generate the small triangle or trapezoidal area number according to the size of the modulation degree; Time calculation step: calculate the first vector action time and the second vector action time according to the magnitude of the modulation index, the mapping phase angle, the modulation index, and the switching period; The first modulation wave generation step: generating a first modulation wave according to the large triangle area number and the first vector action time, wherein the first modulation wave includes a modulation wave , Modulation Wave , Modulation Wave , Modulation Wave , Modulation Wave ; The second modulation wave generating step: generating a second modulation wave according to the large triangle area number and the second vector action time, wherein the second modulation wave includes a modulation wave , Modulation Wave , Modulation Wave , Modulation Wave , Modulation Wave ; The first pulse generating step: generating a first pulse driving signal according to the first modulation wave, the forward carrier wave and the reverse carrier wave; the first pulse driving signal includes a driving signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal The method for generating the first pulse driving signal according to the first modulation wave, the forward carrier wave and the reverse carrier wave is as follows: With reverse carrier u c2 The comparison result generates a driving signal and drive signal , according to the modulation wave With reverse carrier u c2 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal , according to the modulation wave With positive carrier u c1 The comparison result generates a driving signal and drive signal ; The second pulse generating step: generating a final carrier according to the large triangle area number, the forward carrier, and the reverse carrier. When the large triangle area number N is 1, 3, or 5, the final carrier is the reverse carrier; when the large triangle area number N is 2, 4, or 6, the final carrier is the forward carrier; generating a second pulse driving signal according to the second modulation wave, the forward carrier, the forward carrier of the previous cycle, and the final carrier. The second pulse driving signal includes a driving signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal , drive signal ; The method for generating the second pulse drive signal according to the second modulation wave, the positive carrier, the positive carrier of the previous cycle, and the final carrier is: according to the difference between the positive carrier and the positive carrier of the previous cycle, the modulation wave With positive carrier u c1 The size comparison results of the modulation wave With positive carrier u c1 The comparison result generates a driving signal , drive signal , drive signal , drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal , according to the modulation wave With the final carrier u m The comparison result generates a driving signal and drive signal ; Pulse selection step: selecting a driving signal from the first pulse driving signal and the second pulse driving signal according to the small triangle or trapezoidal area number.

2. The hybrid device shared bridge arm three-level split output inverter modulation method according to claim 1, characterized in that: In the reference voltage generation step, the method for generating the reference voltage vector according to the three-phase original modulation wave is: the original modulation wave of phase A u a Add B phase original modulation wave u b of After times, add the original adjustment wave of phase C u c of times the reference voltage vector U ref ,in, j Is an imaginary unit.

3. The hybrid device shared bridge arm three-level split output inverter modulation method according to claim 1, characterized in that: In the large triangle area judgment, the method of generating the large triangle area number and mapping the phase angle according to the actual phase angle is: Control signal generation steps: actual phase angle divided by Then round up to get the control signal; The steps of generating the area number and the mapped phase angle are as follows: when the control signal is 1, the area number of the large triangle is 4, and the actual phase angle is the mapped phase angle; when the control signal is 2, the area number of the large triangle is 5, and the actual phase angle is minus is the mapping phase angle; when the control signal is 3, the large triangle area number is 6, and the actual phase angle is reduced is the mapping phase angle; when the control signal is 4, the large triangle area number is 1, and the actual phase angle is reduced is the mapping phase angle; when the control signal is 5, the large triangle area number is 2, and the actual phase angle is reduced is the mapping phase angle; when the control signal is 6, the large triangle area number is 3, and the actual phase angle is reduced is the mapping phase angle.

4. The hybrid device shared bridge arm three-level split output inverter modulation method according to claim 1, characterized in that: In the small triangle or trapezoidal area judgment step, the method of generating the small triangle or trapezoidal area number according to the size of the modulation degree is: when the modulation degree is ≥ the set threshold, the small triangle or trapezoidal area number is 2; when the modulation degree is < the set threshold, the small triangle or trapezoidal area number is 1.

5. The hybrid device shared bridge arm three-level split output inverter modulation method according to claim 1, characterized in that: The time calculation step further comprises: The first time calculation step: when the modulation index is less than the set threshold, the first vector action time is calculated according to the mapping phase angle, the modulation index, and the switching cycle; the first vector action time includes the action time , Action time , Action time , respectively expressed as: In the formula, is the switching cycle, To adjust the system, is the mapping phase angle; The second time calculation step: when the modulation index is greater than or equal to the set threshold, the second vector action time is calculated according to the mapping phase angle, the modulation index, and the switching cycle; the second vector action time includes the action time , Action time , Action time , Action time , respectively expressed as: 。 6. The hybrid device shared bridge arm three-level split output inverter modulation method according to claim 5, characterized in that: In the first modulation wave generating step, the method of generating the first modulation wave according to the large triangle area number and the first vector action time is: When the large triangle area number is 1, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave for , modulation wave is 0; when the large triangle area number is 2, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0; when the large triangle area number is 3, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1, the modulation wave for ; When the large triangle area number is 4, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave for , modulation wave is 1; when the large triangle area number is 5, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1; when the large triangle area number is 6, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0, the modulation wave for .

7. The hybrid device shared bridge arm three-level split output inverter modulation method according to claim 5, characterized in that: In the second modulation wave generating step, the method for generating the second modulation wave according to the large triangle area number and the second vector action time is: When the large triangle area number is 1, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave for , modulation wave is 0; when the large triangle area number is 2, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0; when the large triangle area number is 3, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1, the modulation wave for ; When the large triangle area number is 4, the modulation wave for , modulation wave for , modulation wave is 0, the modulation wave for , modulation wave is 1; when the large triangle area number is 5, the modulation wave for , modulation wave for , modulation wave for , modulation wave is 0, the modulation wave is 1; when the large triangle area number is 6, the modulation wave for , modulation wave for , modulation wave is 1, the modulation wave is 0, the modulation wave for .

8. A hybrid device common bridge arm three-level split output inverter modulation system, used to implement the hybrid device common bridge arm three-level split output inverter modulation method according to any one of claims 1 to 7, characterized in that: include: A reference voltage generation module generates a reference voltage vector according to the three-phase original modulation wave; The large triangle area judgment module calculates the phase angle of the reference voltage based on the reference voltage vector. The phase angle of the reference voltage is added to The actual phase angle is obtained by the offset, and the large triangle area number and the mapping phase angle are generated according to the actual phase angle; A small triangle or trapezoidal area judgment module calculates the amplitude of the reference voltage according to the reference voltage vector, takes the amplitude as the modulation index, and generates a small triangle or trapezoidal area number according to the size of the modulation index; A time calculation module, which calculates the first vector action time and the second vector action time according to the magnitude of the modulation index, the mapping phase angle, the modulation index, and the switching cycle; A first modulation wave generating module, generating a first modulation wave according to the large triangle area number and the first vector action time; A second modulation wave generating module generates a second modulation wave according to the large triangle area number and the second vector action time; A first pulse generating module generates a first pulse driving signal according to a first modulation wave, a forward carrier wave, and a reverse carrier wave; The second pulse generating module generates a final carrier according to the large triangle area number, the forward carrier and the reverse carrier, and generates a second pulse driving signal according to the second modulation wave, the forward carrier, the forward carrier of the previous cycle and the final carrier; The pulse selection module selects a driving signal from the first pulse driving signal and the second pulse driving signal according to the small triangle or trapezoidal area number.

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