A transimpedance amplifier and a deep-sea heavy metal detection device

Abstract

The present invention discloses a transimpedance amplifier and a deep-sea heavy metal detection device. The transimpedance amplifier includes: a working electrode for generating an input current, an integrator, a buffer, a feedback capacitor, and a feedback resistor; the feedback capacitor is connected between the output end and the input end of the integrator; the feedback resistor is connected between the output end of the buffer and the input end of the integrator; the input end of the integrator is connected to the working electrode, and the integrator is used to amplify the input current and output a first amplified voltage to the buffer; the buffer is used to amplify the received first amplified voltage and output a second amplified voltage. The transimpedance amplifier provided by the present invention integrates an on-chip electrode, so that the distance between the transimpedance amplifier and the electrochemical reaction cell can be reduced to hundreds of micrometers, reducing the capacitive effect of the electrochemical reaction, reducing the noise level, and realizing the quantitative detection of trace heavy metal concentration in the deep sea.

Description

Technical Field

[0001] The present invention relates to the technical field of deep-sea exploration, and particularly to a transimpedance amplifier and a deep-sea heavy metal detection device. Background Art

[0002] Heavy metals are often widely distributed in the ocean at trace concentrations. Heavy metals that are known to cause the greatest damage to the human body, such as cadmium and lead, are difficult to decompose in water. They will have strong interactions with proteins and enzymes in organisms, have high toxicity, and can cause irreversible damage. In the deep sea, the concentration of heavy metals is very low, and any slight disturbance will affect the detection results. Inductively coupled plasma-mass spectrometry (ICP-MS) is a high-fidelity technology for detecting trace heavy metal concentrations, which enables people to have a deeper quantitative analysis of trace heavy metals in the environment. However, due to the high price of the machine, complex sample pretreatment (usually dilution is required), high requirements for external environmental conditions and other adverse factors, it restricts the development of ICP-MS in the detection of trace heavy metals in extreme environments and complex backgrounds. Electrochemical technology has been widely used in the field of heavy metal detection due to its advantages such as small equipment size, simple sample pretreatment (even no pretreatment is required), and low cost. However, compared with traditional ICP-MS, the detection limit and detection sensitivity of electrochemical technology are still a major challenge.

[0003] The core device of an electrochemical workstation is a potentiostat composed of a transimpedance operational amplifier (TIA). By applying a specific input to the instrument and collecting the current output signal of the system, the concentration of heavy metals can be calculated based on the magnitude of the current value. For actual samples in the deep sea, the collected current value is very low, usually in the pA to nA range. Therefore, the performance of the TIA, especially the noise level, directly determines the correctness of the detection results. Existing electrochemical workstations usually adopt a customized solution based on integrated circuits (ICs). However, the customized solution based on integrated circuits has poor suppression of the negative capacitance effect that affects the electrochemical reaction, resulting in a high noise level, making it difficult to achieve good quantitative detection of trace heavy metal concentrations in the deep sea.

[0004] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0005] In view of the above deficiencies of the existing technology, the purpose of the present invention is to provide a transimpedance amplifier and a deep-sea heavy metal detection device to solve the problem of high noise level caused by poor suppression of the negative capacitance effect that affects the electrochemical reaction in existing electrochemical workstations.

[0006] The technical solution of the present invention is as follows:

[0007] In a first aspect, the present invention provides a transimpedance amplifier, which includes: a working electrode for generating an input current, an integrator, a buffer, a feedback capacitor, and a feedback resistor;

[0008] The feedback capacitor is connected between the output terminal and the input terminal of the integrator;

[0009] The feedback resistor is connected between the output terminal of the buffer and the input terminal of the integrator;

[0010] The input terminal of the integrator is connected to the working electrode, the output terminal of the integrator is connected to the input terminal of the buffer, and the integrator is used to amplify the input current and output a first amplified voltage to the buffer;

[0011] The buffer is used to amplify the received first amplified voltage and output a second amplified voltage.

[0012] In a further setting of the present invention, the integrator includes: a first bias voltage providing unit, a first operational amplifier unit, an output amplifier unit, and a low-frequency noise optimization unit;

[0013] The first bias voltage providing unit is connected to the first operational amplifier unit and is used to provide a first bias voltage for the first operational amplifier unit;

[0014] The first operational amplifier unit is connected to the working electrode and is used to increase the gain of the integrator;

[0015] The output amplifier unit is respectively connected to the first operational amplifier unit and the buffer, and the output amplifier unit is used to increase the output swing of the first amplified voltage;

[0016] The low-frequency noise optimization unit is respectively connected to the first operational amplifier unit and the output amplifier unit and is used to reduce low-frequency noise.

[0017] In a further setting of the present invention, the first bias voltage providing unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; wherein,

[0018] The gate of the first MOS transistor is connected to the gate of the second MOS transistor, the drain of the first MOS transistor is connected to a bias current, the source of the first MOS transistor is grounded; the common connection end of the gate of the first MOS transistor and the gate of the second MOS transistor is connected to a bias current;

[0019] The drain of the second MOS transistor is respectively connected to the drain of the third MOS transistor and the first operational amplifier unit, and the source of the second MOS transistor is grounded;

[0020] The gate of the third MOS transistor is connected to the first operational amplifier unit, and the source of the third MOS transistor is respectively connected to the source of the fourth MOS transistor and the gate of the fourth MOS transistor;

[0021] The source of the fourth MOS transistor is connected to the power supply voltage.

[0022] A further setting of the present invention, the first operational amplifier unit includes: a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor and a ninth MOS transistor; wherein,

[0023] The source of the fifth MOS transistor is connected to the power supply voltage, the gate of the fifth MOS transistor is respectively connected to the gate of the fourth MOS transistor and the output amplifier unit, and the drain of the fifth MOS transistor is respectively connected to the source of the sixth MOS transistor and the source of the seventh MOS transistor;

[0024] The gate of the sixth MOS transistor is connected to the first input terminal or the second input terminal of the integrator, and the drain of the sixth MOS transistor is connected to the source of the eighth MOS transistor;

[0025] The gate of the seventh MOS transistor is connected to the first input terminal or the second input terminal of the integrator, and the drain of the seventh MOS transistor is connected to the source of the ninth MOS transistor;

[0026] The gate of the eighth MOS transistor is connected to the gate of the ninth MOS transistor, and the drain of the eighth MOS transistor is connected to the low-frequency noise optimization unit;

[0027] The drain of the ninth MOS transistor is respectively connected to the low-frequency noise optimization unit and the output amplifier unit;

[0028] The low-frequency noise optimization unit includes: a tenth MOS transistor, an eleventh MOS transistor, a first resistor and a second resistor; wherein,

[0029] The gate of the tenth MOS transistor is connected to the gate of the eleventh MOS transistor, the drain of the tenth MOS transistor is connected to the drain of the eighth MOS transistor, the source of the tenth MOS transistor is connected to one end of the first resistor, and the other end of the first resistor is grounded;

[0030] The common connection end of the gate of the eleventh MOS transistor and the gate of the tenth MOS transistor is connected to the drain of the eighth MOS transistor;

[0031] The drain of the eleventh MOS transistor is respectively connected to the drain of the ninth MOS transistor and the output amplification unit. The source of the eleventh MOS transistor is connected to one end of the second resistor, and the other end of the second resistor is grounded.

[0032] A further arrangement of the present invention, the output amplification unit includes: a twelfth MOS transistor, a thirteenth MOS transistor, a third resistor and a first capacitor; wherein,

[0033] The gate of the twelfth MOS transistor is connected to the common connection end of the gates of the fourth MOS transistor and the fifth MOS transistor. The source of the twelfth MOS transistor is connected to the power supply voltage, and the drain of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor; the common connection end of the twelfth MOS transistor and the thirteenth MOS transistor is the output end of the integrator;

[0034] The gate of the thirteenth MOS transistor is connected to the common connection end of the drains of the ninth MOS transistor and the eleventh MOS transistor, and the source of the thirteenth MOS transistor is grounded;

[0035] One end of the third resistor is connected to the gate of the thirteenth MOS transistor, and the other end of the third resistor is connected to the drain of the thirteenth MOS transistor; the first capacitor is connected in series with the third resistor.

[0036] A further arrangement of the present invention, the buffer includes: a second bias voltage providing unit, a fully differential amplification unit and a common mode feedback unit; wherein,

[0037] The second bias voltage providing unit is connected to the fully differential amplification unit for providing a second bias voltage to the fully differential amplification unit;

[0038] The fully differential amplification unit is connected to the output end of the integrator for differentially amplifying the first amplified voltage and outputting a second amplified voltage;

[0039] The common mode feedback unit is connected to the fully differential amplification unit for providing a stable common mode point to the buffer and adjusting the gain of the buffer.

[0040] A further arrangement of the present invention, the second bias voltage providing unit includes: a fourteenth MOS transistor, a fifteenth MOS transistor and a sixteenth MOS transistor; wherein,

[0041] The gates of the fourteenth MOS transistor and the fifteenth MOS transistor are connected. The drain of the fourteenth MOS transistor is connected to a bias current, and the source of the fourteenth MOS transistor is grounded; the common connection end of the gates of the fourteenth MOS transistor and the fifteenth MOS transistor is connected to a bias current;

[0042] The drain of the fifteenth MOS transistor is connected to the drain and gate of the sixteenth MOS transistor, and the source of the fifteenth MOS transistor is grounded;

[0043] The source of the sixteenth MOS transistor is connected to a power supply voltage.

[0044] In a further arrangement of the present invention, the fully differential amplification unit includes: a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, and a twenty-first MOS transistor; wherein,

[0045] The gate of the seventeenth MOS transistor is connected to the gate of the sixteenth MOS transistor, the drain of the seventeenth MOS transistor is connected to the common connection end of the source of the eighteenth MOS transistor and the source of the nineteenth MOS transistor, and the source of the seventeenth MOS transistor is connected to a power supply voltage;

[0046] The gate of the eighteenth MOS transistor is connected to the output end of the integrator or connected to a common-mode voltage, and the drain of the eighteenth MOS transistor is connected to the drain of the twentieth MOS transistor and the first output end of the buffer;

[0047] The gate of the nineteenth MOS transistor is connected to the output end of the integrator or connected to a common-mode voltage, and the drain of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor and the second output end of the buffer;

[0048] The gate of the twentieth MOS transistor is connected to the gate of the twenty-first MOS transistor, and the source of the twentieth MOS transistor is grounded;

[0049] The source of the twenty-first MOS transistor is grounded.

[0050] In a further arrangement of the present invention, the common-mode feedback unit includes: a common-mode feedback amplifier, a fourth resistor, a fifth resistor, a second capacitor, and a third capacitor; wherein,

[0051] The first input end of the common-mode feedback amplifier is connected to a reference voltage, the second input end of the common-mode feedback amplifier is connected to the common connection end of the fourth resistor and the fifth resistor, and the output end of the common-mode feedback amplifier is connected to the common connection end of the gate of the twentieth MOS transistor and the gate of the twenty-first MOS transistor;

[0052] The second capacitor is connected in parallel with the fourth resistor, and the third capacitor is connected in parallel with the fifth resistor.

[0053] The transimpedance amplifier further includes: a range selection unit, the range selection unit is connected in parallel with the feedback resistor, and the range selection unit is used for performing gear switching according to the range of the input current.

[0054] In a second aspect, the present invention further provides a deep-sea heavy metal detection device, which includes: a second operational amplifier unit, a reference electrode, a counter electrode, a channel selection unit, an analog-to-digital conversion unit, a filtering unit, and at least one transimpedance amplifier as described above;

[0055] The inverting input terminal of the second operational amplifier unit is connected to the reference electrode, and the output terminal of the second operational amplifier unit is connected to the counter electrode. The second operational amplifier unit is used to amplify the input signal and then input it to the reference electrode;

[0056] The channel selection unit is respectively connected to the transimpedance amplifier and the analog-to-digital conversion unit. The channel selection unit is used to access the second amplified voltage output by the transimpedance amplifier and output a third amplified voltage to the analog-to-digital conversion unit;

[0057] The analog-to-digital conversion unit is connected to the filtering unit. The analog-to-digital conversion unit is used to convert the third amplified voltage into a digital signal and input it to the filtering unit;

[0058] The filtering unit is used to filter the digital signal and then output it.

[0059] A transimpedance amplifier and a deep-sea heavy metal detection device provided by the present invention. The transimpedance amplifier includes: a working electrode for generating an input current, an integrator, a buffer, a feedback capacitor, and a feedback resistor; the feedback capacitor is connected between the output terminal and the input terminal of the integrator; the feedback resistor is connected between the output terminal of the buffer and the input terminal of the integrator; the input terminal of the integrator is connected to the working electrode, and the output terminal of the integrator is connected to the input terminal of the buffer. The integrator is used to amplify the input current and output a first amplified voltage to the buffer; the buffer is used to amplify the received first amplified voltage and output a second amplified voltage. The transimpedance amplifier provided by the present invention integrates an on-chip electrode, that is, integrates a working electrode, so that the distance between the transimpedance amplifier and the electrochemical reaction cell can be reduced to hundreds of micrometers, reducing the capacitive effect of the electrochemical reaction, thereby reducing the noise level. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0061] Figure 1 It is the working principle diagram of the deep-sea heavy metal detection device in the present invention.

[0062] Figure 2 It is the working schematic diagram of the transimpedance amplifier and the electrochemical reaction cell in the present invention.

[0063] Figure 3 It is the waveform diagram of the input signal in the present invention.

[0064] Figure 4 It is the circuit schematic diagram of the integrator in the present invention.

[0065] Figure 5 It is the circuit schematic diagram of the buffer in the present invention.

[0066] Figure 6 It is the detection result diagram of the deep-sea heavy metal detection device in artificial seawater in an embodiment of the present invention.

[0067] Figure 7 It is the detection result diagram of the deep-sea heavy metal detection device collecting seawater at a depth of 8448 meters in the Mariana Trench in an embodiment of the present invention.

[0068] Each label in the attached drawings: 100, transimpedance amplifier; 110, integrator; 111, first bias voltage providing unit; 112, first operational amplifier unit; 113, low-frequency noise optimization unit; 114, output amplifier unit; 120, buffer; 121, second bias voltage providing unit; 122, fully differential amplifier unit; 123, common-mode feedback unit; 130, range selection unit; 200, second operational amplifier unit; 300, channel selection unit; 400, analog-to-digital conversion unit; 500, filtering unit; 600, capacitance compensation unit. Detailed implementation manners

[0069] The present invention provides a transimpedance amplifier and a deep-sea heavy metal detection device. To make the purpose, technical solution and effects of the present invention clearer and more definite, the following further elaborates on the present invention by way of examples with reference to the attached drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0070] In the embodiments and the scope of the patent application, unless otherwise specifically defined in the text for articles, "a", "an", "the" and "said" may also include the plural form. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second" may explicitly or implicitly include at least one such feature.

[0071] It should be further understood that the term "comprising" used in the description of the present invention means the presence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The phrase "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0072] Those skilled in the art of the present technology can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of those of ordinary skill in the field to which the present invention pertains. It should also be understood that terms such as those defined in a general dictionary should be understood to have a meaning consistent with the meaning in the context of the prior art, and will not be interpreted with an idealized or overly formal meaning unless specifically defined as here.

[0073] In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0074] Please also refer to Figures 1 to 7 , the present invention provides a preferred embodiment of a deep-sea heavy metal detection device.

[0075] In some embodiments, such as Figure 1 and Figure 2As shown in the figure, the present invention provides a deep-sea heavy metal detection device, which includes: a second operational amplifier unit 200, a reference electrode RE, a counter electrode CE, a channel selection unit 300, an analog-to-digital conversion unit 400, a filtering unit 500, and at least one transimpedance amplifier 100. Among them, the inverting input terminal of the second operational amplifier unit 200 is connected to the reference electrode RE, the output terminal of the second operational amplifier unit 200 is connected to the counter electrode CE, and the second operational amplifier unit 200 is used to amplify the input signal and then input it to the reference electrode RE; the channel selection unit 300 is respectively connected to the transimpedance amplifier 100 and the analog-to-digital conversion unit 400, and the channel selection unit 300 is used to access the second amplified voltage output by the transimpedance amplifier 100 and output a third amplified voltage to the analog-to-digital conversion unit 400; the analog-to-digital conversion unit 400 is connected to the filtering unit 500, and the analog-to-digital conversion unit 400 is used to convert the third amplified voltage into a digital signal and input it to the filtering unit 500; the filtering unit 500 is used to filter the digital signal and then output an output signal.

[0076] Among them, the transimpedance amplifier 100 includes: a working electrode WE for generating an input current, an integrator 110, a buffer 120, a feedback capacitor C F and a feedback resistor R F ; the feedback capacitor C F is connected between the output terminal and the input terminal of the integrator 110; the feedback resistor R F is connected between the output terminal of the buffer 120 and the input terminal of the integrator 110; the input terminal of the integrator 110 is connected to the working electrode WE, the output terminal of the integrator 110 is connected to the input terminal of the buffer 120, and the integrator 110 is used to amplify the input current and output a first amplified voltage to the buffer 120; the buffer 120 is used to amplify the received first amplified voltage and output a second amplified voltage.

[0077] Specifically, the working electrode WE on the transimpedance amplifier 100, the reference electrode RE, and the counter electrode CE form an electrochemical reaction cell. When detecting heavy metals in a solution, the working electrode WE is electrically connected to the reference electrode RE and the counter electrode CE through the solution. Please refer to Figure 2 , the circuit model of the working electrode WE is a working electrode capacitor C WE in parallel with a working electrode resistor R WE , the circuit model of the reference electrode RE is a reference electrode resistor R SR , and the circuit model of the counter electrode CE is a counter electrode capacitor C CEIn parallel with a counter electrode resistance R CE where R SW represents the solution impedance.

[0078] The second operational amplifier unit 200 can access a specific input signal Ei, such as an adjustable triangular wave, as shown in a of Figure 3 , and an adjustable differential pulse, as shown in b of Figure 3 . After amplifying and processing the input signal, it can be transmitted to the reference electrode RE. A fixed potential difference is formed between the reference electrode RE and the working electrode WE. The potential of the working electrode WE with respect to ground is constant. Therefore, by controlling the signal applied to the reference electrode RE, the signal applied to the working electrode WE can be precisely controlled and is not affected by the voltage drop caused by the current. It should be understood that when a voltage is applied to the working electrode WE, heavy metal ions in the solution will undergo oxidation-reduction reactions on the surface of the working electrode, thereby generating a current (i.e., the input current to the integrator). When the current generated during the electrochemical reaction and the solution's own impedance generate a voltage drop, the generated voltage drop will not affect the voltage applied to the working electrode.

[0079] The working electrode WE is fixed at the reference potential through the negative feedback of the transimpedance amplifier 100. Therefore, the input current flowing into the inverting terminal of the transimpedance amplifier 100 can be expressed as:

[0080] ; where V WE is the potential difference of the working electrode, V RE is the potential difference of the reference electrode, R WE represents the equivalent impedance of the working electrode itself, C WE represents the equivalent capacitance of the working electrode itself, R SR represents the equivalent impedance of the reference electrode, R SW represents the solution impedance, and s represents the basic signal in the complex frequency domain.

[0081] The selection of the feedback circuit architecture has a great influence on the performance of the transimpedance amplifier. In this embodiment, a resistive continuous-time feedback architecture is adopted, and the feedback resistor is connected between the output terminal of the buffer 120 and the input terminal of the integrator 110. In a resistive transimpedance amplifier, the input current noise can be expressed as:

[0082] ; where represents the feedback current noise, represents the transimpedance amplifier current noise;

[0083] The feedback current noise can be expressed as:

[0084] ; where R F represents the transimpedance, T represents the temperature, and k represents the Boltzmann constant.

[0085] It can be seen from the above expressions that a large transimpedance can reduce the influence of the feedback resistor on the current noise, and at the same time, the magnitude of the transimpedance also determines the gain of the transimpedance amplifier. Since an overly large transimpedance will occupy a large layout area and also reduce the equivalent bandwidth of the system. For the electrochemical input model and signal characteristics, a transimpedance of 257 MΩ can be selected to better balance the performance requirements.

[0086] In some embodiments, the working electrode WE can be a titanium electrode with a size of 75 μm × 75 μm. By using vertical integration technology to integrate the on-chip titanium electrode with the transimpedance amplifier, the traditional electrochemical reaction cell can be reduced to an area of 1 mm², and at the same time, different types of electrochemical experiments can be realized for multiple channels. For example, four channels can be realized. The layout size of the transimpedance amplifier is 1.255 mm × 0.8 mm, which can include four channels. It is fabricated using a 0.18 μm CMOS manufacturing process, and each channel has the same transimpedance amplifier. Each channel can independently complete different types of electrochemical experiments without mutual influence. During specific implementation, after bonding the pads of the transimpedance amplifier to the printed circuit board with gold wires, the periphery of the chip is sealed with epoxy resin to prevent the solution from corroding the chip and the gold wires. Since the electrode surface of the transimpedance amplifier is titanium and aluminum, first, the aluminum needs to be etched. Using type A aluminum etchant, etch for 30 min at room temperature of 25 °C. Observe the electrode surface under an optical lens until it changes from silver-white to black, then the etching stops. After etching, it needs to be carefully washed three times with pure water to ensure no residue of the aluminum etchant. At the same time, the transimpedance amplifier can be compatible with the daughter board of the transimpedance amplifier. The daughter board is used to connect the transimpedance amplifier die to the printed circuit board, thereby conducting signals through gold wire bonding and performing shielding at 0.9 V in a Faraday cage to reduce electromagnetic interference from the external environment and reduce system noise.

[0087] In some embodiments, the reference electrode RE can be a silver (Ag) electrode or a silver chloride (AgCl) electrode. Before detecting heavy metals, the surface of the working electrode needs to be modified with a mercury film. The mercury plating solution uses 0.02 M mercury nitrate. By applying a constant negative potential of -0.3 V to the three-electrode system, the mercury plating time is 15 min. It can be observed under an optical lens that the electrode surface turns silver-gray, and a dense mercury film can be observed on the electrode surface using a scanning electron microscope.

[0088] In the above technical solution, the transimpedance amplifier provided by the present invention integrates an on-chip electrode, that is, a working electrode, so that the distance between the transimpedance amplifier and the electrochemical reaction cell can be reduced to hundreds of micrometers, reducing the capacitive effect of the electrochemical reaction, reducing the parasitic capacitance at the input end, and there is no need for wire connection between the working electrode and the transimpedance amplifier, thereby reducing the noise level and effectively attenuating the noise in the high-frequency band, and quantitative detection of trace heavy metal concentration in the deep sea can be achieved.

[0089] In some embodiments, as Figure 4 shown, the integrator 110 includes: a first bias voltage providing unit 111, a first operational amplification unit 112, an output amplification unit 114 and a low-frequency noise optimization unit 113. The first bias voltage providing unit 111 is connected to the first operational amplification unit 112 for providing a first bias voltage to the first operational amplification unit 112; the first operational amplification unit 112 is connected to the working electrode for increasing the gain of the integrator 110; the output amplification unit 114 is respectively connected to the first operational amplification unit 112 and the buffer 120, and the output amplification unit 114 is used for increasing the output swing of the first amplified voltage; the low-frequency noise optimization unit 113 is respectively connected to the first operational amplification unit 112 and the output amplification unit 114 for reducing the low-frequency noise.

[0090] In this embodiment, the first bias voltage providing unit 111 provides a first bias voltage to the first operational amplification unit 112 by accessing a bias current. The first bias voltage provided by the first bias voltage providing unit 111 to the first operational amplification unit 112 enables the integrator to have a high gain, be able to amplify the input current and output a first amplified voltage, and the output amplification unit 114 can then increase the swing of the first amplified voltage. The low-frequency noise optimization unit 113 is connected to the first operational amplification unit 112 and the output amplification unit 114, and can perform on-chip low-frequency noise optimization to reduce the mismatch caused by process errors.

[0091] In some embodiments, as Figure 4As shown, the first bias voltage providing unit 111 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4. Among them, the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2. The drain of the first MOS transistor M1 is connected to the bias current IBIAS, and the source of the first MOS transistor M1 is grounded to VSS. The common connection terminal of the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 is connected to the bias current IBIAS. The drain of the second MOS transistor M2 is respectively connected to the drain of the third MOS transistor M3 and the first operational amplifier unit 112, and the source of the second MOS transistor M2 is grounded. The gate of the third MOS transistor M3 is connected to the first operational amplifier unit 112, and the source of the third MOS transistor M3 is respectively connected to the source of the fourth MOS transistor M4 and the gate of the fourth MOS transistor M4. The source of the fourth MOS transistor M4 is connected to the power supply voltage VDD.

[0092] Specifically, the first MOS transistor M1 is connected to the bias current IBIAS, and the fourth MOS transistor M4 is connected to the power supply voltage VDD. When the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are turned on, the first bias voltage can be provided for the first operational amplifier unit 112. Among them, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors, and the third MOS transistor M3 and the fourth MOS transistor M4 are NMOS transistors.

[0093] In some embodiments, the first operational amplifier unit 112 includes: a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, and a ninth MOS transistor M9. Among them, the source of the fifth MOS transistor M5 is connected to the power supply voltage VDD. The gate of the fifth MOS transistor M5 is respectively connected to the gate of the fourth MOS transistor M4 and the output amplifier unit 114. The drain of the fifth MOS transistor M5 is respectively connected to the source of the sixth MOS transistor M6 and the source of the seventh MOS transistor M76. The gate of the sixth MOS transistor M6 is connected to the first input terminal or the second input terminal of the integrator 110, and the drain of the sixth MOS transistor M6 is connected to the source of the eighth MOS transistor M8. The gate of the seventh MOS transistor M7 is connected to the first input terminal or the second input terminal of the integrator 110, and the drain of the seventh MOS transistor M7 is connected to the source of the ninth MOS transistor M9. The gate of the eighth MOS transistor M8 is connected to the gate of the ninth MOS transistor M9, and the drain of the eighth MOS transistor M8 is connected to the low-frequency noise optimization unit 113. The drain of the ninth MOS transistor M9 is respectively connected to the low-frequency noise optimization unit 113 and the output amplifier unit 114.

[0094] Specifically, the fifth MOS transistor is connected to the power supply voltage VDD. The sixth MOS transistor M6 or the seventh MOS transistor M7 is connected to the input current. When the sixth MOS transistor M6 is connected to the input current, the seventh MOS transistor M7 is connected to the common-mode voltage. When the seventh MOS transistor M7 is connected to the input current, the sixth MOS transistor M6 is connected to the common-mode voltage. The sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8, and the ninth MOS transistor M9 form a cascode operational amplifier, ensuring a high gain of the integrator 110. Among them, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8, and the ninth MOS transistor M9 are NMOS transistors.

[0095] In some embodiments, as Figure 4 shown, the low-frequency noise optimization unit 113 includes: a tenth MOS transistor M10, an eleventh MOS transistor M11, a first resistor RS1, and a second resistor RS2. Among them, the gate of the tenth MOS transistor M10 is connected to the gate of the eleventh MOS transistor M11. The drain of the tenth MOS transistor M10 is connected to the drain of the eighth MOS transistor M8. The source of the tenth MOS transistor M10 is connected to one end of the first resistor RS1, and the other end of the first resistor RS1 is grounded. The common connection end of the gate of the eleventh MOS transistor M11 and the gate of the tenth MOS transistor M10 is connected to the drain of the eighth MOS transistor M8. The drain of the eleventh MOS transistor M11 is respectively connected to the drain of the ninth MOS transistor M9 and the output amplification unit 114. The source of the eleventh MOS transistor M11 is connected to one end of the second resistor RS2, and the other end of the second resistor RS2 is grounded.

[0096] Specifically, the tenth MOS transistor M10 and the eleventh MOS transistor M11 are load MOS transistors (PMOS transistors), and the first resistor RS1 and the second resistor RS2 are source degeneration resistors. To reduce the noise of the integrator, optimization is carried out at the input stage transistor level (the first MOS transistor M1 and the second MOS transistor M2). Considering the lower flicker noise when using PMOS input, their size can adopt a larger width-to-length ratio. The width W and length L of the channel can be 784 μm and 240 nm respectively. The high-efficiency current efficiency g m / Id and the large-area gate reduce noise and mismatch. g m represents the transconductance, and Id represents the current. The source degeneration resistor can reduce the equivalent transresistance g m,eff of the load transistor, increasing the initial output impedance r o to (1 + g m Rs)r o , where g mis the equivalent transconductance of the load transistor. Through the analysis of the small-signal model, it can be deduced that the introduction of the source degeneration resistor reduces the original equivalent transconductance g m to g m / (1 + g m Rs), and the flicker current noise of the active load can be expressed as:

[0097] ; where, kp represents the flicker noise coefficient, Cox represents the gate oxide capacitance per unit area, f represents the frequency, Rs represents the resistance value of the source degeneration resistor (i.e., the resistance values of the first resistor RS1 and the second resistor RS2), g m represents the transconductance, W represents the width of the MOS transistor channel, and L represents the length of the MOS transistor channel.

[0098] The introduction of the source degeneration resistor can reduce the flicker noise of the load MOS transistor and adjust the stability of the integrator. The thermal noise of the detection device is expressed as follows:

[0099] ; where, represents the thermal noise of the inspection device, γ is the thermal noise coefficient, and the thermal noise coefficient is related to the channel length. For long-channel devices, γ = 2 / 3. For short-channel devices, γ > 1. Generally, γ = 1 is taken; T represents the temperature, k represents the Boltzmann constant, Rs represents the resistance value of the source degeneration resistor (i.e., the resistance values of the first resistor and the second resistor), and g m represents the transconductance.

[0100] From the above expressions, it can be seen that the attenuation of the equivalent transconductance of the active load MOS transistor can optimize the thermal noise. At the same time, the resistor introduced by the source degeneration technology itself brings thermal noise. In order to prevent the source degeneration resistor from becoming the main noise source, it is necessary to satisfy that g m Rs is much less than 1 so that the detection device can obtain the optimal thermal noise level.

[0101] In some embodiments, such as Figure 4As shown, the output amplification unit 114 includes: a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a third resistor R3, and a first capacitor C1. Among them, the gate of the twelfth MOS transistor M12 is connected to the common connection end of the gates of the fourth MOS transistor M4 and the fifth MOS transistor M5. The source of the twelfth MOS transistor M12 is connected to the power supply voltage VDD. The drain of the twelfth MOS transistor M12 is connected to the drain of the thirteenth MOS transistor M13. The common connection end of the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 is the output terminal OUT of the integrator 110. The gate of the thirteenth MOS transistor M13 is connected to the common connection end of the drains of the ninth MOS transistor M9 and the eleventh MOS transistor M11. The source of the thirteenth MOS transistor M13 is grounded. One end of the third resistor R3 is connected to the gate of the thirteenth MOS transistor M13, and the other end of the third resistor R3 is connected to the drain of the thirteenth MOS transistor M13. The first capacitor C1 is connected in series with the third resistor R3.

[0102] Specifically, the twelfth MOS transistor M12 is connected to the power supply voltage VDD. The thirteenth MOS transistor M13 can increase the output swing of the first amplified voltage, thereby reducing the error caused by virtual short circuit in the integrator. Among them, the twelfth MOS transistor M12 is an NMOS transistor, and the thirteenth MOS transistor M13 is a PMOS transistor.

[0103] In some embodiments, as Figure 5 shown, the buffer 120 includes: a second bias voltage providing unit 121, a fully differential amplification unit 122, and a common-mode feedback unit 123. Among them, the second bias voltage providing unit 121 is connected to the fully differential amplification unit 122 for providing a second bias voltage to the fully differential amplification unit 122. The fully differential amplification unit 122 is connected to the output terminal of the integrator 110 for differentially amplifying the first amplified voltage and outputting a second amplified voltage. The common-mode feedback unit 123 is connected to the fully differential amplification unit 122 for providing a stable common-mode point for the buffer 120 and adjusting the gain of the buffer 120.

[0104] In this embodiment, the second bias voltage providing unit 121 provides a second bias voltage to the fully differential amplification unit 122. The fully differential amplification unit 122 outputs a differential amplified voltage, that is, a second amplified voltage, in a differential output manner. In this way, the transimpedance amplifier uses a differential amplification output method with a single-ended output of the integrator and a differential output of the buffer, achieving an equivalent two-fold transimpedance gain, which can reduce the common-mode noise of the system and improve the anti-interference ability of the detection device. The common-mode feedback unit 123 can adjust the output gain and stabilize the common-mode operating point of the system. According to the transfer function formula of the detection device:

[0105] ; wherein, Vout represents the output voltage of the integrator, i.e., the first amplified voltage, represents the input current, R F represents the resistance value of the feedback resistor, CF represents the capacitance value of the feedback capacitor, and s represents the basic signal in the complex frequency domain.

[0106] In this embodiment, the common-mode feedback unit 123 can adjust the voltage gain multiple. Taking 7 times as an example in this embodiment, the buffer with a 7-fold voltage gain can attenuate the equivalent feedback capacitance by 7 times, realizing an on-chip capacitance of 7.14 fF, thereby expanding the bandwidth by 7 times, which can alleviate to a certain extent the problem of bandwidth reduction caused by the introduction of the feedback capacitor, and can also ensure further reduction of the size of the feedback capacitor on the premise of system stability.

[0107] In some embodiments, such as Figure 2 and Figure 5 shown, the second bias voltage providing unit 121 includes: a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16. Among them, the gate of the fourteenth MOS transistor M14 is connected to the gate of the fifteenth MOS transistor M15, the drain of the fourteenth MOS transistor M14 is connected to the bias current IBIAS, and the source of the fourteenth MOS transistor M14 is grounded; the common connection terminal of the gate of the fourteenth MOS transistor M14 and the gate of the fifteenth MOS transistor M15 is connected to the bias current IBIAS; the drain of the fifteenth MOS transistor M15 is connected to the drain and gate of the sixteenth MOS transistor M16, and the source of the fifteenth MOS transistor M15 is grounded to VSS; the source of the sixteenth MOS transistor M16 is connected to the power supply voltage VDD. The fourteenth MOS transistor M14 and the fifteenth MOS transistor M15 are PMOS transistors, and the sixteenth MOS transistor M16 is an NMOS transistor.

[0108] Further, the fully differential amplification unit 122 includes: a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, and a twenty-first MOS transistor M21. Among them, the gate of the seventeenth MOS transistor M17 is connected to the gate of the sixteenth MOS transistor M16, the drain of the seventeenth MOS transistor M17 is connected to the common connection end of the source of the eighteenth MOS transistor M18 and the source of the nineteenth MOS transistor M19, and the source of the seventeenth MOS transistor M17 is connected to the power supply voltage; the gate of the eighteenth MOS transistor M18 is connected to the output of the integrator 110 or connected to the common-mode voltage, and the drain of the eighteenth MOS transistor M18 is connected to the drain of the twentieth MOS transistor M20 and the first output terminal OUT1 of the buffer 120; the gate of the nineteenth MOS transistor M19 is connected to the output terminal of the integrator 110 or connected to the common-mode voltage, and the drain of the nineteenth MOS transistor M19 is connected to the drain of the twenty-first MOS transistor M21 and the second output terminal OUT2 of the buffer 120; the gate of the twentieth MOS transistor M20 is connected to the gate of the twenty-first MOS transistor M21, and the source of the twentieth MOS transistor M20 is grounded; the source of the twenty-first MOS transistor M21 is grounded to VSS.

[0109] Specifically, the fourteenth MOS transistor M14 is connected to the bias current IBIAS, the sixteenth MOS transistor M16 is connected to the power supply voltage VDD, and the drain of the fifteenth MOS transistor M15 is connected to the gate of the seventeenth MOS transistor M17 to provide a second bias voltage for the fully differential amplification unit 122. The gate of the eighteenth MOS transistor M18 or the gate of the nineteenth MOS transistor M19 is connected to the output terminal of the integrator 110. When the gate of the eighteenth MOS transistor M18 is connected to the output terminal of the integrator 110, the gate of the nineteenth MOS transistor M19 is connected to the common-mode voltage. When the gate of the nineteenth MOS transistor M19 is connected to the output terminal of the integrator 110, the gate of the eighteenth MOS transistor M18 is connected to the common-mode voltage. The seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, and the twenty-first MOS transistor M21 form a fully differential amplifier, which has a first output terminal OUT1 and a second output terminal OUT2 to realize differential output of the differential amplification voltage (VOUT+, VOUT-), so that the single-ended output of the integrator can be converted into the differential output of the buffer 120, thereby realizing an equivalent two-fold transimpedance gain and improving the anti-interference ability of the system at the same time. Among them, the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, and the nineteenth MOS transistor M19 are NMOS transistors, and the twentieth MOS transistor M20 and the twenty-first MOS transistor M21 are PMOS transistors.

[0110] In some embodiments, such as Figure 5 shown, the common-mode feedback unit 123 includes: a common-mode feedback amplifier CMFB, a fourth resistor R4, a fifth resistor R5, a second capacitor C2, and a third capacitor C3. Among them, a first input terminal of the common-mode feedback amplifier CMFB is connected to a reference voltage VREF, a second input terminal of the common-mode feedback amplifier CMFB is connected to a common connection terminal of the fourth resistor R4 and the fifth resistor R5, and an output terminal of the common-mode feedback amplifier CMFB is connected to a common connection terminal of a gate of the twentieth MOS transistor M20 and a gate of the twenty-first MOS transistor M21; the second capacitor C2 is connected in parallel with the fourth resistor R4, and the third capacitor C3 is connected in parallel with the fifth resistor R5.

[0111] Specifically, the output terminal of the common-mode feedback amplifier CMFB is connected to the common connection terminal of the gate of the twentieth MOS transistor M20 and the gate of the twenty-first MOS transistor M21. Through common-mode feedback, the common-mode operating point of the detection device can be stabilized. The fourth resistor R4 and the fifth resistor R5 are common-mode detection resistors. Through the fourth resistor R4 and the fifth resistor R5, stable gain can be achieved, and the gain multiple can be adjusted by adjusting the fourth resistor R4 and the fifth resistor R5. The second capacitor C2 is connected in parallel with the fourth resistor R4, and the third capacitor C3 is connected in parallel with the fifth resistor R5, which can reduce the impedance at high frequencies and improve the stability of the common-mode feedback unit.

[0112] In some embodiments, such as Figure 1 shown, the transimpedance amplifier 100 further includes: a range selection unit 130, the range selection unit 130 is connected in parallel with the feedback resistor R F in parallel, and the range selection unit is used for performing gear switching according to the range of the input current.

[0113] Specifically, the range selection unit 130 is composed of a plurality of switching transistors SW and a plurality of sixth resistors R6. Each sixth resistor R6 is connected in parallel with the feedback resistor R F in parallel, and the size of the feedback resistor R F is adjusted by connecting the sixth resistor R6 in parallel, so as to achieve gear switching for different current ranges. When the oxidation-reduction current in the electro-chemical reaction process is large (high concentration), the system will automatically switch to a large-range gear; when the oxidation-reduction current in the electro-chemical reaction process is small (low concentration), the system will automatically switch to a small-range gear.

[0114] In some embodiments, such as Figure 1As shown, the deep-sea heavy metal detection device further includes a capacitance compensation unit 600, and the capacitance compensation unit 600 is connected between the working electrode WE and the inverting input terminal of the transimpedance amplifier. Specifically, due to the unique double-layer capacitance effect during the electrochemical reaction process, compensation through the capacitance compensation unit can improve the signal-to-noise ratio.

[0115] Figure 6 and Figure 7 respectively show the detection results of the detection device in artificially configured seawater and seawater collected from a depth of 8448 m in the Mariana Trench. Differential pulse anodic stripping voltammetry is used to detect lead and cadmium ions. Figure 6 As shown, the solution used is artificially configured seawater with 3.5% NaCl solution as the base solution, Cd 2+ and Pb 2+ standard solutions are 100 μmol / ml cadmium nitrate and 1000 μmol / ml lead nitrate respectively. The working electrode is a chip-on-chip titanium electrode (75 μm × 75 μm) integrated by TIA, the reference electrode is Ag / AgCl, and the counter electrode is Pt. The input signal is a stepped-up square wave generated by MATLAB and provided to the PCB, which includes three stages: enrichment, rest, and stripping. During the enrichment stage, an external potential of -1.4 V is applied for a duration of 400 s or 600 s. During the rest stage, an external potential of -0.9 V is applied for a duration of 10 s. The stripping stage starts with an initial potential of -0.9 V and continuously applies a stepped-up square wave until the termination potential of -0.3 V. The analog-to-digital conversion unit is responsible for collecting the current values at the high and low levels of the input signal during the stripping process, and then two I-V curves are obtained, as shown by a in Figure 6 and b in Figure 6 . The difference between the two currents gives the I-V curve. Curves with different concentrations correspond to different current values. By the relationship between the current peak value of the stripping peak and the concentration, a standard curve of current-concentration can be plotted, and the concentration can be calculated by substituting the measured peak current result of the actual seawater into the standard curve. It should be noted that during the actual detection process, measurements are made from low concentration to high concentration to avoid affecting the accuracy of the recorded current due to insufficient cleaning. To quantify the peak height, the magnitude of the peak current is measured from the baseline. To ensure the accuracy of the results, each curve is repeatedly tested until the two measurements are repeated. Figure 7 As shown, the solution used is a seawater sample from the Mariana Trench, at a depth of 8448 m, located at 142.15717°E, 11.5698°W. The sample is stored in an environment at 3°C. During the detection process, after continuous measurement five times, the average value of the current is calculated. Finally, the concentration of Cd 2+ in the seawater of the Mariana Trench at 8448 m is 0.859 μg / L, and that of Pb 2+The concentration is 0.921 μg / L.

[0116] In summary, a transimpedance amplifier and a deep-sea heavy metal detection device provided by the present invention have the following beneficial effects:

[0117] The transimpedance amplifier is fabricated using CMOS technology. At the same time, by using vertical integration technology, on-chip electrodes are integrated on the surface of the transimpedance amplifier, shortening the distance between the electrochemical reaction cell and the TIA to hundreds of micrometers, breaking through the electrochemical noise limitations caused by human factors and wiring. Thus, the noise level can be reduced, the noise in the high-frequency band can be effectively attenuated, and quantitative detection of trace heavy metal concentrations in the deep sea can be achieved.

[0118] The transimpedance amplifier uses a differential amplification output method with a single-ended output of the integrator and a double-ended output of the buffer to achieve an equivalent two-fold transimpedance gain, while improving the anti-interference ability of the detection device;

[0119] The source degeneration technology is used to optimize the on-chip low-frequency noise, which is beneficial to reducing the mismatch caused by process errors;

[0120] The circuit structure of a cascode operational amplifier and a common-source output is adopted to ensure the high gain and larger output swing of the amplifier, so as to reduce the system gain error under the closed-loop connection of the amplifier;

[0121] The stable gain is achieved through a common-mode detection resistor. By incorporating a capacitor into the common-mode detection resistor, the impedance at high frequencies is reduced, and the stability of the common-mode feedback circuit is improved.

[0122] It should be understood that the application of the present invention is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A transimpedance amplifier, characterized in that, Comprising: A working electrode for generating an input current, an integrator, a buffer, a feedback capacitor, and a feedback resistor; The feedback capacitor is connected between the output terminal and the input terminal of the integrator; The feedback resistor is connected between the output terminal of the buffer and the input terminal of the integrator; The input terminal of the integrator is connected to the working electrode, the output terminal of the integrator is connected to the input terminal of the buffer, and the integrator is configured to amplify the input current and output a first amplified voltage to the buffer; The buffer is configured to amplify the received first amplified voltage and output a second amplified voltage; The integrator includes: a first bias voltage providing unit, a first operational amplifier unit, an output amplifier unit, and a low-frequency noise optimization unit; The first bias voltage providing unit is connected to the first operational amplifier unit and is configured to provide a first bias voltage for the first operational amplifier unit; The first operational amplifier unit is connected to the working electrode and is configured to increase the gain of the integrator; The output amplifier unit is respectively connected to the first operational amplifier unit and the buffer, and the output amplifier unit is configured to increase the output swing of the first amplified voltage; The low-frequency noise optimization unit is respectively connected to the first operational amplifier unit and the output amplifier unit and is configured to reduce low-frequency noise; The first bias voltage providing unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor; wherein, The gate of the first MOS transistor is connected to the gate of the second MOS transistor, the drain of the first MOS transistor is connected to a bias current, and the source of the first MOS transistor is grounded; the common connection terminal of the gate of the first MOS transistor and the gate of the second MOS transistor is connected to a bias current; The drain of the second MOS transistor is respectively connected to the drain of the third MOS transistor and the first operational amplifier unit, and the source of the second MOS transistor is grounded; The gate of the third MOS transistor is connected to the first operational amplifier unit, and the source of the third MOS transistor is respectively connected to the drain of the fourth MOS transistor and the gate of the fourth MOS transistor; The source of the fourth MOS transistor is connected to a power supply voltage; The first operational amplifier unit includes: a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, and a ninth MOS transistor; wherein, The source of the fifth MOS transistor is connected to a power supply voltage, the gate of the fifth MOS transistor is respectively connected to the gate of the fourth MOS transistor and the output amplifier unit, and the drain of the fifth MOS transistor is respectively connected to the source of the sixth MOS transistor and the source of the seventh MOS transistor; The gate of the sixth MOS transistor is connected to the first input terminal or the second input terminal of the integrator, and the drain of the sixth MOS transistor is connected to the source of the eighth MOS transistor; The gate of the seventh MOS transistor is connected to the first input terminal or the second input terminal of the integrator, and the drain of the seventh MOS transistor is connected to the source of the ninth MOS transistor; The gate of the eighth MOS transistor is connected to the gate of the ninth MOS transistor, and the drain of the eighth MOS transistor is connected to the low-frequency noise optimization unit; the gate of the eighth MOS transistor and the gate of the ninth MOS transistor are also connected to the gate of the third MOS transistor; The drain of the ninth MOS transistor is respectively connected to the low-frequency noise optimization unit and the output amplification unit; The low-frequency noise optimization unit includes: a tenth MOS transistor, an eleventh MOS transistor, a first resistor and a second resistor; wherein, The gate of the tenth MOS transistor is connected to the gate of the eleventh MOS transistor, the drain of the tenth MOS transistor is connected to the drain of the eighth MOS transistor, the source of the tenth MOS transistor is connected to one end of the first resistor, and the other end of the first resistor is grounded; The common connection end of the gate of the eleventh MOS transistor and the gate of the tenth MOS transistor is connected to the drain of the eighth MOS transistor; The drain of the eleventh MOS transistor is respectively connected to the drain of the ninth MOS transistor and the output amplification unit, the source of the eleventh MOS transistor is connected to one end of the second resistor, and the other end of the second resistor is grounded.

2. The transimpedance amplifier according to claim 1, wherein The output amplification unit includes: a twelfth MOS transistor, a thirteenth MOS transistor, a third resistor and a first capacitor; wherein, The gate of the twelfth MOS transistor is connected to the common connection end of the gates of the fourth MOS transistor and the fifth MOS transistor, the source of the twelfth MOS transistor is connected to the power supply voltage, and the drain of the twelfth MOS transistor is connected to the drain of the thirteenth MOS transistor; the common connection end of the twelfth MOS transistor and the thirteenth MOS transistor is the output end of the integrator; The gate of the thirteenth MOS transistor is connected to the common connection end of the drain of the ninth MOS transistor and the drain of the eleventh MOS transistor, and the source of the thirteenth MOS transistor is grounded; One end of the third resistor is connected to the gate of the thirteenth MOS transistor, and the other end of the third resistor is connected to the drain of the thirteenth MOS transistor; the first capacitor is connected in series with the third resistor.

3. The transimpedance amplifier according to claim 1, wherein The buffer includes: a second bias voltage providing unit, a fully differential amplification unit and a common-mode feedback unit; wherein, The second bias voltage providing unit is connected to the fully differential amplification unit for providing a second bias voltage to the fully differential amplification unit; The fully differential amplification unit is connected to the output end of the integrator for differentially amplifying the first amplified voltage and outputting a second amplified voltage; The common-mode feedback unit is connected to the fully differential amplification unit for providing a stable common-mode point for the buffer and adjusting the gain of the buffer.

4. The transimpedance amplifier according to claim 3, wherein The second bias voltage providing unit includes: a fourteenth MOS transistor, a fifteenth MOS transistor and a sixteenth MOS transistor; wherein, The gate of the fourteenth MOS transistor is connected to the gate of the fifteenth MOS transistor, the drain of the fourteenth MOS transistor is connected to the bias current, the source of the fourteenth MOS transistor is grounded; the common connection end of the gate of the fourteenth MOS transistor and the gate of the fifteenth MOS transistor is connected to the bias current; The drain of the fifteenth MOS transistor is connected to the drain and gate of the sixteenth MOS transistor, and the source of the fifteenth MOS transistor is grounded; The source of the sixteenth MOS transistor is connected to a power supply voltage.

5. The transimpedance amplifier according to claim 4, wherein The fully differential amplification unit includes: a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, and a twenty-first MOS transistor; wherein, The gate of the seventeenth MOS transistor is connected to the gate of the sixteenth MOS transistor, the drain of the seventeenth MOS transistor is connected to the common connection terminal of the source of the eighteenth MOS transistor and the source of the nineteenth MOS transistor, and the source of the seventeenth MOS transistor is connected to a power supply voltage; The gate of the eighteenth MOS transistor is connected to the output terminal of the integrator or connected to a common-mode voltage, and the drain of the eighteenth MOS transistor is connected to the drain of the twentieth MOS transistor and the first output terminal of the buffer; The gate of the nineteenth MOS transistor is connected to the output terminal of the integrator or connected to a common-mode voltage, and the drain of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor and the second output terminal of the buffer; The gate of the twentieth MOS transistor is connected to the gate of the twenty-first MOS transistor, and the source of the twentieth MOS transistor is grounded; The source of the twenty-first MOS transistor is grounded.

6. The transimpedance amplifier according to claim 5, wherein The common-mode feedback unit includes: a common-mode feedback amplifier, a fourth resistor, a fifth resistor, a second capacitor, and a third capacitor; wherein, One end of the fourth resistor is connected to the common connection terminal of the drain of the eighteenth MOS transistor and the drain of the twentieth MOS transistor, and the other end of the fourth resistor is connected to one end of the fifth resistor; The other end of the fifth resistor is connected to the common connection terminal of the drain of the nineteenth MOS transistor and the drain of the twenty-first MOS transistor; The first input terminal of the common-mode feedback amplifier is connected to a reference voltage, the second input terminal of the common-mode feedback amplifier is connected to the common connection terminal of the fourth resistor and the fifth resistor, and the output terminal of the common-mode feedback amplifier is connected to the common connection terminal of the gate of the twentieth MOS transistor and the gate of the twenty-first MOS transistor; The second capacitor is connected in parallel with the fourth resistor, and the third capacitor is connected in parallel with the fifth resistor; It further includes: a range selection unit, which is connected in parallel with the feedback resistor, and the range selection unit is used to perform gear switching according to the range of the input current.

7. A deep-sea heavy metal detection device, characterized in that, It includes: A second operational amplifier unit, a reference electrode, a counter electrode, a channel selection unit, an analog-to-digital conversion unit, a filtering unit, and at least one transimpedance amplifier as described in any one of claims 1-6; The inverting input terminal of the second operational amplifier unit is connected to the reference electrode, the output terminal of the second operational amplifier unit is connected to the counter electrode, and the second operational amplifier unit is used to amplify the input signal and then input it to the reference electrode; The channel selection unit is respectively connected to the transimpedance amplifier and the analog-to-digital conversion unit, and the channel selection unit is used to access the second amplified voltage output by the transimpedance amplifier and output a third amplified voltage to the analog-to-digital conversion unit; The analog-to-digital conversion unit is connected to the filtering unit. The analog-to-digital conversion unit is used to convert the third amplified voltage into a digital signal and input it into the filtering unit; The filtering unit is used to perform filtering processing on the digital signal and then output it.

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