Voltage comparator and method for comparing input voltages
By introducing a current comparator and a differential stage into the voltage comparator, the contradiction between speed and current consumption in the prior art is solved, and a faster and energy-saving voltage comparator is achieved.
Patent Information
- Application Number
- CN202410715112.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-04
- Filing Date
- 2024-06-04
- Publication Date
- 2025-02-14
AI Technical Summary
Existing voltage comparators will increase the quiescent current Iq when increasing the speed. Conversely, reducing the quiescent current Iq will lead to a decrease in the reaction speed, making it difficult to find a suitable compromise between speed and current consumption.
A voltage comparator including a differential stage and a current comparator is designed, which generates a comparator current based on the input voltage, and the current comparator generates an output voltage based on the comparator current, and provides a digital output signal through the output stage. The current comparator improves transient performance by providing a low impedance connection and limiting voltage swing at the differential stage output node.
The transient performance of the voltage comparator is achieved without increasing the quiescent current Iq, providing a faster and energy-efficient voltage comparator.
Smart Images
Figure CN119448986A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a voltage comparator and a corresponding method for comparing different input voltages. Background Art
[0002] A voltage comparator is an electronic module widely used in various circuits, such as controllers of DC power converters, analog-to-digital converters (ADCs), etc. A voltage comparator is generally configured to compare a first input voltage and a second input voltage at its input port, and provide a digital output signal "0" or "1" at its output port, which indicates whether the first input voltage is greater than or less than the second input voltage.
[0003] The speed and current consumption of the comparator are important requirements for the voltage comparator, which is caused by the quiescent current Iq of the voltage comparator. These parameters are usually related in such a way that increasing the speed of the comparator will lead to an increase in the quiescent current Iq, and / or reducing the quiescent current Iq will usually lead to a decrease in the reaction speed of the comparator.
[0004] The present application document solves the technical problem of providing a voltage comparator which offers an improved compromise between speed and current consumption. Summary of the invention
[0005] According to one aspect, a voltage comparator is described, the voltage comparator comprising a differential stage for providing a comparator current at its output node in dependence on a first input voltage at a first input node of the voltage comparator and a second input voltage at a second input node. In addition, the voltage comparator comprises a current comparator having an input coupled to an output node of the differential stage, wherein the current comparator is used to provide an output voltage at an output node of the current comparator in dependence on the comparator current. The voltage comparator further comprises an output stage configured for providing a (digital) output signal of the voltage comparator in dependence on the output voltage at the output node of the current comparator, wherein the output signal indicates whether the first input voltage is greater than, less than or equal to the second input voltage.
[0006] According to another aspect, a method for comparing a first input voltage and a second input voltage is described. The method includes providing a comparator current at an output node of a differential stage based on a first input voltage at a first input node of a differential stage and a second input voltage at a second input node. In addition, the method includes providing an output voltage at an output node of a current comparator based on the comparator current. The method also includes providing an output signal based on the output voltage at the output node of the current comparator, the output signal indicating whether the first input voltage is greater than, less than, or equal to the second input voltage.
[0007] It should be noted that the methods and systems described in this application document, including preferred embodiments thereof, can be used alone or in combination with other methods and systems disclosed in this application document. In addition, the features described in the system are also applicable to the corresponding method. In addition, all aspects of the methods and systems described in this application document can be combined in any manner. In particular, the features of the claims can be combined with each other in any manner. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The present invention is described below by way of example with reference to the accompanying drawings, in which:
[0009] Figure 1 An example voltage comparator is shown;
[0010] Figure 2 An example voltage comparator with a current comparator is shown;
[0011] Figure 3 Another voltage comparator with a current comparator is shown;
[0012] Figure 4 An example circuit for generating a supply voltage for a current comparator is shown; and
[0013] Figure 5 A flow chart of an example method for comparing a first input voltage and a second input voltage is shown. DETAILED DESCRIPTION
[0014] As mentioned above, the present application document aims to provide a particularly fast and / or energy-saving voltage comparator. In this case, Figure 1 An example voltage comparator 100 is shown, which includes a differential stage 110 and an output stage 120. The differential stage 110 can be an operational transconductance amplifier (OTA). The differential stage 110 includes a first input port 101 (reference numeral POS) for receiving a first input voltage, and a second input port 102 (reference numeral NEG) for receiving a second input voltage. In addition, the differential stage 110 can be configured as:
[0015] generating a first comparator current 121 at the output port 103 of the differential stage 110 in dependence on the first input voltage; and
[0016] A second comparator current 122 is generated at the output port 103 of the differential stage 110 according to the second input voltage.
[0017] Specifically, the differential stage 110 can be configured to generate a first comparator current 121 and a second comparator current 122 at the output port 103 of the differential stage 110 according to the voltage difference between the first input voltage and the second input voltage (specifically, to generate an effective comparator current at the output port 103, which is the difference between the first comparator current 121 and the second comparator current 122).
[0018] If the first comparator current 121 is greater than the second comparator current 122, the output port 103 is pulled toward the reference voltage 112. On the other hand, if the second comparator current 122 is greater than the first comparator current 121, the output port 103 is pulled toward the supply voltage 111 of the differential stage 110.
[0019] The voltage comparator 100 may be configured such that a differential voltage at the input ports 101, 102 of the differential pair N0a and N0b (e.g., NMOS transistors) generates a difference between a second comparator current 122 through P4 (e.g., a PMOS transistor) and a first comparator current 121 through N2 (e.g., an NMOS transistor), wherein the comparator currents 121, 122 are compared in an output node OUT0 103 of the differential stage 110. The voltage at the output node OUT0 103 is typically not a digital signal and may be processed by an output stage 120. The output stage 120 includes one or more additional modules (e.g., Schmitt triggers and / or inverters) configured to shape the voltage into a digital output signal at an output node OUT 104 of the voltage comparator 100.
[0020] Figure 1 The voltage comparator 100 exhibits a relatively large voltage swing at the output node OUT0 103 of the differential stage 110. The relatively large voltage swing that can be achieved from the (almost) reference voltage 112 to the (almost) supply voltage 111 leads to a situation where a parasitic capacitance connected to the output node OUT0 103 of the differential stage 110 needs to be charged or discharged at each swing of the output node OUT0 103. The transfer of relatively high charge usually results in a relatively poor transient performance of the voltage comparator 100. One possibility to improve the transient performance is to increase the bias current 115 within the voltage comparator 100, which can increase the speed of charging or discharging one or more capacitors. However, this will increase the quiescent current Iq, thereby reducing the power efficiency of the voltage comparator 100.
[0021] In this document, a voltage comparator 100 is described, which includes a current comparator 200 (directly) coupled to an output node 103 of a differential stage 110, such as Figure 2 and Figure 3As shown. The current comparator 200 provides a low impedance connection to the output node OUT0 103 and / or is configured to reduce the voltage swing of the voltage at the output node OUT0 103 of the differential stage 110. The current comparator 200 can be configured to change the polarity of the output signal of the voltage comparator 100 when the direction of the comparator current 203 at its input changes. Wherein the change in direction of the comparator current 203 corresponds to a change in the sign of the differential input voltage.
[0022] like Figure 2 As shown, the effective comparator current CCIN 203 of the differential stage 110 (corresponding to the difference between the currents 121, 122) is fed into the input of the current comparator 200. The current comparator 200 includes a plurality of transistors, wherein the transistors PC1 and NC1 (which are referred to herein as "comparator transistors") serve as the comparator itself, and wherein the transistors NC0 and PC0 (which are referred to herein as "follower transistors") are connected as source followers and provide a relatively low impedance to the input of the current comparator 200 (i.e., the output node OUT0 103 of the differential stage 110). The source follower is driven by the output node OUT0 103 of the differential stage 110 so that only one of the transistors NC0 or PC0 is active.
[0023] The current comparator supply voltage VddCC 211 of the current comparator 200 is preferably set to be (preferably slightly) lower than the sum of the threshold voltage Vthp of the PMOS transistor PC0 and the threshold voltage Vthn of the NMOS transistor NC0. Since the current comparator supply voltage VddCC 211 is different from the main supply voltage Vdd 111 (specifically, the current comparator supply voltage VddCC211 is lower than the main supply voltage Vdd 111), a level shifter 220 can be used at the output of the current comparator 200 to provide an output signal at the output node 104, which may be related to the main supply voltage Vdd 111.
[0024] If the first comparator current 121 is higher than the second comparator current 122, the effective comparator current CCIN 203 at the input of the current comparator 200 starts from the current comparator supply voltage VddCC 211, flows through the NMOS transistor NC0, and flows through the NMOS transistor N2 to the reference potential 112. This direction of the comparator current 203 can be referred to as the second direction. The voltage drop 205 of the NMOS transistor NC0 corresponds to Vthn (e.g., 0.5V). Therefore, the voltage value at the output node 103 is VddCC-Vthn, which may be slightly lower than Vthp (where VddCC may be slightly lower than 1.2V and Vthp may be 0.7V).
[0025] If the first comparator current 121 is lower than the second comparator current 122, the effective current CCIN 203 at the input of the current comparator 200 starts from the main power supply voltage Vdd 111, flows through the PMOS transistor P4, and flows through the PMOS transistor PC0 to the reference potential 112. This direction of the comparator current 203 can be called a first direction. The voltage drop 204 of the PMOS transistor PC0 corresponds to Vthp (e.g., 0.7V). Therefore, the voltage value at the output node 103 is Vthp.
[0026] As shown in the above example, the voltage at the output node 103 remains substantially constant (at Vthp). Therefore, the transient performance of the voltage comparator 100 can be improved (without reducing the power efficiency of the voltage comparator 100).
[0027] like Figure 3 As shown, the differential stage (especially the Gm stage) 110 may be simplified and the output node 103 of the differential stage 110 may be coupled to the (low impedance) input node CCIN 203 of the current comparator 200 . Figure 3 The voltage comparator 100 exhibits reduced power consumption and / or reduced gain (compared to Figure 2 compared with the voltage comparator 100).
[0028] Figure 4 An example circuit is shown for generating a current comparator supply voltage VddCC 211 from a main supply voltage 111. The current comparator supply voltage VddCC 211 may be generated by an NMOS transistor NB2 that creates a source follower. The bias voltage for the source follower may be generated by an NMOS transistor NB1 in conjunction with a reference voltage 411 that is provided by a PMOS transistor PR1 (for generating Vthp 412) and an NMOS transistor NR1 (for generating Vthn 413). The dimensions of these MOS transistors and the bias current Ibias may be set so that the current comparator supply voltage VddCC 211 is just below the sum of the threshold voltage 412 of the PMOS transistor PR1 and the threshold voltage 413 of the NMOS transistor NR1.
[0029] The body connections of transistors NB1 and NB2 (connected together) and the body connection of transistor PR1 generally lower the threshold voltages of transistors PR1, NB1, and NB2, thereby helping to produce a current comparator supply voltage VddCC 211 that is slightly lower than the sum of the threshold voltages of transistors PC1 and NC1.
[0030] Herein, a PMOS differential pair is used to describe the voltage comparator 100. It should be noted that an NMOS differential pair may also be used.
[0031] The current comparator 200 is depicted as being coupled to a reference potential 112 (eg, ground). It should be noted that the current comparator may also be connected to the main supply voltage Vdd 111 or any other voltage level.
[0032] Furthermore, it should be noted that other types of differential input stages 110 may be used, such as a folded cascode structure for improved voltage range. The output node 103 of any type of differential stage 110 may be connected to the low impedance input of any type of current comparator 200 .
[0033] Figure 5 A flow chart of an example method 500 for comparing a first input voltage and a second input voltage is shown. The method 500 includes providing 501 a comparator current 203 at an output node 103 of the differential stage 110 based on a first input voltage at a first input node 101 and a second input voltage at a second input node 102 of the differential stage 110. The differential stage 110 may include or may be an OTA and / or a gm stage.
[0034] Furthermore, the method 500 comprises providing 502 an output voltage at an output node 206 of the current comparator 200 in dependence on the comparator current 203, wherein an input of the current comparator 200 is (directly) coupled to or coupled to the output node 103 of the differential stage 110. The current comparator 200 may be configured to limit a voltage swing of the voltage at the output node 103 of the differential stage 110 to a defined value (e.g., to 10% of the main supply voltage 111). Thus, the output voltage at the output node 206 of the current comparator 200 may be provided by limiting the voltage swing at the output node 103 of the differential stage 110.
[0035] The method 500 also includes providing 503 a (digital) output signal indicating whether the first input voltage is greater than or less than (or possibly equal to) the second input voltage based on the output voltage at the output node 206 of the current comparator 200. The output signal may be generated using a level shifting circuit 220.
[0036] Thus, a voltage comparator 100 is described, comprising a differential stage 110 configured to provide a comparator current 203 at an output node 103 of the differential stage 110 in dependence on a first input voltage at a first input node 101 and a second input voltage at a second input node 102 of the voltage comparator 100. The differential stage 110 may comprise an operational transconductance amplifier (OTA). In particular, the differential stage 110 may comprise a differential pair for receiving and comparing a first input voltage and a second input voltage.
[0037] The differential stage 110 may be configured as:
[0038] If the difference between the first input voltage and the second input voltage is positive (or negative), providing a comparator current 203 having a first direction; and
[0039] If the difference between the first input voltage and the second input voltage is negative (or alternatively positive), a comparator current 203 having a second direction (opposite to the first direction) is provided.
[0040] The voltage comparator 100 further comprises a current comparator 200, the input of which is (directly) coupled to the output node 103 of the differential stage 110. The current comparator 200 preferably provides a low impedance input, which results in a relatively small voltage swing at the output node 103 of the voltage comparator 100.
[0041] The current comparator 200 is configured to provide an output voltage at an output node 206 of the current comparator 200 according to the comparator current 203. If the comparator current 203 has a first direction, the output voltage at the output node 206 of the current comparator 200 may be at a first level (e.g., the reference potential 112). On the other hand, if the comparator current 203 has a second direction, the output voltage at the output node 206 of the current comparator 200 may be at a second level (e.g., the current comparator supply voltage 211).
[0042] The current comparator 200 may include a first comparator transistor NC1 (e.g., an NMOS transistor) and a second comparator transistor PC1 (e.g., a PMOS transistor), both of which are controlled using a comparator current 203. The first comparator transistor NC1 and the second comparator transistor PC1 may be arranged in series between the reference potential 112 and the current comparator supply voltage 211. The output node 206 of the current comparator 200 may be located at a midpoint between the first comparator transistor NC1 and the second comparator transistor PC1, and / or may be a midpoint between the first comparator transistor NC1 and the second comparator transistor PC1.
[0043] If the comparator current 203 has a first direction, the first comparator transistor NC1 can be configured to pull the output node 206 of the current comparator 200 to the reference potential 112. If the comparator current 203 has a second direction (opposite to the first direction), the second comparator transistor PC1 can be configured to pull the output node 206 of the current comparator 200 to the current comparator supply voltage 211.
[0044] The current comparator 200 has a relatively low input impedance at its input. Specifically, the current comparator 200 can be used to limit the voltage swing at the output node 103 of the differential stage 110, which is caused by the change in polarity of the voltage difference between the first input voltage and the second input voltage. The voltage swing can be limited to a limited value. The limited value can be 10% or less of the main supply voltage 111 of the differential stage 110. By limiting the voltage swing, the switching speed of the voltage comparator 100 can be improved in an energy-efficient manner.
[0045] The voltage comparator 100 may also include an output stage 220 configured to provide an output signal of the voltage comparator 100 based on the output voltage at the output node 206 of the current comparator 200. The output signal may indicate whether the first input voltage is greater than or less than (or possibly equal to) the second input voltage.
[0046] The differential stage 111 may be operated using the main supply voltage 111, and the current comparator 200 may be operated using a current comparator supply voltage 211, which is different from the main supply voltage 111, and specifically, the current comparator supply voltage 211 is less than the main supply voltage 111. The output stage 220 may include a level conversion circuit configured to convert the output voltage at the output node 206 of the current comparator 200 from the current comparator supply voltage 211 to the main supply voltage 111 (or any other useful voltage level) to generate a (digital) output signal of the voltage comparator 100.
[0047] Thus, a power efficient voltage comparator 100 having improved transient performance is described.
[0048] If the comparator current 203 has a first direction, the current comparator 200 may be configured to couple the output node 103 of the differential stage 110 to a reference potential 112 of the current comparator 200 via a first follower transistor PC0 (e.g., a PMOS transistor). Additionally, if the comparator current 203 has a second direction, the current comparator 200 may be configured to couple the output node 103 of the differential stage 110 to a current comparator supply voltage 211 of the current comparator 200 via a second follower transistor NC0 (e.g., an NMOS transistor).
[0049] The first follower transistor PC0 and the second follower transistor NC0 can be set as source followers. Specifically, the first follower transistor PC0 and the second follower transistor NC0 can be set in series between the reference potential 112 and the current comparator supply voltage 211. The output node 103 of the differential stage 110 can be (directly) coupled to the midpoint between the first follower transistor PC0 and the second follower transistor NC0 (corresponding to the input terminal of the current comparator 200).
[0050] The first follower transistor PC0 may have a first threshold voltage Vthp, and the second follower transistor NC0 may have a second threshold voltage Vthn. The difference between the current comparator supply voltage 211 and the reference potential 112 may be:
[0051] equal to or less than the sum of the first threshold voltage Vthp and the second threshold voltage Vthn; and
[0052] Greater than 90% of the sum of the first threshold voltage Vthp and the second threshold voltage Vthn.
[0053] By using follower transistors NC0, PC0, the current comparator 200 can be configured such that
[0054] If the comparator current 203 has a first direction, the voltage at the output node 103 of the differential stage 110 corresponds to the first threshold voltage Vthp; and
[0055] If the comparator current 203 has the second direction, the voltage at the output node 103 of the differential stage 110 corresponds to the voltage difference between the current comparator supply voltage 211 and the second threshold voltage Vthn.
[0056] Therefore, the voltage swing at the output node 103 of the differential stage 110 can be limited in an efficient and reliable manner.
[0057] Control ports of the first and second comparator transistors NC1 and PC1 may be coupled (directly) to the output node 103 of the differential stage 110. Furthermore, control ports of the first and second follower transistors PC0 and NC0 may be coupled (directly) to the output node 206 of the current comparator 200.
[0058] The voltage comparator 100 may include a circuit configured to generate a current comparator supply voltage 211 from a main supply voltage 111. The circuit for generating the current comparator supply voltage 211 may include a first reference transistor PR1 (e.g., a PMOS transistor) for generating a first reference threshold voltage 412 and a second reference transistor NR1 (e.g., an NMOS transistor) for generating a second reference threshold voltage 413, wherein the first reference transistor PR1 and the second reference transistor NR1 are arranged in series to provide a reference voltage 411 corresponding to the sum of the first reference threshold voltage 412 and the second reference threshold voltage 413.
[0059] The reference voltage 412 may correspond to the current comparator supply voltage 211. Therefore, the reference voltage 411 may be mirrored to the current comparator 200 as the current comparator supply voltage 211. The circuit for mirroring the reference voltage 411 may include,
[0060] a first mirror transistor NB1 (eg, an NMOS transistor) arranged in series with the first reference transistor NR1 and the second reference transistor NR2, and a bias current source; and
[0061] A second mirror transistor NB2 (eg, a PMOS transistor) which is arranged between the main supply voltage 111 and the current comparator supply voltage 211 .
[0062] The first mirror transistor NB1 and the second mirror transistor NB2 may form a current mirror. Using such a circuit, the current comparator supply voltage 211 may be generated in an efficient and accurate manner.
[0063] It should be noted that the description and drawings illustrate only the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements, which, although not explicitly described or shown herein, embody the principles of the present invention and are included in the spirit and scope of the present invention. In addition, all examples and embodiments described in this application document are primarily intended for explanation purposes only to help the reader understand the principles of the proposed method and system. In addition, all statements of the principles, aspects, and embodiments of the present invention and specific examples thereof are provided herein, and are intended to cover their equivalents.
Claims
1. A voltage comparator, the voltage comparator comprising: a differential stage configured to provide a comparator current at its output node as a function of a first input voltage at the first input node and a second input voltage at the second input node of the voltage comparator; - a current comparator having an input coupled to the output node of the differential stage; wherein the current comparator is configured to provide an output voltage at the output node of the current comparator as a function of the comparator current; and - an output stage configured to provide an output signal of the voltage comparator according to an output voltage at the output node of the current comparator; wherein the output signal indicates whether the first input voltage is greater than, less than or equal to the second input voltage.
2. The voltage comparator according to claim 1, characterized in that: - the current comparator is configured to limit a voltage swing at the output node of the differential stage to a defined value, the voltage swing being caused by a change in polarity of a voltage difference between the first input voltage and the second input voltage; and - the limit value is 10% or less of the main supply voltage of the differential stage.
3. The voltage comparator according to claim 1, wherein the current comparator is configured as: - if the comparator current has a first direction, coupling the output node of the differential stage to a reference potential of the current comparator via a first follower transistor; and - if the comparator current has a second direction opposite to the first direction, coupling the output node of the differential stage to a current comparator supply voltage of the current comparator via a second follower transistor.
4. The voltage comparator according to claim 3, wherein: - the first follower transistor exhibits a first threshold voltage; - the second follower transistor exhibits a second threshold voltage; - the difference between the current comparator supply voltage and the reference potential is equal to or less than the sum of the first threshold voltage and the second threshold voltage; as well as - the difference between the current comparator supply voltage and the reference potential is greater than 90% of the sum of the first threshold voltage and the second threshold voltage.
5. The voltage comparator according to claim 4, wherein the current comparator is configured such that - if the comparator current has the first direction, the voltage at the output node of the differential stage corresponds to the first threshold voltage; - If the comparator current has the second direction, the voltage at the output node of the differential stage corresponds to the difference between the current comparator supply voltage and the second threshold voltage.
6. The voltage comparator according to claim 3, wherein: The first follower transistor and the second follower transistor are arranged as source followers. 7 . The voltage comparator according to claim 3 , wherein the first follower transistor is a PMOS (P-channel Metal Oxide Semiconductor) transistor, and the second follower transistor is an NMOS (N-channel Metal Oxide Semiconductor) transistor.
8. The voltage comparator according to claim 3, wherein: - the current comparator comprises a first comparator transistor and a second comparator transistor, wherein the first comparator transistor and the second comparator transistor are both controlled using a comparator current; - if the comparator current has a first direction, the first comparator transistor is configured to pull the output node of the current comparator to a reference potential; as well as - If the comparator current has a second direction opposite to the first direction, the second comparator transistor is configured to pull the output node of the current comparator to a current comparator supply voltage.
9. The voltage comparator according to claim 8, wherein: - the control ports of the first comparator transistor and the second comparator transistor are both connected to the output node of the differential stage; as well as - The control ports of the first follower transistor and the second follower transistor are both connected to the output node of the current comparator.
10. The voltage comparator according to claim 1, wherein: - operating the differential stage using a main supply voltage; - operating the current comparator using a current comparator supply voltage different from the main supply voltage; as well as The output stage comprises a level shifting circuit configured to shift the output voltage at the output node of the current comparator from the current comparator supply voltage to the main supply voltage, thereby generating the output signal of the voltage comparator. 11 . The voltage comparator of claim 10 , wherein the voltage comparator comprises circuitry configured to generate the current comparator supply voltage from the main supply voltage.
12. The voltage comparator according to claim 11, wherein: The circuit for generating the current comparator supply voltage comprises: a first reference transistor for generating a first reference threshold voltage and a second reference transistor for generating a second reference threshold voltage, the first reference transistor and the second reference transistor being arranged in series so as to provide a reference voltage corresponding to the sum of the first reference threshold voltage and the second reference threshold voltage; and - a circuit for mirroring said reference voltage as supply voltage for the current comparator to said current comparator.
13. The voltage comparator according to claim 12, wherein: The circuit for mirroring the reference voltage to the current comparator comprises: - a first mirror transistor, the first mirror transistor being arranged in series with the first reference transistor, the second reference transistor and a bias current source; and - a second mirror transistor, said second mirror transistor being arranged between said main supply voltage and said current comparator supply voltage; wherein said first mirror transistor and said second mirror transistor form a current mirror.
14. The voltage comparator of claim 1, wherein the differential stage comprises an operational transconductance amplifier.
15. A method for comparing a first input voltage and a second input voltage, wherein the method comprises: - providing a comparator current at an output node of the differential stage in dependence on the first input voltage at a first input node of the differential stage and the second input voltage at a second input node; - providing an output voltage at an output node of the current comparator according to the comparator current; wherein an input terminal of the current comparator is coupled to the output node of the differential stage; as well as - providing an output signal as a function of the output voltage at the output node of the current comparator, the output signal indicating whether the first input voltage is greater than, less than or equal to the second input voltage.