Compensation circuit, compensation method and control circuit
By introducing compensation circuits for detection, judgment, logic and adjustment circuits into the signal generation circuit, the problem of aging of signal generation components is solved, resulting in the inability to operate normally by the core circuit, and effective compensation of signals and normal operation of core circuits are achieved.
Patent Information
- Application Number
- CN202410391590.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-31
- Filing Date
- 2024-04-02
- Publication Date
- 2025-02-14
AI Technical Summary
When an abnormal operation of the signal-generating component (such as aging), the core circuit of the backend using the component will not work properly.
Design a compensation circuit, including detection circuit, judgment circuit, logic circuit and adjustment circuit. The detection circuit detects the output signal, determines whether the detection result meets the preset conditions, the logic circuit blocks or allows the signal to enter the core circuit based on the judgment result, and the adjustment circuit adjusts the setting parameters according to the detection result to correct the output signal.
By blocking abnormal output signals into the core circuit and adjusting the set parameters, ensure that the signals received by the core circuit meet the target value, thereby maintaining the normal operation of the core circuit.
Smart Images
Figure CN119449004A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a compensation circuit, in particular to a compensation circuit for compensating for abnormality of a signal generating circuit. Background Art
[0002] With the advancement of technology, the types and functions of electronic devices are increasing. There are many components inside electronic devices. When the signal generating component operates abnormally (such as aging), the core circuit using the component at the back end will not operate normally. Summary of the invention
[0003] An embodiment of the present invention provides a compensation circuit for compensating an output signal generated by a signal generating circuit, and includes a detection circuit, a judgment circuit, a logic circuit and an adjustment circuit. The detection circuit detects the output signal to generate a detection result. The judgment circuit determines whether the detection result meets a preset condition. When the detection result does not meet the preset condition, the logic circuit blocks the output signal from entering a core circuit, and the adjustment circuit provides a set parameter. When the detection result meets the preset condition, the logic circuit allows the output signal to enter the core circuit. The signal generating circuit adjusts the output signal according to the set parameter.
[0004] The present invention further provides a control circuit, comprising a signal generating circuit, a core circuit and a compensation circuit. The signal generating circuit generates an output signal according to a set parameter. The core circuit receives the output signal. The compensation circuit comprises a detection circuit, a judgment circuit, a logic circuit and an adjustment circuit. The detection circuit detects the output signal to generate a detection result. The judgment circuit determines whether the detection result meets a preset condition. When the detection result does not meet the preset condition, the logic circuit blocks the output signal from entering the core circuit. When the detection result does not meet the preset condition, the adjustment circuit adjusts the set parameter. When the detection result meets the preset condition, the logic circuit allows the output signal to enter the core circuit.
[0005] The present invention further provides a compensation method, comprising: detecting an output signal output by a signal generating circuit to generate a detection result, wherein the signal generating circuit sets the output signal according to a set parameter; determining whether the detection result meets a preset condition; when the detection result does not meet the preset condition, blocking the output signal from entering a core circuit and adjusting the set parameter; when the detection result meets the preset condition, allowing the output signal to enter the core circuit.
[0006] The compensation method of the present invention can be implemented through the compensation circuit and control circuit of the present invention, which are hardware or firmware that can perform specific functions, or can be recorded in a recording medium in the form of program code and implemented in combination with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes a compensation circuit and control circuit for implementing the present invention.
[0007] The present invention can solve the problem that when a signal generating element operates abnormally (such as aging), the core circuit of the back-end using the element cannot operate normally. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1 is a schematic diagram of a control circuit of the present invention.
[0009] Figure 2 FIG. 4 is another schematic diagram of the control circuit of the present invention.
[0010] Figure 3 It is a schematic diagram of the flow chart of the compensation method of the present invention.
[0011] Reference numerals:
[0012] 100, 200: Control circuit
[0013] 110, 140, 210, 240: Signal generating circuit
[0014] 120, 220: Compensation circuit
[0015] 121, 221A~221C: Detection circuit
[0016] 122, 222A~222C: Judgment circuit
[0017] 123, 223: Logic circuit
[0018] 124, 224: Adjustment circuit
[0019] 130, 230: core circuit
[0020] 225: Select Circuit
[0021] SP1, SP2: Setting parameters
[0022] SO1, SO2: output signal
[0023] SD1~SD3: Test results
[0024] SC1~SC3: control signal
[0025] LG1, LG2: Logic gate DETAILED DESCRIPTION
[0026] In order to make the purpose, features and advantages of the present invention more clearly understood, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. The present invention specification provides different embodiments to illustrate the technical features of different implementations of the present invention. Among them, the configuration of each element in the embodiment is for illustrative purposes and is not intended to limit the present invention. In addition, some repetitions of the figure numbers in the embodiments are for the purpose of simplifying the description and do not mean the relevance between different embodiments.
[0027] Figure 1 FIG. 1 is a schematic diagram of a control circuit of the present invention. Figure 1 As shown, the control circuit 100 includes a signal generating circuit 110, a compensation circuit 120 and a core circuit 130. The signal generating circuit 110 generates an output signal SO1 according to a setting parameter SP1. In a possible embodiment, the signal generating circuit 110 adjusts the electrical characteristics of the output signal SO1 according to the setting parameter SP1, such as at least one of voltage, current, frequency and amplitude.
[0028] The present invention does not limit the type of the signal generating circuit 110. In one possible embodiment, the signal generating circuit 110 is a frequency generating circuit, such as an RC oscillator. In this example, the output signal SO1 is a clock signal. The signal generating circuit 110 adjusts the frequency of the output signal SO1 according to the setting parameter SP1. In another possible embodiment, the signal generating circuit 110 is a voltage regulator, such as a low-dropout regulator (LDO). In this example, the output signal SO1 is a voltage level. The signal generating circuit 110 adjusts the voltage level of the output signal SO1 according to the setting parameter SP1.
[0029] The compensation circuit 120 determines whether the operation of the signal generating circuit 110 is normal according to the output signal SO1. In one possible embodiment, when the signal generating circuit 110 ages, the processing speed of the signal generating circuit 110 may slow down, resulting in the output signal SO1 not meeting a target value. At this time, if the core circuit 130 operates according to the output signal SO1, it is easy to malfunction. Therefore, the compensation circuit 120 blocks the output signal SO1 from entering the core circuit 130 and adjusts the setting parameter SP1. The signal generating circuit 110 adjusts the output signal SO1 according to the adjusted setting parameter SP1. Then, the compensation circuit 120 determines whether the output signal SO1 meets a target value (such as 12MHz). When the output signal SO1 meets a target value, it means that the compensation operation has been completed. Therefore, the compensation circuit 120 allows the output signal SO1 to enter the core circuit 130. In some embodiments, after adjusting the output signal SO1, if the output signal SO1 still does not meet the target value, the compensation circuit 120 continues to adjust the setting parameter SP1 until the output signal SO1 meets the target value.
[0030] In some embodiments, the control circuit 100 further includes a signal generating circuit 140. The signal generating circuit 140 generates an output signal SO2 to the core circuit 130 according to a setting parameter SP2. In one possible embodiment, the signal generating circuit 140 adjusts the electrical characteristics of the output signal SO2, such as at least one of voltage, current, frequency, and amplitude, according to the setting parameter SP2. The present invention does not limit the type of the signal generating circuit 140. In one possible embodiment, the type of the signal generating circuit 140 may be the same as the type of the signal generating circuit 110. For example, the signal generating circuits 110 and 140 are both frequency generating circuits or voltage regulators. In some embodiments, the type of the signal generating circuit 140 may be different from the type of the signal generating circuit 110. For example, the signal generating circuit 110 is a frequency generating circuit, and the signal generating circuit 140 is a voltage regulator. In this example, at least one element in the core circuit 130 uses the output signal SO1 as an operation clock and operates according to the operation clock. In addition, at least one element in the core circuit 130 uses the output signal SO2 as an operating voltage and operates according to the operating voltage.
[0031] In other embodiments, when the signal generating circuit 110 ages, the components (standard cells) inside the core circuit 130 also age, so that the processing speed of the components slows down. In this example, the compensation circuit 120 adjusts the setting parameter SP2 so that the signal generating circuit 140 adjusts the output signal SO2 to compensate for the aging problem of the internal components of the core circuit 130. In some embodiments, the compensation circuit 120 compensates for the aging problem of the signal generating circuit 140 by setting the parameter SP2.
[0032] The present invention does not limit the number of signal generating circuits. In other embodiments, the control circuit 100 has more signal generating circuits. The compensation circuit 120 compensates for the aging problem of all signal generating circuits. In one possible embodiment, the compensation circuit 120 provides different setting parameters to different signal generating circuits according to the aging degree of the signal generating circuit 110. In some examples, the component size of the compensation circuit 120 is larger than the component size of the signal processing circuit 110 and the core circuit 130, so the aging speed of the compensation circuit 120 is much slower than the aging speed of the signal processing circuit 110 and the core circuit 130.
[0033] In this embodiment, the compensation circuit 120 includes a detection circuit 121, a judgment circuit 122, a logic circuit 123 and an adjustment circuit 124. The detection circuit 121 detects the output signal SO1 to generate a detection result SD1. The present invention does not limit the structure of the detection circuit 121. In one possible embodiment, the detection circuit 121 is a high pass filter, which is used to determine whether the frequency of the output signal SO1 meets a target value. When the frequency of the output signal SO1 meets a target value, the detection circuit 121 directly uses the output signal SO1 as the detection result SD1. When the frequency of the output signal SO1 does not meet a target value, the detection circuit 121 stops using the output signal SO1 as the detection result SD1. In this example, the detection circuit 121 may set the detection result SD1 to maintain a specific level, such as a low level. In another possible embodiment, the detection circuit 121 is a voltage detection circuit, which is used to detect the voltage level of the output signal SO1. In this example, the detection circuit 121 uses the voltage level of the output signal SO1 as the detection result SD1.
[0034] The judgment circuit 122 generates a control signal SC1 according to the detection result SD1. In one possible embodiment, the judgment circuit 122 judges whether the detection result SD1 meets a first preset condition. When the detection result SD1 meets a first preset condition, the judgment circuit 122 sets the control signal SC1 to a first level (e.g., a high level). When the detection result SD1 does not meet a first preset condition, the judgment circuit 122 sets the control signal SC1 to a second level (e.g., a low level).
[0035] The present invention does not limit the type of the judgment circuit 122. In one possible embodiment, the judgment circuit 122 is a counter. In this example, the judgment circuit 122 counts the number of pulses of the detection result SD1. When the number of pulses of the detection result SD1 reaches a preset value, it means that the frequency of the output signal SO1 meets a target value. Therefore, the judgment circuit 122 sets the control signal SC1 to a first level. When the number of pulses of the detection result SD1 does not reach a preset value, it means that the frequency of the output signal SO1 does not meet a target value. Therefore, the judgment circuit 122 sets the control signal SC1 to a second level.
[0036] In other embodiments, the judgment circuit 122 is a comparator. When the voltage level of the detection result SD1 is greater than or equal to a reference value, it means that the voltage level of the output signal SO1 meets a target value. Therefore, the judgment circuit 122 sets the control signal SC1 to a first level. When the voltage level of the detection result SD1 is less than the reference value, it means that the voltage level of the output signal SO1 does not meet a target value. Therefore, the judgment circuit 122 sets the control signal SC1 to a second level.
[0037] The logic circuit 123 determines whether to block the output signal SO1 from entering the core circuit 130 according to the control signal SC1. In one possible embodiment, when the control signal SC1 is at the second level, it indicates that the electrical characteristics of the output signal SO1 do not meet the target value. Therefore, the logic circuit 123 blocks the output signal SO1 from entering the core circuit 130. When the control signal SC1 is at the first level, it indicates that the electrical characteristics of the output signal SO1 meet the target value. Therefore, the logic circuit 123 allows the output signal SO1 to enter the core circuit 130. In some embodiments, when the logic circuit 123 blocks the output signal SO1 from entering the core circuit 130, the signal generating circuit 140 continues to provide the output signal SO2 to the core circuit 130. In another possible example, when the logic circuit 123 blocks the output signal SO1 from entering the core circuit 130, the logic circuit 123 also blocks the output signal SO2 from entering the core circuit 130.
[0038] The adjustment circuit 124 provides a setting parameter SP1 according to the control signal SC1. For example, when the control signal SC1 is at the second level, it indicates that the electrical characteristic of the output signal SO1 does not meet a target value. Therefore, the adjustment circuit 124 adjusts the setting parameter SP1. The signal generating circuit 110 adjusts the output signal SO1 according to the adjusted setting parameter. When the control signal SC1 is at the first level, it indicates that the electrical characteristic of the output signal SO1 meets a target value. Therefore, the adjustment circuit 124 maintains the setting parameter SP1. In other embodiments, when the control signal SC1 is at the second level, the adjustment circuit 124 adjusts the setting parameter SP2. The signal generating circuit 140 adjusts the output signal SO2 according to the adjusted setting parameter SP2.
[0039] In some embodiments, when the control signal SC1 is at the second level, it indicates that the detection result SD1 does not meet a preset condition. Therefore, the adjustment circuit 124 enables a warning signal (not shown). In this example, the user may replace the aged component according to the warning signal.
[0040] Figure 2 FIG. 2 is another schematic diagram of the control circuit of the present invention. Figure 2 As shown, the control circuit 200 includes signal generating circuits 210 and 240, a compensation circuit 220 and a core circuit 230. Since the characteristics of the signal generating circuits 210 and 240 and the core circuit 230 are similar to Figure 1 The characteristics of the signal generating circuits 110, 140 and the core circuit 130 are not described in detail. For the convenience of description, it is assumed that the signal generating circuit 210 is an RC oscillator and the signal generating circuit 240 is an LDO. The signal generating circuit 210 sets the frequency of the output signal SO1 according to the setting parameter SP1. The signal generating circuit 240 sets the voltage level of the output signal SO2 according to the setting parameter SP2.
[0041] The compensation circuit 220 includes detection circuits 221A-221C, determination circuits 222A-222C, a logic circuit 223, and an adjustment circuit 224. In some embodiments, the compensation circuit 220 further includes a selection circuit 225. When the control circuit 200 is powered on, the selection circuit 225 uses an initial signal trim_1 as the setting parameter SP1 and provides it to the signal generating circuit 210. The signal generating circuit 210 generates the output signal SO1 according to the initial signal trim_1.
[0042] The detection circuit 221A detects the frequency of the output signal SO1. When the frequency of the output signal SO1 meets a first preset condition (such as 12 MHz), the detection circuit 221A uses the output signal SO1 as the detection result SD1. The present invention does not limit the architecture of the detection circuit 221A. In one possible embodiment, the detection circuit 221A is a high-pass filter. In this example, when the frequency of the output signal SO1 is greater than a first preset value (such as 12 MHz), the detection circuit 221A directly outputs the output signal SO1. When the frequency of the output signal SO1 is not greater than a first preset value, the detection circuit 221A filters out the output signal SO1. Therefore, the detection result SD1 may be equal to a specific level, such as a low level.
[0043] The detection circuit 221B detects the frequency of the output signal SO1. When the frequency of the output signal SO1 meets a second preset condition (such as 11MHz), the detection circuit 221B uses the output signal SO1 as the detection result SD2. The present invention does not limit the architecture of the detection circuit 221B. In one possible embodiment, the detection circuit 221B is a high-pass filter. In this example, when the frequency of the output signal SO1 is greater than a second preset value (such as 11MHz), the detection circuit 221B directly outputs the output signal SO1. At this time, the detection result SD2 is equal to the output signal SO1. When the frequency of the output signal SO1 is not greater than a second preset value, the detection circuit 221B blocks the output signal SO1. At this time, the detection circuit 221B may set the detection result SD2 to be maintained at a specific level, such as a low level.
[0044] The detection circuit 221C detects the frequency of the output signal SO1. When the frequency of the output signal SO1 meets a third preset condition (such as 10 MHz), the detection circuit 221C uses the output signal SO1 as the detection result SD3. The present invention does not limit the architecture of the detection circuit 221C. In one possible embodiment, the detection circuit 221C is a high-pass filter. In this example, when the frequency of the output signal SO1 is greater than a third preset value (such as 10 MHz), the detection circuit 221C directly outputs the output signal SO1. When the frequency of the output signal SO1 is not greater than a third preset value, the detection circuit 221C filters out the output signal SO1. At this time, the detection circuit 221C may set the detection result SD3 to be equal to a specific level, such as a low level.
[0045] The judgment circuit 222A generates a control signal SC1 according to the detection result SD1. For example, when the judgment circuit 222A receives the output signal SO1, it indicates that the frequency of the output signal SO1 meets the first preset condition. Therefore, the judgment circuit 222A enables the control signal SC1. At this time, the control signal SC1 may be a first level, such as a high level. When the detection result SD1 is a specific level, it indicates that the frequency of the output signal SO1 does not meet the first preset condition. Therefore, the judgment circuit 222A does not enable the control signal SC1. At this time, the control signal SC1 may be a second level, such as a low level.
[0046] The judgment circuit 222B generates a control signal SC2 according to the detection result SD2. For example, when the judgment circuit 222B receives the output signal SO1, it indicates that the frequency of the output signal SO1 meets the second preset condition. Therefore, the judgment circuit 222B enables the control signal SC2. At this time, the control signal SC2 may be a first level, such as a high level. When the detection result SD2 is a specific level, it indicates that the frequency of the output signal SO1 does not meet the second preset condition. Therefore, the judgment circuit 222B does not enable the control signal SC2. At this time, the control signal SC2 may be a second level, such as a low level.
[0047] The judgment circuit 222C generates a control signal SC3 according to the detection result SD3. For example, when the judgment circuit 222C receives the output signal SO1, it indicates that the frequency of the output signal SO1 meets the third preset condition. Therefore, the judgment circuit 222C enables the control signal SC3. At this time, the control signal SC3 may be a first level, such as a high level. When the detection result SD3 is a specific level, it indicates that the frequency of the output signal SO1 does not meet the third preset condition. Therefore, the judgment circuit 222C does not enable the control signal SC3. At this time, the control signal SC3 may be a second level, such as a low level.
[0048] The present invention does not limit the number of detection circuits. In some embodiments, the compensation circuit 220 may have more or fewer detection circuits. Similarly, the present invention does not limit the number of determination circuits. In some embodiments, the compensation circuit 220 may have more or fewer determination circuits.
[0049] In a possible embodiment, when the signal generating circuit 210 is an LDO, the compensation circuit 220 uses a single detection circuit to detect the voltage level of the output signal SO1 and provides the detection result to the judgment circuits 222A-222C. In this example, the judgment circuits 222A-222C may be comparators for comparing the voltage level of the output signal SO1 with different reference values. For example, the judgment circuit 222A compares the voltage level of the output signal SO1 with a first reference value (e.g., 1.1V). When the voltage level of the output signal SO1 is greater than or equal to the first reference value, the judgment circuit 222A enables the control signal SC1. When the voltage level of the output signal SO1 is less than the first reference value, the judgment circuit 222A does not enable the control signal SC1. In addition, the judgment circuit 222B may compare the voltage level of the output signal SO1 with a second reference value (e.g., 1.0V). When the voltage level of the output signal SO1 is greater than or equal to the second reference value, the judgment circuit 222B enables the control signal SC2. When the voltage level of the output signal SO1 is less than the second reference value, the judgment circuit 222B does not enable the control signal SC2. In addition, the judgment circuit 222C compares the voltage level of the output signal SO1 with a third reference value (e.g., 0.9V). When the voltage level of the output signal SO1 is greater than or equal to the third reference value, the judgment circuit 222C enables the control signal SC3. When the voltage level of the output signal SO1 is less than the third reference value, the judgment circuit 222C does not enable the control signal SC3.
[0050] In other embodiments, the judgment circuits 222A-222C generate control signals No_1-No_3 according to the detection results SD1-SD3. Taking the judgment circuit 222A as an example, when the judgment circuit 222A receives the output signal SO1, it indicates that the frequency of the output signal SO1 meets the first preset condition. Therefore, the judgment circuit 222A sets the control signal No_1 to a first level, such as a high level. When the detection result SD1 is a specific level, it indicates that the frequency of the output signal SO1 does not meet the first preset condition. Therefore, the judgment circuit 222A sets the control signal No_1 to a second level, such as a low level.
[0051] The adjustment circuit 224 learns the aging degree of the signal generating circuit 210 according to the control signals No_1-No_3. In one possible embodiment, when the control signals No_1-No_3 are all at the first level, it means that the signal generating circuit 210 has not aged. Therefore, the adjustment circuit 224 does not provide the adjustment signal trim_2. In this example, the selection circuit 225 uses the initial signal trim_1 as the setting parameter SP1. However, when one of the control signals No_1-No_3 is at the second level, it means that the signal generating circuit 210 has aged. Therefore, the adjustment circuit 224 provides a suitable adjustment signal trim_2. In this example, the selection circuit 225 uses the adjustment signal trim_2 as the setting parameter SP1.
[0052] For example, when the control signal No_1 is at the second level, and the control signals No_2 and No_3 are at the first level, it indicates that the aging degree of the signal generating circuit 210 has reached the first stage (e.g., five years). Therefore, the adjustment circuit 224 sets the adjustment signal trim_2 to a first preset value. The selection circuit 225 then uses the adjustment signal trim_2 as the setting parameter SP1. When the control signals No_1 and No_2 are at the second level, and the control signal No_3 is at the first level, it indicates that the aging degree of the signal generating circuit 210 has reached the second stage (e.g., ten years). Therefore, the adjustment circuit 224 sets the adjustment signal trim_2 to a second preset value. The selection circuit 225 then uses the adjustment signal trim_2 as the setting parameter SP1.
[0053] In some embodiments, the adjustment circuit 224 sets the adjustment signal trim_2 according to the control signals SC1-SC3. For example, when the control signals SC1-SC3 are enabled, it indicates that the signal generating circuit 210 has not yet had an aging problem. Therefore, the adjustment circuit 224 does not provide the adjustment signal trim_2. In this example, the selection circuit 225 uses the initial signal trim_1 as the setting parameter SP1. When the control signal SC1 is not enabled, and the control signals SC2 and SC3 are enabled, it indicates that the aging degree of the signal generating circuit 210 has reached the first stage (such as five years). Therefore, the adjustment circuit 224 sets the adjustment signal trim_2 to a first preset value. The selection circuit 225 then uses the adjustment signal trim_2 as the setting parameter SP1. When the control signals SC1 and SC2 are not enabled, and the control signal SC3 is enabled, it indicates that the aging degree of the signal generating circuit 210 has reached the second stage (such as ten years). Therefore, the adjustment circuit 224 sets the adjustment signal trim_2 to a second preset value. The selection circuit 225 then uses the adjustment signal trim_2 as the setting parameter SP1. When the control signals SC1-SC3 are all disabled, it indicates that the aging degree of the signal generating circuit 210 has reached the third stage (e.g., fifteen years). Therefore, the adjustment circuit 224 sets the adjustment signal trim_2 to a third preset value. The selection circuit 225 then uses the adjustment signal trim_2 as the setting parameter SP1.
[0054] In a possible embodiment, the selection circuit 225 may be omitted. In this example, the adjustment signal trim_2 generated by the adjustment circuit 224 is directly used as the setting parameter SP1. For example, when the signal generating circuit 210 has not aged, the adjustment circuit 224 sets the setting parameter SP1 to a first initial value. When the aging degree of the signal generating circuit 210 reaches the first stage, the adjustment circuit 224 sets the setting parameter SP1 to a first preset value. When the aging degree of the signal generating circuit 210 reaches the second stage, the adjustment circuit 224 sets the setting parameter SP1 to a second preset value.
[0055] In other embodiments, the adjustment circuit 224 learns the aging degree of the signal generating circuit 210 according to the control signals SC1-SC3 or No_1-No_3, and provides the setting parameter SP2 according to the aging degree of the signal generating circuit 210. For example, when the signal generating circuit 210 has not yet had an aging problem. Therefore, the adjustment circuit 224 sets the setting parameter SP2 to a second initial value. When the aging degree of the signal generating circuit 210 reaches the first stage (e.g., five years), the adjustment circuit 224 sets the setting parameter SP2 to a fourth preset value. When the aging degree of the signal generating circuit 210 reaches the second stage (e.g., ten years), the adjustment circuit 224 sets the setting parameter SP2 to a fifth preset value.
[0056] The logic circuit 223 determines whether to transmit the output signal SO1 to the core circuit 230 according to the control signals SC1-SC3. When the control signals SC1-SC3 are all enabled, the logic circuit 223 transmits the output signal SO1 to the core circuit 230. When one of the control signals SC1-SC3 is not enabled, the logic circuit 223 stops transmitting the output signal SO1 to the core circuit 230.
[0057] The present invention does not limit the architecture of the logic circuit 223. In one possible embodiment, the logic circuit 223 includes logic gates LG1 and LG2. The logic gate LG1 receives control signals SC1-SC3 to generate a logic signal SL1. In one possible embodiment, when the control signals SC1-SC3 are all enabled, the logic gate LG1 enables the logic signal SL1. At this time, the logic signal SL1 may be a first level. When one of the control signals SC1-SC3 is not enabled, the logic gate LG1 does not enable the logic signal SL1. At this time, the logic signal SL1 may be a second level. In this embodiment, the logic gate LG1 is an AND gate.
[0058] The logic gate LG2 receives the output signal SO1 and the logic signal SL1 to generate a logic signal SL2. In one possible embodiment, when the logic signal SL1 is enabled, the logic gate LG2 uses the output signal SO1 as the logic signal SL2. When the logic signal SL1 is not enabled, the logic gate LG2 stops using the output signal SO1 as the logic signal SL2. At this time, the logic gate LG2 may set the logic signal SL2 to a low level.
[0059] By detecting the operating state of the signal generating circuit 210 (whether aging occurs) through the compensation circuit 220, the abnormal output signal SO1 can be immediately blocked from entering the core circuit 230. The compensation circuit 220 appropriately adjusts the setting parameter SP1 according to the operating state of the signal generating circuit 210, so that the output signal SO1 is restored to the target value. After the output signal SO1 meets the target value, the compensation circuit 220 allows the output signal SO1 to enter the core circuit 230, thereby ensuring that the core circuit 230 operates normally.
[0060] Figure 3 FIG. 1 is a flow chart of the compensation method of the present invention. The compensation method of the present invention can be performed by Figure 1 or Figure 2 In addition, the compensation method of the present invention can be implemented by program code. When the program code is loaded and executed by a machine, the machine becomes a compensation circuit or a control circuit for implementing the present invention.
[0061] First, a first output signal output by a first signal generating circuit is detected to generate a detection result (step S311). In one possible embodiment, the first signal generating circuit sets the electrical characteristics of the first output signal, such as voltage, current, frequency, or amplitude, according to a first setting parameter. In some embodiments, step S311 determines whether the frequency of the first output signal reaches a target value. When the frequency of the first output signal reaches the target value, the first output signal is used as the detection result. When the frequency of the first output signal does not reach the target value, stop using the first output signal as the detection result. In one possible embodiment, when the frequency of the first output signal does not reach the target value, step S311 sets the detection result equal to a specific level.
[0062] Determine whether the detection result meets a preset condition (step S312). When the detection result meets the preset condition, it means that the electrical characteristics of the first output signal meet a target value. Therefore, the first output signal is allowed to enter the core circuit (step S313). The core circuit operates according to the first output signal (such as a clock signal).
[0063] When the detection result does not meet the preset condition, it means that the electrical characteristics of the first output signal do not meet a target value. Therefore, the first output signal is blocked from entering the core circuit (step 314), and the first setting parameter is adjusted (step S315). In one possible embodiment, the first signal generating circuit adjusts the electrical characteristics of the first output signal according to the adjusted first setting parameter. In some embodiments, when the core circuit does not receive the first output signal, the core circuit may suspend operation.
[0064] In other embodiments, step S315 further provides a second setting parameter to a second signal generating circuit. In this example, the second signal generating circuit generates a second output signal to the core circuit according to the second setting parameter. In one possible embodiment, step S314 blocks the first output signal from entering the core circuit, but the core circuit continues to receive the second output signal. In another possible embodiment, step S314 also blocks the second output signal from entering the core circuit.
[0065] It should be understood that when an element or layer is referred to as being "coupled" to another element or layer, it may be directly coupled or connected to the other element or layer, or have other elements or layers intervening therebetween. Conversely, if an element or layer is "connected" to another element or layer, there will be no other elements or layers intervening therebetween. In addition, "enable" shall mean changing the state of a Boolean signal. Boolean signals can be enabled to be high or have a higher voltage, and Boolean signals can be enabled to be low or have a lower voltage at the discretion of the circuit designer. Similarly, "disable" shall mean changing the state of a Boolean signal to a voltage level opposite to the enabled state.
[0066] The compensation method of the present invention, or a specific form or part thereof, may exist in the form of program code. The program code may be stored in a physical medium, such as a floppy disk, a CD, a hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product not limited to an external form, wherein when the program code is loaded and executed by a machine, such as a computer, the machine becomes used to participate in the compensation circuit and control circuit of the present invention. The program code may also be transmitted through some transmission medium, such as wires or cables, optical fibers, or any transmission form, wherein when the program code is received, loaded and executed by a machine, such as a computer, the machine becomes used to participate in the compensation circuit and control circuit of the present invention. When implemented in a general-purpose processing unit, the program code combines with the processing unit to provide a unique device that operates similarly to an application-specific logic circuit.
[0067] Unless otherwise defined, all words (including technical and scientific words) herein are generally understood by those skilled in the art. In addition, unless expressly indicated, the definitions of words in general dictionaries should be interpreted as consistent with the meanings in articles in the relevant technical field, and should not be interpreted as ideal or overly formal. Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.
[0068] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. For example, the system, device or method described in the embodiments of the present invention may be implemented in a physical embodiment of hardware, software or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the attached claims.
Claims
1. A compensation circuit, characterized in that: The invention is used to compensate an output signal generated by a signal generating circuit, and comprises: a detection circuit, detecting the output signal to generate a detection result; A judging circuit, for judging whether the detection result meets a preset condition, and generating a control signal; a logic circuit, which blocks the output signal from entering a core circuit when the detection result does not meet the preset condition; and an adjustment circuit, which provides a setting parameter when the detection result does not meet the preset condition; in: The signal generating circuit adjusts the output signal according to the set parameter; When the detection result meets the preset condition, the logic circuit allows the output signal to enter the core circuit.
2. The compensation circuit according to claim 1, characterized in that: The detection circuit is a high-pass filter. When the frequency of the output signal reaches a target value, the high-pass filter provides the output signal as the detection result to the judgment circuit. When the frequency of the output signal does not reach the target value, the high-pass filter blocks the output signal from entering the judgment circuit.
3. The compensation circuit according to claim 2, characterized in that: When the output signal enters the judgment circuit, the judgment circuit commands the logic circuit to allow the output signal to enter the core circuit; when the output signal does not enter the judgment circuit, the judgment circuit commands the logic circuit to block the output signal from entering the core circuit.
4. The compensation circuit according to claim 1, characterized in that: The detection circuit is a voltage detection circuit for detecting the voltage of the output signal.
5. The compensation circuit according to claim 4, characterized in that: When the voltage of the output signal does not reach a preset voltage, the judgment circuit commands the logic circuit to block the output signal from entering the core circuit. When the voltage of the output signal reaches the preset voltage, the judgment circuit commands the logic circuit to allow the output signal to enter the core circuit.
6. A control circuit, characterized in that: include: A first signal generating circuit generates a first output signal according to a first setting parameter; a core circuit, receiving the first output signal; as well as A compensation circuit comprising: a detection circuit, detecting the first output signal to generate a first detection result; a judgment circuit, for judging whether the first detection result meets a first preset condition; a logic circuit, which blocks the first output signal from entering the core circuit when the first detection result does not meet the first preset condition; and an adjustment circuit, which adjusts the first setting parameter when the first detection result does not meet the first preset condition; When the first detection result meets the first preset condition, the logic circuit allows the first output signal to enter the core circuit.
7. The control circuit according to claim 6, characterized in that: Also includes: a second signal generating circuit, generating a second output signal according to a second setting parameter and sending it to the core circuit; When the first detection result does not meet the first preset condition, the adjustment circuit adjusts the second setting parameter.
8. The control circuit according to claim 7, characterized in that: The first signal generating circuit is a frequency generating circuit, and the second signal generating circuit is a voltage regulator.
9. The control circuit according to claim 8, characterized in that: When the logic circuit blocks the first output signal from entering the core circuit, the second signal generating circuit continues to provide the second output signal to the core circuit.
10. A compensation method, characterized in that: include: Detecting an output signal output by a signal generating circuit to generate a detection result, wherein the signal generating circuit sets the output signal according to a setting parameter; Determining whether the test result meets a preset condition; When the detection result does not meet the preset condition, blocking the output signal from entering a core circuit and adjusting the setting parameter; as well as When the detection result meets the preset condition, the output signal is allowed to enter the core circuit.