Circuit for resisting digital IO (input / output) upset noise

Abstract

The invention discloses an anti-digital IO flip noise circuit, which relates to the field of integrated circuit design, and comprises a first power supply noise sensitive circuit, a second power supply noise sensitive circuit, a first isolation unit I1, a second isolation unit I2, a first digital IO output driving circuit and a second digital IO output driving circuit, the first power supply noise sensitive circuit is connected with the first digital IO output driving circuit through a first isolation unit I1; and the second power supply noise sensitive circuit is connected with the first digital IO output driving circuit through a second isolation unit I2. According to the invention, the isolation unit is inserted between the last-stage output inverter of the sensitive circuit power domain and the output driving inverter of the digital IO driving power domain, so that the problem of crosstalk of switching noise generated on a power supply / the ground when a plurality of IOs of a chip are turned over at the same time to a digital signal normally output by the IOs is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a digital IO flip noise resistant circuit. Background Art

[0002] In processor-type chips, digital IO is responsible for enhancing the logic signal output drive capability and identifying external input logic signals. Due to the instantaneous change of driving current when digital IO flips, an instantaneous ringing signal will be generated on the parasitic inductance of the chip power and ground binding lines. This signal is usually called IO flip noise. The amplitude of this flip noise increases as the number of IOs flipped at the same time increases. In order to reduce the impact of this flip noise on sensitive circuits, it is usually necessary to separate the sensitive circuit power / ground from the IO driver power / ground, such as Figure 1 A simplified circuit model of the prior art is shown.

[0003] The disadvantage of the prior art is that when the power / ground flip noise interference reaches a certain amplitude, it will affect the stability of the normal digital signal output level. Figure 1 As shown in the figure, when the IO PAD needs to output a fixed 0 level, the sensitive circuit power domain device MN4 turns on and outputs a non-interference 0 level. Under normal circumstances, the inverter formed by MN2 and MP2 outputs a non-interference 1 level to turn off the output driver MP0. When multiple digital IOs flip at the same time, the large interference on the digital IO drive power supply will turn on the output driver MP0, resulting in abnormal high pulses on the PAD.

[0004] Therefore, there is currently a problem that when multiple IOs of the chip flip at the same time, the large switching noise crosstalk generated affects the digital signal output.

[0005] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims of this application and are not admitted to be prior art by inclusion in this section. Summary of the invention

[0006] In view of the above technical problems in the related art, the present invention proposes an anti-digital IO flip noise circuit, which includes a first power supply noise sensitive circuit, a second power supply noise sensitive circuit, a first isolation unit I1, a second isolation unit I2, a first digital IO output driving circuit and a second digital IO output driving circuit; the first power supply noise sensitive circuit and the second power supply noise sensitive circuit constitute an internal sensitive logic signal generation channel; the first digital IO output driving circuit and the second digital IO output driving circuit constitute an IO PAD output stage;

[0007] The first power supply noise sensitive circuit is connected to the first digital IO output driving circuit through the first isolation unit I1; the second power supply noise sensitive circuit is connected to the first digital IO output driving circuit through the second isolation unit I2; the power supply and ground of the first isolation unit I1 and the second isolation unit I2 need to be connected to the digital IO driving power supply and the digital IO driving ground respectively; the power supply and ground of the first isolation unit I1 and the second isolation unit I2 are connected to the digital IO driving power supply and the digital IO driving ground respectively;

[0008] The first isolation unit I1 includes: a first resistor R0, a first interference noise feedback path, and a first forward signal path; the first power supply noise sensitive circuit is connected to the first interference noise feedback path and the first forward signal path through the first resistor R0; at the same time, the first interference noise feedback path and the first forward signal path are connected to the first digital IO output drive circuit;

[0009] The second isolation unit I2 includes: a second resistor R1, a second interference noise feedback path, and a second forward signal path; the second power supply noise sensitive circuit is connected to the second interference noise feedback path and the second forward signal path respectively through the second resistor R1; at the same time, the second interference noise feedback path and the second forward signal path are connected to the second digital IO output drive circuit.

[0010] Specifically, the first interference noise feedback path is composed of a first isolation transistor XMP1 and a second isolation transistor XMN1; the source end of the first isolation transistor XMP1 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the second isolation transistor XMN1 and then connected to the first digital IO output drive circuit, the drain end is connected to the drain end of the second isolation transistor XMN1 and then connected to the first resistor R0; the source end of the second isolation transistor XMN1 is connected to the digital I0 drive ground.

[0011] Specifically, the first forward signal path is composed of a third isolation transistor XMP2 and a fourth isolation transistor XMN2; the source end of the third isolation transistor XMP2 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the fourth isolation transistor XMN2 and then connected to the first resistor R0, the drain end is connected to the drain end of the second isolation transistor XMN1 and then connected to the first digital IO output drive circuit; the source end of the fourth isolation transistor XMN2 is connected to the digital I0 drive ground.

[0012] Specifically, the second interference noise feedback path is composed of a fifth isolation transistor XMP3 and a sixth isolation transistor XMN3; the source end of the fifth isolation transistor XMP3 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the sixth isolation transistor XMN3 and then connected to the second digital IO output drive circuit, the drain end is connected to the drain end of the sixth isolation transistor XMN3 and then connected to the second resistor R1; the source end of the sixth isolation transistor XMN3 is connected to the digital I0 drive ground.

[0013] Specifically, the second forward signal path is composed of a seventh isolation transistor XMP4 and an eighth isolation transistor XMN4; the source terminal of the seventh isolation transistor XMP4 is connected to the digital IO drive power supply, the gate terminal is connected to the gate terminal of the eighth isolation transistor XMN4 and then connected to the second resistor R1, the drain terminal is connected to the drain terminal of the eighth isolation transistor XMN4 and then connected to the second digital IO output drive circuit; the source terminal of the eighth isolation transistor XMN4 is connected to the digital I0 drive ground.

[0014] Specifically, the anti-digital IO flip noise circuit also includes: a first IO driving tube MN0 and a second IO driving tube MP0; the source end of the first IO driving tube MN0 is connected to the digital IO driving ground, the gate end is connected to the first digital IO output driving circuit, and the drain end is connected to the drain end of the second IO driving tube MP0 and then output to the IO PAD; the source end of the second IO driving tube MP0 is connected to the digital IO driving power supply, and the gate end is connected to the second digital IO output driving circuit.

[0015] Specifically, the first power supply noise sensitive circuit includes a fifth power supply transistor MP3, a sixth power supply transistor MN3 and a sensitive circuit digital signal output; the source end of the fifth power supply transistor MP3 is connected to the sensitive circuit power supply, the gate end is connected to the gate end of the sixth power supply transistor MN3 and then connected to the sensitive circuit digital signal output, the drain end is connected to the drain end of the sixth power supply transistor MN3 and then connected to the first isolation unit I1; the source end of the sixth power supply transistor MN3 is connected to the sensitive power ground;

[0016] The first digital IO output drive circuit includes a first power transistor MP1 and a second power transistor MN1; the source end of the first power transistor MP1 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the second power transistor MN1 and then connected to the first isolation unit I1, the drain end is connected to the drain end of the second power transistor MN1 and then connected to MN0; the source end of the second power transistor MN1 is connected to the digital I0 drive ground.

[0017] Specifically, the second power supply noise sensitive circuit includes a seventh power supply transistor MP4, an eighth power supply transistor MN4 and a sensitive circuit digital signal output; the source terminal of the seventh power supply transistor MP4 is connected to the sensitive circuit power supply, the gate terminal is connected to the gate terminal of the eighth power supply transistor MN4 and then connected to the sensitive circuit digital signal output, the drain terminal is connected to the drain terminal of the eighth power supply transistor MN4 and then connected to the second isolation unit I2; the source terminal of the eighth power supply transistor MN4 is connected to the sensitive power ground;

[0018] The second digital IO output drive circuit includes a third power transistor MP2 and a fourth power transistor MN2; the source end of the third power transistor MP2 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the fourth power transistor MN2 and then connected to the second isolation unit I2, the drain end is connected to the drain end of the fourth power transistor MN2 and then connected to MP0; the source end of the fourth power transistor MN2 is connected to the digital I0 drive ground.

[0019] Specifically, when the IO PAD output is logic 0, the gate of the second power transistor MN1 is associated with the digital IO driving ground, so that when there is IO flip noise interference at the source level of the second power transistor MN1, the flip noise interference signal can be fed back to the gate level of the second power transistor MN1 in time, thereby maintaining the gate-source voltage difference of the second power transistor MN1 below the turn-on threshold, and the second power transistor MN1 remains turned off;

[0020] When the IO PAD output is logic 1, the gate of the first power transistor MP1 is associated with the digital IO driving power supply, so that when there is IO flip noise interference at the source level of the first power transistor MP1, the flip noise interference signal can be fed back to the gate level of the first power transistor MP1 in time, thereby maintaining the gate-source voltage difference of the first power transistor MP1 below the turn-on threshold, and the first power transistor MP1 remains turned off.

[0021] Specifically, when the IO PAD output is logic 0, the gate of the fourth power transistor MN2 is associated with the digital IO driving ground, so that when there is IO flip noise interference at the source of the fourth power transistor MN2, the flip noise interference signal can be fed back to the gate of the fourth power transistor MN2 in time, thereby maintaining the gate-source voltage difference of the fourth power transistor MN2 below the turn-on threshold, and the fourth power transistor MN2 remains turned off;

[0022] When the IO PAD output is logic 1, the gate of the third power transistor MP2 is associated with the digital IO driving power supply, so that when there is IO flip noise interference at the source level of the third power transistor MP2, the flip noise interference signal can be fed back to the gate level of the third power transistor MP2 in time, thereby maintaining the gate-source voltage difference of the third power transistor MP2 below the turn-on threshold, and the third power transistor MP2 remains turned off.

[0023] The digital IO flip noise resistance circuit of the present invention effectively reduces the problem of crosstalk on the normal output digital signal of the IO caused by the switching noise on the power supply / ground when multiple IOs of the chip flip simultaneously.

[0024] Furthermore, the isolation unit of the present invention reduces the crosstalk effect of the digital IO driving power supply / ground on the sensitive circuit power supply / ground by increasing the isolation resistance; at the same time, the feedback response speed of the transistor gate in the isolation unit to the digital IO driving power supply / ground noise is enhanced, thereby optimizing the overall performance of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 1 is a schematic diagram of a conventional circuit structure for resisting digital IO upset noise provided according to an embodiment of the present invention;

[0027] Figure 2 1 is a schematic diagram of a circuit structure for resisting digital IO upset noise provided according to an embodiment of the present invention;

[0028] Figure 3 It is a schematic diagram of a digital IO flip noise resistance circuit and an isolation circuit structure provided according to an embodiment of the present invention;

[0029] Figure 4 The present invention is a schematic diagram of a structure in which a sensitive circuit is added to an anti-digital IO flip noise circuit and an isolation circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0031] Embodiment 1

[0032] refer to Figure 2-3This embodiment provides a digital IO flip noise resistance circuit, which includes a first power supply noise sensitive circuit, a second power supply noise sensitive circuit, a first isolation unit I1, a second isolation unit I2, a first digital IO output drive circuit and a second digital IO output drive circuit; the first power supply noise sensitive circuit and the second power supply noise sensitive circuit constitute an internal sensitive logic signal generation channel; the first digital IO output drive circuit and the second digital IO output drive circuit constitute an IO PAD output stage;

[0033] The first power supply noise sensitive circuit is connected to the first digital IO output driving circuit through the first isolation unit I1; the second power supply noise sensitive circuit is connected to the first digital IO output driving circuit through the second isolation unit I2; the power supply and ground of the first isolation unit I1 and the second isolation unit I2 need to be connected to the digital IO driving power supply and the digital IO driving ground respectively; the power supply and ground of the first isolation unit I1 and the second isolation unit I2 are connected to the digital IO driving power supply and the digital IO driving ground respectively;

[0034] The anti-digital IO flip noise circuit also includes: a first IO driving tube MN0, a second IO driving tube MP0, a sensitive circuit power supply, a sensitive circuit ground, a digital IO driving power supply, a digital IO driving ground and an IO PAD; the power supply and ground of the first power supply noise sensitive circuit and the second power supply noise sensitive circuit are respectively connected to the sensitive power supply and the sensitive power supply ground; the power supply and ground of the first digital IO output driving circuit and the second digital IO output driving circuit are respectively connected to the digital IO driving power supply and the digital IO driving ground; the source end of the first IO driving tube MN0 is connected to the digital IO driving ground, the gate end is connected to the first digital IO output driving circuit, the drain end is connected to the drain end of the second IO driving tube MP0 and then output to the IO PAD; the source end of the second IO driving tube MP0 is connected to the digital IO driving power supply, and the gate end is connected to the second digital IO output driving circuit.

[0035] A first isolation unit I1 and a second isolation unit I2 are inserted between the last output inverter of the sensitive circuit power domain and the output driver inverter of the digital IO driver power domain.

[0036] The first isolation unit I1 is composed of a first resistor R0, a first interference noise feedback path, and a first forward signal path; the first output inverter is connected to the first interference noise feedback path and the first forward signal path respectively through the first resistor R0; at the same time, the first interference noise feedback path and the first forward signal path are connected to the first output drive inverter;

[0037] The power supply and ground of the first isolation unit I1 are connected to the digital IO driving power supply and the digital IO driving ground respectively;

[0038] Specifically, the first interference noise feedback path is composed of a first isolation transistor XMP1 and a second isolation transistor XMN1; the source end of the first isolation transistor XMP1 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the second isolation transistor XMN1 and then connected to the first output drive inverter, the drain end is connected to the drain end of the second isolation transistor XMN1 and then connected to the first resistor R0; the source end of the second isolation transistor XMN1 is connected to the digital I0 drive ground;

[0039] The first isolation transistor XMP1 and the second isolation transistor XMN1 form a digital IO driving power supply / digital IO driving ground interference noise feedback path of the first isolation unit I1.

[0040] The first forward signal path is formed by a third isolation transistor XMP2 and a fourth isolation transistor XMN2; the source end of the third isolation transistor XMP2 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the fourth isolation transistor XMN2 and then connected to the first resistor R0, the drain end is connected to the drain end of the second isolation transistor XMN1 and then connected to the first output drive inverter; the source end of the fourth isolation transistor XMN2 is connected to the digital I0 drive ground;

[0041] The third isolation transistor XMP2 and the fourth isolation transistor XMN2 form a first forward signal path for forward transmission of digital logic signals.

[0042] The first resistor R0 is the sensitive power domain isolation resistor of the first isolation unit I1; the larger the resistance of the first resistor R0, the less crosstalk between the sensitive power supply / ground and the digital IO driving power supply / ground, the faster the isolation unit effect speed, and the stronger the overall anti-interference ability of the system.

[0043] The fifth power transistor MP3, the sixth power transistor MN3 and the sensitive circuit digital signal output constitute a first output inverter; the source terminal of the fifth power transistor MP3 is connected to the sensitive circuit power supply, the gate terminal is connected to the gate terminal of the sixth power transistor MN3 and then connected to the sensitive circuit digital signal output, the drain terminal is connected to the drain terminal of the sixth power transistor MN3 and then connected to the first isolation unit I1; the source terminal of the sixth power transistor MN3 is connected to the sensitive power ground;

[0044] The first power supply noise sensitive circuit includes a first output inverter;

[0045] The first power transistor MP1 and the second power transistor MN1 form a first output drive inverter; the source end of the first power transistor MP1 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the second power transistor MN1 and then connected to the first isolation unit I1, the drain end is connected to the drain end of the second power transistor MN1 and then connected to MN0; the source end of the second power transistor MN1 is connected to the digital I0 drive ground;

[0046] The first digital IO output drive circuit includes a first output drive inverter;

[0047] The first isolation unit I1 realizes the function: when the subsequent driver makes the IO PAD output a logic 0, the first isolation unit I1 realizes associating the gate of the second power transistor MN1 with the digital IO drive ground, so that when there is IO flip noise interference at the source level of the second power transistor MN1, the flip noise interference signal can be fed back to the gate of the second power transistor MN1 in time, thereby maintaining the gate-source voltage difference of the second power transistor MN1 below the conduction threshold, and the second power transistor MN1 remains turned off, avoiding misleading output of a low level to the gate of MN0, causing MN0 to be mistakenly turned off, and forming a short-time high pulse interference to the IO PAD output logic 0.

[0048] On the contrary, when the subsequent driver makes the IO PAD output a logic 1, the first isolation unit I1 associates the gate of the first power transistor MP1 with the digital IO driving power supply, so that when there is IO flip noise interference at the source level of the first power transistor MP1, the flip noise interference signal can be fed back to the gate of the first power transistor MP1 in time, thereby maintaining the gate-source voltage difference of the first power transistor MP1 below the conduction threshold, and the first power transistor MP1 remains turned off, avoiding misleading output of a high level to the gate of MN0, causing misleading conduction of MN0, and forming a short-time low pulse interference to the IO PAD output logic 1.

[0049] The second isolation unit I2 is composed of a second resistor R1, a second interference noise feedback path, and a second forward signal channel; the second output inverter is connected to the second interference noise feedback path and the second forward signal channel respectively through the second resistor R1; at the same time, the second interference noise feedback path and the second forward signal channel are connected to the second output drive inverter.

[0050] The power supply and ground of the second isolation unit I2 need to be connected to the digital IO driving power supply and the digital IO driving ground respectively;

[0051] Specifically, the second interference noise feedback path is composed of a fifth isolation transistor XMP3 and a sixth isolation transistor XMN3; the source end of the fifth isolation transistor XMP3 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the sixth isolation transistor XMN3 and then connected to the second output drive inverter, the drain end is connected to the drain end of the sixth isolation transistor XMN3 and then connected to the second resistor R1; the source end of the sixth isolation transistor XMN3 is connected to the digital I0 drive ground;

[0052] The second pre-positive signal channel is composed of a seventh isolation transistor XMP4 and an eighth isolation transistor XMN4; the source end of the seventh isolation transistor XMP4 is connected to the digital IO driving power supply, the gate end is connected to the gate end of the eighth isolation transistor XMN4 and then connected to the second resistor R1, the drain end is connected to the drain end of the eighth isolation transistor XMN4 and then connected to the second output driving inverter; the source end of the eighth isolation transistor XMN4 is connected to the digital I0 driving ground;

[0053] The seventh isolation transistor XMP4 and the eighth isolation transistor XMN4 form a second forward signal channel for forward transmission of digital logic signals.

[0054] The second resistor R1 is a sensitive power domain isolation resistor of the second isolation unit I2;

[0055] The second resistor R1 is the sensitive power domain isolation resistor of the second isolation unit I2; the larger the resistance value of the second resistor R1, the less crosstalk between the sensitive power supply / ground and the digital IO driving power supply / ground, the faster the isolation unit effect speed, and the stronger the overall anti-interference ability of the system.

[0056] The fifth isolation transistor XMP3 and the sixth isolation transistor XMN3 constitute a digital IO driving power supply / digital IO driving ground interference noise feedback path of the second isolation unit I2;

[0057] The seventh power transistor MP4, the eighth power transistor MN4 and the sensitive circuit digital signal output form a second output inverter; the source terminal of the seventh power transistor MP4 is connected to the sensitive circuit power supply, the gate terminal is connected to the gate terminal of the eighth power transistor MN4 and then connected to the sensitive circuit digital signal output, the drain terminal is connected to the drain terminal of the eighth power transistor MN4 and then connected to the second resistor R1 of the second isolation unit I2; the source terminal of the eighth power transistor MN4 is connected to the sensitive power ground;

[0058] The second power supply noise sensitive circuit includes a second output inverter;

[0059] refer to Figure 4 In a specific implementation manner provided in this embodiment, a sensitive circuit may be added to the first output inverter and / or the second output inverter.

[0060] The sensitive circuit is respectively connected to the sensitive circuit power supply and the sensitive power supply ground, and provides a digital signal output; the digital signal output of the sensitive circuit is used as the digital signal output of the sensitive circuit;

[0061] The sensitive circuit can be a weak signal amplification circuit, a reference voltage circuit or a reference current circuit, etc. All circuits sensitive to voltage or current are protected. The selection of sensitive circuits is determined according to specific task requirements and is not specifically limited here.

[0062] The sensitive circuits added to the first output inverter and the second output inverter may be the same or different, which is not limited here.

[0063] The second output drive inverter is composed of a third power transistor MP2 and a fourth power transistor MN2; the source end of the third power transistor MP2 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the fourth power transistor MN2 and then connected to the second isolation unit I2, the drain end is connected to the drain end of the fourth power transistor MN2 and then connected to MP0; the source end of the fourth power transistor MN2 is connected to the digital I0 drive ground;

[0064] The second digital IO output drive circuit includes a first output drive inverter;

[0065] Specifically, the first output inverter and the second output inverter are the last-stage output inverters of the sensitive circuit power domain;

[0066] Specifically, the first output drive inverter and the second output drive inverter are digital IO drive power domain output drive inverters;

[0067] The second isolation unit I2 realizes the function: when the subsequent driver makes the IO PAD output a logic 0, the second isolation unit I2 realizes associating the gate of the fourth power supply transistor MN2 with the digital IO drive ground, so that when there is IO flip noise interference at the source level of the fourth power supply transistor MN2, the flip noise interference signal can be fed back to the gate level of the fourth power supply transistor MN2 in time, thereby maintaining the gate-source voltage difference of the fourth power supply transistor MN2 below the conduction threshold, and the fourth power supply transistor MN2 remains turned off, avoiding misleading output of a low level to the MP0 gate, causing misleading conduction of MP0, and forming a short-time high pulse interference to the IO PAD output logic 0. On the contrary, when the subsequent driver makes the IO PAD output logic 1, the second isolation unit I2 associates the gate of the third power transistor MP2 with the digital IO driving power supply, so that when there is IO flip noise interference at the source level of the third power transistor MP2, the flip noise interference signal can be fed back to the gate of the third power transistor MP2 in time, so as to maintain the gate-source voltage difference of the third power transistor MP2 below the conduction threshold, and the third power transistor MP2 remains turned off, avoiding mis-conduction of the output high level to the MP0 gate, causing the MP0 to be mistakenly turned off, and forming a short-time low pulse interference to the IO PAD output logic 1.

[0068] The second IO driving transistor MP0, the first power transistor MP1, the third power transistor MP2, the fifth power transistor MP3, and the seventh power transistor MP4 are PMOS transistors; the first IO driving transistor MN0, the second power transistor MN1, the fourth power transistor MN2, the sixth power transistor MN3, and the eighth power transistor MN4 are NMOS transistors;

[0069] The first isolation transistor XMP1, the third isolation transistor XMP2, the fifth isolation transistor XMP3, and the seventh isolation transistor XMP4 are PMOS transistors; the second isolation transistor XMN1, the fourth isolation transistor XMN2, the sixth isolation transistor XMN3, and the eighth isolation transistor XMN4 are NMOS transistors;

[0070] This embodiment does not limit the type or specification of the first resistor R0 or the second resistor R1 , and other resistive devices with resistive characteristics are all protected.

[0071] When the IO PAD output is logic 0, the second isolation transistor XMN1 is turned on, and the gate of the fourth isolation transistor XMN2 is connected to the digital IO drive ground through the second isolation transistor XMN1 to prevent the interference noise on the IO drive ground from misleadingly turning on the fourth isolation transistor XMN2; at the same time, the sixth isolation transistor XMN3 is turned on, and the gate of the eighth isolation transistor XMN4 is connected to the digital IO drive ground through the sixth isolation transistor XMN3 to prevent the interference noise on the IO drive ground from misleadingly turning on the eighth isolation transistor XMN4.

[0072] When the IO PAD output is logic 1, the first isolation transistor XMP1 is turned on, and the gate of the third isolation transistor XMP2 is connected to the digital IO drive power supply through the first isolation transistor XMP1 to prevent the interference noise on the IO drive power supply from misleadingly turning on the third isolation transistor XMP2; at the same time, the fifth isolation transistor XMP3 is turned on, and the gate of the seventh isolation transistor XMP4 is connected to the digital IO drive power supply through the fifth isolation transistor XMP3 to prevent the interference noise on the IO drive ground from misleadingly turning on the seventh isolation transistor XMP4.

[0073] Since the first isolation transistor XMP1 and the fifth power transistor MP3, the fifth isolation transistor XMP3 and the seventh power transistor MP4, the second isolation transistor XMN1 and the sixth power transistor MN3, and the sixth isolation transistor XMN3 and the eighth power transistor MN4 are turned on at the same time, it is necessary to increase the isolation resistors R0 and R1 to reduce the crosstalk effect of the digital IO drive power supply / ground on the sensitive circuit power supply / ground, and at the same time improve the feedback response speed of the gate of the third isolation transistor XMP2 / the fourth isolation transistor XMN2, the seventh isolation transistor XMP4 / the eighth isolation transistor XMN4 to the noise interference of the digital IO drive power supply / ground.

[0074] The digital IO flip noise resistance circuit of this embodiment effectively reduces the crosstalk problem of the switching noise generated on the power supply / ground when multiple IOs of the chip flip simultaneously on the normal output digital signal of the IO.

[0075] Furthermore, the isolation unit of this embodiment reduces the crosstalk effect of the digital IO driving power supply / ground on the sensitive circuit power supply / ground by increasing the isolation resistance; at the same time, it enhances the feedback response speed of the transistor gate in the isolation unit to the digital IO driving power supply / ground noise, thereby optimizing the overall performance of the circuit.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital IO flip noise resistance circuit, comprising a first power supply noise sensitive circuit, a second power supply noise sensitive circuit, a first isolation unit I1, a second isolation unit I2, a first digital IO output drive circuit and a second digital IO output drive circuit; The first power supply noise sensitive circuit and the second power supply noise sensitive circuit constitute an internal sensitive logic signal generation channel; the first digital IO output drive circuit and the second digital IO output drive circuit constitute an IO PAD output stage; characterized in that: The first power supply noise sensitive circuit is connected to the first digital IO output driving circuit through the first isolation unit I1; the second power supply noise sensitive circuit is connected to the first digital IO output driving circuit through the second isolation unit I2; the power supply and ground of the first isolation unit I1 and the second isolation unit I2 need to be connected to the digital IO output driving power supply and the digital IO output driving ground respectively; The first isolation unit I1 includes: a first resistor R0, a first interference noise feedback path, and a first forward signal path; the first power supply noise sensitive circuit is connected to the first interference noise feedback path and the first forward signal path through the first resistor R0; at the same time, the first interference noise feedback path and the first forward signal path are connected to the first digital IO output drive circuit; The second isolation unit I2 includes: a second resistor R1, a second interference noise feedback path, and a second forward signal path; the second power supply noise sensitive circuit is connected to the second interference noise feedback path and the second forward signal path respectively through the second resistor R1; at the same time, the second interference noise feedback path and the second forward signal path are connected to the second digital IO output drive circuit.

2. The circuit for resisting digital IO upset noise according to claim 1, characterized in that: The first interference noise feedback path is composed of a first isolation transistor XMP1 and a second isolation transistor XMN1; the source end of the first isolation transistor XMP1 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the second isolation transistor XMN1 and then connected to the first digital IO output drive circuit, the drain end is connected to the drain end of the second isolation transistor XMN1 and then connected to the first resistor R0; the source end of the second isolation transistor XMN1 is connected to the digital I0 drive ground.

3. The circuit for resisting digital IO upset noise according to claim 2, characterized in that: The first forward signal path is composed of a third isolation transistor XMP2 and a fourth isolation transistor XMN2; the source end of the third isolation transistor XMP2 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the fourth isolation transistor XMN2 and then connected to the first resistor R0, the drain end is connected to the drain end of the second isolation transistor XMN1 and then connected to the first digital IO output drive circuit; the source end of the fourth isolation transistor XMN2 is connected to the digital I0 drive ground.

4. The circuit for resisting digital IO upset noise according to claim 3, characterized in that: The second interference noise feedback path is composed of a fifth isolation transistor XMP3 and a sixth isolation transistor XMN3; the source end of the fifth isolation transistor XMP3 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the sixth isolation transistor XMN3 and then connected to the second digital IO output drive circuit, the drain end is connected to the drain end of the sixth isolation transistor XMN3 and then connected to the second resistor R1; the source end of the sixth isolation transistor XMN3 is connected to the digital I0 drive ground.

5. The circuit for resisting digital IO upset noise according to claim 4, characterized in that: The second forward signal path is composed of a seventh isolation transistor XMP4 and an eighth isolation transistor XMN4; the source end of the seventh isolation transistor XMP4 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the eighth isolation transistor XMN4 and then connected to the second resistor R1, the drain end is connected to the drain end of the eighth isolation transistor XMN4 and then connected to the second digital IO output drive circuit; the source end of the eighth isolation transistor XMN4 is connected to the digital I0 drive ground.

6. The circuit for resisting digital IO upset noise according to claim 5, characterized in that: The anti-digital IO flip noise circuit also includes: a first IO driving tube MN0 and a second IO driving tube MP0; the source end of the first IO driving tube MN0 is connected to the digital IO driving ground, the gate end is connected to the first digital IO output driving circuit, and the drain end is connected to the drain end of the second IO driving tube MP0 and then output to the IO PAD; the source end of the second IO driving tube MP0 is connected to the digital IO driving power supply, and the gate end is connected to the second digital IO output driving circuit.

7. The circuit for resisting digital IO upset noise according to claim 6, characterized in that: The first power supply noise sensitive circuit includes a fifth power supply transistor MP3, a sixth power supply transistor MN3 and a sensitive circuit digital signal output; the source end of the fifth power supply transistor MP3 is connected to the sensitive circuit power supply, the gate end is connected to the gate end of the sixth power supply transistor MN3 and then connected to the sensitive circuit digital signal output, the drain end is connected to the drain end of the sixth power supply transistor MN3 and then connected to the first isolation unit I1; the source end of the sixth power supply transistor MN3 is connected to the sensitive power ground; The first digital IO output drive circuit includes a first power transistor MP1 and a second power transistor MN1; the source end of the first power transistor MP1 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the second power transistor MN1 and then connected to the first isolation unit I1, the drain end is connected to the drain end of the second power transistor MN1 and then connected to MN0; the source end of the second power transistor MN1 is connected to the digital I0 drive ground.

8. The circuit for resisting digital IO upset noise according to claim 7, characterized in that: The second power supply noise sensitive circuit includes a seventh power supply transistor MP4, an eighth power supply transistor MN4 and a sensitive circuit digital signal output; the source terminal of the seventh power supply transistor MP4 is connected to the sensitive circuit power supply, the gate terminal is connected to the gate terminal of the eighth power supply transistor MN4 and then connected to the sensitive circuit digital signal output, the drain terminal is connected to the drain terminal of the eighth power supply transistor MN4 and then connected to the second isolation unit I2; the source terminal of the eighth power supply transistor MN4 is connected to the sensitive power ground; The second digital IO output drive circuit includes a third power transistor MP2 and a fourth power transistor MN2; the source end of the third power transistor MP2 is connected to the digital IO drive power supply, the gate end is connected to the gate end of the fourth power transistor MN2 and then connected to the second isolation unit I2, the drain end is connected to the drain end of the fourth power transistor MN2 and then connected to MP0; the source end of the fourth power transistor MN2 is connected to the digital I0 drive ground.

9. The circuit for resisting digital IO upset noise according to claim 8, characterized in that: When the IO PAD output is logic 0, the gate of the second power transistor MN1 is associated with the digital IO driving ground, so that when there is IO flip noise interference at the source of the second power transistor MN1, the flip noise interference signal can be fed back to the gate of the second power transistor MN1 in time, thereby maintaining the gate-source voltage difference of the second power transistor MN1 below the turn-on threshold, and the second power transistor MN1 remains turned off; When the IO PAD output is logic 1, the gate of the first power transistor MP1 is associated with the digital IO driving power supply, so that when there is IO flip noise interference at the source level of the first power transistor MP1, the flip noise interference signal can be fed back to the gate level of the first power transistor MP1 in time, thereby maintaining the gate-source voltage difference of the first power transistor MP1 below the turn-on threshold, and the first power transistor MP1 remains turned off.

10. The circuit for resisting digital IO upset noise according to claim 9, characterized in that: When the IO PAD output is logic 0, the gate of the fourth power transistor MN2 is associated with the digital IO driving ground, so that when there is IO flip noise interference at the source of the fourth power transistor MN2, the flip noise interference signal can be fed back to the gate of the fourth power transistor MN2 in time, thereby maintaining the gate-source voltage difference of the fourth power transistor MN2 below the turn-on threshold, and the fourth power transistor MN2 remains turned off; When the IO PAD output is logic 1, the gate of the third power transistor MP2 is associated with the digital IO driving power supply, so that when there is IO flip noise interference at the source level of the third power transistor MP2, the flip noise interference signal can be fed back to the gate level of the third power transistor MP2 in time, thereby maintaining the gate-source voltage difference of the third power transistor MP2 below the turn-on threshold, and the third power transistor MP2 remains turned off.

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