A low jitter charge pump phase-locked loop circuit

Abstract

The present application relates to a low-jitter charge pump phase-locked loop circuit. The circuit is connected to a frequency detector and phase detector module by a digital integral path and an analog proportional path, and both the digital integral path and the analog proportional path are connected to a combined voltage-controlled oscillator module; the combined voltage-controlled oscillator module is connected to a frequency divider to output a feedback clock signal and input it into the frequency detector and phase detector again; the combined voltage-controlled oscillator module includes two voltage-controlled oscillators, one of which operates in a region where the frequency increases with the voltage at a rate exceeding the linear proportional region, and the other operates in a region where the frequency increases with the voltage at a rate lower than the linear proportional region; the output frequencies of the two voltage-controlled oscillators are processed to suppress nonlinear characteristics to obtain linear voltage-frequency characteristics. Linear output can suppress output jitter problems, thereby further reducing the output jitter problem of the phase-locked loop.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and particularly to a charge pump phase-locked loop circuit with low jitter. Background Art

[0002] To meet the applications in scenarios with extremely low clock jitter, including high-performance processors, 5G wireless communication, high-speed wired communication (such as 56 / 112 Gbps high-speed communication), and next-generation Ethernet communication, etc. In high-performance CPUs, as a clock generator, the PLL poses very high requirements for the stability of the clock system. Any tiny clock jitter may lead to a decline in CPU performance or functional abnormalities. With the improvement of communication speed, low-jitter PLLs become particularly important for maintaining the stability and reliability of high-speed data transmission.

[0003] In this context, a phase-locked loop that is stable, has good noise immunity, and can output a signal with extremely low output jitter becomes extremely important. A low-jitter phase-locked loop circuit can reduce phase noise, which is very important for fields such as wireless communication and high-speed data communication because phase noise directly affects the signal quality and transmission distance. And it can provide a more stable clock signal, with reduced sensitivity to power supply noise and environmental changes, thus enhancing the anti-interference ability of the system, which is very important for ensuring the reliability and stability of communication systems.

[0004] Compared with the currently widely used all-digital phase-locked loop (ADPLL), which usually has higher jitter problems due to quantization noise and higher sensitivity to power supply noise, the charge pump phase-locked loop (CPPLL) itself has characteristics such as high-frequency and high-precision output clocks, low-jitter output, and small phase error. Due to its simplicity and robustness, the charge pump phase-locked loop is the most widely used analog mixed-signal phase-locked loop architecture.

[0005] The traditional dual-loop charge pump phase-locked loop splits the single-loop path of the basic CPPLL into a proportional path and an integral path, such as Figure 1 the dual-loop CPPLL shown. By setting a smaller Icp-i (Icp-i << Icp-p), the capacitance of the integral capacitor C1 can be reduced without changing the loop dynamics, but the existence of the integral capacitor still brings parasitic capacitance that affects phase noise. The control voltage output by the loop filter adjusts the frequency of the voltage-controlled oscillator (VCO) so that the output signal of the VCO is synchronized with the frequency of the input signal, achieving phase locking between the two. However, due to the relatively high non-linearity of the frequency response curve of the voltage-controlled oscillator in the design of the traditional dual-loop charge pump phase-locked loop, the single voltage-controlled oscillator V-F characteristic curve is as Figure 2 shown, or the response of the output frequency of the VCO to the control voltage may not be instantaneous, all of which will lead to an increase in the phase noise and jitter of the phase-locked loop. Summary of the invention

[0006] Based on this, it is necessary to provide a low-jitter charge pump phase-locked loop circuit to address the above technical issues.

[0007] A low-jitter charge pump phase-locked loop circuit comprises a frequency detector and a phase detector, an analog proportional path, a digital integral path, a combined voltage-controlled oscillator module and a frequency divider.

[0008] The phase frequency detector is used to compare the phase of the input parameter clock signal and the clock signal fed back by the frequency divider to obtain the phase difference.

[0009] The analog proportional path is used to convert the phase difference into a current through a charge pump, and then processed through a loop filter to obtain a first control voltage.

[0010] The digital integration path is used to perform serial-to-parallel conversion, storage, phase detection, accumulation, and digital-to-analog conversion on the phase difference to obtain a second control voltage.

[0011] A combined voltage-controlled oscillator module is used to use the values ​​of the first control voltage and the second control voltage as the voltage-controlled voltage, input the voltage-controlled voltage into a controllable bias circuit, control the two voltage-controlled oscillators after adding them to two different adjustable bias voltages, process the clock signals output by the two voltage-controlled oscillators through a first counter and then through a first digital processing unit, transmit the output signal to a frequency divider, process the clock signals output by the two voltage-controlled oscillators through a second counter and then through a second digital processing unit, and output the clock signal.

[0012] The frequency divider is used to divide the frequency of the signal output by the first digital processing unit, and feed back the divided clock signal to the frequency and phase detector.

[0013] In one embodiment, the analog proportional path includes a charge pump and a loop filter.

[0014] The input end of the charge pump is connected to the output end of the frequency and phase detector, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the combined voltage-controlled oscillator.

[0015] In one embodiment, the digital integration path includes a serial-to-parallel conversion module, a register module, a phase detector, a digital accumulator, and a digital-to-analog converter connected in sequence.

[0016] In one embodiment, the digital accumulator is a digital accumulator with a set gain, wherein the gain is not greater than a preset value.

[0017] In one embodiment, the phase detector is a bang-bang phase detector.

[0018] In one embodiment, the combined voltage-controlled oscillator module includes: an adder, a controllable bias circuit, two counters, two voltage-controlled oscillators, and two digital processing units.

[0019] The two input ends of the adder receive the first control voltage and the second control voltage respectively, the output end of the adder is connected to the input end of the controllable bias circuit, the output end of the controllable bias circuit is connected to the control end of the first voltage-controlled oscillator and the second voltage-controlled oscillator respectively, the input ends of the two counters are connected to the output ends of the two voltage-controlled oscillators, the output end of the first counter is connected to the input end of the first digital processing unit, the output end of the first digital processing unit is connected to the input end of the frequency divider, the output end of the second counter is connected to the input end of the second digital processing unit, and the output end of the second digital processing unit is used to output a clock signal.

[0020] In one embodiment, the bias voltage is provided by a controllable bias circuit, which is obtained by applying a power supply voltage to a variable resistor and a resistor of a fixed resistance in series, and the bias voltage is adjusted by changing the value of the variable resistor.

[0021] In one embodiment, the voltage controlled oscillator includes an inverter-based ring oscillator with a latch structure.

[0022] The above-mentioned low-jitter charge pump phase-locked loop circuit, the circuit is connected to a digital integral path and an analog proportional path after the frequency detector module, and the digital integral path and the analog proportional path are both connected to a combined voltage-controlled oscillator module; the combined voltage-controlled oscillator module is connected to a frequency divider to output a feedback clock signal and input it into the frequency detector again; the combined voltage-controlled oscillator module includes two voltage-controlled oscillators, one of which works in a region where the frequency increases with the voltage at a rate exceeding the linear proportional region, and the other works in a region where the frequency increases with the voltage at a rate below the linear proportional region; the output frequencies of the two voltage-controlled oscillators are processed to suppress nonlinear characteristics to obtain linear voltage-frequency characteristics. Linear output can suppress output jitter problems, thereby further reducing the output jitter problem of the phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the circuit composition of a traditional dual-loop charge pump phase-locked loop;

[0024] Figure 2 It is a schematic diagram of the VF characteristic curve of a single voltage-controlled oscillator;

[0025] Figure 3 A block diagram of a low-jitter charge pump phase-locked loop circuit in one embodiment;

[0026] Figure 4 A schematic diagram of a controllable bias voltage circuit of a combined voltage-controlled oscillator in another embodiment;

[0027] Figure 5 A circuit diagram of a combined voltage-controlled oscillator in another embodiment. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] In one embodiment, Figure 3 As shown, a low-jitter charge pump phase-locked loop circuit is provided, which includes: a frequency detector 10, an analog proportional path 20, a digital integral path 30, a combined voltage-controlled oscillator module 40 and a frequency divider 50.

[0030] The phase frequency detector 10 is used to compare the phases of the input parameter clock signal and the clock signal fed back by the frequency divider 50 to obtain a phase difference.

[0031] Specifically, a reference clock signal and a feedback clock signal are input to the frequency and phase detector, and the phase difference between the two signals is input into the analog proportional path 20 and the digital integral path 30 respectively through comparison.

[0032] The analog proportional path 20 is used to convert the phase difference into a current through a charge pump, and then process it through a loop filter to obtain a first control voltage.

[0033] Specifically, in the analog proportional path, the phase difference signal is transmitted to the charge pump, and the charge pump converts the phase difference into a current which is transmitted through the loop filter to obtain the first control voltage Vp.

[0034] The digital integration path 30 is used to obtain a second control voltage after processing the phase difference through a serial-to-parallel conversion module, a register module, a phase detector, a digital accumulator, and a digital-to-analog converter.

[0035] Specifically, the introduction of a digital integral path and a combined voltage-controlled phase-locked loop can suppress phase noise and improve jitter performance.

[0036] The digital integration path 30 is used to perform serial-to-parallel conversion, storage, phase detection, accumulation, and digital-to-analog conversion on the phase difference to obtain a second control voltage.

[0037] Specifically, in the digital integration path 30, the phase difference is output as a parallel signal through the serial-to-parallel conversion module, and the data is stored once through the register module. The bang-bang phase detector can realize multiple identifications at the same time, improve the locking speed and judge the two previous and subsequent data, greatly improve the identification accuracy, and reduce the loop jitter error. By setting the gain α of the digital accumulator at The accumulator can further reduce the quantization noise by limiting the amplification effect of the accumulator on the quantization error. The data output by the bang-bang phase detector is output as a digital quantity through the accumulator, and then converted into the second control voltage Vi through the digital-to-analog converter.

[0038] The combined voltage-controlled oscillator module 40 is used to add the values ​​of the first control voltage and the second control voltage as the voltage-controlled voltage, input the voltage-controlled voltage into the controllable bias circuit, and control the two voltage-controlled oscillators after adding them to two different adjustable bias voltages respectively, and process the clock signals output by the two voltage-controlled oscillators through the first counter and then through the first digital processing unit, and transmit the output signal to the divider 50, and process the clock signals output by the two voltage-controlled oscillators through the second counter and then through the second digital processing unit to output the clock signal.

[0039] Specifically, after the first control voltage Vp and the second control voltage Vi are input into the combined voltage-controlled oscillator, the first control voltage Vp and the second control voltage Vi are added to obtain Vctrl, the combined voltage-controlled oscillator is adjusted, and the output clock signal is divided by the frequency divider to obtain a feedback clock signal as the input of the frequency detector and phase detector.

[0040] The output jitter of the phase-locked loop is mainly caused by the nonlinearity of the voltage-controlled oscillator output. For the improvement of the voltage-controlled oscillator of the traditional dual-loop charge pump phase-locked loop, the nonlinearity problem of the single voltage-controlled oscillator is serious. When the control voltage is low, the frequency increases with the voltage at a rate exceeding the linear proportional area, and when the control voltage is high, the frequency increases with the voltage at a rate lower than the linear proportional area. This situation will cause a larger output signal jitter problem. The voltage-frequency (VF) characteristics of a single voltage-controlled oscillator will show nonlinearity in certain voltage ranges, such as Figure 2 As shown. Improving the nonlinear characteristics of the voltage-controlled oscillator is the key to reducing the jitter of the phase-locked loop output signal. The combined voltage-controlled oscillator module includes a controllable bias circuit, two ring voltage-controlled oscillators VCO1 and VCO2, and different adjustable bias voltages V1 and V2 are added based on the control voltages input to the proportional path and the integral path respectively; V1 and V2 can be dynamically adjusted by adjusting the resistance value of the variable resistor.

[0041] The controllable bias circuit can adjust the bias voltage by changing the variable resistor according to the linearity of the voltage-frequency characteristic curve of the voltage-controlled oscillator, adjust the working area of ​​the voltage-controlled oscillator, and prevent the control voltage from being too large or too small to affect the linearity of the output voltage-frequency characteristic.

[0042] One of the two voltage-controlled oscillators works in the region where the frequency increases with the voltage at a rate exceeding the linear ratio, and the other works in the region where the frequency increases with the voltage at a rate below the linear ratio; the outputs of the two voltage-controlled oscillators are then added to eliminate the nonlinear effect and obtain a linear output. The output frequencies of the two voltage-controlled oscillators are processed to suppress the nonlinear characteristics of each other and obtain a linear voltage-frequency characteristic; V1 and V2 can be dynamically adjusted by adjusting the resistance value of the variable resistor, and the voltage-frequency characteristic of the output of the two voltage-controlled oscillators can be adjusted at any time to maintain good linearity, and the output linearity will not be affected by excessive or too small input control voltage. The linear output can suppress the output jitter problem, thereby further reducing the output jitter problem of the phase-locked loop.

[0043] The frequency divider 50 is used to divide the frequency of the signal output by the first digital processing unit, and feed back the divided clock signal to the frequency detector 10 .

[0044] Specifically, the combined voltage-controlled oscillator module 40 is connected to the frequency divider 50, and after being processed by the frequency divider 50, it is input as a feedback clock signal into the frequency and phase detector module to form a closed loop.

[0045] In the above-mentioned low-jitter charge pump phase-locked loop circuit, the circuit is connected to a frequency detector module by connecting a digital integral path and an analog proportional path, and both the digital integral path and the analog proportional path are connected to a combined voltage-controlled oscillator module; the combined voltage-controlled oscillator module is connected to a frequency divider to output a feedback clock signal and input it into the frequency detector again; the combined voltage-controlled oscillator module includes two voltage-controlled oscillators, one of which works in a region where the frequency increases with the voltage at a rate exceeding the linear proportional region, and the other works in a region where the frequency increases with the voltage at a rate below the linear proportional region; the output frequencies of the two voltage-controlled oscillators are processed to suppress nonlinear characteristics to obtain linear voltage-frequency characteristics. Linear output can suppress output jitter problems, thereby further reducing the output jitter problem of the phase-locked loop.

[0046] In one embodiment, the analog proportional path 20 includes a charge pump and a loop filter; the input end of the charge pump is connected to the output end of the frequency detector 10, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the combined voltage controlled oscillator.

[0047] In one embodiment, the digital integration path 30 includes a serial-to-parallel conversion module, a register module, a phase detector, a digital accumulator, and a digital-to-analog converter connected in sequence.

[0048] Specifically, based on the traditional dual-loop charge pump phase-locked loop, the present application optimizes the analog integral path into a digital integral path, and uses a serial-to-parallel conversion module, a register module, a bang-bang phase detector, a digital accumulator, and a digital-to-analog converter to replace it, and performs serial-to-parallel conversion processing on the signal of the input integral path. The bang-bang phase detector makes multiple judgments in the same time, which can speed up the locking speed. In addition, the register module can store data once for comparison with the next data, and the two data before and after participate in the bang-bang phase detector judgment together, which can prevent errors caused by quantization noise interference. Furthermore, the output of the bang-bang phase detector is set to a smaller gain α through the digital accumulator, and the quantization noise interference of the digital integral path can be well suppressed. Finally, the analog control voltage signal is processed by the digital-to-analog converter to output. The digital design of this part of the integral path greatly reduces the noise interference caused by the integral capacitor of the traditional dual-loop charge pump phase-locked loop and reduces output jitter.

[0049] The digital accumulator is used to accumulate the output of the phase detector. It updates the accumulated value in each clock cycle based on the phase difference information provided by the phase detector. If the phase detector outputs a positive value indicating phase advance, the accumulator will add this positive value to the current accumulated value; conversely, if it is a negative value indicating phase lag, the corresponding value will be subtracted from the accumulated value. The output of the accumulator represents the output result of the digital integration path and is used for subsequent loop control.

[0050] In one embodiment, the digital accumulator is a digital accumulator with a set gain, wherein the gain is not greater than a preset value.

[0051] In one embodiment, the phase detector is a bang-bang phase detector.

[0052] In one embodiment, the combined voltage-controlled oscillator module 40 includes: an adder, a controllable bias circuit, two counters, two voltage-controlled oscillators, and two digital processing units.

[0053] The two input ends of the adder receive the first control voltage and the second control voltage respectively, the output end of the adder is connected to the input end of the controllable bias circuit, the output end of the controllable bias circuit is connected to the control ends of the first voltage-controlled oscillator and the second voltage-controlled oscillator respectively, the input ends of the two counters are connected to the output ends of the two voltage-controlled oscillators, the output end of the first counter is connected to the input end of the first digital processing unit, the output end of the first digital processing unit is connected to the input end of the frequency divider 50, the output end of the second counter is connected to the input end of the second digital processing unit, and the output end of the second digital processing unit is used to output a clock signal.

[0054] Specifically, the first control voltage and the second control voltage output by the analog proportional path 20 and the digital integral path 30 are accumulated to obtain Vctrl, which is input into the combined voltage-controlled oscillator module, and then input into the controllable bias circuit after being pre-processed by the adder, and two adjustable bias voltages V1 and V2 are added respectively, and finally Vcont1 and Vcont2 are obtained. The specific implementation circuit of the combined voltage-controlled oscillator bias voltage circuit is as follows: Figure 4 As shown, V1 and V2 are obtained by connecting a variable resistor in series with a fixed resistance resistor. The introduction of the variable resistor can adjust the size of V1 and V2 by adjusting the resistance ratio. Vctrl is combined with the DC bias voltage V1 and V2 after passing through a capacitor to obtain the first voltage-controlled voltage Vcont1 and the second voltage-controlled voltage Vcont2. The C1 capacitor is a coupling capacitor that isolates the DC voltage of the input signal to avoid affecting the set bias voltage. C2 and C3 are decoupling capacitors that reduce the impact of power supply ripple noise in order to obtain a stable bias voltage.

[0055] The first voltage-controlled voltage Vcont1 and the second voltage-controlled voltage Vcont2 are input into the first voltage-controlled oscillator VCO1 and the second voltage-controlled oscillator VCO2 respectively, so that the first voltage-controlled oscillator VCO1 operates in the region where the frequency increases with the voltage at a rate lower than the linear ratio, and the second voltage-controlled oscillator VCO2 operates in the region where the frequency increases with the voltage at a rate higher than the linear ratio. The output ends of the two voltage-controlled oscillators are connected to a counter, which counts according to the edge of the input signal. When the edge of the VCO output signal (such as the rising edge) arrives, the counter increases the count. At each rising edge, the count register inside the counter is increased by 1. For each clock cycle, the counter simultaneously detects the edges of the two VCO output signals and records their number of cycles. The count value is then input into the digital processing unit. The digital processing unit uses the formula Calculate and get the output frequency. Due to the double-ended output (one output is composed of a counter and a digital processing unit; the double-ended output includes the above two outputs), one end output is directly output as the output clock signal, and the other end output is input as the feedback clock signal through the frequency divider and input into the frequency detector and phase detector for further judgment with the reference clock signal to form feedback and dynamically adjust until the feedback clock signal is consistent with the reference clock signal in phase and frequency. The PLL is considered to be locked. At this time, the signal output by the PLL maintains a fixed phase relationship with the reference signal.

[0056] The specific implementation circuit of the combined voltage-controlled oscillator module is as follows: Figure 5 shown.

[0057] In one embodiment, the bias voltage is provided by a controllable bias circuit, which is obtained by applying a power supply voltage to a variable resistor and a resistor of a fixed resistance in series, and the bias voltage is adjusted by changing the value of the variable resistor.

[0058] Specifically, Figure 4 As shown, both paths of the controllable bias circuit are obtained by dividing the voltage of V1 and V2 by connecting a variable resistor in series with a fixed resistor. The introduction of the variable resistor makes it easy to adjust the voltage values ​​of V1 and V2 at any time. The voltage Vctrl is combined with the DC bias voltage after passing through a capacitor, and passes through C2 and C3 as decoupling capacitors to reduce the interference of power supply noise on the DC bias.

[0059] In one embodiment, the voltage controlled oscillator includes an inverter-based ring oscillator with a latch structure.

[0060] Specifically, the combined voltage-controlled oscillator module is composed of two inverter-based ring oscillators with a latch structure, and the latch structure is added to achieve signal interlocking to improve signal stability and reduce phase noise.

[0061] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A low-jitter charge pump phase-locked loop circuit, characterized in that: The circuit comprises: a frequency and phase detector, an analog proportional path, a digital integral path, a combined voltage-controlled oscillator module and a frequency divider; The frequency and phase detector is used to compare the phases of the input parameter clock signal and the clock signal fed back by the frequency divider to obtain a phase difference; The analog proportional path is used to convert the phase difference into a current through a charge pump, and then process it through a loop filter to obtain a first control voltage; The digital integration path is used to perform serial-to-parallel conversion, storage, phase detection, accumulation, and digital-to-analog conversion on the phase difference to obtain a second control voltage; The combined voltage-controlled oscillator module is used to use the values ​​of the first control voltage and the second control voltage as voltage-controlled voltages, input the voltage-controlled voltages into a controllable bias circuit, respectively add the voltages to two different adjustable bias voltages to control the two voltage-controlled oscillators, process the clock signals output by the two voltage-controlled oscillators through a first counter and then through a first digital processing unit, transmit the output signals to the frequency divider, process the clock signals output by the two voltage-controlled oscillators through a second counter and then through a second digital processing unit, and output clock signals; The frequency divider is used to divide the frequency of the signal output by the first digital processing unit, and feed back the divided clock signal to the frequency and phase detector; The combined voltage-controlled oscillator module is also used to make one of the two voltage-controlled oscillators work in a region where the rate of increase of frequency with voltage exceeds the linear proportion, and the other work in a region where the rate of increase of frequency with voltage is lower than the linear proportion; and then add the outputs of the two voltage-controlled oscillators to eliminate nonlinear effects and obtain a linear output.

2. The low-jitter charge pump phase-locked loop circuit according to claim 1, characterized in that: The analog proportional path includes a charge pump and a loop filter; The input end of the charge pump is connected to the output end of the frequency and phase detector, the output end of the charge pump is connected to the input end of the loop filter, and the output end of the loop filter is connected to the combined voltage-controlled oscillator.

3. The low-jitter charge pump phase-locked loop circuit according to claim 1, characterized in that: The digital integration path includes a serial-to-parallel conversion module, a register module, a phase detector, a digital accumulator and a digital-to-analog converter which are connected in sequence.

4. The low-jitter charge pump phase-locked loop circuit according to claim 3, characterized in that: The digital accumulator is a digital accumulator with a set gain, wherein the gain is not greater than a preset value.

5. The low-jitter charge pump phase-locked loop circuit according to claim 3, characterized in that: The phase detector is a bang-bang phase detector.

6. The low-jitter charge pump phase-locked loop circuit according to claim 1, characterized in that: The combined voltage-controlled oscillator module includes: an adder, a controllable bias circuit, two counters, two voltage-controlled oscillators, and two digital processing units; Two input ends of the adder receive the first control voltage and the second control voltage respectively, the output end of the adder is connected to the input end of the controllable bias circuit, the output end of the controllable bias circuit is connected to the control ends of the first voltage-controlled oscillator and the second voltage-controlled oscillator respectively, the input ends of the two counters are connected to the output ends of the two voltage-controlled oscillators, the output end of the first counter is connected to the input end of the first digital processing unit, the output end of the first digital processing unit is connected to the input end of the frequency divider, the output end of the second counter is connected to the input end of the second digital processing unit, and the output end of the second digital processing unit is used to output a clock signal.

7. The low-jitter charge pump phase-locked loop circuit according to claim 1, characterized in that: The bias voltage is provided by a controllable bias circuit, which is obtained by applying a power supply voltage to a variable resistor and a resistor of a fixed resistance in series, and the bias voltage is adjusted by changing the value of the variable resistor.

8. The low-jitter charge pump phase-locked loop circuit according to claim 1, characterized in that: The voltage controlled oscillator includes an inverter-based ring oscillator with a latch structure.

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