Conversion circuit of analog-to-digital converter

Abstract

The embodiment of the invention provides a conversion circuit of an analog-to-digital converter, and the circuit comprises a multipath sampling module which comprises a plurality of sampling circuits which are used for collecting input signals at the same time; the kernel is connected with the multi-channel sampling module and is used for receiving the input signals sent by the plurality of sampling circuits respectively and quantizing the input signals of the plurality of sampling circuits respectively; and the sampling polling module is connected with the kernel and the multi-channel sampling module and is used for controlling the kernel to be connected with the sampling circuits one by one. A plurality of sampling circuits are used for sampling at the same time through the sampling module, signals sampled by the plurality of sampling circuits at the same time are quantized through the kernel, and the purposes that one kernel is used for sampling multiple paths of signals at the same time and converting the multiple paths of sampled signals are achieved. And too high cost caused by sampling multiple paths of signals through a plurality of kernels is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of information processing, and in particular to a conversion circuit of an analog-to-digital converter. Background Art

[0002] The existing ADC (Analog-to-Digital Converter) chips on the market need to be equipped with multiple ADC cores if they need to sample and convert multiple signals at the same time. This method is costly, and multiple ADC cores can only collect the voltage or current values ​​of multiple signals at the same time, but not collect and convert the voltage or current values ​​of multiple signals at the same time. Summary of the invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a conversion circuit of an analog-to-digital converter that overcomes the above problems or at least partially solves the above problems.

[0004] In order to solve the above problem, an embodiment of the present invention discloses a conversion circuit of an analog-to-digital converter, comprising:

[0005] A multi-channel sampling module, comprising a plurality of sampling circuits, wherein the plurality of sampling circuits are used to simultaneously collect input signals;

[0006] A core connected to the multi-channel sampling module, configured to respectively receive input signals sent by the plurality of sampling circuits, and respectively quantize the input signals of the plurality of sampling circuits;

[0007] The sampling polling module is connected to the core and the multi-channel sampling module, and is used to control the core to connect to the multiple sampling circuits one by one.

[0008] Optionally, each of the sampling circuits includes a multiplexer and a corresponding sampling capacitor;

[0009] The multiplexers are respectively used to simultaneously receive channel selection signals, select a target sampling channel according to the channel selection signal, obtain an input signal through the target sampling channel, and transmit the input signal to a corresponding sampling capacitor.

[0010] Optionally, the kernel includes:

[0011] A sampling switch, a sampling mode selection module connected to the sampling switch, a first capacitor array and a second capacitor array connected to the sampling mode selection module, a comparator and a control module connected to the sampling mode selection module;

[0012] The sampling mode selection module is used for mirroring the input signal collected by the sampling circuit to the first capacitor array and the second capacitor array according to the type of the input signal when the sampling switch is turned on;

[0013] The first capacitor array and the second capacitor array are used to transmit the mirrored input signal to the comparator;

[0014] The comparator is used for comparing input signals of the first capacitor array and the second capacitor array to obtain a comparison result.

[0015] Optionally, the sampling mode selection module is used to control the upper and lower plates of the capacitors of the first capacitor array and the second capacitor array to be disconnected when the input signal is a differential input signal, so that the first capacitor array and the second capacitor array receive the positive signal and the negative phase signal of the differential input signal; when the input signal is a single-ended input signal, control the upper and lower plates of the capacitors of the first capacitor array and the second capacitor array to be connected, so that the first capacitor array and the second capacitor array receive the single-ended input signal.

[0016] Optionally, the conversion circuit further includes a digital module, and the sampling polling module includes a start conversion module;

[0017] The digital module is used to send a first start conversion signal corresponding to the sampling circuit to the start conversion module before the preset time when the multi-channel sampling module performs sampling and the sampling ends;

[0018] The startup conversion module is used to generate a plurality of second startup conversion signals according to the first startup conversion signal and the oversampling configuration information, and send the plurality of second startup conversion signals to the control module;

[0019] The control module is used to send the multiple second start conversion signals to the multi-channel sampling module one by one, so that the sampling circuit, when receiving the corresponding second start conversion signal, maintains the sampled input signal and mirrors the input signal to the first capacitor array and the second capacitor array.

[0020] Optionally, the sampling polling module includes an end conversion module;

[0021] The conversion end module is used to obtain the number of input signals corresponding to the sampling circuit that have completed comparison, and when the number of input signals corresponding to the sampling circuit that have completed comparison meets the target number in the oversampling configuration information, send a conversion completion signal corresponding to the sampling circuit to the digital module;

[0022] The digital module is used for sending a next start conversion signal corresponding to the sampling circuit to the start conversion module after receiving the conversion completion signal corresponding to the sampling circuit.

[0023] Optionally, the sampling circuit further includes an analog buffer; and the control module is used to mirror the input signal to the first capacitor array and the second capacitor array through the analog buffer.

[0024] Optionally, the conversion circuit further includes:

[0025] A digital calibration module connected to the core module, the digital calibration module is used to digitally calibrate the signals obtained after the core quantizes the input signals of the multiple sampling circuits respectively.

[0026] Optionally, the preset time is two clock cycles; the digital module is used to send a first start conversion signal corresponding to the sampling circuit to the start conversion module two clock cycles before the multi-channel sampling module performs sampling and the sampling ends.

[0027] Optionally, the number of the sampling switches is two; when the input signal is a differential input signal, the control module is used to control the two sampling switches to be turned on; when the input signal is a single-ended input signal, the control module is used to control one of the two sampling switches to be turned on.

[0028] The embodiments of the present invention include the following advantages:

[0029] A conversion circuit of an analog-to-digital converter according to an embodiment of the present invention includes a multi-channel sampling module, including multiple sampling circuits, and the multiple sampling circuits are used to collect input signals simultaneously; a core connected to the multi-channel sampling module, used to respectively receive input signals sent by the multiple sampling circuits, and respectively quantify the input signals of the multiple sampling circuits; a sampling polling module connected to the core and the multi-channel sampling module, used to control the core to connect to the multiple sampling circuits one by one. The multiple sampling circuits are sampled simultaneously through the sampling module, and the signals sampled simultaneously by the multiple sampling circuits are quantified respectively through the core, so that the multiple signals are sampled simultaneously using one core, and the multiple sampled signals are converted, thereby avoiding the high cost caused by sampling the multiple signals through multiple cores. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of a conversion circuit of an analog-to-digital converter according to an embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of a conversion circuit of another analog-to-digital converter according to an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of a sampling polling module according to an embodiment of the present invention;

[0033] Figure 4 is a schematic diagram of a circuit simulation waveform of a startup conversion module according to an embodiment of the present invention;

[0034] Figure 5 is a schematic diagram of a circuit simulation waveform of an end conversion module according to an embodiment of the present invention;

[0035] Figure 6 It is a schematic diagram of the polling logic simulation result of an embodiment of the present invention.

[0036] Figure numerals: multi-channel sampling module 10, sampling circuit 11, multiplexer 111, sampling capacitor 112, analog buffer 113, core 20, sampling switch 21, sampling mode selection module 22, first capacitor array 23, second capacitor array 24, comparator 25, control module 26, sampling polling module 30, start conversion module 31, end conversion module 32, polling control module 33, digital calibration module 40. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The existing analog-to-digital converter chips on the market need to be equipped with multiple analog-to-digital converter cores if they need to sample and convert multiple signals at the same time. This method is costly, and what is achieved through multiple analog-to-digital converter cores is the sampling of the voltage or current values ​​of multiple signals at the same time, rather than sampling and converting the voltage or current values ​​of multiple signals at the same time.

[0039] One of the core concepts of the embodiments of the present invention is to perform sampling simultaneously on multiple sampling circuits through a sampling module, and to quantize the signals sampled simultaneously by the multiple sampling circuits through the cores, thereby realizing the simultaneous sampling of multiple signals using one core and the conversion of multiple sampled signals, thereby avoiding the excessively high cost caused by sampling multiple signals through multiple cores.

[0040] Reference Figure 1 , shows a schematic diagram of a conversion circuit of an analog-to-digital converter according to an embodiment of the present invention, which may specifically include the following structure:

[0041] A multi-channel sampling module 10 , a core 20 and a sampling polling module 30 .

[0042] An analog-to-digital converter (ADC) is an electronic device used to convert an analog signal (such as voltage or current) into a digital signal. For example, the analog-to-digital converter can be a SAR ADC (Successive Approximation Register ADC). The successive approximation register analog-to-digital converter gradually compares the input analog signal with an internal reference voltage by successive approximation, and finally determines the digital representation of the input signal. The working process includes: sampling, the input analog signal is sampled and held in a sample-and-hold circuit; comparison, the sampled signal is compared with the internal reference voltage to determine the most significant bit (MSB); approximation, the reference voltage is gradually adjusted to determine the value of each bit bit by bit until the least significant bit (LSB); output, finally obtaining the digital representation of the input signal.

[0043] The multi-channel sampling module 10 includes a plurality of sampling circuits 11 , and the plurality of sampling circuits 11 are used to collect input signals simultaneously.

[0044] The core 20 is connected to the multi-channel sampling module 10 and is used to receive input signals sent by multiple sampling circuits 11 respectively and quantize the input signals of the multiple sampling circuits 11 respectively.

[0045] The sampling polling module 30 is connected to the core 20 and the multi-channel sampling module 10, and is used to control the core 20 to connect with the multiple sampling circuits 11 one by one, so that the core 20 quantizes the input signals of the multiple sampling circuits 11 one by one, thereby realizing that the multiple sampling circuits 11 collect the multiple input signals at the same time, and quantizes the multiple input signals collected simultaneously by the sampling circuits 11 one by one.

[0046] A conversion circuit of an analog-to-digital converter according to an embodiment of the present invention includes a multi-channel sampling module, including multiple sampling circuits, and the multiple sampling circuits are used to collect input signals simultaneously; a core connected to the multi-channel sampling module, used to respectively receive input signals sent by the multiple sampling circuits, and respectively quantify the input signals of the multiple sampling circuits; a sampling polling module connected to the core and the multi-channel sampling module, used to control the core to connect to the multiple sampling circuits one by one. The multiple sampling circuits are sampled simultaneously through the sampling module, and the signals sampled simultaneously by the multiple sampling circuits are quantified respectively through the core, so that the multiple signals are sampled simultaneously using one core, and the multiple sampled signals are converted, thereby avoiding the high cost caused by sampling the multiple signals through multiple cores.

[0047] Reference Figure 2, shows a schematic diagram of a conversion circuit of another analog-to-digital converter according to an embodiment of the present invention. The multi-channel sampling module 10 includes three sampling circuits 11, and each sampling circuit 11 includes a multiplexer 111 and a corresponding sampling capacitor 112. The multiple multiplexers 111 are respectively used to simultaneously receive a channel selection signal, select a target sampling channel according to the channel selection signal, obtain an input signal through the target sampling channel, and transmit the input signal to the corresponding sampling capacitor 112.

[0048] A multiplexer (MUX) is an electronic device used to select one signal from multiple input signals and pass it to an output terminal. Exemplarily, the multiplexer 111 can be composed of a 16-to-1 switch, which can select one signal from 16 input signals and pass it to an output terminal. Such a multiplexer is usually composed of 16 switches and a set of control signals.

[0049] There are 48 input signals in total, which are divided into 3 groups, each group of 16 input signals. The multiplexer 111 can be composed of a 16-to-1 switch. Each group of 16 input signals corresponds to 1 multiplexer 111, and 3 groups of input signals correspond to 3 multiplexers 111. Each multiplexer 111, under the control of the CHSEL signal, selects 16 from each group of input signals, selects the target sampling channel, obtains the input signal through the target sampling channel, and transmits the input signal to the corresponding sampling capacitor 112. The CHSEL signal is also a channel selection signal, which is used to select the input channel so that the signal of a specific channel can be transmitted to the output end or sampled.

[0050] Exemplarily, the input signal of the first sampling circuit 11 may be Vin<15:0>, Vin<15:0> may be a general term for Vip<15:0>, Vin<15:0>, Vip and Vin are connected to different input signals for differential input, and Vip and Vin are connected to the same input signal for single-ended input, the input signal of the second sampling circuit 11 may be Vin<31:16>, and the input signal of the third sampling circuit 11 may be Vin<47:32>.

[0051] Each multiplexer 111 selects an input channel under the control of the CHSEL signal at the same time, and performs sampling when the channel is selected. The sampling when the channel is selected is to convert the input signal voltage into a charge amount and store it on the sampling capacitor. The length of this time is determined by the signal voltage, the channel impedance and the sampling capacitor size as well as the required accuracy.

[0052] The actual sampling start time is based on the channel configuration signal CH1SEL<3:0>. If it is configured to 0001, it means that the multiplexer 111 selects the first channel, and the D_ADC_SOC0 digital initial configuration is low. The path is turned on by default, so sampling starts when the channel configuration is completed. The sampling time is determined by the time interval between the channel configuration and the D_ADC_SOC0 signal being set high.

[0053] In the embodiment of the present invention, the kernel 20 includes:

[0054] A sampling switch 21 , a sampling mode selection module 22 connected to the sampling switch 21 , a first capacitor array 23 and a second capacitor array 24 connected to the sampling mode selection module 22 , a comparator 25 and a control module 26 connected to the sampling mode selection module 22 .

[0055] The sampling mode selection module 22 is used for mirroring the input signal collected by the sampling circuit 11 to the first capacitor array 23 and the second capacitor array 24 according to the type of the input signal when the sampling switch 21 is turned on.

[0056] The sampling mode selection module 22 is a DS module (Differential / Single, differential single-ended mode control switch). For different input signals, the sampling mode selection module 22 selects different sampling modes. In the sampling mode corresponding to the input signal, the input signal collected by the sampling circuit 11 is mirrored to the first capacitor array 23 and the second capacitor array 24.

[0057] The first capacitor array 23 and the second capacitor array 24 are used to transmit the mirrored input signal to the comparator 25 .

[0058] A capacitor digital-to-analog converter (CDAC) is a capacitor array-based digital-to-analog converter, usually consisting of a group of capacitors and a switch network. The value of the capacitor can be controlled by a digital input signal to produce different output voltages.

[0059] The first capacitor array 23 and the second capacitor array 24 are both composed of a plurality of capacitors. The specific number of capacitors depends on the accuracy of the analog-to-digital converter and different strategies. For example, if the accuracy of the analog-to-digital converter is 6 bits, 2 0 Cu, 2 1 Cu, 2 2 Cu, 2 3 Cu, 2 4 Cu, 2 5Cu, 6 capacitors with corresponding weights, each capacitor corresponds to different switching during the quantization process to change the voltage value to approximate the input signal bit by bit, realizing the conversion function of the analog-to-digital converter.

[0060] The comparator 25 is used for comparing the input signals of the first capacitor array 23 and the second capacitor array 24 to obtain a comparison result.

[0061] The comparator 25 is used to compare the input signals of the first capacitor array 23 and the second capacitor array 24. The first capacitor array 23 and the second capacitor array 24 store input signals mirrored from the input signals in the sampling capacitor 112. The input signals of the first capacitor array 23 and the second capacitor array 24 are compared to obtain a comparison result, that is, the input signal in the sampling capacitor 112 is quantized and converted.

[0062] The control module 26 (SARLOGIC, successive approximation register logic) is a control module of the successive approximation analog-to-digital converter (SARADC), and controls the operation of other modules.

[0063] In an embodiment of the present invention, the sampling mode selection module 20 is used to control the upper and lower plates of the capacitors of the first capacitor array 23 and the second capacitor array 24 to be disconnected when the input signal is a differential input signal, so that the first capacitor array 23 and the second capacitor array 24 receive the positive signal and the negative phase signal of the differential input signal; when the input signal is a single-ended input signal, control the upper and lower plates of the capacitors of the first capacitor array 23 and the second capacitor array 24 to be connected, so that the first capacitor array 23 and the second capacitor array 24 receive the single-ended input signal.

[0064] Each capacitor in the first capacitor array 23 and the second capacitor array 24 has an upper and lower electrode plate, and the capacitor array can be used for single-ended input or differential input configuration.

[0065] When the input signal is a differential input signal, the sampling mode selection module 20 controls the upper and lower plates of the capacitors of the first capacitor array 23 and the second capacitor array 24 to be disconnected, the first capacitor array 23 is connected to the VIP signal, and the second capacitor array 24 is connected to the VIN signal. The differential input configuration can improve the anti-interference ability and dynamic range. At this time, the comparator is used to compare the voltages of the first capacitor array 23 and the second capacitor array 24. The voltages of the first capacitor array 23 and the second capacitor array 24 are the voltage values ​​of the VIP and VIN input signals after continuous successive approximation. For example, the differential signal input: the initial values ​​are the input signals of VIP=2v and VIN=1v respectively. During the initial comparison, the input voltage of the comparator is the voltage of the input signal, which is VIP1=2v, VIN1=1v respectively. If the analog-to-digital converter has a 3-bit accuracy (***), the output result of the comparator is 1, indicating that VIP1>VIN1. At this time, the analog-to-digital converter obtains the highest bit of the first quantization result = 1 (1**). After quantization, the corresponding highest bit capacitors of the first capacitor array 23 and the second capacitor array 24 are set respectively, thereby changing the values ​​of VIP1 and VIN1 to obtain VIP2 and VIN2. Then, the values ​​of VIP2 and VIN2 are compared. The second quantization result is The result of quantization is 0 (10*). After quantization, the corresponding high-order capacitors of the first capacitor array 23 and the second capacitor array 24 are set respectively (the highest order has been set in the last comparison, and the high-order value remains unchanged when the low-order comparison is performed later), thereby changing the values ​​of VIP2 and VIN2 to obtain VIP3 and VIN3, and then comparing the values ​​of VIP3 and VIN3. If VIP3>VIN3 at this time, the comparison result of the last bit will be 1 (101), thereby completing the bit-by-bit comparison, and finally obtaining the quantization result of 101, and outputting 101 to the digital. 101=VIP-VIN=2v-1v. (We can obtain the analog voltage from the digital code based on the conversion relationship between the code and the voltage. Of course, the accuracy of the 3-bit analog-to-digital converter has an error of 1 / . For example, if it is a 3.3v range, the error is ≈3.3 / =0.4125v.

[0066] When the input signal is a single-ended input signal, the sampling mode selection module 20 controls the upper and lower plates of the capacitors of the first capacitor array 23 and the second capacitor array 24 to be connected. At this time, the input signal shares the first capacitor array 23 and the second capacitor array 24, which is equivalent to doubling the capacitance of the capacitor array, and correspondingly can reduce the quantization noise by multiples, thereby improving the performance of the analog-to-digital converter. At this time, the input signals of the first capacitor array 23 and the second capacitor array 24 are the same, and the comparator is used for the input signal and a preset fixed signal to obtain a comparison result, that is, a quantization conversion result of the input signal collected by the sampling circuit 11.

[0067] Reference Figure 3, shows a schematic diagram of a sampling polling module according to an embodiment of the present invention. The conversion circuit further includes a digital module (not shown in the figure). The sampling polling module 30 includes a start conversion module 31.

[0068] The digital module is used to send a first start conversion signal corresponding to the sampling circuit 11 to the start conversion module 31 before a preset time when the multi-channel sampling module 10 performs sampling and the sampling ends.

[0069] The digital module sends a SOC<2:0>_pre signal to the startup conversion module 31 in advance at a preset time before the sampling is completed. The first startup conversion signal is the SOC<2:0> signal. The first startup conversion signal sent in advance is the SOC<2:0>_pre signal. The SOC<2:0> signal is also called a three-in-one switch selection signal. The three-in-one switch selection signal is used to determine whether the input signal collected by the multi-channel sampling module 10 enters the core 20 for quantization conversion. After the three-in-one switch is enabled, the voltage on the sampling capacitor 112 is mirrored to the first capacitor array 23 and the second capacitor array 24 (which can be called the sampling of the capacitor array). This time is completed by this analog circuit. The time required is the charging time of the capacitor array capacitor. The simulation result is less than about 20ns. If the clock is 50Mhz, it is equivalent to 1 clcok time. The action of mirroring the voltage of the sampling capacitor 121 to the array capacitor is initiated by the digital module sending a high SOC control signal, and the high SOC control signal will select the corresponding switch, thereby starting the sampling and subsequent quantization of the capacitor array. The effective time of the high SOC control signal must be equal to the sampling and subsequent quantization time of the capacitor array. After the quantization is completed, the digital module sets the SOC control signal low until it is set to a high level next time, and restarts the next sampling and quantization. The entire conversion time of a collected signal is equal to the SOC high level sampling time plus the SOC high level quantization time.

[0070] The startup conversion module 31 is used to generate a plurality of second startup conversion signals according to the first startup conversion signal and the oversampling configuration information, and send the plurality of second startup conversion signals to the control module 26 .

[0071] Oversampling configuration information refers to register configuration information, which is output by the digital module to the sampling polling module 30 (analog module). For example, the 3-bit oversampling register OS<2:0>: 000: no oversampling, 001: 4 times oversampling, 010: 8 times oversampling, 011: 46 times oversampling, 100: 32 times oversampling, 101: 64 times oversampling, 110: 128 times oversampling, 111: 256 times oversampling. After the digital configuration register is given to the analog module, the analog design circuit completes the corresponding required function. For example, if the digital configuration register is 010 for the 8 times oversampling function, the 3-bit control signal 010 is output to the start conversion module 31 (analog circuit). The analog circuit completes the conversion of the 3-bit signal 010 into the 8 times oversampling function, and finally outputs 8 times of data back to the digital register. The digital module adds and averages the results of these 8 times to obtain the final result after oversampling.

[0072] The startup conversion module 31 (SOC generate module) is used to generate multiple second startup conversion signals according to the first startup conversion signal and the oversampling configuration information. Exemplarily, the oversampling configuration information indicates that 8 times oversampling is required. The startup conversion module 31 generates 8 SOC control signals and sends these 8 SOC control signals to the control module 26.

[0073] The SOC generate module receives the SOC control signal from the digital module and combines it with the oversampling setting. For example, if the oversampling value is configured as OS<2:0>=010, it means oversampling 8 times. That is, one SOC control signal from the digital module needs to be triggered and generated in the analog circuit. 8 SOC control signals will be sampled and quantized once in the analog circuit. 8 times of oversampling will result in 8 sampling and quantization conversion results. The subsequent digital module needs to average these 8 results to get the final result. The sampling polling module is all analog module and is implemented through analog circuit.

[0074] The three sampling channels have corresponding three SOC signals (SOC0, SOC1, SOC2). SOC<2:0> is controlled by the digital module and is input to the analog module (sampling polling module 30) by the digital module. Initially, SOC<2:0>=000, and the selection channel of the multiplexer 111 can start sampling the sampling capacitor 112. When the digital module sets the SOC signal to 1, the sampling and quantization of the first capacitor array 23 and the second capacitor array 24 are started, that is, the conversion of the analog-to-digital converter is performed.

[0075] Before the SOC signal is set to 1, the digital module needs to configure the oversampling configuration OS<2:0> and send the oversampling configuration OS<2:0> to the analog module (sampling polling module 30).

[0076] When the SOC signal is set to 1, the start conversion module 31 generates a corresponding number of SOC signals according to the oversampling configuration value to determine whether to oversample and the oversampling multiple. For example, if the oversampling value OS<2:0>=010 is configured to be 8 times oversampling, SOC0 will generate 8 SOC0s in sequence.

[0077] For example, if the oversampling register is set to 000, it means no oversampling, and the generated SOC signal is the SOC signal input by the digital module. If the oversampling register is set to 010, then according to the design of the analog circuit, it is oversampled 8 times, and 8 SOC signals will be generated. The time interval between the 8 SOC signals is a conversion cycle (sampling time + quantization time) designed by the analog circuit. The 8 oversampled SOC intervals are generated by the timing logic of the analog circuit.

[0078] The control module 26 is used to send the multiple second start conversion signals to the multi-channel sampling module 10 one by one, so that the sampling circuit, when receiving the corresponding second start conversion signal, maintains the sampled input signal and mirrors the input signal to the first capacitor array 23 and the second capacitor array 24.

[0079] The first start conversion signal corresponds to a certain sampling circuit 11, that is, the sampling circuit 11 is quantized and converted. The multiple second start conversion signals generated according to the first start conversion signal and the oversampling configuration information also correspond to the sampling circuit 11, and are used to perform quantization conversion on the sampling circuit 11. The control module 26 is used to send the multiple second start conversion signals to the multi-channel sampling module 10 one by one, so that the sampling circuit, when receiving the corresponding second start conversion signal, maintains the sampled input signal, mirrors the input signal to the first capacitor array 23 and the second capacitor array 24, and performs subsequent quantization. One second start conversion signal corresponds to one quantization conversion, and multiple second start conversion signals correspond to multiple quantization conversions.

[0080] In the embodiment of the present invention, the sampling polling module 30 includes an end conversion module 32 .

[0081] The end conversion module 32 (EOCgenerate module) is used to obtain the number of input signals corresponding to the sampling circuit 11 that have completed comparison. When the number of input signals corresponding to the sampling circuit 11 that have completed comparison meets the target number in the oversampling configuration information, the conversion completion signal corresponding to the sampling circuit 11 is sent to the digital module. The end conversion module 32 generates the final EOC EOC_out according to the EOC_in signal and OS<2:0>. When the number of input signals corresponding to the sampling circuit 11 that have completed comparison is equal to the target number in the sampling configuration information, the conversion completion signal EOC_out corresponding to the sampling circuit 11 is sent to the digital module. Exemplarily, when the number of input signals corresponding to the sampling circuit 11 that have completed comparison is 8, that is, the sampling circuit 11 has completed 8 quantization conversions according to 8 SOC signals, and the target number in the oversampling configuration information is 8 times, it means that the quantization conversion of the sampling circuit 11 has been completed, and the end conversion module 32 sends the conversion completion signal corresponding to the sampling circuit 11 to the digital module.

[0082] The digital module is used for sending a start conversion signal corresponding to the next sampling circuit 11 to the start conversion module 31 after receiving the conversion completion signal corresponding to the sampling circuit 11 .

[0083] The digital module is used to determine that the conversion of the sampling circuit 11 has been completed after receiving the conversion completion signal corresponding to the sampling circuit 11, and can send a start conversion signal corresponding to the next sampling circuit 11 to the start conversion module 31 to convert the next sampling circuit 11, thereby performing quantization conversion on the three sampling circuits 11 that are sampled simultaneously in turn, and realizing the sampling and quantization of multiple signals at the same time through the core of an analog-to-digital converter.

[0084] The sampling polling module 30 also includes a polling control module 33. The polling control module 33 can receive SOC0, SOC1 and SOC2 sent by the start conversion module 31. The three SOC signals corresponding to the three-way sampling are SOC0, SOC1 and SOC2 respectively. The polling control module 33 can also receive the EOC_out signal sent by the end conversion module 32. The EOC_out signal indicates that the conversion of the corresponding sampling circuit 11 is completed. The polling control module 33 can also receive a RESET reset signal. The polling control module 33 is used to output Switch0, Switch1 and Switch2 signals. The SOC<2:0> signal of the start conversion module 31 is sent by a trigger. The sampling polling module 30 includes two triggers. The digital module needs to control the preset clock to send the SOC<2:0>_pre signal to the start conversion module 31 in advance before the sampling is completed, so two triggers are required to achieve data synchronization.

[0085] The trigger is used to store and transfer data to ensure the stability and consistency of the analog-to-digital conversion process. The functions of the trigger are: Data storage: The trigger is used to store input data and output data under the control of the clock signal; Data transfer: The trigger is used to transfer data between different modules to ensure the stability and consistency of the data. Main components: D input: used to receive input data; Q output: used to output stored data; Clock signal (CLK): used to control the storage and output operations of the trigger; Reset signal (RST): used to reset the trigger and clear the stored data. By connecting two triggers, you can achieve: Data synchronization: By connecting two triggers, you can achieve synchronous data transmission to ensure data stability and consistency; Data transmission control: By connecting two triggers, you can achieve data transmission control to ensure data transmission order and timing; Timing control: By connecting two triggers, you can achieve complex timing control to ensure system stability and consistency.

[0086] In the embodiment of the present invention, the sampling circuit 11 further includes an analog buffer 113 ; the control module 26 is used to mirror the input signal to the first capacitor array 23 and the second capacitor array 24 through the analog buffer 113 .

[0087] The circuit of analog buffer 113 (Analog Buffer, A_buffer) can be composed of an operational amplifier, whose input is connected to the signal source and whose output is connected to the load. The feedback network of the operational amplifier is usually a unity gain configuration, that is, the output is directly fed back to the input to achieve accurate replication of the signal. The analog buffer is an electronic circuit used to provide signal isolation and enhancement during the transmission of analog signals. Its main functions include: signal isolation: prevent mutual influence between the signal source and the load, and ensure that the output of the signal source is not affected by load changes; signal enhancement: provide sufficient current driving capability to drive subsequent circuits or loads; impedance matching: provide appropriate impedance matching between the signal source and the load to reduce signal reflection and distortion.

[0088] According to the channel selection signal, the sampling circuit 11 samples when the channel is selected, and the input signal charges the sampling capacitor 11 in front of the analog buffer 113; according to the three-to-one switch SOC<2:0>, after the three-to-one switch is selected, the voltage on the sampling capacitor is mirrored to the capacitor array through the analog buffer 113 (which can be called Cdac sampling), which is completed by the sampling capacitor 112, the switch, the analog buffer 113, and the holding capacitor (Cdac capacitor array).

[0089] The sampling during channel selection is to convert the input signal voltage into a charge amount and store it on the sampling capacitor 112. The length of this time is determined by the signal voltage, the channel impedance and the size of the sampling capacitor and the required accuracy. This time is determined by the time interval between the channel selection signal and the SOC signal sent by the digital module. The digital module can control the length of the time interval to set the sampling time.

[0090] The input end of the analog buffer 113 is connected to the sampling capacitor 112 , and the output end is connected to the capacitor array, so that the signal of the sampling capacitor 112 can be mirror-copied to the capacitor array, while providing signal isolation and enhancement.

[0091] In an embodiment of the present invention, the conversion circuit further includes:

[0092] The digital calibration module 40 is connected to the core module 20 , and is used to digitally calibrate the signals obtained after the core 20 quantizes the input signals of the plurality of sampling circuits 11 .

[0093] The digital calibration module 40 (Digital Calibration) performs digital filtering and gain / offset error calibration on the output signal of the analog-to-digital converter. The main goals of digital calibration are: improving accuracy: reducing system errors through calibration and improving the accuracy of measurement and conversion; compensating nonlinearity: calibration can compensate for the nonlinear characteristics of the system and make the output closer to the ideal value; temperature compensation: through digital calibration, the performance of the system can be kept stable at different temperatures; reducing noise: calibration can reduce noise and interference in the system and improve signal quality. In the analog-to-digital converter, digital calibration can be used to compensate for offset error, gain error and nonlinear error, thereby improving conversion accuracy. For example, assuming that we have a 12-bit ADC whose output has offset error and gain error, we can perform digital calibration through the following steps: data acquisition: input known voltages (such as 0V and 5V) and record the output value of the ADC. Error analysis: calculate offset error and gain error. Offset error = actual output - ideal output (when 0V input), gain error = (actual output - offset error) / ideal output (when 5V input), calibration coefficient calculation: offset calibration coefficient = - offset error, gain calibration coefficient = 1 / gain error. Calibration is achieved by applying a calibration factor at the output of the ADC to adjust the output value.

[0094] In the embodiment of the present invention, the preset time is two clock cycles; the digital module is used to send the first start conversion signal corresponding to the sampling circuit to the start conversion module 31 two clock cycles before the multi-channel sampling module 10 performs sampling and the sampling ends.

[0095] The digital module controls the SOC<2:0>_pre signal to start the conversion module 31 2 clock cycles before the sampling is completed. This is an asynchronous to synchronous design. By sending the SOC 2 clock cycles before the end of the sampling, the reliability of data reception can be further improved without reducing the sampling rate. The sampling time can be configured by the digital register.

[0096] In the embodiment of the present invention, the number of the sampling switches 21 is two; when the input signal is a differential input signal, the control module 26 is used to control the two sampling switches 21 to be turned on; when the input signal is a single-ended input signal, the control module 26 is used to control one of the two sampling switches 21 to be turned on.

[0097] There are two sampling switches 21 (Sample Switch, Sample_sw). When the input signal is a differential input signal, the control module 26 is used to control the two sampling switches 21 to be fully turned on so that the positive signal and the negative signal of the differential input signal are transmitted to the first capacitor array 23 and the second capacitor array 24 through the two sampling switches 21.

[0098] When the input signal is a single-ended input signal, the control module 26 is used to control one of the two sampling switches 21 to be turned on, so that the single-ended input signal is transmitted to the first capacitor array 23 and the second capacitor array 24 through one of the sampling switches 21 .

[0099] Reference Figure 4 , which is a schematic diagram showing a simulation waveform of a startup conversion module according to an embodiment of the present invention, Figure 4 The simulation waveform of the SOC generating circuit with OS<2:0>=010 and an 8-time oversampling configuration is shown. The SOC generating circuit is the startup conversion module 31, which is an analog circuit. The startup conversion module 31 determines whether to oversample according to the oversampling configuration to generate SOC and EOC corresponding to the oversampling times. Figure 4 The signals from top to bottom are: clock signal, SOC enable signal, SOC_OUT SOC output signal, OS <0> , OS <1> , OS <2> Oversampling configuration signal, SOC enables and starts generating the corresponding number of SOC_OUT according to the number of OS oversampling times.

[0100] The SOC (Start of Conversion) enable signal is an important control signal used to start the conversion process of the analog-to-digital converter. The SOC signal is usually a pulse signal. When it is activated, the analog-to-digital converter starts sampling and converting the input signal.

[0101] SOC_OUT The SOC output signal refers to the output of the conversion start signal. This signal can be used to notify the external circuit or system that the ADC has started the conversion process. The SOC_OUT signal is usually a pulse signal, which is activated for one clock cycle when the ADC starts converting.

[0102] Reference Figure 5 , which is a schematic diagram showing a circuit simulation waveform of an end conversion module according to an embodiment of the present invention, Figure 5 The simulation waveform of the EOC generating circuit configured for 32 times oversampling when OS<2:0>=100 is shown. The EOC generating circuit is the end conversion module 32, which is an analog circuit. The EOC generating circuit generates the final eoc (eoc_out) output according to eoc (eoc_in) and the number of oversampling times to indicate whether the conversion is completed. Figure 5 The signals from top to bottom are: reset signal, clock signal, EOC enable signal, EOC_OUT EOC output signal. EOC enable, EOC_OUT is generated according to the number of EOC_IN corresponding to the number of OS oversampling times.

[0103] The EOC enable signal is usually an internal signal used to indicate that the ADC conversion process has been completed. It is mainly used for internal logic control to ensure that the ADC performs corresponding processing after the conversion is completed. The EOC_OUT signal is an output signal used to notify the external system that the ADC conversion process has been completed. It is mainly used for synchronization and data reading of external systems.

[0104] Reference Figure 6 , which shows a schematic diagram of the polling logic simulation result of an embodiment of the present invention, Figure 5 The signals from top to bottom are: reset signal, SAR ADC quantization end signal, channel conduction selection signal, channel conduction completion signal, channel switch. When the SOC signal is high, the channel is selected for quantization. After the SAR ADC quantization is completed, an EOC signal will be generated so that the SAR ADC will start to select another channel to store information.

[0105] The embodiment of the present invention can realize the function of 3-way simultaneous sampling and 1-way conversion. Through channel configuration, 3-way simultaneous sampling is realized, and through polling design, 3-way polling conversion is completed. Finally, the function of 3-way simultaneous sampling and 1-way conversion is realized. At the same time, the conversion start SOC signal is output to the conversion circuit 2 beats in advance, and 2 beats are made in the conversion circuit to realize asynchronous to synchronous conversion, which enhances the reliability of accurate data reception. Oversampling design is added to the sampling function to further improve the accuracy of data sampling.

[0106] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0107] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0108] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0109] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable terminal device. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0111] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0112] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0113] The above is a detailed introduction to the conversion circuit of an analog-to-digital converter provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A conversion circuit of an analog-to-digital converter, characterized in that: include: A multi-channel sampling module, comprising a plurality of sampling circuits, wherein the plurality of sampling circuits are used to simultaneously collect input signals; A core connected to the multi-channel sampling module, configured to respectively receive input signals sent by the plurality of sampling circuits, and respectively quantize the input signals of the plurality of sampling circuits; The sampling polling module is connected to the core and the multi-channel sampling module, and is used to control the core to connect to the multiple sampling circuits one by one.

2. The conversion circuit according to claim 1, characterized in that: Each of the sampling circuits includes a multiplexer and a corresponding sampling capacitor; The multiplexers are respectively used to simultaneously receive channel selection signals, select a target sampling channel according to the channel selection signal, obtain an input signal through the target sampling channel, and transmit the input signal to a corresponding sampling capacitor.

3. The conversion circuit according to claim 1, characterized in that: The kernel includes: A sampling switch, a sampling mode selection module connected to the sampling switch, a first capacitor array and a second capacitor array connected to the sampling mode selection module, a comparator and a control module connected to the sampling mode selection module; The sampling mode selection module is used for mirroring the input signal collected by the sampling circuit to the first capacitor array and the second capacitor array according to the type of the input signal when the sampling switch is turned on; The first capacitor array and the second capacitor array are used to transmit the mirrored input signal to the comparator; The comparator is used for comparing input signals of the first capacitor array and the second capacitor array to obtain a comparison result.

4. The conversion circuit according to claim 3, characterized in that: The sampling mode selection module is used to control the upper and lower plates of the capacitors of the first capacitor array and the second capacitor array to be disconnected when the input signal is a differential input signal, so that the first capacitor array and the second capacitor array receive the positive signal and the negative phase signal of the differential input signal; when the input signal is a single-ended input signal, control the upper and lower plates of the capacitors of the first capacitor array and the second capacitor array to be connected, so that the first capacitor array and the second capacitor array receive the single-ended input signal.

5. The conversion circuit according to claim 3, characterized in that: The conversion circuit further includes a digital module, and the sampling polling module includes a start conversion module; The digital module is used to send a first start conversion signal corresponding to the sampling circuit to the start conversion module before the preset time when the multi-channel sampling module performs sampling and the sampling ends; The startup conversion module is used to generate a plurality of second startup conversion signals according to the first startup conversion signal and the oversampling configuration information, and send the plurality of second startup conversion signals to the control module; The control module is used to send the multiple second start conversion signals to the multi-channel sampling module one by one, so that the sampling circuit, when receiving the corresponding second start conversion signal, maintains the sampled input signal and mirrors the input signal to the first capacitor array and the second capacitor array.

6. The conversion circuit according to claim 5, characterized in that: The sampling polling module includes an end conversion module; The conversion end module is used to obtain the number of input signals corresponding to the sampling circuit that have completed comparison, and when the number of input signals corresponding to the sampling circuit that have completed comparison meets the target number in the oversampling configuration information, send a conversion completion signal corresponding to the sampling circuit to the digital module; The digital module is used for sending a next start conversion signal corresponding to the sampling circuit to the start conversion module after receiving the conversion completion signal corresponding to the sampling circuit.

7. The conversion circuit according to claim 5, characterized in that: The sampling circuit further includes an analog buffer; the control module is used for mirroring the input signal to the first capacitor array and the second capacitor array through the analog buffer.

8. The conversion circuit according to claim 1, characterized in that: Also includes: A digital calibration module connected to the core module, the digital calibration module is used to digitally calibrate the signals obtained after the core quantizes the input signals of the multiple sampling circuits respectively.

9. The conversion circuit according to claim 5, characterized in that: The preset time is two clock cycles; the digital module is used to send a first start conversion signal corresponding to the sampling circuit to the start conversion module two clock cycles before the multi-channel sampling module performs sampling and the sampling ends.

10. The conversion circuit according to claim 3, characterized in that: The number of the sampling switches is two; when the input signal is a differential input signal, the control module is used to control the two sampling switches to be turned on; when the input signal is a single-ended input signal, the control module is used to control one of the two sampling switches to be turned on.

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