Clock synchronization method and circuit for different roll-off signals

Abstract

The invention provides a clock synchronization method and circuit for different roll-off signals. The method comprises the following steps: determining whether an asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal; if the asynchronous sampling sequence signal is a large roll-off signal, performing clock synchronization on the large roll-off signal by a first clock synchronization loop, and outputting a first synchronization sequence signal; and if the asynchronous sampling sequence signal is a small roll-off signal, performing clock synchronization on the small roll-off signal by a second clock synchronization loop, and outputting a second synchronization sequence signal. The method can be suitable for optical transmission systems with different roll-off factors, and meanwhile, the clock recovery requirements of signals with different rates and different roll-off factors are met, so that a receiving end can sample at the optimal sampling moment, and then information sent by a sending end is accurately recovered.

Description

Technical Field

[0001] The present invention relates to the technical field of communication signal processing, and in particular to a clock synchronization method and circuit for different roll-off signals. Background Art

[0002] With the explosive growth of data traffic and the diversification of application requirements, traditional fixed grid optical networks can no longer meet the needs of existing optical networks. To meet this challenge, elastic optical networks (EONs) are proposed to break the bandwidth limitations of fixed channels. Through gridless, multi-granular transceivers, EONs can achieve more flexible and efficient spectrum resource allocation. This flexible spectrum management can meet the diverse application requirements of different data rates. However, EON requires transceivers to have higher dynamic adaptability, such as the ability to support multiple modulation formats and dynamically adjust the transmission rate, in order to maintain efficient and stable signal transmission under different spectrum conditions.

[0003] Digital signal processing (DSP) technology provides coherent optical communication systems with support for high-order modulation formats and the ability to flexibly adapt to different transmission environments. As an important component of DSP, clock synchronization can effectively reduce or eliminate interference caused by misalignment of the receiver and transmitter clocks, which can cause symbol overlap or displacement. In order to accurately determine the clock, the Gardner algorithm is a typical clock recovery algorithm, which is known for its simplicity, stability and wide applicability, but it cannot be applied to low roll-off transmission systems. In low-speed Nyquist transmission systems, large roll-off shaping filters are generally widely used. In high-speed Nyquist communication systems, the roll-off factor is usually designed to be as small as possible. The existing Gardner algorithm is difficult to meet the clock recovery requirements of different rate signals with different roll-off factors.

[0004] In order to solve the above problems, Li et al. used an extended hardware clock phase-locked loop (PLL) circuit to handle larger clock frequency offsets; Zhu et al. used gain control processing in the interpolation loop to achieve fast adjustment and reduce timing errors; Bazin et al. proposed a non-data-assisted timing delay estimation method in an iterative manner, which is an algorithm that can recover all symbols in short pulse transmission and is easy to implement. Although the above methods have good effects in systems with higher roll-off factors, they lack improvement and still do not achieve good results in optical transmission systems with lower roll-off factors.

[0005] Therefore, based on the fourth-law PD (4PPD) algorithm proposed by Fang et al., et al. proposed a fourth-order improved Gardner algorithm specifically for low roll-off transmission systems, called MGPD (improved 4PPD algorithm). However, the existing Gardner algorithm and its improved method have the following defects: they are only applicable to a single low roll-off system or a high roll-off system, and their application scope is relatively limited. Even if data is transmitted through EON, it is easy to cause a waste of spectrum resources. Summary of the invention

[0006] In view of this, an embodiment of the present invention provides a clock synchronization method and circuit for different roll-off signals to eliminate or improve one or more defects in the prior art.

[0007] One aspect of the present invention provides a clock synchronization method for different roll-off signals, the method comprising the following steps:

[0008] Determine whether the asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal, wherein the asynchronous sampling sequence signal is obtained by asynchronously sampling a signal received by a receiving end;

[0009] If the asynchronous sampling sequence signal is a large roll-off signal, the first clock synchronization loop performs clock synchronization on the large roll-off signal and outputs a first synchronization sequence signal; the first clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a preprocessing filter is provided between the interpolation filter and the timing error detector, and the algorithm adopted by the timing error detector is realized by the difference between the theoretical value and the actual value of the interpolation point between every two symbols in the signal output by the preprocessing filter when the interpolation is accurate and the peak symbol function;

[0010] If the asynchronous sampling sequence signal is a small roll-off signal, the second clock synchronization loop performs clock synchronization on the small roll-off signal and outputs a second synchronization sequence signal; the second clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a multiplication operation module is provided between the loop filter and the interpolation controller.

[0011] In some embodiments of the present invention, determining whether the asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal includes:

[0012] If the number of positive sample values ​​among the multiple sample values ​​at the end of the sequence of the asynchronous sampling sequence signal is greater than the number of negative sample values, then the asynchronous sampling sequence signal is a large roll-off signal;

[0013] If the number of positive sample values ​​among the multiple sample values ​​at the end of the sequence of the asynchronous sampling sequence signal is less than the number of negative sample values, the asynchronous sampling sequence signal is a small roll-off signal.

[0014] In some embodiments of the present invention, the first clock synchronization loop includes a first interpolation filter, a preprocessing filter, a first timing error detector, a first loop filter and a first interpolation controller; the first clock synchronization loop performs clock synchronization on the large roll-off signal and outputs a first synchronization sequence signal, including:

[0015] The first interpolation filter performs interpolation processing on the large roll-off signal based on an initial first fractional interval, outputs a large roll-off interpolation sequence signal, and transmits the output large roll-off interpolation sequence signal to the preprocessing filter;

[0016] The preprocessing filter performs filtering preprocessing on the output large roll-off interpolation sequence signal, outputs the large roll-off interpolation sequence signal after removing the loop self-noise, and transmits the output large roll-off interpolation sequence signal after removing the loop self-noise to the first timing error detector;

[0017] The first timing error detector detects and calculates the clock phase error of the output large roll-off interpolation sequence signal after the loop self-noise is removed, outputs a first timing error, and transmits the output first timing error to the first loop filter;

[0018] The first loop filter generates a first control signal based on the output first timing error, and transmits the generated first control signal to the first interpolation controller;

[0019] The first interpolation controller generates a first interpolation base point based on the output first control signal, outputs a first fractional interval based on the generated first interpolation base point, and transmits the output first fractional interval to the first interpolation filter;

[0020] The first interpolation filter adjusts and updates the output large roll-off interpolation sequence signal based on the output first fractional interval until the absolute value of the difference between the first fractional interval output by the first interpolation controller and the first target fractional interval is less than a first preset threshold, and the first interpolation filter correspondingly outputs the large roll-off interpolation sequence signal as the first synchronization sequence signal.

[0021] In some embodiments of the present invention, the coefficients of the pre-processing filter are calculated by a particle swarm algorithm that dynamically updates the inertia weight and the acceleration coefficient.

[0022] In some embodiments of the present invention, the timing error detector in the first clock synchronization loop uses an improved Gardner algorithm to detect and calculate the clock phase error of the large roll-off interpolation sequence signal output by the preprocessing filter after removing the loop self-noise, and outputs a first timing error. The calculation formula is as follows:

[0023]

[0024] Among them, te(kT i ) high Represents the first timing error of the output, α is the roll-off factor, x I (kT i ) and x Q (kT i ) represent the kTth value in the large roll-off interpolation sequence signal after removing the loop self-noise received by the timing error detector. i The in-phase component and the kT i orthogonal components, and Respectively represent the kT i The previous interpolation point of the in-phase component and the orthogonal component, x I (kT i -1) and x Q (kT i -1) respectively represent the kT i The first second interpolation point of the in-phase component and the orthogonal component, sgn() represents the peak sign function.

[0025] In some embodiments of the present invention, the second clock synchronization loop includes a second interpolation filter, a second timing error detector, a second loop filter, a multiplication module, and a second interpolation controller; the second clock synchronization loop performs clock synchronization on the small roll-off signal and outputs a second synchronization sequence signal, including:

[0026] The second interpolation filter performs interpolation processing on the small roll-off signal based on the initial second fractional interval, outputs a small roll-off interpolation sequence signal, and transmits the output small roll-off interpolation sequence signal to the second timing error detector;

[0027] The second timing error detector detects and calculates the clock phase error of the output small roll-off interpolation sequence signal, outputs a second timing error, and transmits the output second timing error to the second loop filter;

[0028] The second loop filter generates a second control signal based on the output second timing error, and transmits the generated second control signal to the multiplication operation module;

[0029] The multiplication module multiplies the output second control signal and the gain factor, outputs the second control signal after the gain factor acts on it, and transmits the output second control signal after the gain factor acts on it to the second interpolation controller;

[0030] The second interpolation controller generates a second interpolation base point based on the output second control signal after the output gain factor is applied, outputs a second fractional interval based on the generated second interpolation base point, and transmits the output second fractional interval to the second interpolation filter;

[0031] The second interpolation filter adjusts and updates the output small roll-off interpolation sequence signal based on the output second fractional interval until the absolute value of the difference between the second fractional interval output by the second interpolation controller and the second target fractional interval is less than a second preset threshold, and the corresponding small roll-off interpolation sequence signal output by the second interpolation filter is used as the second synchronization sequence signal.

[0032] In some embodiments of the present invention, the multiplication module multiplies the output second control signal and the gain factor, and outputs the second control signal after the gain factor is applied. The calculation formula is as follows:

[0033] ω(k+1)={ω(k)+C1[te(k+1)-te(k)]+C2te(k+1)}*G

[0034] Among them, ω(k+1) represents the second control signal after the output gain factor acts, k represents the interpolation point number in the output small roll-off interpolation sequence signal, C1 represents the proportional coefficient, C2 represents the integral coefficient, and C1 is much larger than C2, te(k+1) represents the second timing error of the output, and G represents the gain factor.

[0035] Another aspect of the present invention provides a clock synchronization circuit for different roll-off signals, the circuit comprising:

[0036] A signal determination module, used to determine whether an asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal, wherein the asynchronous sampling sequence signal is obtained by asynchronously sampling a signal received by a receiving end;

[0037] a first clock synchronization loop, used for performing clock synchronization on the large roll-off signal and outputting a first synchronization sequence signal when the asynchronous sampling sequence signal is a large roll-off signal; the first clock synchronization loop comprises an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a preprocessing filter is provided between the interpolation filter and the timing error detector, and the algorithm adopted by the timing error detector is realized by the difference between the theoretical value and the actual value of the interpolation point between every two symbols in the signal output by the preprocessing filter when the interpolation is accurate and the peak symbol function; and

[0038] The second clock synchronization loop is used to perform clock synchronization on the small roll-off signal and output a second synchronization sequence signal when the asynchronous sampling sequence signal is a small roll-off signal; the second clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a multiplication operation module is provided between the loop filter and the interpolation controller.

[0039] In some embodiments of the present invention, the first clock synchronization loop includes a first interpolation filter, a preprocessing filter, a first timing error detector, a first loop filter and a first interpolation controller.

[0040] The first interpolation filter is used to perform interpolation processing on the large roll-off signal based on an initial first fractional interval, output a large roll-off interpolation sequence signal, and transmit the output large roll-off interpolation sequence signal to the preprocessing filter;

[0041] The preprocessing filter is used to perform filtering preprocessing on the output large roll-off interpolation sequence signal, output the large roll-off interpolation sequence signal after removing the loop self-noise, and transmit the output large roll-off interpolation sequence signal after removing the loop self-noise to the first timing error detector;

[0042] The first timing error detector is used to detect and calculate the clock phase error of the output large roll-off interpolation sequence signal after the loop self-noise is removed, output a first timing error, and transmit the output first timing error to the first loop filter;

[0043] The first loop filter is used to generate a first control signal based on the output first timing error, and transmit the generated first control signal to the first interpolation controller;

[0044] The first interpolation controller is used to generate a first interpolation base point based on the output first control signal, output a first fractional interval based on the generated first interpolation base point, and transmit the output first fractional interval to the first interpolation filter;

[0045] The first interpolation filter is used to adjust and update the output large roll-off interpolation sequence signal based on the output first fractional interval until the absolute value of the difference between the first fractional interval output by the first interpolation controller and the first target fractional interval is less than a first preset threshold, and the first interpolation filter corresponds to the output large roll-off interpolation sequence signal as the first synchronization sequence signal.

[0046] In some embodiments of the present invention, the second clock synchronization loop includes a second interpolation filter, a second timing error detector, a second loop filter, a multiplication module and a second interpolation controller.

[0047] The second interpolation filter is used to perform interpolation processing on the small roll-off signal based on the initial second fractional interval, output a small roll-off interpolation sequence signal, and transmit the output small roll-off interpolation sequence signal to the second timing error detector;

[0048] The second timing error detector is used to detect and calculate the clock phase error of the output small roll-off interpolation sequence signal, output a second timing error, and transmit the output second timing error to the second loop filter;

[0049] The second loop filter is used to generate a second control signal based on the output second timing error, and transmit the generated second control signal to the multiplication operation module;

[0050] The multiplication module is used for multiplying the output second control signal and the gain factor, outputting the second control signal after the gain factor acts on it, and transmitting the output second control signal after the gain factor acts on it to the second interpolation controller;

[0051] The second interpolation controller is used to generate a second interpolation base point based on the output second control signal after the gain factor is applied, output a second fractional interval based on the generated second interpolation base point, and transmit the output second fractional interval to the second interpolation filter;

[0052] The second interpolation filter is used to adjust and update the output small roll-off interpolation sequence signal based on the output second fractional interval until the absolute value of the difference between the second fractional interval output by the second interpolation controller and the second target fractional interval is less than a second preset threshold, and the small roll-off interpolation sequence signal corresponding to the output of the second interpolation filter is used as the second synchronization sequence signal.

[0053] Another aspect of the present invention provides an electronic device, which includes: a computer device, wherein the computer device includes a processor and a memory, wherein the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. When the computer instructions are executed by the processor, the device implements the steps of the aforementioned clock synchronization method.

[0054] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to implement the steps of the aforementioned clock synchronization method.

[0055] Another aspect of the present invention provides a computer program product, comprising computer instructions, which implement the steps of the aforementioned clock synchronization method when executed by a processor.

[0056] The clock synchronization method and circuit for different roll-off signals of the present invention adaptively adopt corresponding clock synchronization loops to complete clock synchronization for different roll-off signals, and can be applicable to optical transmission systems with different roll-off coefficients, while meeting the clock recovery requirements of different rate signals with different roll-off factors, so that the receiving end can achieve that different roll-off signals can be sampled at the optimal sampling time, and then accurately recover the information sent by the sending end.

[0057] Additional advantages, purposes, and features of the present invention will be described in part in the following description, and will become apparent to those skilled in the art after studying the following, or may be learned from the practice of the present invention. The purposes and other advantages of the present invention may be achieved and obtained by the structures specifically indicated in the specification and the accompanying drawings.

[0058] Those skilled in the art will appreciate that the objectives and advantages that can be achieved with the present invention are not limited to the above specific description, and the above and other objectives that can be achieved by the present invention will be more clearly understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention.

[0060] Figure 1 1 is a flow chart of a clock synchronization method for different roll-off signals according to an embodiment of the present invention;

[0061] Figure 2 It is a schematic diagram of a specific flow chart of a clock synchronization method for different roll-off signals in one embodiment of the present invention;

[0062] Figure 3 Schematic diagram of the structure of a clock synchronization circuit for different roll-off signals in one embodiment of the present invention;

[0063] Figure 4 It is a schematic diagram comparing the convergence speeds of the first clock synchronization loop and the Gardner algorithm for a large roll-off signal in one embodiment of the present invention;

[0064] Figure 5 Schematic diagram of timing jitter comparison between the second clock synchronization loop for small roll-off signals and the MPGD and 4PPD algorithms in one embodiment of the present invention. DETAILED DESCRIPTION

[0065] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments and the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0066] It should also be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0067] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0068] It should also be noted that, unless otherwise specified, the term “connection” herein may refer not only to a direct connection but also to an indirect connection involving an intermediate.

[0069] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar components, or the same or similar steps.

[0070] The receiving end of the elastic optical network usually uses a local sampling clock to extract the input signal. s Equal to the symbol rate period T i , and when sampling is performed at the optimal sampling time, the symbol information sent by the transmitter can be accurately recovered. However, in actual application systems, the receiving end cannot perform sampling at the optimal sampling time due to the timing phase offset caused by the channel transmission delay, the heterogeneous clock frequency deviation at both ends of the transmitter and receiver, and the timing frequency offset caused by the Doppler frequency shift. However, different sampling times correspond to different signal amplitudes, which causes a deviation between the recovered symbol information and the symbol information sent by the transmitter. Therefore, in order to solve the above problems, and to be applicable to optical transmission systems with different roll-off factors, while meeting the clock recovery requirements of different rate signals with different roll-off factors, an embodiment of the present invention proposes a clock synchronization method and circuit for different roll-off signals.

[0071] Figure 1 and Figure 2 They are respectively a flow chart and a specific flow chart of a clock synchronization method for different roll-off signals in one embodiment of the present invention. Figure 1 and Figure 2 As shown, the method is executed by a receiving end of an elastic optical network and includes the following steps:

[0072] Step S110, determining whether the asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal, wherein the asynchronous sampling sequence signal is obtained by asynchronously sampling a signal received by a receiving end.

[0073] In the field of communications, the definition of a large roll-off signal is as follows: when the roll-off coefficient (or roll-off factor) is large, the signal decays faster at the edge of the spectrum, and this signal is called a large roll-off signal; a large roll-off signal has a narrow spectrum width and a high anti-interference ability. The definition of a small roll-off signal is as follows: when the roll-off coefficient (or roll-off factor) is small, the signal decays slower at the edge of the spectrum, and this signal is called a small roll-off signal; a small roll-off signal has a wide spectrum width and a high spectrum efficiency.

[0074] In some embodiments, determining in step S110 that the asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal includes the following steps:

[0075] Step S111, if the number of positive sample values ​​among the multiple sample values ​​at the end of the sequence of the asynchronous sampling sequence signal is greater than the number of negative sample values, then the asynchronous sampling sequence signal is a large roll-off signal;

[0076] Step S112: If the number of positive sample values ​​among the multiple sample values ​​at the end of the sequence of the asynchronous sampling sequence signal is less than the number of negative sample values, the asynchronous sampling sequence signal is a small roll-off signal.

[0077] Specifically, the transmitter of the elastic optical network adds m0 bits to the end of the bit sequence of the signal to be sent according to the roll-off factor of the shaping filter to form an updated bit sequence for a symbol composed of m0 bits. The Euclidean distance between the corresponding point and the origin on the constellation diagram formed by the constellation mapping is the largest, and when the roll-off factor is large (the roll-off factor is greater than the roll-off factor threshold), the updated bit sequence is mapped to the first quadrant, and when the roll-off factor is small (the roll-off factor is less than the roll-off factor threshold), the updated bit sequence is mapped to the third quadrant. Then, the mapped sequence is shaped by the shaping filter and multiple symbols are output, and the multiple symbols are transmitted to the receiving end (the electrical signal is converted into an optical signal before transmission).

[0078] The coherent receiver at the receiving end receives the in-phase (I) and quadrature (Q) signals composed of multiple symbols from the transmitting end (after receiving, the optical signal is converted into an electrical signal), and transmits the two signals to the ADC sampling module. The ADC sampling module performs asynchronous sampling on the two signals to obtain the I and Q asynchronous sampling sequences X(mT s ), T sis the asynchronous sampling period, and m is the sampling point number of the asynchronous sampling. When the asynchronous sampling frequency is p times the symbol rate, the loop that the asynchronous sampling sequence should enter next can be determined based on the positive and negative values ​​of the 2(p-1) sample values ​​at the end of the I and Q asynchronous sampling sequences. If the number of positive sample values ​​in the 2(p-1) sample values ​​is greater than the number of negative sample values, the asynchronous sampling sequence is determined to be a large roll-off signal and the asynchronous sampling sequence is transmitted to the first clock synchronization loop; if the number of positive sample values ​​in the 2(p-1) sample values ​​is less than the number of negative sample values, the asynchronous sampling sequence is determined to be a small roll-off signal and the asynchronous sampling sequence is transmitted to the second clock synchronization loop.

[0079] Step S120, if the asynchronous sampling sequence signal is a large roll-off signal, the first clock synchronization loop performs clock synchronization on the large roll-off signal and outputs a first synchronization sequence signal; the first clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a preprocessing filter is provided between the interpolation filter and the timing error detector, and the algorithm adopted by the timing error detector is realized by the difference between the theoretical value and the actual value of the interpolation point between every two symbols in the signal output by the preprocessing filter when the interpolation is accurate and the peak symbol function.

[0080] In some embodiments, the first clock synchronization loop includes a first interpolation filter, a preprocessing filter, a first timing error detector, a first loop filter and a first interpolation controller connected in sequence, and the output end of the first interpolation controller is also connected to the input end of the first interpolation filter. In step S120, the first clock synchronization loop performs clock synchronization on the large roll-off signal and outputs a first synchronization sequence signal, including the following steps:

[0081] Step S121, the first interpolation filter performs interpolation processing on the large roll-off signal based on the initial first fractional interval, outputs a large roll-off interpolation sequence signal, and transmits the output large roll-off interpolation sequence signal to the preprocessing filter;

[0082] Step S122, the preprocessing filter performs filtering preprocessing on the output large roll-off interpolation sequence signal, outputs the large roll-off interpolation sequence signal after removing the loop self-noise, and transmits the output large roll-off interpolation sequence signal after removing the loop self-noise to the first timing error detector;

[0083] Step S123, the first timing error detector detects and calculates the clock phase error of the output large roll-off interpolation sequence signal after the loop self-noise is removed, outputs a first timing error, and transmits the output first timing error to the first loop filter;

[0084] Step S124, generating a first control signal by the first loop filter based on the output first timing error, and transmitting the generated first control signal to the first interpolation controller;

[0085] Step S125, the first interpolation controller generates a first interpolation base point based on the output first control signal, outputs a first fractional interval based on the generated first interpolation base point, and transmits the output first fractional interval to the first interpolation filter;

[0086] Step S126, the first interpolation filter adjusts and updates the output large roll-off interpolation sequence signal based on the output first fractional interval until the absolute value of the difference between the first fractional interval output by the first interpolation controller and the first target fractional interval is less than a first preset threshold (the first clock synchronization loop reaches a convergence state), at which time the first interpolation filter corresponds to the output large roll-off interpolation sequence signal as the first synchronization sequence signal.

[0087] Step S130, if the asynchronous sampling sequence signal is a small roll-off signal, the second clock synchronization loop performs clock synchronization on the small roll-off signal and outputs a second synchronization sequence signal; the second clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a multiplication operation module is provided between the loop filter and the interpolation controller.

[0088] In some embodiments, the second clock synchronization loop includes a second interpolation filter, a second timing error detector, a second loop filter, a multiplication module, and a second interpolation controller connected in sequence, and the output end of the second interpolation controller is also connected to the input end of the second interpolation filter. In step S130, the second clock synchronization loop performs clock synchronization on the small roll-off signal and outputs a second synchronization sequence signal, including the following steps:

[0089] Step S131, the second interpolation filter performs interpolation processing on the small roll-off signal based on the initial second fractional interval, outputs a small roll-off interpolation sequence signal, and transmits the output small roll-off interpolation sequence signal to the second timing error detector;

[0090] Step S132, the second timing error detector detects and calculates the clock phase error of the output small roll-off interpolation sequence signal, outputs a second timing error, and transmits the output second timing error to the second loop filter;

[0091] Step S133, the second loop filter generates a second control signal based on the output second timing error, and transmits the generated second control signal to the multiplication operation module;

[0092] Step S134, the multiplication module multiplies the output second control signal and the gain factor, outputs the second control signal after the gain factor is applied, and transmits the output second control signal after the gain factor is applied to the second interpolation controller;

[0093] Step S135, the second interpolation controller generates a second interpolation base point based on the output second control signal after the output gain factor is applied, outputs a second fractional interval based on the generated second interpolation base point, and transmits the output second fractional interval to the second interpolation filter;

[0094] Step S136, the second interpolation filter adjusts and updates the output small roll-off interpolation sequence signal based on the output second fractional interval until the absolute value of the difference between the second fractional interval output by the second interpolation controller and the second target fractional interval is less than the second preset threshold (the second clock synchronization loop reaches a convergence state), at which time the small roll-off interpolation sequence signal corresponding to the output of the second interpolation filter is used as the second synchronization sequence signal.

[0095] Specifically, the first interpolation filter and the second interpolation filter both use the following interpolation method to adjust the local timing phase of the receiving end, so that the sampling result is as close as possible to the sample value obtained by sampling at the optimal sampling time. The interpolation filter outputs the in-phase or orthogonal (large roll-off or small roll-off) interpolation sequence signal X(kT i ) is:

[0096] X(kT i )=∑X(mT s )h(kT i -mT s )

[0097] Where k represents the interpolation point number in the interpolation sequence signal, T i represents the interpolation period (interval between interpolation points), m represents the sampling point number of asynchronous sampling, T s represents the asynchronous sampling period, T i and T s They are related and satisfy the following relationship (2):

[0098] kT i =(kT i / T s )T s =(m k +μ k )T s

[0099] Among them, m k represents the interpolation value X(kT corresponding to the kth interpolation point i) interpolation base point (the location of the added / deleted data points required by the interpolation filter), μ k represents the interpolation value X(kT corresponding to the kth interpolation point i ), the interpolation base point and the fractional interval are calculated by the interpolation controller; h(t) in formula (1) represents the impulse response of the interpolation filter, the first interpolation filter and the second interpolation filter are both implemented using the FARROW structure, and the expression (3) of the FARROW structure is:

[0100]

[0101] Among them, C l (j) represents the FARROW filter coefficient, j = mm k , l represents the interpolation point, N represents the order of the FARROW filter, Represents the fractional interval corresponding to the interpolation point l.

[0102] By combining the above equations (1), (2) and (3), we can get the expression (4) of the interpolation filter:

[0103]

[0104] Where I1 and I2 represent the tap coefficients of the interpolation filter. Substituting equation (4) into equation (1), we can get the following equation (5):

[0105]

[0106] Among them, Y(kT i ) represents the interpolation sequence signal (large roll-off or small roll-off) of the in-phase or orthogonal path finally output by the interpolation filter, which is the synchronization sequence number. It can be seen from formula (5) that the interpolation value can be calculated using only fractional intervals, avoiding the complex calculation of the filter coefficients.

[0107] According to the principle of polynomial-based interpolation filter, Lagrange polynomial is used to approximate the interpolation point. Substituting the Lagrange polynomial function into equation (4), the expression (6) of the Lagrange interpolation filter can be obtained as follows:

[0108]

[0109] Among them, C i (t) represents the Lagrange coefficient (Lagrange interpolation filter coefficient), which is the final interpolation filter coefficient.

[0110] More specifically, the first interpolation filter uses a piecewise parabola interpolation filter. The interpolation filter (four taps) uses four consecutive sampling points to calculate interpolation. Although its accuracy is lower than that of the cubic interpolation filter, it is easier to implement and requires fewer computing resources. The piecewise parabola interpolation coefficient (piecewise parabola interpolation filter coefficient) is as follows (7):

[0111]

[0112]

[0113]

[0114]

[0115] Where a represents a constant;

[0116] The second interpolation filter adopts a cubic interpolation filter. The cubic interpolation filter (four taps) uses four consecutive sampling points to calculate interpolation, which can improve the clock recovery accuracy of small roll-off signals. The cubic interpolation coefficient (cubic interpolation filter coefficient) is as follows (8):

[0117]

[0118]

[0119]

[0120]

[0121] For large roll-off signals, loop self-noise will be introduced when calculating the timing error. Therefore, before calculating the timing error, it is necessary to use a preprocessing filter to perform bandpass filtering on the large roll-off interpolation sequence signal output by the first interpolation filter to obtain a large roll-off interpolation sequence signal X after removing the loop self-noise in the same phase or orthogonal way. ′ (kT i ), the signal expression (9) is as follows:

[0122]

[0123] Among them, N ′ is the order of the preprocessing filter, n represents the order number, and h(n) is the coefficient of the preprocessing filter, which can be calculated by a particle swarm algorithm (improved particle swarm algorithm) that dynamically updates the inertia weight and acceleration coefficient; the improved particle swarm algorithm can make the actual effect of the preprocessing filter reach the effect of the ideal filter. Specifically, the preprocessing filter adopts a FIR (Finite Impulse Response, finite unit impulse response) filter.

[0124] The steps and principles of the improved particle swarm algorithm are as follows:

[0125] 1) Initialize the particle swarm: The position of each particle in each dimension represents a set of possible FIR filter coefficients h(n). Randomly initialize the position (i.e., FIR filter coefficient) and velocity of each particle in the particle swarm. The position and velocity of each particle refer to a set of positions and velocities composed of positions and velocities in multiple dimensions, x id represents the position of the ith particle in the dth dimension, v id represents the velocity of the ith particle in the dth dimension.

[0126] 2) Determine the fitness function, as shown in formula (10):

[0127]

[0128] Where ω is the digital angular frequency, q = 1, 2, ..., M, M represents the number of equally spaced frequency points in the frequency domain [0, π] interval used to evaluate the performance of the preprocessing filter, q represents the sequence number of the equally spaced frequency points, H d (e jω ) is the frequency response of an ideal bandpass filter. When (1-α)π / 4≤|ω|≤(1+α)π / 4, the frequency range is the passband, otherwise it is the stopband. The purpose of the fitness function is to find a set of FIR filter coefficients to minimize the difference between the actual amplitude-frequency response of the FIR filter and the ideal amplitude-frequency response.

[0129] 3) Update the position and velocity of particles: The velocity of each particle in the r+1th step is updated as follows:

[0130]

[0131] in, represents the speed of the i-th particle at the r+1 step, w represents the inertia weight, c1 and c2 represent the acceleration coefficients, and b is a random number ranging from 0 to 1. represents the position of the i-th particle at the r-th step, is the individual optimal position of the i-th particle in the r-th step, gbest r is the global optimal position at the rth step; the dynamic update method of inertia weight and acceleration coefficient is as follows:

[0132]

[0133] Among them, w f is the initial inertia weight, w0 is the final inertia weight, and is the initial acceleration factor, and is the final acceleration coefficient, that is, the acceleration coefficient c1 decreases linearly with the increase of iteration steps, and the acceleration coefficient c2 and inertia weight w increase linearly with the increase of iteration steps; r is the current iteration number, and R is the maximum iteration number. The position update method of each particle in the r+1th step is as follows: Through the dynamic update method of the inertia weight and weighting coefficient, the influence of the group on the individual is weakened in the early stage of iteration, which makes it easier for each excellent individual to quickly find the individual optimal solution in a short time. In the later stage of iteration, the information sharing and cooperation between particles are enhanced, and the group optimal solution is quickly calculated from the individual optimal solutions of multiple excellent individuals, which leads to faster convergence.

[0134] 4) Update the optimal solution by calculating the fitness function, as shown in formula (13):

[0135]

[0136] According to the above formula, the iterative process of the optimal position of the particle swarm is as follows: after the particle swarm updates its position, each particle will calculate the corresponding fitness function value according to the current position. If the fitness function value corresponding to the current position of the particle is less than the fitness function value corresponding to the historical optimal position of the particle, the individual optimal position will be updated to the current position coordinates; after all particles have updated their individual optimal positions, the fitness function values ​​corresponding to the individual optimal positions of all particles will be compared with the fitness function value corresponding to the historical optimal position of the group. If the fitness function value corresponding to the individual optimal position of a particle is less than the fitness function value corresponding to the historical optimal position of the group, the individual optimal position of the particle will be used as the new group optimal position. This will be repeated for multiple times to output the final group optimal position, that is, the FIR filter coefficient that is closest to the ideal bandpass filter amplitude-frequency characteristic.

[0137] According to the Gardner algorithm, the expression (14) for calculating the timing error is:

[0138]

[0139] Among them, x I (kT i ) and x Q (kT i ) represent the kTth value in the large roll-off interpolation sequence signal after removing the loop self-noise received by the timing error detector. i The in-phase component and the kT i orthogonal components, and Respectively represent the kT i The previous interpolation point of the in-phase component and the orthogonal component, xI (kT i -1) and x Q (kT i -1) respectively represent the kT i The second interpolation point before the in-phase component and the orthogonal component. The Gardner algorithm needs to calculate the clock frequency component in the frequency domain to obtain the timing error value. When the roll-off coefficient or roll-off factor α is large, the calculation accuracy of the algorithm is high. However, when α decreases, the effective area of ​​the conjugate multiplication of the positive and negative spectra of the Nyquist integer filter signal also gradually decreases, resulting in a decrease in the sensitivity of error detection and an increase in timing error jitter, thereby reducing the accuracy of data recovery.

[0140] Even though the Gardner algorithm has a high accuracy in calculating the timing error value for a large roll-off signal with a large roll-off factor α, when two or more consecutive code symbols are in phase, the Gardner algorithm cannot accurately estimate the timing error, which has a great impact on subsequent synchronization. Therefore, in a large roll-off optical transmission system, for a large roll-off signal, the first timing error detector uses an improved Gardner algorithm that can be applied to a variety of modulation formats to detect the timing error, and the calculation formula (15) is as follows:

[0141]

[0142] Among them, te(kT i ) high represents a first timing error output by the first timing error detector, sgn() represents the peak sign function. The algorithm calculates the difference between the theoretical value and the actual value of the interpolation point between each two symbols in the large roll-off interpolation sequence signal output by the preprocessing filter after removing the loop self-noise when the interpolation is accurate, that is, using the difference to replace the actual value in the Gardner algorithm, can eliminate the risk of timing error calculation errors caused by the non-zero value of the interpolation point corresponding to the moment between each two symbols in the high-order modulation signal. At the same time, using the peak sign function to replace the peak in the Gardner algorithm can shorten the timing synchronization establishment time, thereby accelerating the convergence speed of the first clock synchronization loop and improving the timing error accuracy.

[0143] In the small roll-off optical transmission system, for the small roll-off signal, the second timing error detector uses the MGPD algorithm to calculate the timing error, and the calculation formula (16) is as follows:

[0144]

[0145] Among them, te(kT i ) low represents a second timing error output by the second timing error detector, Indicates the kTth i The MGPD algorithm strengthens the clock component of the Nyquist signal (small roll-off signal) with a smaller roll-off factor α through a fourth-power operation, so that it can work in a small roll-off Nyquist communication system.

[0146] The loop filter (first loop filter or second loop filter) performs smooth filtering on the high-frequency components in the timing error value te(k) from the timing error detector (first timing error detector or second timing error detector), filters out the timing loop noise, and extracts the stable component ω(k), i.e., the control signal, to control the interpolation controller (first interpolation controller or second interpolation controller). Since the sampling clock of the ADC sampling module at the receiving end and the working clock of the transmitter (transmitting end) have both frequency offset and phase offset, the loop filter uses a second-order proportional integral structure to perform the filtering operation, in which the proportional path is used to track the clock phase change of the signal, and the integral path is used to track the clock frequency change. The output of the loop filter is the sum of the outputs of the proportional and integral paths, and the relationship with the timing error value is as follows (17):

[0147]

[0148] Where z is a complex variable, representing the discretization of time. After simplification of formula (17), we get: ω(k+1)=ω(k)+C1[te(k+1)-te(k)]+C2te(k+1), where ω(k+1) represents the control word (control signal) corresponding to the k+1th interpolation point output by the loop filter; C1 represents the proportional coefficient, C2 represents the integral coefficient, and C1 is much larger than C2; te(k+1) represents the timing error value corresponding to the k+1th interpolation point.

[0149] Since loop self-noise and out-of-band Gaussian noise will cause timing jitter and affect synchronization performance, when the roll-off factor α is small (for small roll-off signals), even if the MGPD algorithm is used to estimate the second timing error, there is still a large timing jitter. Therefore, after the second loop filter outputs the second control signal ω(k), ω(k) does not directly enter the second interpolation controller to calculate the interpolation point, but is first multiplied by the gain factor G before entering the second interpolation controller, that is, the following formula (18):

[0150] ω(k+1)={ω(k)+C1[te(k+1)-te(k)]+C2te(k+1)}*G

[0151] When the gain factor is less than 1, its essential purpose is to reduce the equivalent bandwidth of the second loop filter and enhance the filtering effect of out-of-band Gaussian noise. However, if the gain factor is set too small, the convergence speed of the second clock synchronization loop will be slowed down. Therefore, the present invention designs the value of the gain factor G from the perspectives of system stability and efficiency.

[0152] The interpolation controller (first interpolation controller or second interpolation controller) is mainly composed of a numerically controlled oscillator and a fractional interval calculator. The numerically controlled oscillator overflows to generate a clock, and determines the interpolation base point m according to the control signal ω(k) k , and calculate ω(m k ), the numerically controlled oscillator is essentially a modulo-one phase-decreasing register. The fractional interval calculator is used to calculate the fractional interval μ k , and the calculated fractional interval μ k The input is sent to the interpolation filter for interpolation. Specifically, the fractional interval is calculated by the Euclidean distance between the zero point of the underflow of the numerically controlled oscillator and the previous interpolation moment. The calculation formula is: η(m k ) represents the value of the phase decrement register at the interpolation time corresponding to the kth interpolation point. The fractional interval is obtained by solving the equation (19):

[0153]

[0154] Figure 3 FIG. 1 is a schematic diagram of a clock synchronization circuit for different roll-off signals in an embodiment of the present invention. The embodiment of the present invention also provides a clock synchronization circuit for different roll-off signals, such as Figure 3 As shown, the circuit includes: a signal determination module, a first clock synchronization loop and a second clock synchronization loop;

[0155] A signal determination module, used to determine whether an asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal, wherein the asynchronous sampling sequence signal is obtained by asynchronously sampling a signal received by a receiving end;

[0156] A first clock synchronization loop is used to perform clock synchronization on the large roll-off signal and output a first synchronization sequence signal when the asynchronous sampling sequence signal is a large roll-off signal; the first clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a preprocessing filter is provided between the interpolation filter and the timing error detector, and the algorithm adopted by the timing error detector is realized by the difference between the theoretical value and the actual value of the interpolation point between every two symbols in the signal output by the preprocessing filter when the interpolation is accurate and the peak symbol function;

[0157] The second clock synchronization loop is used to perform clock synchronization on the small roll-off signal and output a second synchronization sequence signal when the asynchronous sampling sequence signal is a small roll-off signal; the second clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a multiplication operation module is provided between the loop filter and the interpolation controller.

[0158] In some embodiments, the first clock synchronization loop includes a first interpolation filter, a preprocessing filter, a first timing error detector, a first loop filter and a first interpolation controller.

[0159] The first interpolation filter is used to perform interpolation processing on the large roll-off signal based on an initial first fractional interval, output a large roll-off interpolation sequence signal, and transmit the output large roll-off interpolation sequence signal to the preprocessing filter;

[0160] The preprocessing filter is used to perform filtering preprocessing on the output large roll-off interpolation sequence signal, output the large roll-off interpolation sequence signal after removing the loop self-noise, and transmit the output large roll-off interpolation sequence signal after removing the loop self-noise to the first timing error detector;

[0161] The first timing error detector is used to detect and calculate the clock phase error of the output large roll-off interpolation sequence signal after the loop self-noise is removed, output a first timing error, and transmit the output first timing error to the first loop filter;

[0162] The first loop filter is used to generate a first control signal based on the output first timing error, and transmit the generated first control signal to the first interpolation controller;

[0163] The first interpolation controller is used to generate a first interpolation base point based on the output first control signal, output a first fractional interval based on the generated first interpolation base point, and transmit the output first fractional interval to the first interpolation filter;

[0164] The first interpolation filter is used to adjust and update the output large roll-off interpolation sequence signal based on the output first fractional interval, until the absolute value of the difference between the first fractional interval output by the first interpolation controller and the first target fractional interval is less than a first preset threshold, at which time the large roll-off interpolation sequence signal corresponding to the output of the first interpolation filter is used as the first synchronization sequence signal;

[0165] In some embodiments, the second clock synchronization loop includes a second interpolation filter, a second timing error detector, a second loop filter, a multiplication module, and a second interpolation controller.

[0166] The second interpolation filter is used to perform interpolation processing on the small roll-off signal based on the initial second fractional interval, output a small roll-off interpolation sequence signal, and transmit the output small roll-off interpolation sequence signal to the second timing error detector;

[0167] The second timing error detector is used to detect and calculate the clock phase error of the output small roll-off interpolation sequence signal, output a second timing error, and transmit the output second timing error to the second loop filter;

[0168] The second loop filter is used to generate a second control signal based on the output second timing error, and transmit the generated second control signal to the multiplication operation module;

[0169] The multiplication module is used for multiplying the output second control signal and the gain factor, outputting the second control signal after the gain factor acts on it, and transmitting the output second control signal after the gain factor acts on it to the second interpolation controller;

[0170] The second interpolation controller is used to generate a second interpolation base point based on the output second control signal after the gain factor is applied, output a second fractional interval based on the generated second interpolation base point, and transmit the output second fractional interval to the second interpolation filter;

[0171] The second interpolation filter is used to adjust and update the output small roll-off interpolation sequence signal based on the output second fractional interval until the absolute value of the difference between the second fractional interval output by the second interpolation controller and the second target fractional interval is less than a second preset threshold. At this time, the small roll-off interpolation sequence signal corresponding to the output of the second interpolation filter is used as the second synchronization sequence signal.

[0172] Finally, the method is verified by simulation. The simulation parameters are as follows: the modulation mode is quadrature phase shift keying (QPSK); the symbol rate R s The signal is a large roll-off signal of 6.94Gboud and a roll-off factor α of 0.8; the symbol rate R s The signal is a small roll-off signal of 38.46Gboud and a roll-off factor α of 0.3; the phase offset is 0.5 symbol period; the coefficients C1 and C2 of the first loop filter and the second loop filter are 2 -6 and 2 -13 ; The gain factor G is 0.1; the roll-off factor threshold is 0.4.

[0173] The simulation verification results are as follows: For a large roll-off signal, the symbol rate is 6.94Gboud and the roll-off factor α is 0.8. Figure 4 As shown, the horizontal axis is the number of simulation calculation steps, and the vertical axis is the fractional interval μ kThe absolute value of the residual error with the final converged value of the fractional interval is given by Figure 4 It can be seen that compared with the Gardner algorithm, the method of the present invention adopts the improved Gardner algorithm, which improves the convergence speed of the clock synchronization loop by about 10%; for small roll-off signals, the symbol rate is 38.46Gboud, and the roll-off factors α are 0.1, 0.15, 0.2, 0.25, and 0.3 respectively. Figure 5 As shown, the horizontal axis is the roll-off factor, and the vertical axis is the average of the absolute value of the timing error to measure the degree of timing jitter. Figure 5 It can be seen that, compared with the MGPD algorithm or the 4PPD algorithm, the method of the present invention reduces the timing jitter of the clock synchronization loop by 43% after adding the gain factor.

[0174] Corresponding to the above method, the present invention also provides an electronic device, which includes a computer device, the computer device includes a processor and a memory, the memory stores computer instructions, the processor is used to execute the computer instructions stored in the memory, and when the computer instructions are executed by the processor, the device implements the steps of the above method.

[0175] The embodiment of the present invention also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the aforementioned method are implemented. The computer-readable storage medium can be a tangible storage medium, such as a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0176] An embodiment of the present invention further provides a computer program product, comprising computer instructions, which implement the steps of the aforementioned method when executed by a processor.

[0177] It should be understood by those skilled in the art that the exemplary components, systems and methods described in conjunction with the embodiments disclosed herein can be implemented in hardware, software or a combination of the two. Whether it is performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present invention are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link via a data signal carried in a carrier.

[0178] It should be clear that the present invention is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present invention.

[0179] In the present invention, features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, and / or combined with features of other embodiments or replace features of other embodiments.

[0180] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A clock synchronization method for different roll-off signals, characterized in that: The method comprises: Determine whether the asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal, wherein the asynchronous sampling sequence signal is obtained by asynchronously sampling a signal received by a receiving end; If the asynchronous sampling sequence signal is a large roll-off signal, the first clock synchronization loop performs clock synchronization on the large roll-off signal and outputs a first synchronization sequence signal; the first clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a preprocessing filter is provided between the interpolation filter and the timing error detector, and the algorithm adopted by the timing error detector is realized by the difference between the theoretical value and the actual value of the interpolation point between every two symbols in the signal output by the preprocessing filter when the interpolation is accurate and the peak symbol function; If the asynchronous sampling sequence signal is a small roll-off signal, the second clock synchronization loop performs clock synchronization on the small roll-off signal and outputs a second synchronization sequence signal; the second clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a multiplication operation module is provided between the loop filter and the interpolation controller.

2. The method according to claim 1, characterized in that Determine whether the asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal, including: If the number of positive sample values ​​among the multiple sample values ​​at the end of the sequence of the asynchronous sampling sequence signal is greater than the number of negative sample values, then the asynchronous sampling sequence signal is a large roll-off signal; If the number of positive sample values ​​among the multiple sample values ​​at the end of the sequence of the asynchronous sampling sequence signal is less than the number of negative sample values, the asynchronous sampling sequence signal is a small roll-off signal.

3. The method according to claim 1, characterized in that The first clock synchronization loop includes a first interpolation filter, a preprocessing filter, a first timing error detector, a first loop filter and a first interpolation controller; The first clock synchronization loop performs clock synchronization on the large roll-off signal and outputs a first synchronization sequence signal, including: The first interpolation filter performs interpolation processing on the large roll-off signal based on an initial first fractional interval, outputs a large roll-off interpolation sequence signal, and transmits the output large roll-off interpolation sequence signal to the preprocessing filter; The preprocessing filter performs filtering preprocessing on the output large roll-off interpolation sequence signal, outputs the large roll-off interpolation sequence signal after removing the loop self-noise, and transmits the output large roll-off interpolation sequence signal after removing the loop self-noise to the first timing error detector; The first timing error detector detects and calculates the clock phase error of the output large roll-off interpolation sequence signal after the loop self-noise is removed, outputs a first timing error, and transmits the output first timing error to the first loop filter; The first loop filter generates a first control signal based on the output first timing error, and transmits the generated first control signal to the first interpolation controller; The first interpolation controller generates a first interpolation base point based on the output first control signal, outputs a first fractional interval based on the generated first interpolation base point, and transmits the output first fractional interval to the first interpolation filter; The first interpolation filter adjusts and updates the output large roll-off interpolation sequence signal based on the output first fractional interval until the absolute value of the difference between the first fractional interval output by the first interpolation controller and the first target fractional interval is less than a first preset threshold, and the first interpolation filter correspondingly outputs the large roll-off interpolation sequence signal as the first synchronization sequence signal.

4. The method according to claim 1 or 3, characterized in that: The coefficients of the pre-processing filter are calculated by a particle swarm algorithm that dynamically updates the inertia weight and the acceleration coefficient; The timing error detector in the first clock synchronization loop uses an improved Gardner algorithm to detect and calculate the clock phase error of the large roll-off interpolation sequence signal output by the preprocessing filter after removing the loop self-noise, and outputs a first timing error. The calculation formula is as follows: Among them, te(kT i ) high Represents the first timing error of the output, α is the roll-off factor, x I (kT i ) and x Q (kT i ) represent the kTth value in the large roll-off interpolation sequence signal after removing the loop self-noise received by the timing error detector. i The in-phase component and the kT i orthogonal components, and Respectively represent the kT i The previous interpolation point of the in-phase component and the orthogonal component, x I (kT i -1) and x Q (kT i -1) respectively represent the kT i The first second interpolation point of the in-phase component and the orthogonal component, sgn() represents the peak sign function.

5. The method according to claim 1, characterized in that The second clock synchronization loop includes a second interpolation filter, a second timing error detector, a second loop filter, a multiplication module and a second interpolation controller; the second clock synchronization loop performs clock synchronization on the small roll-off signal and outputs a second synchronization sequence signal, including: The second interpolation filter performs interpolation processing on the small roll-off signal based on the initial second fractional interval, outputs a small roll-off interpolation sequence signal, and transmits the output small roll-off interpolation sequence signal to the second timing error detector; The second timing error detector detects and calculates the clock phase error of the output small roll-off interpolation sequence signal, outputs a second timing error, and transmits the output second timing error to the second loop filter; The second loop filter generates a second control signal based on the output second timing error, and transmits the generated second control signal to the multiplication operation module; The multiplication module multiplies the output second control signal and the gain factor, outputs the second control signal after the gain factor acts on it, and transmits the output second control signal after the gain factor acts on it to the second interpolation controller; The second interpolation controller generates a second interpolation base point based on the output second control signal after the output gain factor is applied, outputs a second fractional interval based on the generated second interpolation base point, and transmits the output second fractional interval to the second interpolation filter; The second interpolation filter adjusts and updates the output small roll-off interpolation sequence signal based on the output second fractional interval until the absolute value of the difference between the second fractional interval output by the second interpolation controller and the second target fractional interval is less than a second preset threshold, and the corresponding small roll-off interpolation sequence signal output by the second interpolation filter is used as the second synchronization sequence signal.

6. The method according to claim 5, characterized in that The multiplication module multiplies the output second control signal and the gain factor, and outputs the second control signal after the gain factor is applied. The calculation formula is as follows: ω(k+1)={ω(k)+C1[te(k+1)-te(k)]+C2te(k+1)}*G Among them, ω(k+1) represents the second control signal after the output gain factor acts, k represents the interpolation point number in the output small roll-off interpolation sequence signal, C1 represents the proportional coefficient, C2 represents the integral coefficient, and C1 is much larger than C2, te(k+1) represents the second timing error of the output, and G represents the gain factor.

7. A clock synchronization circuit for different roll-off signals, characterized in that: The circuit comprises: A signal determination module, used to determine whether an asynchronous sampling sequence signal is a large roll-off signal or a small roll-off signal, wherein the asynchronous sampling sequence signal is obtained by asynchronously sampling a signal received by a receiving end; a first clock synchronization loop, used for performing clock synchronization on the large roll-off signal and outputting a first synchronization sequence signal when the asynchronous sampling sequence signal is a large roll-off signal; the first clock synchronization loop comprises an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a preprocessing filter is provided between the interpolation filter and the timing error detector, and the algorithm adopted by the timing error detector is realized by the difference between the theoretical value and the actual value of the interpolation point between every two symbols in the signal output by the preprocessing filter when the interpolation is accurate and the peak symbol function; and The second clock synchronization loop is used to perform clock synchronization on the small roll-off signal and output a second synchronization sequence signal when the asynchronous sampling sequence signal is a small roll-off signal; the second clock synchronization loop includes an interpolation filter, a timing error detector, a loop filter and an interpolation controller, and a multiplication operation module is provided between the loop filter and the interpolation controller.

8. An electronic device comprising a processor, a memory and computer instructions stored in the memory, characterized in that: The processor is used to execute the computer instructions, and when the computer instructions are executed, the device implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising computer instructions, characterized in that When the computer instructions are executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

Images