A Formal Security Verification Method for Pre-Silicon Cryptographic Energy Side Channels

Abstract

This application proposes a pre-silicon cryptographic energy side channel formal security verification method, including: using gate-level information flow tracing technology to establish an information flow security model library for circuit design; converting the cryptographic core design into a gate-level netlist, mapping each basic logic unit in the gate-level netlist to the information flow security model library for matching, and obtaining an energy side channel security model; summarizing the target function properties by analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel; simulating and verifying the energy side channel security model with the target function properties as constraints to determine the target register; mining the security properties of the energy side channel based on the energy consumption model and the energy side channel security model; and using formal verification methods to analyze whether the target register has energy leakage based on the security properties and the energy side channel security model. This method can effectively achieve accurate analysis of the energy side channel security of the cryptographic core design.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of cryptographic core design security analysis, and in particular to a pre-silicon cryptographic energy side channel formal security verification method. Background Art

[0002] Energy side channel analysis is a widely used passive side channel analysis method. When a cryptographic device is running, data flipping generates energy consumption. Energy side channel analysis analyzes the relationship between the energy consumption of the cryptographic device and sensitive information when performing cryptographic operations to recover encryption keys. Common energy side channel analysis methods include simple energy analysis, differential energy analysis, correlation energy analysis, template analysis, and mutual information analysis. These methods analyze the energy consumption of the cryptographic device, the data processed, and the operations performed, and use this energy consumption trajectory to retrieve the encryption key.

[0003] Energy side-channel analysis primarily involves four stages: building an energy consumption model, determining a target function, collecting energy traces, and analyzing cryptographic keys. An energy consumption model is established based on the principles of energy consumption generation, and the target function for energy side-channel analysis is determined based on the characteristics of the cryptographic structure. The register corresponding to the target function in the cryptographic core design is the target register. An oscilloscope is used to collect the energy consumption trace generated by the target register during operation as the energy trace. The key is then derived by analyzing the correlation between the energy consumption model and the actual energy trace. While energy side-channel analysis poses a threat to the security of cryptographic core designs, it has also promoted the development of energy side-channel assessment of cryptographic core designs. The difficulty of implementing energy side-channel analysis can be used to infer the security of a cryptographic core design. However, while this method can assess the security of a cryptographic core design to a certain extent, it is complex and costly.

[0004] In recent years, research teams have proposed energy side-channel leakage assessment methods. These methods primarily monitor the energy consumption of cryptographic devices when performing encryption operations, using statistical methods to analyze the correlation between energy consumption and key information. The security of the cryptographic core design is then determined based on the degree of key leakage, such as the test vector leakage assessment method. This method, based on hypothesis testing, is simple, efficient, and highly operational. However, it requires statistical analysis of a large number of energy traces, which is time-consuming and expensive.

[0005] Currently proposed energy side-channel leakage assessment methods primarily perform post-silicon energy side-channel security assessments on cryptographic core designs. While these methods can effectively assess the side-channel security of cryptographic core designs, they hinder design modifications and optimization, and the post-silicon design repair process is complex and costly. These methods require analysts to manually analyze the cryptographic core design, a process that not only takes a long time to collect energy traces but also fails to quantitatively test the energy side channels of the cryptographic core design due to manual measurements, potentially leading to false positives in the assessment results. Currently proposed pre-silicon energy side-channel security assessment methods are mostly applicable only to specific cryptographic algorithms and require manual assessment, which presents certain limitations.

[0006] It can be seen that the field of cryptographic core design security analysis technology still lacks effective pre-silicon energy side channel security verification methods for cryptographic core designs. Summary of the Invention

[0007] In view of this, the embodiments of the present application propose a pre-silicon cryptographic energy side channel formal security verification method, which can realize the automation of energy side channel security model construction and energy side channel security verification in cryptographic core design, complete the precise analysis of the energy side channel security of cryptographic core design before silicon, effectively reduce the time and cost required for post-silicon energy side channel evaluation, and facilitate the optimization and modification of cryptographic core design.

[0008] In a first aspect, an embodiment of the present application proposes a pre-silicon cryptographic energy side channel formal security verification method, the method comprising the following steps: using gate-level information flow tracing technology to establish an information flow security model for each basic logic unit of the circuit design, and integrating each information flow security model to establish an information flow security model library; converting the cryptographic core design into a gate-level netlist, mapping each basic logic unit in the gate-level netlist to the information flow security model library for matching, and logically combining the matched information flow security models to obtain an energy side channel security model established for the cryptographic core design; summarizing the objective function properties by analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel; simulating and verifying the energy side channel security model with the objective function properties as constraints, and using the register corresponding to the encryption transformation that meets the objective function properties in the cryptographic core design as the target register; based on the energy consumption model and its principles, combined with the energy side channel security model, mining the security attributes of the energy side channel to obtain security attributes; using a formal verification tool to analyze whether there is energy leakage in the target register based on the security attributes and the energy side channel security model; if the verification passes, the target register does not have leakage; otherwise, the target register has leakage.

[0009] In addition, the gate-level information flow tracking technology is used to establish an information flow security model for each basic logic unit of the circuit design, including: adding pollution labels to the input and output signals of the circuit design to indicate the state of the signal, and using the flow of pollution labels to identify the change and flip of the signal; wherein, when the pollution label is logic 0, it indicates that the signal is in an uncontaminated state, and when the pollution label is logic 1, it indicates that the signal is in a contaminated state; based on the input and output signals of the basic logic units of each circuit design, and the pollution labels corresponding to the input and output signals, the information flow security model of each basic logic unit is described using a Boolean expression.

[0010] In addition, the objective function properties are summarized by analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel, including: analyzing the structural characteristics of the cryptographic algorithm, and analyzing the characteristics of the energy side channel through simple energy analysis, correlation energy analysis and differential energy analysis, summarizing the common characteristics of the objective function to obtain the objective function properties; wherein, the objective function properties include controllable properties, sensitive properties, obfuscation properties and divide-and-conquer properties, the controllable property indicates that the input of the objective function can be controlled by the analyst, the sensitive property indicates that the objective function needs to be related to the key, the obfuscation property indicates that one key bit should be related to the output bits of multiple objective functions, and the divide-and-conquer property indicates that the output of the objective function should be related to a subset of the key information.

[0011] In addition, the energy side channel security model is simulated and verified with the objective function properties as constraints, and the registers corresponding to the encryption transformations that meet the objective function properties in the cryptographic core design are used as target registers, including: using standard EDA tools to simulate the energy side channel security model and collect simulation traces; wherein, during the simulation process, the pollution label of the key signal is set to 1 bit by bit, and the pollution labels of the remaining signals are all set to 0; the flow of pollution label information in the collected simulation traces is used to simulate the flipping and transformation of the output signal during the encryption process; it is analyzed whether the flow of pollution label information meets all objective function properties, and the registers corresponding to the encryption transformations that meet all objective function properties are used as target registers.

[0012] In addition, based on the energy consumption model and its principles, combined with the energy side channel security model, the security attributes of the energy side channel are mined to obtain security attributes, including: the energy consumption generated by the cryptographic device when performing encryption operations is mainly dynamic energy consumption. Based on the principle that dynamic energy consumption is linearly related to the Hamming distance and Hamming weight of the operation data, combined with the energy side channel security model, the security attributes of the energy side channel are mined to obtain the security attributes of the energy side channel.

[0013] In addition, according to the security attributes and the energy side channel security model, the formal verification tool is used to analyze whether there is energy leakage in the target register, including: using a security attribute description language to formally describe the security attributes as security constraints of the energy side channel security model, and then using the formal verification tool to analyze whether the target register meets the security constraints to determine whether there is energy leakage in the cryptographic core design.

[0014] In addition, the security attribute description language uses a standard hardware design description language.

[0015] Through the above-mentioned method, the present application designs a pre-silicon energy side channel security verification method for cryptographic core design, realizes the automated establishment of the energy side channel security model of the cryptographic core design, makes up for the shortcomings of the existing method of automated modeling, and provides an automated analysis method for the energy side channel security verification of the cryptographic core design in the pre-silicon stage based on formal verification technology, effectively reducing the current cost of post-silicon energy side channel security verification. Compared with the existing pre-silicon energy side channel verification method, the present application is not limited to the type of cryptographic algorithm in the process of establishing the energy side channel security model. By realizing the establishment of the energy side channel security model at the gate level, the accuracy of the model is improved, and it has better scalability and versatility, which facilitates design changes and optimization. At the same time, the present application uses a formal security verification method to achieve accurate analysis of the energy side channel security of the cryptographic core design, effectively improving the accuracy of the side channel security verification of the cryptographic core design.

[0016] In the second aspect, an embodiment of the present application proposes a pre-silicon cryptographic energy side channel formal security verification system, the system comprising: an information flow security model library establishment module, for using gate-level information flow tracing technology to establish information flow security models for each basic logic unit of the circuit design, and integrating each information flow security model to establish an information flow security model library; an energy side channel security model establishment module, for converting the cryptographic core design into a gate-level netlist, mapping each basic logic unit in the gate-level netlist to the information flow security model library for matching, and logically combining each matched information flow security model to obtain an energy side channel security model established for the cryptographic core design; an objective function attribute summary module, for By analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel, the objective function properties are summarized; the target register determination module is used to simulate and verify the energy side channel security model with the objective function properties as constraints, and the register corresponding to the encryption transformation that meets the objective function properties in the cryptographic core design is used as the target register; the security attribute mining module is used to mine the security attributes of the energy side channel based on the energy consumption model and its principles, combined with the energy side channel security model, to obtain security attributes; the security verification module is used to use formal verification tools to analyze whether there is energy leakage in the target register according to the security attributes and the energy side channel security model. If the verification passes, there is no leakage, otherwise, there is leakage.

[0017] In a third aspect, an embodiment of the present application proposes an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute a pre-silicon cryptographic energy side channel formal security verification method as described in the first aspect above.

[0018] In a fourth aspect, an embodiment of the present application proposes a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement a pre-silicon cryptographic energy side channel formal security verification method as described in the first aspect above.

[0019] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related technologies, the following is a brief introduction to the drawings required for use in the embodiments of the present application or the description of the related technologies. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 It is a flow chart of a pre-silicon cryptographic energy side channel formal security verification method provided in one embodiment of the present application;

[0022] Figure 2 This is a schematic diagram of the principle of a pre-silicon cryptographic energy side channel formal security verification method provided in one embodiment of the present application;

[0023] Figure 3 This is a schematic diagram of a process for establishing an energy side channel security model provided in one embodiment of the present application;

[0024] Figure 4 is a schematic diagram of a target register determination process provided in one embodiment of the present application;

[0025] Figure 5 It is a schematic diagram of energy side channel security verification of a cryptographic core design provided in one embodiment of the present application;

[0026] Figure 6 is a structural diagram of an AES_GF cryptographic core design provided in another embodiment of the present application;

[0027] Figure 7 1 is a schematic diagram of the first three rounds of simulation results of an AES_GF energy side channel security model provided in another embodiment of the present application;

[0028] Figure 8 This is a schematic structural diagram of a pre-silicon cryptographic energy side channel formal security verification system provided in another embodiment of the present application;

[0029] Figure 9 It is a structural diagram of an electronic device provided in another embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the various embodiments of the present application, many technical details are proposed to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is only for the convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.

[0031] An embodiment of the present application proposes a pre-silicon cryptographic energy side channel formal security verification method, which is applied to an electronic device, wherein the electronic device can be a terminal or a server. In this embodiment and the following embodiments, the electronic device is described using the server as an example. The implementation details of the pre-silicon cryptographic energy side channel formal security verification method proposed in this embodiment are specifically described below. The following content is only the relevant implementation details provided for the convenience of understanding and is not necessary for the implementation of this solution.

[0032] The specific process of the formal security verification method for pre-silicon cryptographic energy side channel proposed in this embodiment can be as follows: Figure 1 As shown, the principle can be Figure 2 As shown, the method specifically includes:

[0033] Step 101 : Using gate-level information flow tracing technology, establish information flow security models for each basic logic unit of the circuit design, and integrate each information flow security model to establish an information flow security model library.

[0034] In the specific implementation, the server first needs to model the commonly used circuit design, that is, it needs to use gate-level information flow tracking technology to establish information flow security models for each basic logic unit of the circuit design, and integrate each information flow security model to establish an information flow security model library.

[0035] In one example, the server needs to add pollution labels to the input and output signals of the circuit design to indicate the state of the signal, and use the flow of pollution labels to identify the changes and flips of the signal. Among them, when the pollution label is logical 0, it means that the signal is in an unpolluted state, and when the pollution label is logical 1, it means that the signal is in a polluted state. The propagation of pollution labels in the information flow security model meets the logical constraints of the circuit design, that is, the pollution state of the input signal can only be propagated to the output signal when the input data has an impact on the value of the output data. Therefore, the server can use Boolean expressions to describe the information flow security model of each basic logic unit based on the input and output signals of the basic logic units of each circuit design, and the pollution labels corresponding to the input and output signals. After the information flow security model of each basic logic unit is established, the information flow security models can be integrated to establish an information flow security model library.

[0036] For a NOT gate circuit, the change of input signal A will directly affect the output signal O. Therefore, the information flow security model of the NOT gate can be described by Boolean expression as t =A t , A t and O t are the pollution labels corresponding to the input signal A and the output signal O respectively.

[0037] For a two-input NAND gate circuit, changes in the input signals A and B will affect the output signal O. Part of the truth table of the information flow security model of the two-input NAND gate is shown in Table 1.

[0038] Table 1: Partial truth table of the information flow security model for a two-input NAND gate

[0039] A B <![CDATA[A t ]]> <![CDATA[B t ]]> O <![CDATA[O t ]]> 1 0 0 1 0 1 0 2 0 0 0 1 1 0 3 0 1 1 0 1 1 4 0 1 0 1 1 0 5 1 0 1 0 1 0 6 1 0 0 1 1 1 7 1 1 1 0 0 1 8 1 1 0 1 0 1

[0040] From the two rows numbered 3 and 4 in Table 1, we can see that although the input signal values ​​are the same, the difference in the pollution labels of the input signals leads to different values ​​of the pollution labels of the output signals. The reason is that when the input signal B of the two-input NAND gate is 1, the value of the output signal O depends on the input signal A, so A t The pollution state will flow to O t This shows that the information flow security model of the two-input NAND gate can accurately measure the transformation and flipping of the signal of the two-input NAND gate. Through logical simplification, the Boolean expression of the information flow security model of the two-input NAND gate can be obtained as follows: t =BA t +AB t +A t B t .

[0041] Using the same method, the server can establish information flow security models for other basic logic units, such as AND gates and OR gates, and further integrate the information flow security models of all basic logic units to establish an information flow security model library.

[0042] Step 102: Convert the cryptographic core design into a gate-level netlist, map each basic logic unit in the gate-level netlist to the information flow security model library for matching, and logically combine the matched information flow security models to obtain an energy side channel security model established for the cryptographic core design.

[0043] In the specific implementation, after establishing the information flow security model library, the server can convert the cryptographic core design into a gate-level netlist, map the basic logic units in the gate-level netlist to the information flow security model library for matching, and logically combine the matched information flow security models to obtain the energy side channel security model established for the cryptographic core design.

[0044] In one example, the process of establishing the energy side channel security model can be as follows: Figure 3 shown.

[0045] It's worth noting that establishing an energy side channel security model for cryptographic core designs doesn't require a specific cryptographic algorithm. It can be applied to any cryptographic core design, demonstrating its versatility. This model is based on the combinatorial principles of circuit design, ensuring its correctness by combining the information flow security models of basic logic units.

[0046] Step 103: Summarize the properties of the objective function by analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel.

[0047] In specific implementations, while establishing an energy side channel security model for cryptographic core design, the server also analyzes the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel to summarize the properties of the target function. The extracted target function properties are closely related to the cryptographic structure and the energy side channel analysis method used. The comprehensiveness of the extracted target properties is ensured by analyzing and summarizing the characteristics of multiple energy side channel analysis methods. The target function is the cryptographic transformation studied by the energy side channel analysis method that may leak sensitive information. By summarizing the characteristics of the energy side channel analysis method implemented post-silicon on the cryptographic core design, the basic properties satisfied by the target function that may leak side channels can be derived.

[0048] In one example, the server analyzes the structural characteristics of a cryptographic algorithm and analyzes the characteristics of the energy side channel using simple energy analysis, correlation energy analysis, and differential energy analysis. The server then summarizes the common characteristics of the target function to obtain target function properties. Target function properties include controllability, sensitivity, obfuscation, and divide-and-conquer. The controllability property indicates that the input of the target function can be controlled by the analyst, the sensitivity property indicates that the target function must be related to the key, the obfuscation property indicates that one key bit should be related to multiple output bits of the target function, and the divide-and-conquer property indicates that the output of the target function should be related to a subset of the key information. It is worth noting that target function properties are not limited to these four properties and can also include diffusion properties, etc. The specific target function properties are related to the energy side channel analysis method used. Using multiple energy side channel analysis methods ensures the comprehensiveness of the extracted target function properties.

[0049] Step 104 , performing simulation verification on the energy side channel security model with the objective function attribute as a constraint, and taking the register corresponding to the encryption transformation that satisfies the objective function attribute in the cryptographic core design as the target register.

[0050] In the specific implementation, after extracting the objective function attributes, the server immediately simulates and verifies the energy side channel security model with the objective function attributes as constraints, and uses the register corresponding to the encryption transformation that meets the objective function attributes in the cryptographic core design as the target register.

[0051] In one example, the target register determination process can be as follows: Figure 4 As shown in the figure, the server simulates the energy side channel security model using standard EDA tools and collects simulation traces. During the simulation, the contamination tag of the key signal is set to 1 bit by bit, while the contamination tags of all other signals are set to 0. The principle of information flow tracking shows that the bits with a logical 1 in the contamination tag of the output signal are related to the key information. The server uses the flow of contamination tag information in the collected simulation traces to simulate the flipping and transformation of the output signal during the encryption process. It then further analyzes whether the flow of contamination tag information satisfies all the objective function properties and selects the register corresponding to the transformation that satisfies all the objective function properties as the target register.

[0052] In one example, the standard EDA tool may be Modelsim or the like.

[0053] It is worth noting that each target attribute has a corresponding judgment method. The target function attributes can be screened by analyzing the simulation results of the energy side channel security model of the cryptographic core design to determine the target register.

[0054] Step 105 , based on the energy consumption model and its principles, combined with the energy side channel security model, security attribute mining of the energy side channel is performed to obtain security attributes.

[0055] In a specific implementation, after determining the target register, the server can mine the security attributes of the energy side channel based on the energy consumption model and its principles, combined with the energy side channel security model, to obtain security attributes.

[0056] In one example, the energy consumption generated by a cryptographic device when performing encryption operations is mainly dynamic energy consumption. Based on the principle that dynamic energy consumption is linearly related to the Hamming distance and Hamming weight of the operation data, combined with the energy side channel security model, the security attributes of the energy side channel are mined to obtain the security attributes of the energy side channel.

[0057] Step 106 , based on the security attributes and the energy side channel security model, use a formal verification tool to analyze whether there is energy leakage in the target register. If the verification passes, there is no leakage; otherwise, there is leakage.

[0058] In the specific implementation, after the server digs out the security properties of the energy side channel, it can use formal verification tools to analyze whether there is energy leakage in the target register based on the security properties and the energy side channel security model. If the verification passes, there is no leakage, otherwise, there is leakage.

[0059] In one example, the formal verification tool may be Yosys.

[0060] In one example, the process of energy side channel security verification of cryptographic core design is as follows: Figure 5 As shown, the server uses a security property description language to formally describe security properties as security constraints for the energy side channel security model. Formal verification tools are then used to analyze whether the target registers meet the security constraints to determine whether the cryptographic core design has energy leaks. The security property description language uses a standard hardware design description language, such as System Verilog.

[0061] This embodiment designs a pre-silicon energy side channel security verification method for cryptographic core design, realizes the automated establishment of the energy side channel security model of the cryptographic core design, makes up for the shortcomings of the existing method of automated modeling, and based on formal verification technology, provides an automated analysis method for the energy side channel security verification of the cryptographic core design in the pre-silicon stage, effectively reducing the current cost of post-silicon energy side channel security verification. Compared with the existing pre-silicon energy side channel evaluation method, this embodiment is not limited to the type of cryptographic algorithm in the process of establishing the energy side channel security model. By realizing the establishment of the energy side channel security model at the gate level, the accuracy of the model is improved, and it has better scalability and versatility, which facilitates design changes and optimization. At the same time, the application uses a formal security verification method, which can achieve accurate analysis of the energy side channel security of the cryptographic core design, effectively improving the accuracy of the side channel security verification of the cryptographic core design.

[0062] The step division of the above various methods is only for the purpose of clear description. During implementation, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications or introducing insignificant designs to the algorithm or process without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0063] In another embodiment, the feasibility and effectiveness of the proposed pre-silicon cryptographic energy side-channel formal security verification method are demonstrated using the design of an AES cryptographic core based on a Galois finite field (AES_GF). The hardware environment used for implementation is as follows: Intel Core i7, Ubuntu 18.0, and Windows 11. The proposed method is implemented using the GCC compilation environment, SystemVerilog language, the formal verification tool Yosys, and the standard EDA tool Modelsim.

[0064] The specific implementation of this embodiment is as follows:

[0065] 1) Establish an energy side channel security model for AES_GF cryptographic core design.

[0066] The design structure of AES_GF cryptographic core is as follows Figure 7 As shown in Figure 1, PT is the plaintext signal, Key is the key signal, and Reg is the register. The Yosys tool performs logic synthesis on the AES_GF design implemented in a standard hardware description language to generate a gate-level netlist. The basic logic units in the gate-level netlist are then mapped to the constructed information flow security model library to automatically generate the energy side channel security model for the AES cryptographic core design.

[0067] 2) Determine the objective function properties of the AES_GF cryptographic core design.

[0068] Combining the cryptographic algorithm structure and existing energy side channel analysis methods such as related energy analysis for AES, it is concluded that the target function must satisfy function properties, input controllability, divide-and-conquer properties, and obfuscation properties, as shown in Table 2.

[0069] Table 2: Objective function properties of AES_GF cryptographic core design

[0070] property meaning Explanation P1 Sensitive attributes The target function is a function related to the key P2 Controllable properties The input of the target function should be related to the plaintext P3 Obfuscation attributes One key bit affects multiple output bits of the target function P4 Divide and conquer property The target function needs to be a function of a small subset of the key (less than 32 bits)

[0071] 3) Determine the target registers for the AES_GF cryptographic core design.

[0072] Target registers are selected based on the target function properties determined in the previous step. The target registers are identified by analyzing each function transformation to see if it satisfies the target function properties listed in Table 2. Sensitive, controllable, and divide-and-conquer properties can be analyzed through cryptographic algorithm analysis to select transformations that meet these three properties as candidate functions. The obfuscation property requires analyzing the tag signal in the AES_GF energy side-channel security model to further determine the target function. Multiple simulations are performed using the same plaintext and key, with only the key bit being studied set to logic 1 in each simulation. Based on the principles of fan-in, fan-out, and information flow tracking, the Hamming weight of the candidate function's output label is determined relative to the input label. If the Hamming weight is greater than the input label, the candidate function is the target function, thus determining the target register.

[0073] The experiment uses the 32-bit key bit Key

[32] of the encryption process as an example. First, the information flow label Key_t

[32] of the key bit is set to logic 1. Using the information flow tracking method, the data register Data_Reg

[32] (storing the encryption intermediate round data result) and the key register Key_Reg (storing the intermediate key expansion result) to which the Key

[32] bit pollution label is propagated are searched step by step. Then, these candidate registers are checked to see if they meet the four properties of the objective function. Figure 7 The simulation results of the first three rounds of the AES_GF energy side channel security model are shown. After attribute screening, it is determined that the key register and data register in the second round meet the four attributes, and the two registers are the target registers.

[0074] 4) AES_GF energy side channel security verification.

[0075] The energy side channel security property requires that the flow of key information during encryption operations remain unchanged by changes in the encrypted plaintext. If the target register meets this security property, it indicates that there is no energy side channel security risk. This property can be described in SystemVerilog. For example, when encrypting different plaintexts with the same key, if the Hamming weight of the target register is consistent, it indicates that there is no energy side channel in the target register; otherwise, there is energy leakage.

[0076] Using the key 128'h000102030405060708090a0b0c0d0e0f as a benchmark test, two different plaintexts, 128'h004488cd115599de2266aaef3377bbfc and 128'h022446688aaccef1133557799bbddfe1, were encrypted. The Yosys tool was used to verify that the Hamming weights of the key register and data register in the second round of the two encryptions were equal to determine if the target registers were leaked. The data register was verified to be leaked, but the key register was not. This is consistent with the conclusions of existing evaluation methods and demonstrates the effectiveness of the proposed pre-silicon cryptographic energy side channel formal security verification method.

[0077] Another embodiment of the present application proposes a pre-silicon cryptographic energy side channel formal security verification system. The following is a detailed description of the implementation details of the pre-silicon cryptographic energy side channel formal security verification system proposed in this embodiment. The following content is only for the convenience of understanding the implementation details provided and is not necessary for the implementation of this example. Figure 8 This is a structural diagram of a pre-silicon cryptographic energy side channel formal security verification system proposed in this embodiment, which includes: an information flow security model library establishment module 201, an energy side channel security model establishment module 202, an objective function property summary module 203, a target register determination module 204, a security property mining module 205 and a security verification module 206.

[0078] The information flow security model library establishment module 201 is used to establish an information flow security model for each basic logic unit of the circuit design using gate-level information flow tracing technology, and integrate each information flow security model to establish an information flow security model library.

[0079] The energy side channel security model establishment module 202 is used to convert the cryptographic core design into a gate-level netlist, map each basic logic unit in the gate-level netlist to the information flow security model library for matching, and logically combine the matched information flow security models to obtain the energy side channel security model established for the cryptographic core design.

[0080] The objective function attribute summarizing module 203 is used to summarize the objective function attributes by analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel.

[0081] The target register determination module 204 is used to simulate the energy side channel security model with the objective function attribute as a constraint, and use the register corresponding to the transformation that meets the objective function attribute in the cryptographic core design as the target register.

[0082] The security attribute mining module 205 is used to mine the security attributes of the energy side channel based on the energy consumption model and its principles in combination with the energy side channel security model to obtain security attributes.

[0083] The security verification module 206 is used to analyze whether there is energy leakage in the target register using formal verification tools based on security attributes and energy side channel security model. If the verification passes, there is no leakage, otherwise, there is leakage.

[0084] It is worth mentioning that all modules involved in this embodiment are logical modules. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovation of this application, this embodiment does not include units that are not closely related to solving the technical problem proposed by this application. However, this does not mean that other units do not exist in this embodiment.

[0085] It is not difficult to find that this embodiment is a system embodiment corresponding to the above-mentioned method embodiment, and this embodiment can be implemented in conjunction with the above-mentioned method embodiment. The relevant technical details and technical effects mentioned in the above-mentioned embodiments are still valid in this embodiment, and to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above-mentioned embodiments.

[0086] Another embodiment of the present application provides an electronic device, the specific structure of which is as follows: Figure 9 As shown, it includes: at least one processor 301; and a memory 302 communicatively connected to the at least one processor 301; wherein the memory 302 stores instructions that can be executed by the at least one processor 301, and the instructions are executed by the at least one processor 301 to enable the at least one processor 301 to execute a pre-silicon cryptographic energy side channel formal security verification method as described in the above method embodiments.

[0087] The memory and processor are connected via a bus, which can include any number of interconnected buses and bridges. The bus connects various circuits of one or more processors and memories. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits. These are all well known in the art and will not be described further in this article. The bus interface is responsible for providing an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. Data processed by the processor is transmitted via an antenna on a wireless medium. Furthermore, the antenna also receives data and transmits it to the processor.

[0088] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0089] The memory stores a program that implements a pre-silicon cryptographic energy side channel formal security verification method proposed in this application. When the processor needs to perform pre-silicon cryptographic energy side channel formal security verification, it reads the program stored in the processor and executes it, thereby achieving accurate analysis and security verification of the energy side channel security of the cryptographic core design.

[0090] Another embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement a pre-silicon cryptographic energy side channel formal security verification method as described in the above method embodiments.

[0091] That is, those skilled in the art will understand that all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program, which is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard drive, a ROM (Read-Only Memory), a RAM (Random Access Memory), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0092] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A pre-silicon cryptographic energy side channel formal security verification method, characterized by: include: Using gate-level information flow tracing technology, information flow security models are established for each basic logic unit of circuit design, and each information flow security model is integrated to establish an information flow security model library; The cryptographic core design is converted into a gate-level netlist, each basic logic unit in the gate-level netlist is mapped to the information flow security model library for matching, and each matched information flow security model is logically combined to obtain the energy side channel security model established for the cryptographic core design; By analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel, the properties of the objective function are summarized; The energy side channel security model is simulated and verified with the objective function properties as constraints, and the register corresponding to the encryption transformation that meets the objective function properties in the cryptographic core design is used as the target register; Based on the energy consumption model and its principles, combined with the energy side channel security model, the security attributes of the energy side channel are mined to obtain security attributes; According to the security properties and energy side channel security model, formal verification tools are used to analyze whether there is energy leakage in the target register. If the verification passes, there is no leakage; otherwise, there is leakage.

2. The method according to claim 1, characterized in that The gate-level information flow tracking technology is used to establish an information flow security model for each basic logic unit of the circuit design, including: By adding pollution labels to the input and output signals of the circuit design, the signal state is indicated, and the flow of pollution labels is used to identify signal changes and flips. When the pollution label is logic 0, it means that the signal is in an uncontaminated state, and when the pollution label is logic 1, it means that the signal is in a contaminated state. Based on the input and output signals of the basic logic units of each circuit design and the pollution labels corresponding to the input and output signals, the information flow security model of each basic logic unit is described using Boolean expressions.

3. The method according to claim 1, characterized in that By analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel, the objective function properties are summarized, including: Analyze the structural characteristics of the cryptographic algorithm, and analyze the characteristics of the energy side channel through simple energy analysis, correlation energy analysis and differential energy analysis, and summarize the common characteristics of the target function to obtain the target function properties; Among them, the objective function attributes include controllable attributes, sensitive attributes, obfuscation attributes and divide-and-conquer attributes. The controllable attribute means that the input of the objective function can be controlled by the analyst, the sensitive attribute means that the objective function must be related to the key, the obfuscation attribute means that one key bit should be related to multiple output bits of the objective function, and the divide-and-conquer attribute means that the output of the objective function should be related to a subset of the key information.

4. The method according to claim 3, characterized in that The energy side channel security model is simulated and verified with the objective function attribute as a constraint, and the register corresponding to the encryption transformation that satisfies the objective function attribute in the cryptographic core design is used as the target register, including: The energy side channel security model was simulated using standard EDA tools and simulation traces were collected. During the simulation, the contamination labels of the key signal were set to 1 bit by bit, and the contamination labels of all other signals were set to 0. The flow of contaminated label information in the collected simulation trajectory is used to simulate the flipping and transformation of the output signal during the encryption process; Analyze whether the flow of contamination label information satisfies all the target function properties, and use the register corresponding to the encryption transformation that satisfies all the target function properties as the target register.

5. The method according to claim 4, characterized in that Based on the energy consumption model and its principles, combined with the energy side channel security model, the security attributes of the energy side channel are mined to obtain the following security attributes: The energy consumption generated by cryptographic devices when performing encryption operations is dynamic energy consumption. Based on the principle that dynamic energy consumption is linearly related to the Hamming distance and Hamming weight of the operation data, combined with the energy side channel security model, the security attributes of the energy side channel are mined to obtain the security attributes of the energy side channel.

6. The method according to claim 5, characterized in that According to the security attributes and energy side channel security model, the formal verification tool is used to analyze whether there is energy leakage in the target register, including: The security attributes are formally described using a security attribute description language as security constraints for the energy side channel security model. Formal verification tools are then used to analyze whether the target registers meet the security constraints to determine whether there is energy leakage in the cryptographic core design.

7. The method according to claim 6, characterized in that The security attribute description language uses a standard hardware design description language.

8. A pre-silicon cryptographic energy side channel formal security verification system, characterized by: include: An information flow security model library establishment module is used to establish information flow security models for each basic logic unit of the circuit design using gate-level information flow tracing technology, and integrate each information flow security model to establish an information flow security model library; The energy side channel security model establishment module is used to convert the cryptographic core design into a gate-level netlist, map each basic logic unit in the gate-level netlist to the information flow security model library for matching, and logically combine the matched information flow security models to obtain the energy side channel security model established for the cryptographic core design; The objective function attribute summary module is used to summarize the objective function attributes by analyzing the structural characteristics of the cryptographic algorithm and the characteristics of the energy side channel; The target register determination module is used to simulate and verify the energy side channel security model with the objective function attributes as constraints, and the register corresponding to the encryption transformation that meets the objective function attributes in the cryptographic core design is used as the target register; The security attribute mining module is used to mine the security attributes of the energy side channel based on the energy consumption model and its principles, combined with the energy side channel security model, to obtain security attributes; The security verification module is used to analyze whether there is energy leakage in the target register using formal verification tools based on security attributes and energy side channel security models. If the verification passes, there is no leakage; otherwise, there is leakage.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; In which, the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a pre-silicon cryptographic energy side channel formal security verification method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, it can implement a pre-silicon cryptographic energy side channel formal security verification method as described in any one of claims 1 to 7.

Images