Distributed ramp linearity compensation circuit

Abstract

The invention relates to a distributed ramp linearity compensation circuit. An imaging system includes a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column of unit cells includes at least one of a plurality of comparators, wherein each comparator is coupled to receive a ramp signal from a ramp generator through a ramp signal line. Each column of unit cells further comprises a compensation current unit coupled to the ramp signal line, and each compensation current unit comprises a compensation current source and a compensation current switch coupled to the compensation current source. Wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, and so forth of the image sensors in as many ways as possible (e.g., resolution, power consumption, dynamic range), both through device architecture design and image acquisition processing. The technology used to manufacture image sensors has continued to advance rapidly. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges upon absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on a column bit line that varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and the image charge is read out from the column bit line as an analog image signal and converted to a digital value to generate a digital image (e.g., image data) representing the external scene. The analog image signals on the bit lines are coupled to a readout circuit that includes an input stage having an analog-to-digital conversion (ADC) circuit to convert those analog image signals from the pixel array into digital image signals. Summary of the invention

[0004] In one aspect, the present disclosure relates to an imaging system, comprising: a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; and a readout circuit system coupled to the pixel array, the readout circuit system including a plurality of column unit cells, wherein each column unit cell comprises: at least one of a plurality of comparators, wherein each comparator is coupled to receive a corresponding one of the image charge voltage signals from the pixel array, compare the corresponding one of the image charge voltage signals with a ramp signal from a ramp generator and provide a digital representation of the corresponding one of the image charge voltage signals in response, and wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line; and a compensation current unit coupled to the ramp signal line, comprising: a compensation current source; and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line.

[0005] In another aspect, the present disclosure relates to a method of operating an imaging system, comprising: coupling a plurality of column unit cells to a pixel array, wherein each column unit cell comprises: at least one of a plurality of comparators, wherein each comparator is coupled to receive a ramp signal from a ramp generator through a ramp signal line; and a compensation current unit coupled to the ramp signal line, comprising: a compensation current source; and a compensation current switch coupled to the compensation current source, wherein the compensation current switch is configured to be controlled by a switch signal, and wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line; bi-state switching each switch signal at the beginning of a ramp period; and bi-state switching each switch signal at the end of the ramp period, thereby causing the compensation current source to generate a compensation current. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 An example of an imaging system including a pixel array according to the teachings of the present disclosure is illustrated.

[0008] Figure 2 A schematic diagram illustrating a portion of an exemplary readout circuit including a compensation current cell according to the teachings of the present disclosure is illustrated.

[0009] Figure 3 A schematic diagram illustrating a portion of an exemplary readout circuit including a compensation current cell according to the teachings of the present disclosure is illustrated.

[0010] Figure 4 A schematic diagram illustrating a portion of an exemplary readout circuit including a compensation current cell according to the teachings of the present disclosure is illustrated.

[0011] Figure 5 Illustrated is a timing diagram of a readout cycle of a compensation current cell in an exemplary readout circuit according to the teachings of the present disclosure.

[0012] Fig. 6A , 6B and 6C illustrate schematic diagrams of three exemplary compensation current units according to the teachings of the present disclosure.

[0013] Figure 7 Illustrated is a timing diagram of a readout cycle of a compensation current cell in an exemplary readout circuit according to the teachings of the present disclosure.

[0014] Figure 8 A schematic diagram illustrating a portion of an exemplary readout circuit including a compensation current cell according to the teachings of the present disclosure is illustrated.

[0015] Fig. 9 Illustrated is a timing diagram of a readout cycle of a compensation current cell in an exemplary readout circuit according to the teachings of the present disclosure.

[0016] Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the various figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present disclosure. In addition, common and well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted in order to facilitate a less obstructed view of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] An example of an imaging system having a compensation current unit distributed in a readout circuit that provides improved slope linearity is disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, a person skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or may be practiced with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring certain aspects.

[0018] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present disclosure. Thus, the appearance of the phrase "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0019] Spatially relative terms (e.g., "below," "below," "above," "below," "above," "upper," "top," "bottom," "left," "right," "center," "middle," etc.) may be used herein for ease of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device when in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, then the elements described as being "below" or "below" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" may encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. In addition, it will also be understood that when an element is referred to as being "between" two other elements, the element may be the only element between the two other elements, or one or more intervening elements may also be present.

[0020] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they belong, unless otherwise specifically defined herein or the context in which they are used clearly implies otherwise. It should be noted that in this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, the two have the same meaning.

[0021] As will be discussed, various examples of an imaging system having a compensation current unit distributed in a readout circuit that provides improved ramp linearity are disclosed. In various examples, the readout circuit includes a plurality of column unit cells coupled to a ramp signal line to receive a ramp signal from a ramp generator, each column unit cell including a compensation current unit and one or more comparators. Each compensation current unit may include a compensation current source and a compensation current switch that may be toggled during a readout cycle.

[0022] In image sensors using a single slope analog-to-digital conversion (ADC), nonlinearity in the ramp signal is detrimental to the performance of the image sensor. In conventional imaging systems, there is a large linearity error near the beginning of the ADC when the ramp signal begins to rise or fall (depending on the polarity of the ramp signal). Existing methods for addressing this error include adding a step signal to the ramp signal and compensating for the settling error in the ramp signal. However, one cause of the linearity error is the inherent metal wiring resistance ("parasitic resistance") in the ramp signal line through which the ramp signal propagates, and the aforementioned methods involve changing the operation of the ramp generator, so parasitic resistance remains a problem. As image sensor size increases with large format sensors, this metal wiring resistance of the ramp signal line is not negligible.

[0023] In various examples of the present disclosure, a plurality of compensation current units are distributed in the readout circuit so that the compensation current unit is included in each column unit cell. In various examples, the compensation current unit is shared between multiple column unit cells. Each compensation current unit can be controlled (e.g., via a switch included in the compensation current unit) to locally draw current from the ramp signal or supply current to the ramp signal. In various examples, the local parasitic capacitance is locally charged by the current. In various examples, the charging current is localized and does not actually flow through the parasitic resistance, thereby reducing the IR drop across the ramp signal line.

[0024] In various examples, an imaging system includes a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and a readout circuit system coupled to the pixel array, the readout circuit system including a plurality of column unit cells. Each column unit cell includes at least one of a plurality of comparators (e.g., one comparator, two comparators, three comparators, etc.), wherein each comparator is coupled to receive a corresponding one of the image charge voltage signals from the pixel array through a column bit line, compare the corresponding one of the image charge voltage signals with a ramp signal from a ramp generator, and provide a digital representation of the corresponding one of the image charge voltage signals in response, and wherein each comparator is coupled to receive a ramp signal from the ramp generator through a ramp signal line. Each column unit cell also includes a compensation current unit coupled to the ramp signal line, each compensation current unit including a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line.

[0025] For illustration purposes, Figure 1 One example of an imaging system 100 having a readout circuit 106 including a column unit cell 122 is shown in accordance with the teachings of the present disclosure. In particular, Figure 11 illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and function logic 108. In one example, pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to reproduce an image of the person, place, object, etc.

[0026] In various examples, the readout circuit 106 may be configured to read out the image charge voltage signal through the column bit line 112. As will be discussed, in various examples, the readout circuit 106 may include an analog-to-digital converter (ADC). As shown in the depicted example, the ADC 118 is coupled to the column bit line 112 and is configured to convert the analog signal from the column bit line 112 into a digital signal. In various examples, a column amplifier may also be included and the column amplifier may be coupled to the column bit line 112 to amplify the analog signal received from the column bit line 112 for conversion to a digital signal by the ADC 118. In various examples, the ADC 118 includes a ramp generator 114 and a column unit cell 122. The ramp generator 114 has a ramp generator output from which a ramp signal is provided to the column unit cell 122 via a ramp signal line 120. In an example, the digital image data value generated by the column unit cell 122 may then be received by the function logic 108. Function logic 108 may simply store the digital image data or even manipulate the digital image data by applying post image effects (eg, cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or otherwise).

[0027] In one example, control circuit 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuit 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect such as a flash.

[0028] In one example, the imaging system 100 may be included in a digital camera, a mobile phone, a laptop computer, an endoscope, a security camera, or an imaging device for an automobile, etc. In addition, the imaging system 100 may be coupled to other pieces of hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), a light / flash, an electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other pieces of hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100.

[0029] Figure 2 A schematic diagram illustrating a portion of an exemplary readout circuit 206 including a compensation current unit 230 according to the teachings of the present disclosure. It should be understood that Figure 2 The readout circuit 206 may be included in Figure 1 1. An example of readout circuitry 106 in imaging system 100 is shown in FIG. 1, and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0030] The readout circuit 206 may include a global ramp generator 214 configured to generate a ramp signal. The ramp signal is provided to a plurality of column unit cells 222 via a ramp signal line 220. In the illustrated embodiment, each column unit cell 222 includes at least one of a plurality of comparators 216. Thus, in one embodiment, each column unit cell 222 includes one comparator 216. In another embodiment, each column unit cell 222 may include two comparators 216, etc. Each comparator 216 may be coupled to receive an image charge voltage signal from the pixel array 202 via one of the plurality of bit lines 212 and to receive a ramp signal from one of a plurality of nodes 228a, 228b, ... 228n (collectively referred to as "nodes 228") along or on the ramp signal line 220. As shown in the depicted example, the ramp signal line 220 spans across several columns of the pixel array 202 to provide a ramp signal to a plurality of column unit cells 222. Each comparator 216 can then compare the image charge voltage signal with the ramp signal and provide a digital representation of the image charge voltage signal in response. Each column unit cell 222 can include a compensation current unit (CCU) 230 and a representative local parasitic capacitance 242, each coupled to a respective one of the nodes 228 on the ramp signal line 220. The output of each comparator 216 is coupled to a counter 226, which is configured to respond to when the comparator 216 flips, thereby indicating when the image charge voltage signal from the bit line 212 crosses the ramp signal from the ramp signal line 220. In various examples, each column unit cell 222 can further include a local ramp buffer coupled between the respective node 228 and the comparator 216.

[0031] In the illustrated embodiment, column unit cells 222 are coupled to different ones of nodes 228 on ramp signal line 220. In practice, ramp signal line 220 has an inherent metal wiring resistance ("parasitic resistance") R along its length. P 240. When the ramp signal starts to rise or fall (depending on the polarity of the ramp signal), this parasitic resistance R P240 may cause a linearity error in the ramp signal near the beginning of the ADC. This linearity error is greater for the column unit cells 222 coupled further along the ramp signal line 220. As will be described in further detail below, according to the teachings of the present disclosure, the compensation current unit 230 distributed among the column unit cells 222 along the ramp signal line 220 across the pixel array 202 may be controlled to locally draw current from the ramp signal or supply current to the ramp signal and reduce the current flowing through the parasitic resistance R along the ramp signal line 220. P 240 current changes.

[0032] Figure 3 A schematic diagram illustrating a portion of an exemplary readout circuit 306 including a compensation current unit 330 according to the teachings of the present disclosure. It should be understood that Figure 3 The compensation current unit 330 may be as follows Figure 2 0048. An example of one of the compensation current units 230 shown in FIG. 2 is provided, and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0033] In the illustrated embodiment, the compensation current unit 330 and the local parasitic capacitance C P 342 may be included in the column unit cell. The ramp signal generated by the ramp generator 314 may propagate along the ramp signal line 320 to the output node VO 315, which may be coupled to a comparator (eg, Figure 2 330). The compensation current unit 330 may include a compensation current source 334 and a compensation current switch 332 coupled to the compensation current source 334. The compensation current source 334 and the compensation current switch 332 are coupled between a first node 328 on the ramp signal line 320 and a second node 339 coupled to the ground 338. When the compensation current switch 332 is turned off, the compensation current source 334 is part of an open circuit, so there is no current flow. When the compensation current switch 332 is turned on, the compensation current source 334 can draw a current I from the ramp signal line 320. C 336 or supplies the current to the ramp signal line to locally charge / discharge the local parasitic capacitance 342. Since both the compensation current unit 330 and the local parasitic capacitance 342 are coupled to the ramp signal line 320 and the ground 338, the current I C 336 flows only locally and there is virtually no current flowing to ground 338 or flowing along the ramp signal line 320 through the parasitic resistance R P In particular, reducing the current flow to ground 338 can reduce power line noise (eg, linearity or horizontal noise to ground 338), which can affect image quality.

[0034] Figure 4 A schematic diagram illustrating a portion of an exemplary readout circuit 406 including a compensation current unit 430 according to the teachings of the present disclosure. It should be understood that Figure 4 The compensation current unit 430 may be as follows Figure 2 , and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0035] In the illustrated embodiment, each of the compensation current cells 430 and the representative local parasitic capacitance C P 442 may be included in a column unit cell. Each compensation current unit 430 may include a compensation current source 434 and a compensation current switch 432 coupled to the compensation current source 434. The compensation current source 434 and the compensation current switch 432 are coupled between a first node 428a / b / ... / m / n and a second node 439, wherein the first node is on a ramp signal line 420 coupled to propagate a ramp signal generated by a ramp generator 414, and the second node is coupled to ground 438. The compensation current switch 432 may be configured to be controlled by a switch signal Ramp_en 462. In the illustrated embodiment, all compensation current switches 432 are configured to be controlled by the same switch signal Ramp_en 462.

[0036] When the compensation current switch 432 is turned off, the compensation current source 434 is part of an open circuit, so no current flows. When the compensation current switch 432 is turned on, the compensation current source 434 can draw a current I from the ramp signal line 420. C 436 or supplies the current to the ramp signal line to charge / discharge the local parasitic capacitance 442. Since both the compensation current unit 430 and the local parasitic capacitance 442 are coupled to the ramp signal line 420 and the ground 438, the current I C 436 flows only locally and there is virtually no current flowing to ground 438 or flowing along the ramp signal line 420 through the parasitic resistance R P 440 current.

[0037] Figure 5 The following is a timing diagram illustrating a readout cycle of a compensation current unit in an exemplary readout circuit according to the teachings of the present disclosure. It should be understood that Figure 5 The timing diagram can be used for operations such as Figure 4 1 and 2. An exemplary timing diagram of the compensation current unit 430 is shown in FIG. 4, and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0038] In the illustrated timing diagram, the switch signal Ramp_en 562 is configured to remain off before the ramp period of the ramp signal (ie, between time t1 and t2). At time t1, the switch signal Ramp_en 562 is toggled on so that the compensation current source (eg, Figure 4 The compensation current source 434 illustrated in FIG. 4 may draw a current I from a ramp signal line (eg, ramp signal line 420). C 536 or supplying the current to the ramp signal line to charge the local parasitic capacitance (e.g., local parasitic capacitance 442) as the ramp signal decreases. The switch signal Ramp_en 562 can be configured to remain on during the entire ramp period and be switched off at time t2, which causes the current I C 536 falls back to zero as the ramp signal returns to its nominal voltage level.

[0039] As mentioned above about Figure 3 and 4 As discussed, by locally drawing current I from the ramp signal line C 536 or supplying the current to the ramp signal line can locally charge the local parasitic capacitance and can actually avoid the current from flowing through the parasitic resistance on the ramp signal line. Therefore, the linearity error at the beginning of the ramp cycle can be reduced. In addition, there is a negligible IR drop along the ramp signal line, so various nodes along the ramp signal line (e.g., Vramp 528a、Vramp <m>528m、Vramp <n> The voltage value at 528n) can be equal throughout the entire ADC cycle, such as< / n> < / m> Figure 5 In other embodiments, it should be understood that according to the teachings of the present disclosure, the polarity of the ramp signal and the polarity of the corresponding circuit element can be reversed so that the ramp signal starts to rise at time t1.

[0040] Fig. 6A , 6B 6C illustrates schematic diagrams of three exemplary compensation current units 630 according to the teachings of the present disclosure. It should be understood that Fig. 6A , 6B The compensation current unit 630 of 6C may be as follows Figure 2 , and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0041] First reference Fig. 6A , the compensation current unit 630 includes a signal line coupled to a ramp signal line (eg, Figure 4 The output node Vramp on the ramp signal line 420) illustrated in FIG. <n>628 and ground 638 and a compensation current source NB 634 and a first compensation current switch SWA 632. The compensation current source NB 634 may be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to a bias voltage source VBN 686. The first compensation current switch SWA 632 may be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to be controlled by a first switch signal Ramp_en 662. When the first switch signal Ramp_en 662 is switched to on by a binary state, the compensation current source NB 634 may be switched from an output node Vramp on a ramp signal line. <n>628 Current draw I C 636 or supplying the current to the output node.

[0042] In various examples, the compensation current unit 630 may also include a first cascode device NCA 678 coupled to the first compensation current switch SWA 632, such that the compensation current source NB 634, the first compensation current switch SWA 632, and the first cascode device NCA 678 are coupled to the output node Vramp. <n>628 and ground 638. The first cascode device NCA 678 may be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to a bias voltage source VCN 676. During a read cycle, the first cascode device NCA 678 may at least partially switch the first compensation current switch SWA 632 from an output node Vramp on a ramp signal line to a ground node Vramp. <n>628 decouples (ie, electrically separates) the first compensation current switch SWA 632 so that the channel capacitance does not affect the output node Vramp. <n>628. In various examples, the first cascode device NCA 678 can be alternatively coupled between the compensation current source NB 634 and the first compensation current switch SWA 632.

[0043] In various examples, the compensation current unit 630 may further include a first sample and hold circuit (SHC) 670 coupled between a bias voltage source VCN 676 and a first cascode device NCA 678. The first SHC may include a capacitor 674 coupled between the cascode device NCA 678 and ground 638 and an SHC switch 672 coupled between the bias voltage source VCN 676 and the first cascode device NCA 678. In various examples, the compensation current unit 630 may further include a second SHC 680 coupled between a bias voltage source VBN 686 and a compensation current source NB 634. The second SHC may include a capacitor 684 coupled between the compensation current source NB 634 and ground 638 and an SHC switch 682 coupled between the bias voltage source VBN 686 and the compensation current source NB 634. Each of the first SHC 670 and the second SHC 680 may be configured to at least partially connect the output node Vramp to the output node Vramp. <n>628 is decoupled from bias voltage source VCN 676 or bias voltage source VBN 686, respectively, so that noise does not propagate from the bias voltage source to the output during a read cycle.

[0044] Next reference Figure 6B , the compensation current unit 630 and Fig. 6A 634 and the first compensation current switch SWA 632. The branch includes a second compensation current switch SWB 692 coupled between the compensation current source NB 634 and the power line VDD 664. The second compensation current switch SWB 692 may be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to be controlled by a second switch signal Swb_en 696. In various embodiments, the branch may further include a second cascode device NCB 698 coupled to the second compensation current switch SWB 692. The second cascode device NCB 698 may be a transistor (e.g., an NMOS transistor) having a gate terminal coupled to the same bias voltage source VCN 676 as the first cascode device NCA 678. In other embodiments, the first cascode device NCA 678 and the second cascode device NCB 698 may have gate terminals coupled to different bias voltage sources. The second compensation current switch SWB 692 may be bi-state switched to allow the precharge current I CB 690 flows to the compensation current source NB 634. As will be described below with respect to Figure 7 Describing in more detail, the branch can reduce the current I during the read cycle C Delay in 636.

[0045] Next reference Figure 6C , the compensation current unit 630 and Figure 6B 632 and the second cascode device NCA 678. In addition, the cascode device NCA 678 is coupled between the compensation current source NB 634 and each of the first compensation current switch SWA 632 and the second compensation current switch SWB 692.

[0046] In various examples, ground 638 may be replaced by a non-zero voltage source, as will be described below with respect to Figure 8 and 9 Therefore, the compensation current source NB 634, the first compensation current switch SWA 632 and the second compensation current switch SWB 692 and / or the first cascode device NCA 678 and the second cascode device NCB 698 may be PMOS transistors.

[0047] Figure 7 The following is a timing diagram illustrating a readout cycle of a compensation current unit in an exemplary readout circuit according to the teachings of the present disclosure. It should be understood that Figure 7 The timing diagram can be used for operations such as Figure 6B 0048] An exemplary timing diagram of the compensation current unit 630 is shown in FIG. 10, and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0048] In the illustrated timing diagram, the second switch signal Swb_en 796 can be configured to be pulsed before the ramp period (ie, between time t1 and t2). CB 790 may flow to a compensation current source (eg, Figure 6B At time t1, the second switch signal Swb_en 796 may be bi-state switched to off, and the first switch signal Ramp_en 762 may be bi-state switched to on to allow the compensation current source to be connected from the corresponding node Vramp on the ramp signal line. 728a、Vramp <m>728m、Vramp <n>728n draws current I C 736 or supplying the current to the corresponding node. At time t2 (ie, the end of the ramp period), the first switch signal Ramp_en 762 may be switched to off in a binary state, which causes the current I C 736 falls back to zero as the ramp signal returns to its nominal voltage level.

[0049] < / n> < / m> Figure 6B and 7 The circuit system and timing diagrams illustrated in the figures provide advantages over Fig. 6A Advantages of the circuit system illustrated in FIG. Return to Reference Fig. 6A , although the first switch signal Ramp_en 662 remains off before the ramp period, the voltage level at the drain terminal of the compensation current source 634 can be pulled down to ground because the compensation current source is still configured to conduct current. When the first switch signal Ramp_en 662 is toggled on at time t1, the voltage level at the drain terminal of the compensation current source 634 begins to increase (or decrease, depending on polarity) and eventually reaches a certain voltage level at which the compensation current source 634 can sink or supply the ideal current I for compensation. C 636. However, while the voltage level at the drain terminal of the compensation current source 634 is changing, the first cascode device NCA 678 may draw too much current and the node Vramp on the ramp signal line <n>628 may cause undesired interference.

[0050] Figure 6B The additional "branches" illustrated in the figure can solve this problem. Figure 7 As shown in FIG. 6 , pulsing the second switch signal Swb_en 696 / 796 before the ramp period allows the compensation current source NB 634 to draw the pre-charge current I CB 690, which can pre-charge the drain terminal of the compensation current source 634 before the ramp cycle. Then, at time t1, when the second switch signal Swb_en 696 / 796 is switched off and the first switch signal Ramp_en 662 / 762 is switched on, the compensation current source NB 634 can be switched to sink or supply current I with a small change in the voltage level at the drain terminal of the compensation current source 634. C 636, thereby reducing the optimal current I C The delay in 636 and the reduction of the node Vramp on the ramp signal line <n>Any unwanted interference on 628.

[0051] Figure 8 A schematic diagram illustrating a portion of an exemplary readout circuit including a compensation current unit according to the teachings of the present disclosure. It should be understood that Figure 8 The compensation current unit 830 may be as follows Figure 2 , and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0052] In the illustrated embodiment, each of the compensation current cells 830 and the representative local parasitic capacitance C P 842 may be included in a column unit cell. Each compensation current unit 830 may include a compensation current source 834 and a compensation current switch 832 coupled to the compensation current source 834. The compensation current source 834 and the compensation current switch 832 are coupled between a first node 828a / b / ... / m / n and a second node 839, wherein the first node is on a ramp signal line 820 coupled to the ramp generator 814, and the second node is coupled to a non-zero voltage source (i.e., a power line) VDD 838. The compensation current switch 832 may be configured to be controlled by an inverted switch signal Ramp_en_863. The inverted switch signal Ramp_en_863 may be an inverted signal of the non-inverted switch signal Ramp_en 862 (e.g., via an inverter 868). In the illustrated embodiment, all compensation current switches 832 are configured to be controlled by the same inverted switch signal Ramp_en_863.

[0053] Fig. 9 The following is a timing diagram illustrating a readout cycle of a compensation current unit in an exemplary readout circuit according to the teachings of the present disclosure. It should be understood that Fig. 9 The timing diagram can be used for operations such as Figure 8 8. An exemplary timing diagram of the compensation current unit 830 is shown in FIG. 8, and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0054] In the illustrated timing diagram, the inverted switching signal Ramp_en_963 is an inverted version of the non-inverted switching signal Ramp_en 962. Before the ramp period (i.e., before time t1), the inverted switching signal Ramp_en_963 can be configured to remain on, allowing the compensation current source (e.g., compensation current source 834) to draw current I from the power line (e.g., VDD 838). C 936 and the current I C 936 is supplied to the ramp generator (e.g., ramp generator 814). Then at time t1 (i.e., the start of the ramp cycle), the inverted switch signal Ramp_en_963 can be switched off in a two-state manner so that the compensation current unit (e.g., compensation current unit 830) is disabled and the ramp generator charges the local parasitic capacitance (e.g., local parasitic capacitance 842). At time t2 (i.e., the end of the ramp cycle), the inverted switch signal Ramp_en_963 can be switched back on in a two-state manner so that the current I C 936 flows again.

[0055] and Figures 3 to 7 Compared to the embodiment illustrated in FIG. Figure 8 and 9 The embodiment illustrated in FIG. 8 may have several disadvantages. One disadvantage is that since the compensation current unit 830 and the local parasitic capacitance 842 are coupled to different voltage levels (i.e., VDD 838 and ground, respectively), bi-state switching of the inverted switching signal Ramp_en_863 / 963 may change the current at those respective voltage level nodes, thereby causing power line noise (e.g., linearity or horizontal noise) that affects image quality. Another disadvantage is that since the current I C 936 flows before time t1, so there may be an IR drop along the ramp signal line 820, such as Fig. 9 Through the node Vramp <n>928n、Vramp <m>928m and Vramp However, in various examples, IR drop can remain constant during the ADC cycle because the charging current supplied by ramp generator 814 during the ADC cycle can be configured to be equal to the current I supplied to ramp generator 814 during the non-ADC cycle (e.g., before time t1). C 836 / 936 , thereby reducing or eliminating changes in the current flowing through the ramp signal line 820 . Figure 8 and 9 An advantage of the embodiment illustrated in is that the compensation current source 834 is disabled during the ADC cycle, so the design does not need to account for random noise, current consistency, etc., because the ramp signal and the current conducted by the compensation current source flow in the readout circuit at the same time. Another advantage is that in various embodiments, the settling time can be shortened.

[0056] The above description of the illustrated examples of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific examples of the present disclosure are described herein for illustrative purposes, as those skilled in the relevant art will recognize, various modifications may be made within the scope of the present disclosure.

[0057] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the appended claims should not be understood to limit the present disclosure to the specific examples disclosed in this specification. Instead, the scope of the present disclosure will be determined entirely by the appended claims, which will be interpreted according to established claim interpretation principles.< / m> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. An imaging system, comprising: a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; as well as a readout circuit system coupled to the pixel array, the readout circuit system comprising a plurality of column unit cells, wherein each column unit cell comprises: at least one of a plurality of comparators, wherein each comparator is coupled to receive a corresponding one of the image charge voltage signals from the pixel array, compare the corresponding one of the image charge voltage signals with a ramp signal from a ramp generator and responsively provide a digital representation of the corresponding one of the image charge voltage signals, and wherein each comparator is coupled to receive the ramp signal from the ramp generator via a ramp signal line; and A compensation current unit, coupled to the ramp signal line, comprises: a compensation current source; and A compensation current switch is coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line.

2. The imaging system of claim 1 , wherein each column unit cell further comprises a local parasitic capacitance coupled to the first node, wherein each compensation current unit is configured to locally conduct a current that is conducted through the local parasitic capacitance of the corresponding column unit cell. 3 . The imaging system of claim 1 , wherein each compensation current unit further comprises a sample and hold circuit coupled between the compensation current source and a bias voltage source.

4. The imaging system of claim 1 , wherein each compensation current unit further comprises a cascode device coupled to the compensation current switch, wherein the compensation current source, the cascode device, and the compensation current switch are coupled between the first node and the second node. 5 . The imaging system of claim 4 , wherein the cascode device is coupled between the first node and the compensation current switch.

6. The imaging system of claim 4, wherein each compensation current unit further comprises a sample and hold circuit coupled between the cascode device and a bias voltage source. 7 . The imaging system of claim 1 , wherein the compensation current switch is a first compensation current switch, wherein each compensation current unit further comprises a second compensation current switch coupled between the compensation current source and a power line.

8. The imaging system of claim 7, wherein each compensation current unit further comprises a cascode device coupled to the second compensation current switch, wherein the cascode device, the second compensation current switch, and the compensation current source are coupled between the power line and the second node.

9. The imaging system of claim 1, wherein each second node is coupled to ground.

10. The imaging system of claim 1, wherein each second node is coupled to a non-zero voltage value.

11. A method of operating an imaging system, comprising: A plurality of column unit cells are coupled to the pixel array, wherein each column unit cell comprises: at least one of a plurality of comparators, wherein each comparator is coupled to receive a ramp signal from a ramp generator via a ramp signal line; and A compensation current unit, coupled to the ramp signal line, comprises: a compensation current source; and a compensation current switch coupled to the compensation current source, wherein the compensation current switch is configured to be controlled by a switch signal, and wherein the compensation current source and the compensation current switch are coupled between a first node and a second node on the ramp signal line; toggling each switch signal at the beginning of a ramp period; and Each switch signal is toggled at the end of the ramp period, thereby causing the compensation current source to generate a compensation current.

12. The method of claim 11 , wherein each column unit cell further comprises a local parasitic capacitance coupled to the first node, and wherein toggling each switch signal at the beginning and the end of the ramping period causes the compensation current to be locally conducted through the local parasitic capacitance in each respective column unit.

13. The method according to claim 11, wherein the compensation current switch is a first compensation current switch, wherein the switch signal is a first switch signal, wherein each compensation current unit further comprises a second compensation current switch coupled between the compensation current source and a power line, wherein the second compensation current switch is configured to be controlled by a second switch signal, the method further comprising: The second switching signal is pulsed before the start of the ramp period, thereby precharging the compensation current source and reducing a delay of the compensation current before the start of the ramp period. 14 . The method of claim 13 , pulsing the second switching signal comprises turning off the second switching signal at the beginning of the ramp period.

15. The method of claim 11, wherein each second node is coupled to ground, wherein toggling the switch signal at the beginning of the ramp period comprises turning the switch signal on at the beginning of the ramp period, and wherein toggling the switch signal at the end of the ramp period comprises turning the switch signal off at the end of the ramp period.

16. The method of claim 11, wherein each second node is coupled to a non-zero voltage value, wherein toggling the switch signal at the beginning of the ramp period comprises turning the switch signal off at the beginning of the ramp period, and wherein toggling the switch signal at the end of the ramp period comprises turning the switch signal on at the end of the ramp period.

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