Circuit board, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention relates to the technical field of circuit boards, and provides a circuit board, a preparation method thereof and electronic equipment. The circuit board comprises a base material layer, a first electrode, an insulating medium layer and a second electrode. A through hole is defined in the base material layer. The first electrode is located on the inner wall of the through hole. The insulating medium layer is located on the base material layer and wraps the first electrode. And the second electrode is partially embedded in the insulating medium layer. In the thickness direction of the circuit board, the second electrode is at least partially parallel to the first electrode, and the second electrode, the first electrode and the insulating dielectric layer form a first capacitor.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to a circuit board, a method for preparing the same, and an electronic device. Background Art

[0002] In existing circuit boards, embedded capacitors usually include an upper electrode layer, a dielectric layer, and a lower electrode layer stacked in sequence along the thickness direction of the circuit board. In a limited space, an ultra-thin dielectric layer is usually used to achieve a large capacitor, but when the dielectric layer is thin, the dielectric loss is large, which is not conducive to high-frequency and high-speed transmission. In addition, since the size of the capacitor is proportional to the facing area of ​​the upper electrode layer and the lower electrode layer, in order to achieve a large capacitor in existing circuit boards, the facing area of ​​the upper electrode layer and the lower electrode layer is large, which is not conducive to high-density integration of circuits. Summary of the invention

[0003] In a first aspect, the present application provides a circuit board. The circuit board comprises:

[0004] a substrate layer, defined with through holes;

[0005] A first electrode, located on the inner wall of the through hole;

[0006] an insulating dielectric layer, located on the substrate layer and wrapping the first electrode; and

[0007] A second electrode, partially embedded in the insulating dielectric layer;

[0008] Along the thickness direction of the circuit board, the second electrode is at least partially parallel to the first electrode, and the second electrode, the first electrode and the insulating medium layer constitute a first capacitor.

[0009] Since the first electrode and the second electrode of the circuit board are at least partially arranged in parallel in the thickness direction of the circuit board, the first capacitor is vertically embedded in the circuit board, which is beneficial to reducing the surface area occupied by the first capacitor in the direction perpendicular to the thickness of the circuit board, thereby facilitating high-density integration of the circuit.

[0010] The second aspect of the present application provides an electronic device, wherein the electronic device comprises the circuit board described in the first aspect of the present application.

[0011] The electronic device has the same advantages as the circuit board described in the first aspect, which will not be described in detail here.

[0012] The third aspect of the present application provides a method for preparing a circuit board. The method for preparing a circuit board comprises:

[0013] forming a through hole on the substrate layer;

[0014] forming a first electrode on an inner wall of the through hole;

[0015] forming an insulating dielectric layer on the substrate layer to wrap the first electrode; and

[0016] A second electrode is embedded in the insulating medium layer; along the thickness direction of the circuit board, the second electrode and the first electrode are at least partially parallel, and the first electrode, the second electrode and the insulating medium layer constitute a first capacitor.

[0017] In the method for preparing the circuit board, along the thickness direction of the circuit board, a first electrode is formed on the inner wall of the through hole, and a second electrode is embedded in the insulating dielectric layer to obtain a first capacitor vertically embedded in the circuit board, which is beneficial to reducing the surface area occupied by the first capacitor in the direction perpendicular to the thickness of the circuit board, and further beneficial to high-density integration of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a circuit board in the prior art.

[0019] Figure 2A A cross-sectional view of a circuit board according to an embodiment of the present application.

[0020] Figure 2B for Figure 2A A three-dimensional diagram of the first electrode, the second electrode and the third electrode.

[0021] Figure 3 A circuit diagram of a circuit board according to an embodiment of the present application.

[0022] Figure 4 This is a circuit diagram of a circuit board according to another embodiment of the present application.

[0023] Figure 5 This is a circuit diagram of a circuit board according to yet another embodiment of the present application.

[0024] Figure 6 The present invention is a flow chart of a method for preparing a circuit board according to an embodiment of the present application.

[0025] Fig. 7A and Figure 7B for Figure 6 A cross-sectional view of step S1 in FIG.

[0026] FIG. 8A to FIG. 8E for Figure 6 A cross-sectional view of step S2 in FIG.

[0027] Fig. 9 for Figure 6 A cross-sectional view of step S3 in FIG.

[0028] Figures 10A to 10F for Figure 6 A cross-sectional view of step S4 in FIG.

[0029] Description of main component symbols:

[0030] Circuit board 10, 10'

[0031] Base material layer 11

[0032] First surface 11a

[0033] Second surface 11b

[0034] Via 11h

[0035] First electrode 12

[0036] First end surface 12a

[0037] Second end surface 12b

[0038] Outer ring surface 121

[0039] Insulating dielectric layer 13

[0040] The third surface 13a

[0041] Fourth surface 13b

[0042] The first groove 131

[0043] The second groove 132

[0044] The second electrode 14

[0045] Inner ring surface 141, 151

[0046] The third electrode 15

[0047] Signal layer 16

[0048] First ground layer 17

[0049] The second ground layer 18

[0050] The first capacitor C1

[0051] The second capacitor C2

[0052] Direction Z, Z'

[0053] The first filter capacitor FC1

[0054] The second filter capacitor FC2

[0055] Pole spacing d1, d2

[0056] Ring diameter d3

[0057] First height h1

[0058] The second height h2

[0059] Capacitors C, Ca, Cb

[0060] Power line L1

[0061] Signal line L2

[0062] Ground wire L3

[0063] Lower electrode layer 1

[0064] Dielectric layer 2

[0065] Upper electrode layer 3

[0066] Copper clad substrate 20

[0067] The first copper foil layer 21

[0068] The second copper foil layer 22

[0069] The first copper plating layer 30

[0070] The second copper plating layer 40

[0071] The third copper plating layer 50

[0072] First dry film M1

[0073] The first dry film M1' after exposure

[0074] The first dry film M1 after development

[0075] Second dry film M2

[0076] The second dry film M2' after exposure

[0077] The second dry film M2 after development

[0078] The third dry film M3

[0079] The third dry film M3' after exposure

[0080] The third dry film M3 after development

[0081] Fourth dry film M4

[0082] The fourth dry film M4' after exposure

[0083] The fourth dry film M4 after development

[0084] Steps S1, S2, S3, S4 DETAILED DESCRIPTION

[0085] like Figure 1As shown, in the existing circuit board 10', the embedded capacitor C usually includes a lower electrode layer 1, a dielectric layer 2 and an upper electrode layer 3 stacked in sequence along the thickness direction Z' of the circuit board 10'. Since the size of the capacitor C is proportional to the facing area of ​​the upper electrode layer 3 and the lower electrode layer 1, in order to achieve a large capacitance in the existing circuit board 10', the facing area of ​​the lower electrode layer 1 and the upper electrode layer 3 is large, which is not conducive to high-density integration of circuits.

[0086] In this regard, the present application provides a circuit board, a method for preparing a circuit board, and an electronic device. The circuit board includes a substrate layer, a first electrode, an insulating dielectric layer, and a second electrode. The substrate layer defines a through hole. The first electrode is located on the inner wall of the through hole. The insulating dielectric layer is located on the substrate layer and wraps the first electrode. The second electrode is partially embedded in the insulating dielectric layer. Along the thickness direction of the circuit board, the second electrode is at least partially parallel to the first electrode, and the second electrode, the first electrode, and the insulating dielectric layer constitute a first capacitor. The circuit board forms a first electrode on the inner wall of the through hole of the substrate layer, and embeds the second electrode in the insulating dielectric layer. Since the first electrode and the second electrode are at least partially arranged in parallel in the thickness direction of the circuit board, the first capacitor is vertically embedded in the circuit board (or the first capacitor is formed in the lateral direction, or the first capacitor is formed in the horizontal direction), which is conducive to reducing the surface area occupied by the first capacitor in the direction perpendicular to the thickness of the circuit board (also referred to as the lateral or horizontal direction), increasing the internal wiring space of the circuit board, and thus facilitating high-density integration and thin design of the circuit.

[0087] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0088] like Figure 2A As shown, the circuit board 10 includes a substrate layer 11 , a first electrode 12 , an insulating medium layer 13 and a second electrode 14 .

[0089] The substrate layer 11 has a first surface 11a and a second surface 11b opposite to each other along the thickness direction Z of the circuit board 10. The substrate layer 11 defines a through hole 11h penetrating the first surface 11a and the second surface 11b.

[0090] The first electrode 12 is located on the inner wall of the through hole 11h. In the thickness direction Z of the circuit board 10, the two ends of the first electrode 12 extend beyond the first surface 11a and the second surface 11b respectively. For the convenience of description below, the end surface of the first electrode 12 extending beyond the first surface 11a is defined as the first end surface 12a (shown in FIG. Figure 2B ), the end surface of the first electrode 12 extending beyond the second surface 11b is the second end surface 12b (shown in Figure 2B middle).

[0091] The insulating dielectric layer 13 is located on the substrate layer 11 and completely wraps the first electrode 12. Along the thickness direction Z of the circuit board 10, the insulating dielectric layer 13 has a third surface 13a and a fourth surface 13b opposite to each other. The third surface 13a is closer to the first surface 11a of the substrate layer 11 than the fourth surface 13b.

[0092] A first groove 131 is provided on one side of the third surface 13a of the insulating dielectric layer 13, and the second electrode 14 is embedded in the first groove 131 of the insulating dielectric layer 13, and partially exposes the third surface 13a of the insulating dielectric layer 13. Along the thickness direction Z of the circuit board 10, the second electrode 14 is at least partially parallel to the first electrode 12. Along the thickness direction Z perpendicular to the circuit board 10, the parallel and opposite parts of the first electrode 12 and the second electrode 14 and the part of the insulating dielectric layer 13 located at the first electrode 12 and the second electrode 14 constitute the first capacitor C1. Since the first capacitor C1 is vertically embedded in the circuit board 10, it is beneficial to reduce the surface area occupied by the first capacitor C1 in the thickness direction Z perpendicular to the circuit board 10, thereby facilitating high-density integration of the circuit.

[0093] In some embodiments, the material of the substrate layer 11 is, for example, polyimide (PI), modified polyimide (MPI), liquid crystal polymer (LCP), FR4 glass fiber, and ajinomoto build-up film (ABF), but not limited thereto. The material of the first electrode 12 and the second electrode 14 is, for example, electroplated copper, but not limited thereto. The material of the insulating dielectric layer 13 is, for example, pure rubber, LCP, ABF, photosensitive resin, etc., but not limited thereto.

[0094] Please continue reading Figure 2AA second groove 132 is provided on the side where the fourth surface 13b of the insulating dielectric layer 13 is located, and the circuit board 10 also includes a third electrode 15 located on the side of the substrate layer 11 away from the second electrode 14. The third electrode 15 is embedded in the second groove 132 of the insulating dielectric layer 13 and partially exposes the fourth surface 13b of the insulating dielectric layer 13. Along the thickness direction Z of the circuit board 10, the third electrode 15 is at least partially parallel to the first electrode 12. Along the thickness direction Z perpendicular to the circuit board 10, the portion of the first electrode 12 that is parallel and directly opposite to the third electrode 15 and the portion of the insulating dielectric layer 13 located at the first electrode 12 and the third electrode 15 constitute the second capacitor C2. Since the second capacitor C2 is vertically embedded in the circuit board 10, it is beneficial to reduce the surface area occupied by the second capacitor C2 in the thickness direction Z perpendicular to the circuit board 10, thereby facilitating high-density integration of the circuit.

[0095] Figure 2A Only two through holes 11h defined on the substrate layer 11 are shown schematically, and a first capacitor C1 and a second capacitor C2 are formed corresponding to each through hole 11h. Figure 2A Two first capacitors C1 and two second capacitors C2 are schematically shown. In other embodiments, the number of through holes 11h on the substrate layer 11, the number of first capacitors C1 and the number of second capacitors C2 are not limited thereto. In addition, when the number of first capacitors C1 is multiple, each two first capacitors C1 can be connected in series or in parallel. Similarly, when the number of second capacitors C2 is multiple, each two second capacitors C2 can be connected in series or in parallel.

[0096] Further, the size of the first capacitor C1 can be set by the inter-electrode distance d1 between the first electrode 12 and the second electrode 14, the facing area A1 between the first electrode 12 and the second electrode 14, and the permittivity ε1 of the insulating medium between the first electrode 12 and the second electrode 14. Similarly, the size of the second capacitor C2 can be set by the inter-electrode distance d2 between the first electrode 12 and the third electrode 15, the facing area A2 between the first electrode 12 and the third electrode 15, and the permittivity ε2 of the insulating medium between the first electrode 12 and the third electrode 15. Figure 2A In the illustrated embodiment, the insulating dielectric layer 13 between the first electrode 12 and the second electrode 14 and the insulating dielectric layer 13 between the first electrode 12 and the third electrode 15 are made of the same material layer. In other embodiments, the insulating dielectric layer 13 between the first electrode 12 and the second electrode 14 and the insulating dielectric layer 13 between the first electrode 12 and the third electrode 15 can be respectively set to insulating materials with different permittivities.

[0097] Figure 2AIn the embodiment shown, the first surface 11a of the substrate layer 11 is the bottom surface of the first groove 131, and the second surface 11b of the substrate layer 11 is the bottom surface of the second groove 132. The second electrode 14 is located on the first surface 11a of the substrate layer 11, and the third electrode 15 is located on the second surface 11b of the substrate layer 11. Therefore, Figure 2A The distance from the first surface 11a of the substrate layer 11 to the first end surface 12a of the first electrode 12 is the first height h1, which is the height of the first electrode 12 and the second electrode 14 facing each other. The distance from the second surface 11b of the substrate layer 11 to the second end surface 12b of the first electrode 12 is the second height h2, which is the height of the first electrode 12 and the third electrode 15 facing each other. Figure 2A In the embodiment shown, the through hole 11h is circular, and the first groove 131 and the second groove 132 are both annular. Figure 2A and Figure 2B , the first electrode 12, the second electrode 14 and the third electrode 15 are all closed rings. Therefore, Figure 2A The inter-pole spacing d1 in the figure is the ring spacing between the first electrode 12 and the second electrode 14, and the inter-pole spacing d2 is the ring spacing between the first electrode 12 and the third electrode 15. The facing area A1 between the first electrode 12 and the second electrode 14 is the facing area between the outer annular surface 121 of the first electrode 12 and the inner annular surface 141 of the second electrode 14. The facing area A2 between the first electrode 12 and the third electrode 15 is the facing area between the outer annular surface 121 of the first electrode 12 and the inner annular surface 151 of the third electrode 15. In this way, the facing area A1 between the first electrode 12 and the second electrode 14 can be set by adjusting the size of the inter-pole spacing d1, the size of the first height h1, or the size of the hole ring diameter d3. Among them, the hole ring diameter d3 is defined as the minimum distance between the outer annular surfaces 121 of two adjacent first electrodes 12. The facing area A2 between the first electrode 12 and the third electrode 15 can be set by adjusting the size of the inter-pole spacing d2, the size of the second height h2, or the size of the hole ring diameter d3.

[0098] In other embodiments, the second electrode 14 is not limited to being located on the first surface 11a of the substrate layer 11, and the third electrode 15 is not limited to being located on the second surface 11b of the substrate layer 11. It is only necessary to ensure that the first electrode 12 and the second electrode 14 are at least partially parallel and face to face, and the first electrode 12 and the third electrode 15 are at least partially parallel and face to face in the thickness direction Z perpendicular to the circuit board 10. In other embodiments, the first electrode 12, the second electrode 14, and the third electrode 15 are not limited to being closed rings or circular rings.

[0099] Please continue reading Figure 2AThe circuit board 10 further includes a first ground layer 17 located on the first surface 11a, a signal layer 16 located on the second surface 11b, and a second ground layer 18 located on the fourth surface 13b. The signal layer 16 includes a signal line L2. The signal line L2, the first ground layer 17, and the second ground layer 18 constitute a stripline.

[0100] It should be noted that in a high-speed transmission circuit board, the smaller the thickness of the dielectric layer between the signal line and the two ground layers in the strip line, the greater the dielectric loss, which is less conducive to high-speed signal transmission. Therefore, in order to reduce dielectric loss, a large dielectric layer thickness (such as greater than 50 microns) is usually required. Figure 2A In the circuit board 10 shown, along the thickness direction Z of the circuit board 10, the substrate layer 11 between the signal layer 16 and the first ground layer 17 is required to have a large thickness, and the insulating dielectric layer 13 between the signal layer 16 and the second ground layer 18 is required to have a large thickness. However, since the size of the capacitor is inversely proportional to the thickness of the dielectric layer between the two parallel electrodes, in order to achieve a large capacitance, the thickness of the dielectric layer in the circuit board is required to be as small as possible (such as less than 16 microns). Therefore, the embedded capacitor and signal transmission in the circuit board have different requirements for the thickness of the dielectric layer, resulting in the embedded capacitor and the signal layer cannot be designed in the same layer, or in other words, the embedded capacitor and the strip line cannot share the same dielectric layer.

[0101] In the embodiment of the present application, the first capacitor C1 and the second capacitor C2 are vertically embedded in the circuit board 10, and the portion of the insulating dielectric layer 13 perpendicular to the thickness direction Z of the circuit board 10 is used as the dielectric layer of the first capacitor C1 and the second capacitor C2, and the portion of the insulating dielectric layer 13 along the thickness direction Z of the circuit board 10 is used as the dielectric layer of the strip line, so that the signal layer and the embedded capacitor (i.e., the first capacitor C1 and the second capacitor C2) can share the same dielectric layer.

[0102] In a possible application scenario, the first capacitor C1 and the second capacitor C2 are used in bypass capacitors to filter signals or power supplies. Figure 3 As shown, the circuit board 10 includes a power line L1, a signal line L2, a ground line L3, a first filter capacitor FC1 and a second filter capacitor FC2. The first filter capacitor FC1 is connected between the signal line L2 (or the power line L1) and the ground line L3, and the second filter capacitor FC2 is connected in parallel with the first filter capacitor FC1, and is also connected between the signal line L2 (or the power line L1) and the ground line L3. The first filter capacitor FC1 includes a first capacitor C1. The second filter capacitor FC2 includes a second capacitor C2. By connecting the first filter capacitor FC1 and the second filter capacitor FC2 in parallel, a better filtering effect can be achieved for a specific frequency band. In other embodiments, the number of filter capacitors in the circuit board 10 is not limited to two.

[0103] Specifically, the number of the first capacitors C1 in the first filter capacitor FC1 may be one or more. When the number of the first capacitors C1 in the first filter capacitor FC1 is multiple, the multiple first capacitors C1 may be connected in series or in parallel. Similarly, the number of the second capacitors C2 in the second filter capacitor FC2 may be one or more. When the number of the second capacitors C2 in the second filter capacitor FC2 is multiple, the multiple second capacitors C2 may be connected in series or in parallel.

[0104] In some embodiments, in order to improve the filtering effect, the first filter capacitor FC1 and the second filter capacitor FC2 are not equal in size. Specifically, by setting the size of the first capacitor C1, the size of the second capacitor C2, the number N1 of the first capacitor C1 in the first filter capacitor FC1, the number N2 of the second capacitor C2 in the second filter capacitor FC2, the connection method of the first capacitor C1 in the first filter capacitor FC1, and the connection method of the second capacitor C2 in the second filter capacitor FC2, the first filter capacitor FC1 and the connection method of the second capacitor C2 in the second filter capacitor FC2 make the first filter capacitor FC1 and the second filter capacitor FC2 unequal in size. The size of the first capacitor C1 depends on the inter-pole spacing d1 between the first electrode 12 and the second electrode 14, the facing area A1 between the first electrode 12 and the second electrode 14, and the permittivity ε1 of the insulating dielectric layer 13 between the first electrode 12 and the second electrode 14. The size of the second capacitor C2 depends on the inter-pole spacing d2 between the first electrode 12 and the third electrode 15, the facing area A2 between the first electrode 12 and the third electrode 15, and the permittivity ε2 of the insulating dielectric layer 13 between the first electrode 12 and the third electrode 15. Therefore, at least one of the inter-pole spacing d1 and the inter-pole spacing d2, the facing area A1 and the facing area A2, the permittivity ε1 and the permittivity ε2, the number N1 and the number N2, and the connection method of the first capacitor C1 in the first filter capacitor FC1 and the connection method of the second capacitor C2 in the second filter capacitor FC2 is different.

[0105] In a possible application scenario, the first electrodes 12 of multiple first capacitors C1 are connected in series to form a first filter capacitor FC1, one electrode of which is electrically connected to the ground line L3, and the second electrodes 14 of multiple first capacitors C1 are connected in series to form the other electrode of the first filter capacitor FC1, which is electrically connected to the signal line L2 or the power line L1; the first electrodes 12 of multiple second capacitors C2 are connected in series to form a second filter capacitor FC2, one electrode of which is electrically connected to the ground line L3, and the third electrodes 15 of multiple second capacitors C2 are connected in series to form the other electrode of the second filter capacitor FC2, which is electrically connected to the signal line L2 or the power line L1. The first filter capacitor FC1 and the second filter capacitor FC2 are connected in parallel. The sizes of the first filter capacitor FC1 and the second filter capacitor FC2 can be adjusted by the d1 and the d2, the A1 and the A2, the ε1 and the ε2, and the N1 and the N2. Specifically, Figure 4 In the embodiment shown, Figure 4 The four first capacitors C1 shown in Figure (a) are connected in series to obtain Figure 4 The first filter capacitor FC1 in Figure (b) and the four second capacitors C2 are connected in series to obtain Figure 4 The second filter capacitor FC2 in Figure (b).

[0106] In another possible application scenario, the first filter capacitor FC1 may include a first capacitor C1 connected in parallel, and the second filter capacitor FC2 may include a second capacitor C2 connected in parallel. Specifically, Figure 5 In the embodiment shown, Figure 5 The three first capacitors C1 shown in Figure (a) are connected in series to form a capacitor Ca, which is then connected in parallel with a first capacitor C1 to obtain Figure 5 The first filter capacitor FC1 in Figure (b) is connected in series with three second capacitors C2 to form a capacitor Cb, which is then connected in parallel with a second capacitor C2 to form a capacitor Cb. Figure 5 In summary, the circuit board 10 of the embodiment of the present application can obtain a large capacitance by increasing the number of first capacitors C1 or second capacitors C2 connected in series or in parallel in the thickness direction Z perpendicular to the circuit board 10, rather than the conventional method of increasing the facing area of ​​the two electrodes of the capacitor in the thickness direction Z perpendicular to the circuit board 10. This can reduce the surface space of the circuit board occupied by the embedded capacitor, which is beneficial to the high-density integration of the circuit.

[0107] The embodiment of the present application also provides an electronic device, which includes the above-mentioned circuit board. The electronic device is, for example, a consumer electronic product such as a mobile phone, a wireless Bluetooth headset, a smart watch, an augmented reality device or a virtual reality device. Since the electronic device includes the above-mentioned circuit board, it has the advantages of miniaturization, high packaging density, and high signal transmission integrity.

[0108] The present application also provides a method for preparing a circuit board. Figure 6 As shown, the preparation method includes steps S1 to S4. It can be understood that some steps can be combined or omitted.

[0109] Step S1: forming a through hole on the substrate layer.

[0110] Specifically, step S1 includes providing a copper-clad substrate and performing laser drilling on the copper-clad substrate.

[0111] like Fig. 7A As shown, the copper clad substrate 20 includes a substrate layer 11, a first copper foil layer 21 located on a first surface 11a of the substrate layer 11, and a second copper foil layer 22 located on a second surface 11b of the substrate layer 11. The second surface 11b is opposite to the first surface 11a.

[0112] like Figure 7BAs shown, after the laser drilling process, the through hole 11 h penetrates the first surface 11 a and the second surface 11 b of the substrate layer 11 , the first copper foil layer 21 and the second copper foil layer 22 .

[0113] Step S2: forming a first electrode on the inner wall of the through hole.

[0114] Specifically, step S2 includes the following steps S21 to S25.

[0115] Step S21: forming a first copper plating layer on the inner wall of the through hole.

[0116] In step S21, a first copper plating layer 30 is formed, for example, by an electroplating process. Fig. 8A As shown, the first copper plating layer 30 covers not only the inner wall of the through hole 11 h , but also the surface of the first copper foil layer 21 away from the base layer 11 and the surface of the second copper foil layer 22 away from the base layer 11 .

[0117] Step S22: forming a first dry film and a second dry film on opposite sides of the first copper plating layer.

[0118] like Figure 8B As shown, the first dry film M1 covers the side of the first copper plating layer 30 where the first surface 11 a of the substrate layer 11 is located, and the second dry film M2 covers the side of the second surface 11 b of the substrate layer 11 is located.

[0119] Step S23: exposing the first dry film and the second dry film.

[0120] Specifically, the first dry film M1′ after exposure and the second dry film M2′ after exposure are as follows: Figure 8C shown.

[0121] Step S24: developing the first dry film and the second dry film, and etching the first copper plating layer using the developed first dry film and the developed second dry film as masks.

[0122] like Fig.8D As shown, the first copper foil layer 21 and the first copper plating layer 30 are etched on one side of the first surface 11a of the substrate layer 11 using the developed first dry film M1″ as a mask, and the first grounding layer 17 is formed on the first surface 11a of the substrate layer 11. The second copper foil layer 22 and the first copper plating layer 30 are etched on one side of the second surface 11b of the substrate layer 11 using the developed second dry film M2″, and the signal layer 16 is formed on the second surface 11b of the substrate layer 11. In addition, the first copper plating layer 30 is etched using the developed first dry film M1″ and the developed second dry film M2″ as masks, and the first electrode 12 is also formed on the inner wall of the through hole 11h.

[0123] Step S25: removing the developed first dry film and the second dry film.

[0124] like Fig. 8E As shown, the developed first dry film M1 ″ and the developed second dry film M2 ″ are removed.

[0125] Step S3: forming an insulating dielectric layer wrapping the first electrode on the substrate layer.

[0126] like Fig. 9 As shown, the insulating dielectric layer 13 completely wraps the substrate layer 11, the first electrode 12, the signal layer 16 and the first ground layer 17, and fills the through hole 11h. The insulating dielectric layer 13 has a third surface 13a and a fourth surface 13b opposite to each other. The third surface 13a is closer to the first surface 11a of the substrate layer 11 than the fourth surface 13b. In one embodiment, the third surface 13a and the fourth surface 13b are both flat surfaces, but are not limited thereto.

[0127] Step S4: embed the second electrode in the insulating dielectric layer. Along the thickness direction of the circuit board, the second electrode and the first electrode are at least partially parallel, and the first electrode, the second electrode and the insulating dielectric layer constitute a first capacitor.

[0128] In some embodiments, while forming the second electrode in step S4, the method for preparing the circuit board further includes forming a third electrode embedded in the insulating dielectric layer on a side of the substrate layer away from the second electrode; along the thickness direction of the circuit board, the third electrode is at least partially parallel to the first electrode, and the third electrode, the first electrode and the insulating dielectric layer constitute a second capacitor. FIG. 10A to FIG. 10F and Figure 2A illustrate.

[0129] Specifically, step S4 includes the following steps S41 to S47.

[0130] Step S41: forming a first groove and a second groove on a third surface and a fourth surface opposite to the insulating dielectric layer, respectively.

[0131] like Fig. 10A As shown, a first groove 131 is formed on the side where the third surface 13a of the insulating dielectric layer 13 is located, and a second groove 132 is formed on the side where the fourth surface 13b of the insulating dielectric layer 13 is located. The first groove 131 is annular and exposes the first surface 11a of the substrate layer 11, and the second groove 132 is annular and exposes the second surface 11b of the substrate layer 11. In other embodiments, the depths of the first groove 131 and the second groove 132 are not limited thereto.

[0132] In some embodiments, the insulating dielectric layer 13 is made of photosensitive material, and the first groove 131 and the second groove 132 are formed by exposure and development in step S41. In other embodiments, the first groove 131 and the second groove 132 can be formed by laser cutting, but the present invention is not limited thereto.

[0133] Step S42: forming a second copper plating layer on the first groove and the third surface of the insulating dielectric layer, and forming a third copper plating layer on the second groove and the fourth surface of the insulating dielectric layer.

[0134] like Fig. 10B As shown, after metallization and electroplating processes, the second copper plating layer 40 fills the first groove 131 and covers the third surface 13 a of the insulating dielectric layer 13 , and the third copper plating layer 50 fills the second groove 132 and covers the fourth surface 13 b of the insulating dielectric layer 13 .

[0135] Step S43: forming a third dry film on the second copper plating layer, and forming a fourth dry film on the third copper plating layer.

[0136] like Fig. 10C As shown, the third dry film M3 covers the surface of the second copper plating layer 40 away from the substrate layer 11 , and the fourth dry film M4 covers the surface of the third copper plating layer 50 away from the substrate layer 11 .

[0137] Step S44: exposing the third dry film and the fourth dry film.

[0138] Specifically, the third dry film M3′ after exposure and the fourth dry film M4′ after exposure are as follows: Fig. 10D shown.

[0139] Step S45: developing the third dry film and the fourth dry film.

[0140] Specifically, the third dry film M3" after development and the fourth dry film M4" after development are as follows: Fig.10E shown.

[0141] Step S46: using the developed third dry film as a mask to etch the second copper plating layer, and using the developed fourth dry film as a mask to etch the third copper plating layer.

[0142] like Fig.10F As shown, the second copper-plated layer 40 is etched to form a second electrode 14 embedded in the insulating dielectric layer 13, and the third copper-plated layer 50 is etched to form a third electrode 15 embedded in the insulating dielectric layer 13. In addition, in step S46, after the third copper-plated layer 50 is etched, a second grounding layer 18 is also formed on the side of the signal layer 16 away from the insulating dielectric layer 13. In this way, the signal layer 16 and the first grounding layer 17 and the second grounding layer 18 respectively located on the opposite sides of the signal layer 16 constitute a microstrip line.

[0143] Step S47: removing the developed third dry film and the developed fourth dry film.

[0144] Fig.10F After the third dry film M3" and the fourth dry film M4" after development are removed, the following is obtained: Figure 2A The circuit board 10 is shown.

[0145] It is understandable that the above description is made by taking the circuit board including four circuit layers as an example, and other embodiments are not limited thereto.

[0146] In summary, in the circuit board of the embodiment of the present application, the above-mentioned first capacitor and second capacitor are vertical embedded buried capacitors, a through hole is formed on the substrate layer by laser processing and other processes, a first electrode is formed on the side wall of the through hole by, for example, an electroplating process, and the first groove and the second groove are formed by laser cutting or image transfer (when the insulating medium layer is a photosensitive material) of the insulating medium layer, and then chemical plating and electroplating and other steps are performed to form the second electrode and the third electrode, the first electrode, the second electrode and the insulating medium layer located therebetween form a first parallel capacitor, and the first electrode, the third electrode and the insulating medium layer located therebetween form a second parallel capacitor.

[0147] In the circuit board of the embodiment of the present application, the first capacitor and the second capacitor can be in parallel, in series or independent of each other. The size of the first capacitor and the second capacitor can be determined by the interpolar spacing d1, the interpolar spacing d2, the first height h1, the second height h2, the diameter of the hole ring d3 and the number of capacitors in series or in parallel. In some embodiments, the first capacitor and the second capacitor are connected in parallel, and the first capacitor is greater than the second capacitor, then the interpolar spacing d1 can be less than the interpolar spacing d2, or the second height h2 is less than the first height h1, or the permittivity of the insulating medium layer between the first capacitor and the second capacitor is changed to achieve a better filtering effect.

[0148] In the circuit board of the embodiment of the present application, the signal layer and the embedded capacitor layer can be arranged in the same layer (or a common insulating dielectric layer and a substrate layer). Specifically, by forming an electrode of the embedded capacitor on the side wall of the through hole, and vertically embedding the second electrode and the third electrode in the insulating dielectric layer, and forming a larger capacitor by connecting the embedded capacitors corresponding to multiple through holes in parallel, compared with the traditional capacitor, in which the two electrodes are stacked along the thickness direction of the circuit board, the circuit board of the embodiment of the present application, the embedded capacitor is formed in the horizontal direction, and is arranged up and down in the thickness direction of the circuit board, which can be flexibly designed, which is conducive to reducing the surface space occupied by the embedded capacitor and achieving higher density integration.

[0149] In some embodiments, such as a high-speed transmission circuit board, the signal layer and the first ground layer and the second ground layer form a stripline. In order to reduce dielectric loss, in a traditional circuit board, the thickness of the dielectric layer between the signal layer and the first ground layer and the thickness of the dielectric layer between the signal layer and the second ground layer are required to be relatively thick (such as greater than 50 microns). In order to achieve a larger capacitance, the smaller the inter-electrode spacing, the better. Therefore, the inter-electrode spacing of the embedded capacitor is usually required to be less than 20 microns, that is, to achieve a large embedded capacitor, the thickness of the dielectric layer between the two electrodes is required to be less than 20 microns. In this way, in a traditional circuit board, the embedded capacitor cannot share the same dielectric layer with the stripline, and the embedded capacitor layer and the signal layer cannot be designed in the same layer. In the embodiment of the present application, the first capacitor and the second capacitor are vertically embedded. The first capacitor and the second capacitor use the portion of the insulating dielectric layer in the direction perpendicular to the thickness of the circuit board as the dielectric layer of the embedded capacitor. The stripline is conducive to the substrate layer and the portion of the insulating dielectric layer in the direction of the thickness of the circuit board as the dielectric layer. In this way, the two are compatible, which is conducive to the transmission of high-frequency and high-speed signals.

[0150] In some embodiments, the first capacitor and the second capacitor can be used in a bypass capacitor to filter the signal or power supply. For a specific signal frequency band, multiple capacitors in parallel (including but not limited to two) can achieve better filtering, and the circuit board of the embodiment of the present application is conducive to the parallel connection of multiple capacitors without occupying more surface space.

[0151] The above implementation modes are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred implementation modes, a person skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A circuit board, characterized in that: include: a substrate layer, defined with through holes; A first electrode, located on the inner wall of the through hole; an insulating dielectric layer, located on the substrate layer and wrapping the first electrode; as well as A second electrode, partially embedded in the insulating dielectric layer; Along the thickness direction of the circuit board, the second electrode is at least partially parallel to the first electrode, and the second electrode, the first electrode and the insulating medium layer constitute a first capacitor.

2. The circuit board according to claim 1, characterized in that The circuit board also includes a third electrode, which is located on a side of the substrate layer away from the second electrode and is partially embedded in the insulating medium layer; along the thickness direction of the circuit board, the third electrode is at least partially parallel to the first electrode, and the third electrode, the first electrode and the insulating medium layer constitute a second capacitor.

3. The circuit board according to claim 2, characterized in that: The circuit board also includes a power line, a signal line and a ground line. A first filter capacitor is connected between the power line and the ground line, and / or between the signal line and the ground line; the first filter capacitor includes one first capacitor, or the first filter capacitor includes multiple first capacitors connected in series, or the first filter capacitor includes multiple first capacitors connected in parallel.

4. The circuit board according to claim 3, characterized in that: A second filter capacitor is further connected between the power line and the ground line, and / or between the signal line and the ground line, and the second filter capacitor is connected in parallel with the first filter capacitor; The second filter capacitor includes one second capacitor, or the second filter capacitor includes a plurality of second capacitors connected in series, or the first filter capacitor includes a plurality of second capacitors connected in parallel.

5. The circuit board according to claim 4, characterized in that: The distance between the first electrode and the second electrode is d1, and the distance between the first electrode and the third electrode is d2; The facing area between the first electrode and the second electrode is A1, and the facing area between the first electrode and the third electrode is A2; The dielectric constant of the insulating dielectric layer between the first electrode and the second electrode is ε1, and the dielectric constant of the insulating dielectric layer between the first electrode and the third electrode is ε2; The number of the first capacitors in the first filter capacitor is N1, and the number of the second capacitors in the first filter capacitor is N2; At least one of the connection mode of d1 and d2, A1 and A2, ε1 and ε2, N1 and N2, and the connection mode of the first capacitor in the first filter capacitor and the connection mode of the second capacitor in the second filter capacitor is different.

6. The circuit board according to any one of claims 1 to 5, characterized in that: The circuit board also includes a signal layer, a first ground layer and a second ground layer. The signal layer and the first ground layer are respectively located on two opposite surfaces of the substrate layer. The insulating medium layer also wraps the signal layer. The second ground layer is located on a side of the insulating medium layer away from the signal layer.

7. An electronic device, characterized in that: Comprising a circuit board as claimed in any one of claims 1 to 6.

8. A method for preparing a circuit board, characterized in that: include: forming a through hole on the substrate layer; forming a first electrode on an inner wall of the through hole; forming an insulating dielectric layer on the substrate layer to wrap the first electrode; as well as A second electrode is embedded in the insulating medium layer; along the thickness direction of the circuit board, the second electrode and the first electrode are at least partially parallel, and the first electrode, the second electrode and the insulating medium layer constitute a first capacitor.

9. The method for preparing a circuit board according to claim 8, characterized in that: The method for preparing the circuit board also includes forming a third electrode embedded in the insulating medium layer on a side of the substrate layer away from the second electrode; along the thickness direction of the circuit board, the third electrode is at least partially parallel to the first electrode, and the third electrode, the first electrode and the insulating medium layer constitute a second capacitor.

10. The method for preparing a circuit board according to claim 9, characterized in that: Forming the first electrode also includes forming a signal layer and a first ground layer on two opposite surfaces of the substrate layer respectively; forming the insulating medium layer also wraps the signal layer; forming the third electrode also includes forming a second ground layer on the side of the signal layer away from the insulating medium layer.

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