Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, and belongs to the technical field of semiconductors. The semiconductor structure comprises a substrate, wherein the substrate comprises isolation structures and active regions located between the adjacent isolation structures; bit line structures arranged on the substrate at intervals; the node contact pads are located between the isolation structures and the active regions between the adjacent bit line structures, and one side surfaces of the node contact pads are in contact with at least part of the side surfaces of the corresponding active regions; and the node contact structures are positioned between the adjacent bit line structures, and the lower surfaces of the node contact structures are at least partially contacted with the upper surfaces of the node contact pads. According to the semiconductor structure provided by the embodiment of the invention, the contact area between the node contact structure and the active region is increased by additionally arranging the node contact pad in contact with at least part of the side surface of the active region, so that the open circuit between the node contact structure and the active region can be avoided, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of semiconductor technology, and in particular relates to a semiconductor structure and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that can write and read data and is widely used in data storage devices or apparatuses. DRAM includes multiple memory cells, each of which usually includes a transistor and a capacitor. The source of the transistor is electrically connected to the bit line (BL) through a bit line contact structure (BLC), and the active area (AA) is electrically connected to the capacitor through a node contact structure (NC). Based on the relevant process, AA needs to be electrically connected to BL and NC respectively. In terms of structure, it is easy to have the problem of NC and AA being open, which affects the final yield of the product and creates difficulties for the process technology and process window. Summary of the invention

[0003] An embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate, wherein the substrate comprises an isolation structure and an active region located between adjacent isolation structures; bit line structures spaced apart on the substrate; a node contact pad, wherein the node contact pad is located between the isolation structure and the active region between adjacent bit line structures, and a side surface of the node contact pad is in contact with at least a portion of a side surface of the corresponding active region; and a node contact structure located between adjacent bit line structures, wherein a lower surface of the node contact structure is in at least partial contact with an upper surface of the node contact pad.

[0004] An embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate, and forming an isolation structure and an active area located between adjacent isolation structures in the substrate; forming a node contact pad between at least a portion of the isolation structure and the active area, and a side surface of the node contact pad is in contact with at least a portion of the side surface of the corresponding active area; forming a spaced-apart bit line structure on the substrate; forming a node contact structure between adjacent bit line structures, and a lower surface of the node contact structure is in at least partial contact with an upper surface of the node contact pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A top view of a semiconductor structure in the related art is shown.

[0006] Figure 2 Shows Figure 1 Schematic diagram of a slice of the semiconductor structure shown.

[0007] Figures 3 to 18 A structural schematic diagram of each step of a method for preparing a semiconductor structure in the related art is shown.

[0008] Fig.19 A top view of a semiconductor structure provided by an embodiment of the present disclosure is shown.

[0009] Figures 20 to 38 A structural schematic diagram of each step of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0010] like Figure 1 As shown, the semiconductor structure in the related art includes a BL 11 extending along a first direction (e.g., a vertical direction), a WL (word line) 12 extending along a second direction (e.g., a horizontal direction), an AA 13 extending along a third direction, and a BLC 14. The first direction and the second direction may be perpendicular to each other, and the third direction may have a certain angle with the first direction and the second direction, respectively, but the present disclosure is not limited thereto. The BLC 14 is generally a truncated cone structure. Figure 2 For polishing from above Figure 1 Slice to the position where NC 15 and AA 13 appear on the upper part of the BLC 14 frustum.

[0011] Figure 3 (a) is a cross-sectional view parallel to NC 15, i.e. parallel to WL 12 and perpendicular to BL 11, Figure 3 (b) is a cross-sectional view parallel to BL 11, passing beside BL 11, and the cutting position is the NC hole. Figure 3 (a) An isolation structure 22 (e.g., STI (shallow trench isolation)) and an active region between two adjacent isolation structures 22 are formed in a substrate 21. The isolation structure 22 covers the upper surface of the active region. A silicon nitride layer 23 is formed on the isolation structure 22. Figure 3 (b), an isolation structure 22 is formed on a substrate 21, a buried wordline (BW) 24 is disposed adjacent to the isolation structure 22, and a buried wordline silicon nitride layer 25 is formed on the buried wordline 24. A silicon nitride layer 23 is formed on the buried wordline silicon nitride layer 25 and the isolation structure 22. Figure 4 (a), removing the silicon nitride layer 23 located on the isolation structure 22. Figure 4(b) The silicon nitride layer 23 on the isolation structure 22 and the buried word line silicon nitride layer 25 is removed, and a portion of the buried word line silicon nitride layer 25 is removed by an etch back process, and the remaining buried word line silicon nitride layer is represented by 251. The upper surface of the remaining buried word line silicon nitride layer 251 is lower than the upper surface of the isolation structure 22. Figure 5 (a), taking the upper surface of the active region as the etching end point, a portion of the isolation structure 22 is removed so that the upper surface of the remaining isolation structure 221 is flush with the upper surface of the active region. Figure 5 (b), taking the upper surface of the remaining buried word line silicon nitride layer 251 as the etching end point, removing part of the isolation structure 22, and the upper surface of the remaining isolation structure 221 is flush with the upper surface of the remaining buried word line silicon nitride layer 251. Figure 6 (a) An oxide layer (the oxide layer can be made of the same material as the isolation structure, i.e., silicon dioxide), a silicon nitride layer 26, and a polysilicon layer 27 are sequentially deposited on the upper surface of the remaining isolation structure 221 and the active region. Figure 6 (b), an oxide layer, a silicon nitride layer 26 and a polysilicon layer 27 are sequentially deposited on the upper surface of the remaining buried word line silicon nitride layer 251 and the remaining isolation structure 221. The polysilicon layer 27 can be a PG (periphery gate) poly. The oxide layer, silicon nitride layer 26 and polysilicon layer 27 deposited in the entire area can be removed (removed) by a PNR (periphery nitride removed) process in the peripheral area in the subsequent process. This is because the peripheral circuit needs to deposit gate oxide polysilicon (poly) to make CMOS (Complementary Metal Oxide Semiconductor), and the oxide layer and silicon nitride layer in the central area are retained for insulation of the pass BL and the active area below.

[0012] like Figure 7 (a) and 7(b), a silicon dioxide layer 28, a SOH layer 29, a silicon nitride layer 210, a SOH layer 211, a silicon nitride layer 212, a silicon dioxide layer 213, a SOH (spin on hard mask) layer 214, a silicon nitride layer 215 and a patterned photoresist (Photoresist, PR) 216 are sequentially deposited on the polysilicon layer 27 to define the following by a photolithography process (photo, PH). Figure 8 The BLC patterns shown in (a) and 8(b) are transferred to the active area. Figure 8As shown in (a), a part of the active area at the position of the self-bit line (self BL, i.e., the bit line electrically connected to the active area) is removed, and a part of the two isolation structures adjacent to the active area electrically connected to the self BL can also be removed, and the remaining isolation structure is represented as 222 to form a bit line contact hole between the remaining silicon nitride layer 261, the remaining polysilicon layer 271, and the remaining silicon dioxide layer 281 stacked in sequence, and then a polysilicon layer 240 is deposited to cover the exposed surface and sidewall of the bit line contact hole, the remaining isolation structure 222, the remaining silicon nitride layer 261, the remaining polysilicon layer 271, and the remaining silicon dioxide layer 281. Figure 8 As shown in (b), a hole is formed between the remaining silicon nitride layer 261, the remaining polysilicon layer 271 and the remaining silicon dioxide layer 281 stacked in sequence, the hole is located on the remaining buried word line silicon nitride layer 251, and a polysilicon layer 240 is deposited to cover the exposed surface and sidewall of the hole, the remaining buried word line silicon nitride layer 251 and the remaining silicon dioxide layer 281. Fig. 9 As shown in (a), the remaining silicon nitride layer 261 is used as the etching end point, the remaining polysilicon layer 271 and the remaining silicon dioxide layer 281 are removed, and then a polysilicon layer 217 is deposited in the bit line contact hole and on the upper surface of the remaining silicon nitride layer 261. Fig. 9 As shown in (b), the remaining silicon nitride layer 261 is used as the etching end point, the remaining polysilicon layer 271 and the remaining silicon dioxide layer 281 are removed, and then a polysilicon layer 217 is deposited in the hole and on the upper surface of the remaining silicon nitride layer 261. The polysilicon layer 217 is BLC poly, that is, polysilicon used to make BLC. Fig.10 As shown in (a) and 10(b), a tungsten (W) layer 218, a silicon nitride layer 219, an ACL (Amorphous carbon layer) layer 220, a silicon nitride layer 224, a SOH layer 225, a silicon nitride layer 226 and a photoresist 227 are deposited on the polysilicon layer 217 in sequence.

[0013] in, Fig.10 (a) shows a patterned photoresist 227, which is used to define the following through a photolithography process: Fig.11(a) shows the BL pattern. The polysilicon layer 2171 remaining after the photolithography process serves as a BLC, which is electrically connected to the upper surface of the active area exposed by the bit line contact hole. The W layer 2181 remaining on the remaining polysilicon layer 2171 after the photolithography process serves as a BL, and the silicon nitride layer 2191 remaining on the BL after the photolithography process serves as a protective layer for the BL. The BL electrically connected to the active area through the BLC is called a self BL, and the BL not electrically connected to the active area and located on the remaining isolation structure 222 is called a (pass BL, passing the bit line). The silicon nitride layer 262 remaining after the photolithography process is also included between the pass BL and the remaining isolation structure 222. As shown Fig.11 (b) The remaining silicon nitride layer 261, the polysilicon layer 217, the W layer 218, the silicon nitride layer 219, the ACL layer 220, the silicon nitride layer 224, the SOH layer 225, the silicon nitride layer 226 and the photoresist 227 are removed.

[0014] like Fig.12 As shown in (a), an oxide layer 228 and a silicon nitride layer 229 are sequentially formed on the exposed surfaces and sidewalls of BLC, BL and the protective layer of BL. When the protective layer of BL is a silicon nitride layer, a NON (nitride-oxide-nitride) structure covering BLC and BL is formed, and silicon dioxide 230 is filled between the NON structures. Fig.12 As shown in (b), silicon dioxide 230 is deposited on the remaining buried word line silicon nitride layer 251 and the remaining isolation structure 222. Fig.13 As shown in FIGS. 13(a) and 13(b), an ACL layer 231, a silicon nitride layer 232, a SOH layer 233, a silicon nitride layer 234 and a photoresist 235 are sequentially deposited on the silicon dioxide 230. Fig.13 As shown in (b), the photoresist 235 is patterned to define the following through photolithography: Fig.14 (b) shows the NC pattern 2301, which can be made of oxide such as silicon dioxide. Fig.14 As shown in (a), the ACL layer 231, the silicon nitride layer 232, the SOH layer 233, the silicon nitride layer 234 and the photoresist 235 are removed. Fig.15 As shown in (a), a silicon nitride layer 2213 is deposited on the silicon dioxide 230. Fig.15 As shown in (b), a silicon nitride layer 2213 is deposited on the NC pattern 2301 and fills the gap between adjacent NC patterns 2301. The silicon nitride layer 2213 can be used to form NC. Fig.16 As shown in (a), the silicon nitride layer 2213 and the silicon dioxide 230 are removed by an etch-back process. Fig.16As shown in (b), the NC pattern 2301 is used as the etching end point, a portion of the silicon nitride layer 2213 is removed, and then the NC pattern 2301 is removed, and the remaining silicon nitride layer 2213 is represented by 22131. Fig.17 As shown in (a), the silicon nitride layer 229 and part of the remaining isolation structure 222 at the active region position in the bit line contact hole are removed to expose the upper surface of part of the active region. The remaining silicon nitride layer 229 is represented by 2291. Fig.17 The remaining isolation structure 222 after (a) is denoted as 223. Fig.17 (b) shows that compared with Fig.16 (b) No treatment. Fig.17 As shown in (a), conductive polysilicon 2214 is filled between adjacent word line structures (which may be referred to as NC holes), as shown in FIG. Fig.17 As shown in (b), conductive polysilicon 2214 is filled between adjacent remaining silicon nitride layers 22131 (which may be referred to as NC holes) to form NC holes electrically connected to the active region.

[0015] From the above Figures 1 to 18 It can be seen from the related technologies that based on the related processes, AA needs to contact BL and NC respectively. However, on the one hand, due to the squeezing of BL on both sides, the space for NC to contact AA is compressed and offset, which is easy to open. On the other hand, AA is not evenly arranged. For example, AA is designed to be 3*2, with only 2 positions in the NC direction, which is relatively close. When NC contacts AA, it is easy to be squeezed by BL, resulting in NC and AA being unable to contact. On the other hand, BL and its NON structure compress the space for NC to connect AA, that is, the NON structure of the bit line and its side wall leads to a smaller space between adjacent bit lines, which is easy to cause the problem of NC and AA opening in structure, causing inevitable difficulties for process technology and process window. In addition, during the BL etching process, BLC is made of polysilicon. If the NON structure is incomplete, such as damaged, the BLC sidewall poly residue and NON structural defects are easy to cause NC and BLC short circuit, which ultimately affects the product yield. NC poly must ensure contact with AA in a limited space, but also cannot contact with BLC poly, which increases the process difficulty.

[0016] Based on the problems existing in the above-mentioned related technologies, an embodiment of the present disclosure provides a semiconductor structure, including: a substrate, the substrate including an isolation structure and an active area located between adjacent isolation structures; a bit line structure arranged at intervals on the substrate; a node contact pad (NC AA Landing Pad), the node contact pad is located between the isolation structure and the active area between adjacent bit line structures, and a side surface of the node contact pad is in contact with at least a portion of the side surface of the corresponding active area; a node contact structure located between adjacent bit line structures, the lower surface of the node contact structure is in at least partial contact with the upper surface of the node contact pad.

[0017] The semiconductor structure provided by the embodiment of the present disclosure increases the contact area between NC and AA by adding an NC AA Landing Pad between the isolation structure and the active area, which contacts at least a portion of the side surface of the corresponding active area. The NC AA Landing Pad then contacts the node contact structure NC thereon, thereby effectively avoiding an open circuit between NC and AA, thereby improving the reliability of the semiconductor structure and increasing the product yield.

[0018] In an exemplary embodiment, the semiconductor structure further includes: a node contact trench between adjacent isolation structures and the active region, wherein the node contact pad is disposed in the node contact trench.

[0019] In an exemplary embodiment, the semiconductor structure further includes: a groove located between adjacent isolation structures, and the node contact structure is at least partially disposed in the groove.

[0020] In an exemplary embodiment, the node contact pad has a depth of 5 to 15 nm and a width of 3 to 5 nm. In the disclosed embodiment, the insulation between AA and the isolation structure (e.g., STI) is related to the width and depth of the node contact point, as well as the material and structure of the STI. When the width and depth of the NC AA Landing Pad are within this value range, it can ensure that there is sufficient contact area between NC and AA, providing good electrical connection performance; on the other hand, the additional NC AA Landing Pad will not affect the insulation between the isolation structure and the active area, thereby ensuring the reliability of the semiconductor structure.

[0021] In the disclosed embodiment, the length of the node contact pad (NC AA landing pad) can be equal to the length of the polysilicon deposited in the NC hole, that is, the node contact structure formed in the NC hole, and the width of the NC AA landing pad is less than the width of the node contact structure. In other embodiments, the upper surface of the NC AA landing pad is in full contact with the lower surface of the node contact structure, which can ensure that the NC AA landing pad has the maximum contact area with the node contact structure. In yet other embodiments, the NC AA landing pad can fall at the exact center of the top view orthographic projection of the node contact structure to ensure that the NCAA landing pad is in direct contact with the node contact structure and to ensure the reliability of the contact.

[0022] In the disclosed embodiment, the depth of the node contact pad is no greater than the buried word line silicon nitride layer, that is, the height of the lower surface of the node contact pad is greater than the lower surface of the buried word line silicon nitride layer, thereby preventing a short circuit between the node contact pad and the buried word line.

[0023] In an exemplary embodiment, the bit line structure includes a self-bit line structure and a through-bit line structure, and the self-bit line structure and the through-bit line structure are disposed on the substrate at intervals.

[0024] In an exemplary embodiment, the self-bit line structure includes a self-word line and a self-word line isolation structure covering the self-word line, and the self-word line is in contact with the corresponding active area. In the semiconductor structure provided by the embodiment of the present disclosure, the BL is no longer electrically connected to the active area through the BLC, thereby avoiding the short circuit problem caused by the electrical connection between the bit line and the BLC in the bit line structure.

[0025] In an exemplary embodiment, the reference bit line structure includes a bit line and a bit line isolation structure covering the bit line, the bit line is located on the corresponding isolation structure; the first surface of the active area in contact with the self-word line is flush with the first surface of the isolation structure connected to the bit line. The semiconductor structure provided by the embodiment of the present disclosure omits the manufacturing process of BLC, simplifies the process flow and steps, and avoids the short circuit problem caused by the electrical connection between the bit line and the BLC in the bit line structure.

[0026] The disclosed embodiments also provide a method for preparing a semiconductor structure, comprising: providing a substrate, and forming an isolation structure and an active area between adjacent isolation structures in the substrate; forming a node contact pad between at least part of the isolation structure and the active area, and a side surface of the node contact pad is in contact with at least part of the side surface of the corresponding active area; forming a spaced-apart bit line structure on the substrate; forming a node contact structure between adjacent bit line structures, and a lower surface of the node contact structure is in at least part of contact with an upper surface of the node contact pad. The disclosed embodiments provide a method for preparing a semiconductor structure, by adding an NC AA Landing Pad between the isolation structure and the active area, which contacts at least part of the side surface of the corresponding active area, and the NC AA Landing Pad is in contact with the node contact structure NC thereon, thereby increasing the contact area between NC and AA, effectively avoiding the open circuit between NC and AA, thereby improving the reliability of the semiconductor structure and the product yield.

[0027] In an exemplary embodiment, a node contact pad is formed between at least a portion of an isolation structure and an active area, including: forming mask layers that are spaced apart on the active area and the isolation structure, and exposing at least a portion of the active area between adjacent mask layers; using the mask layer as a mask, removing a portion of the isolation structure adjacent to the at least partially exposed active area to form a node contact groove between the remaining isolation structure and the at least partially exposed active area; and forming the node contact pad in the node contact groove.

[0028] In an exemplary embodiment, a disposition position of the mask layer corresponds to a disposition position of the bit line structure, and a width of the mask layer is greater than a critical dimension of a bit line in the bit line structure.

[0029] In an exemplary embodiment, the node contact pad is formed in the node contact groove, including: filling the node contact groove with a first conductive material; removing a portion of the first conductive material in the node contact groove and a portion of the active area in contact with the first conductive material, and using the remaining first conductive material in the node contact groove as the node contact pad, the first surface of the node contact pad is flush with the first surface of the active area in contact with the node contact pad, and a groove is formed between adjacent isolation structures; removing the mask layer, and filling the groove with a protective structure.

[0030] In an exemplary embodiment, the active region in contact with the node contact pad is used as the first active region, the active region not in contact with the node contact pad is used as the second active region, the isolation structure with the node contact pad between the first active region is used as the first isolation structure, and the isolation structure between the two first active regions is used as the second isolation structure. Wherein, forming the spaced bit line structure on the first surface of the substrate includes: exposing the second active region and the second isolation structure and part of the first isolation structure; forming the spaced bit line structure on the second active region and the second isolation structure.

[0031] In an exemplary embodiment, removing the mask layer includes: forming a first protection layer on the node contact pad; removing the mask layer; and removing the first protection layer.

[0032] In an exemplary embodiment, filling the groove with a protective structure includes: forming a first isolation layer on the groove and the isolation structure; forming a second isolation layer on the first isolation layer; and removing a portion of the first isolation layer and a portion of the second isolation layer to form the protective structure in the groove.

[0033] In an exemplary embodiment, the bit line structure spaced apart is formed on the second active area and the second isolation structure, including: forming a second conductive material on the second active area, the second isolation structure and a portion of the first isolation structure; forming a bit line insulating protection layer on the second conductive material; graphing the second conductive material and the bit line insulating protection layer to form a bit line and a bit line protection layer on the second active area and the second isolation structure; and forming a bit line insulating layer covering the bit line, the bit line protection layer and the protection structure to form the bit line structure.

[0034] In an exemplary embodiment, the substrate further includes a word line and a word line insulating layer located on the word line. Wherein, forming a bit line insulating layer covering the bit line, the bit line protective layer and the protective structure includes: forming a bit line insulating layer covering the bit line, the bit line protective layer and the protective structure; forming a node contact patterning layer on the bit line insulating layer and the word line insulating layer; performing a patterning process on the node contact patterning layer to form a node contact dielectric line between the word line insulating layers; filling a second dielectric material between the node contact dielectric lines; removing the node contact patterning layer to form the bit line insulating layer, removing the node contact dielectric line to form a node contact line corresponding to the word line insulating layer using the second dielectric material. Wherein, when forming a node contact structure between adjacent bit line structures, it also includes: filling a second conductive material between the node contact lines to form the node contact structure. The second conductive material and the first conductive material can be the same, for example, both can be doped polysilicon, or they can be different, and the present disclosure does not limit this.

[0035] Combine the following Figures 19 to 38 The semiconductor structure and the manufacturing method thereof provided in the embodiments of the present disclosure are illustrated by way of example, but the present disclosure is not limited thereto.

[0036] like Fig.19 As shown in FIG. 1 , the semiconductor structure provided by the embodiment of the present disclosure includes a BL 31 extending along a first direction, a WL 32 extending along a second direction, and an AA 33 extending along a third direction. Fig.19 It can be seen that the semiconductor structure provided by the embodiment of the present disclosure does not include BLC.

[0037] Fig. 20 (a) is along Fig.19 BB′ in FIG. 1 , that is, a cross-sectional view parallel to NC and WL 32 and perpendicular to BL 31 . Fig. 20 (b) is along Fig.19 The cross-sectional view of AA' in FIG. 1 is a cross-sectional view perpendicular to NC and WL 32 and parallel to BL 31. Fig. 20 As shown in (a), an isolation structure 35a is formed in the substrate 34a, and the isolation structures 35a are arranged at intervals. The active area 36 in the substrate 34a is defined by adjacent isolation structures 35a. The first surface of the active area 36 is flush with the first surface of the isolation structure 35a. Here, the first surface is taken as the upper surface for illustration. Fig. 20(a), a mask layer 39a is formed on the active area 36 and the isolation structure 35a. In the embodiment of the present disclosure, the extension direction of the mask layer 39a is parallel to the extension direction of the BL 31. In an exemplary embodiment, the placement position of the mask layer 39a on the active area 36 and the isolation structure 35a completely overlaps or nearly completely overlaps with the BL formed in the subsequent process. In other embodiments, in order to form the NON structure of the subsequent BL, the width of the mask layer 39a is greater than the critical dimension (CD) of the BL. For example, the width of the mask layer 39a is greater than the BL CD by about 5nm, but the present disclosure is not limited to this and can be set according to actual needs. Among them, the width of the mask layer 39a refers to the size of the mask layer 39a along the extension direction of the WL. Fig. 20 (a) In the embodiment, the center of a portion of the mask layer 39a is aligned with the center of a portion of the active region 36, and the corresponding position of this portion of the mask layer 39a can be used to subsequently form a self BL. Optionally, this portion of the mask layer 39a also partially covers the partial upper surfaces of two adjacent isolation structures 35a of the active region 39a below it. The center of another portion of the mask layer 39a is aligned with the center of the portion of the isolation structure 35a, and the corresponding position of this portion of the mask layer 39a can be used to subsequently form a pass BL. Optionally, this another portion of the mask layer 39a also partially covers the partial upper surfaces of two adjacent active regions 39a of the isolation structure 35a below it, so as to expose a portion of the upper surface of the corresponding active region 39a. Exemplarily, the self BL and the pass BL can be arranged at intervals.

[0038] In an exemplary embodiment, the width of the mask layer 39a ranges from 15 to 25 nm, depending on the etching selectivity in the actual process. When the width of the mask layer 39a is smaller, the etching selectivity between the mask layer 39a and the isolation structure 35a is greater, and the process difficulty is greater; when the value of the mask layer 39a is larger, the cost of depositing the mask layer 39a is higher. The mask layer 39a with a width within this range can better balance the process difficulty and deposition cost.

[0039] like Fig. 20 As shown in (b), an isolation structure 35b is formed on the substrate 34b, and word lines 37 are formed in the isolation structure 35b. Here, the word lines are buried word lines (BW) for example. The upper surface of BW 37 is lower than the upper surface of the isolation structure 35b. A word line insulation layer 38 is formed on BW 37. The upper surface of the word line insulation layer 38 is flush with the upper surface of the isolation structure 35b. A mask layer 39b is formed on the isolation structure 35b and the word line insulation layer 38.

[0040] In the embodiment of the present disclosure, the substrates 34a and 34b may be silicon substrates, the isolation structures 35a and 35b may be silicon dioxide materials, the mask layers 39a and 39b may be silicon nitride materials, BW37 may be titanium nitride materials, and the word line insulation layer 38 may be silicon nitride materials, but the present disclosure is not limited to this and is only used for illustration here.

[0041] In the embodiment of the present disclosure, an etch-back process may be performed on the word line insulation layer 38 to form the word line insulation layer 38 flush with the upper surface of the isolation structure 35 b , but the present disclosure is not limited thereto.

[0042] like Fig.21 As shown in (a) and (b), with the mask layer as a mask, the word line insulation layer 38 and the mask layer intersect to form a node contact groove 310 corresponding to the NCAA Landing Pad, and the isolation structure 35a in the node contact groove 310 is removed. In the embodiment of the present disclosure, the partially removed isolation structure is referred to as the first isolation structure 351a, and the partially removed isolation structure is referred to as the second isolation structure 352a. The active area with a portion of the side surface exposed by the node contact groove 310 and a portion of the upper surface exposed by the mask layer is referred to as the first active area 361, and the active area completely covered by the mask layer is referred to as the second active area 362.

[0043] In an exemplary embodiment, the width of the node contact groove 310 is 3 to 5 nm, and the depth is 20 nm to 40 nm. When the width of the node contact groove 310 is within this range, the NC AA Landing Pad in the node contact groove 310 can have sufficient contact area with the NC, and the isolation performance of the STI will not be affected. When the depth of the node contact groove 310 is within this range, sufficient AA side area can be exposed to enhance the electrical connection between the NC and the AA, avoid open, and avoid the subsequent short circuit between the NC AA Landing Pad and the BW 37 in the node contact groove 310. Optionally, the depth of the node contact groove 310 is 20 nm. Depth refers to the dimension in the direction perpendicular to the upper surface of the substrate.

[0044] like Fig. 22 As shown in (a), the node contact groove 310 is filled with a first conductive material 311a, such as conductive poly, but the present disclosure is not limited thereto. The first conductive material is also filled between and on the mask layer 39a. Fig. 22 As shown in (a), a first conductive material 311b is deposited on the mask layer 39b.

[0045] like Fig.23As shown in (a), the first conductive material 311a and the first active region 361 in the node contact groove are partially removed to form a groove 312 between the adjacent first isolation structure 351a and the second isolation structure 352a. At this time, the remaining first conductive material 311a in the node contact groove forms a node contact pad 3111a. One side surface of the node contact pad 3111a is partially in contact with one side surface of the first isolation structure 351a, and the other opposite side surface of the node contact pad 3111a is partially in contact with one side surface of the first active region 361. The upper surface of the first active region 361 is flush with the upper surface of the node contact pad 3111a. At this time, the upper surface of the first active region 361 is lower than the upper surface of the second active region 362. In an exemplary embodiment, the first active region 361 and the first conductive material 311a in the node contact groove can be partially removed by an isotropic chemical etching process, but the present disclosure is not limited thereto. Specifically, microwaves can be used to dissociate HBr (hydrogen bromide), and the free radicals formed are then input into an etching chamber, namely, RSP (Remote Plasma Source) to perform chemical etching without physical damage. HBr etching has a higher selectivity ratio for poly relative oxides.

[0046] In the disclosed embodiment, the depth of the first conductive material 311a and the first active region 361 may be about half of the node contact groove 310, that is, the depth of the groove 312 may be 10nm to 20nm. The depth of the back etching may be controlled by controlling the etching time. The groove 312 formed by the back etching may provide a height difference between the formed node contact pad 3111a and the subsequently formed bit line, thereby preventing the polysilicon short circuit between the NC AA Landing Pad and the bit line.

[0047] The etching endpoint is to stop etching when it touches the side wall OXI Fig.23 (b) with Fig. 22 (b) The node contact pad formed by the first conductive material contacts the first active region, which can expand the contact area between AA and NC and avoid disconnection between NC and AA in subsequent processes.

[0048] In the disclosed embodiment, the node contact pad 3111 a has a depth ranging from 5 to 15 nm, and a width ranging from 3 to 5 nm.

[0049] like Fig.24(a) and 24 (b), the mask layers 39a and 39b are removed respectively. In the embodiment of the present disclosure, the mask layer can be removed by a CMP (Chemical Mechanical Polishing) mask process or an etching process, but the present disclosure is not limited to this. For example, before removing the mask layers 39a and 39b, a first protective layer (not shown in the figure) can be formed in the groove on the node contact pad 3111a. For example, SOC (Spin on Carbon) coating can be performed to form a first protective layer, but the present disclosure is not limited to this. In this way, the groove and the node contact pad can be protected to prevent the groove from being blocked during the removal of the mask layer, and at the same time, damage to the node contact pad 3111a can be avoided when removing the mask layer. After removing the mask layer, the first protective layer can be removed again.

[0050] like Fig.25 As shown in (a), a first isolation layer is stacked in sequence on the first active region 361, the second active region 362, the first isolation structure 351a, the second isolation structure 352a, and the node contact pad 3111a, wherein the first isolation layer can be a single layer of insulating material or a combination of multiple layers of stacked materials, which is not limited in the present disclosure. Here, the first isolation layer includes a stacked first oxide layer 313a and a first nitride layer 314a for illustration. Fig.25 As shown in (b), a first oxide layer 313b and a first nitride layer 314b are sequentially stacked on the isolation structure 35b and the word line insulation layer 38. In an exemplary embodiment, the first nitride layer may be, for example, silicon dioxide, and the first nitride layer may be, for example, silicon nitride, but the present disclosure is not limited thereto and is only used for illustration. The first oxide layer and the first nitride layer may be used to isolate the NC AA and the BL AA in subsequent processes, wherein the NC AA refers to an active area electrically connected to the NC, and the BL AA refers to an active area electrically connected to the BL.

[0051] like Fig.26 As shown in (a), a second isolation layer 315a is deposited on the first isolation layer, for example, the first nitride layer 314a in the first isolation layer. Fig.26 As shown in (b), a second isolation layer 315b is deposited on the first isolation layer, for example, the first nitride layer 314b in the first isolation layer. In the embodiment of the present disclosure, the second isolation layer may be made of SOH, for example, SOC, but the present disclosure is not limited thereto.

[0052] like Fig. 27 As shown in (a), a portion of the second isolation layer 315a is removed, and the upper surface of the remaining second isolation layer 3151a is flush with the upper surface of the second active region 362. Fig. 27 As shown in (b), the second isolation layer 315b is removed.

[0053] like Fig.28 As shown in (a), the remaining second isolation layer 3151a is used as the etching end point, and part of the first isolation layer is removed, for example, part of the first oxide layer 313a and part of the first nitride layer 314a are removed to form a protection structure located in the groove, the protection structure includes the remaining second isolation layer 3151a and the remaining first nitride layer 3141a, the remaining first oxide layer 3131a, and the second active area 362, the first isolation structure 351a, the second isolation structure 352a and the upper surface of the protection structure are exposed, and the exposed second active area 362 can be used to form a self BL in contact with the active area in subsequent processes. That is, the second isolation layer can be used to remove the first oxide layer and the first nitride layer on the AA connected to the self BL to improve the electrical connection reliability between the self BL and the AA. As shown in FIG. Fig.28 As shown in (b), the first oxide layer 313b and the first nitride layer 314b are removed.

[0054] like Fig.29 As shown in (a), a second conductive material 316a is deposited on the upper surfaces of the second active region 362, the first isolation structure 351a, the second isolation structure 352a and the protection structure. Fig.29 As shown in (b), a second conductive material 316b is deposited on the isolation structure 35b and the word line insulating layer 38. The second conductive material may be, for example, polysilicon, but the present disclosure is not limited thereto. The second conductive material may be used to form a BL later. After the second conductive material is deposited, the power function and the turn-on voltage may be adjusted by ion implantation (Implant, IMP). The bandgap width of polysilicon may be adjusted by ion implantation, and different turn-on voltages may be set according to different CMOS requirements.

[0055] like Fig.30 As shown in (a) and 30(b), metal layers 317a and 317b (for example, W, but only for illustration) are deposited on the second conductive material, and a bit line insulating protection layer is formed on the metal layer. The bit line insulating protection layer may include, for example, a second nitride layer 318a and 318b, a first hard mask layer 319a and 319b, a first silicon oxynitride layer 320a and 320b, a second hard mask layer 321a and 321b, a second silicon oxynitride layer 322a and 322b, and a first photoresist layer 323a and 323b stacked in sequence, but the present disclosure is not limited thereto. The first hard mask layer may be, for example, an ACL layer, and the second hard mask layer may be a SOH layer, but the present disclosure is not limited thereto. In the embodiment of the present disclosure, the first photoresist layer 323a is patterned for patterning to form a BL pattern, and to form a pattern such as Fig.31(a) shows a BL and a BL protection layer, wherein the BL includes the remaining second conductive material 3161a and the remaining metal layer 3171a after the patterning process, and the BL protection layer includes the remaining second nitride layer 3181a after the patterning process. Fig.31 As shown in (b), the second conductive material 316b, the metal layer 317b, the second nitride layer 318b, the first hard mask layer 319b, the first silicon oxynitride layer 320b, the second hard mask layer 321b, the second silicon oxynitride layer 322b and the first photoresist layer 323b are removed.

[0056] like Fig.32 As shown in (a), a bit line insulating layer 324a is deposited, and the bit line insulating layer 324a covers the sidewalls of the BL, the sidewalls and the upper surface of the BL protection layer, and the upper surface of the protection structure and the first isolation structure 351a. The bit line insulating layer 324a may include silicon nitride, or include silicon nitride and silicon dioxide to form a NON structure to protect the BL, which is not limited in the present disclosure. Fig.32 As shown in FIG. 5( b ), a bit line insulating layer 324 b is deposited on the isolation structure 35 b and the word line insulating layer 38 .

[0057] A node contact patterning layer is formed on the bit line insulating layer. Fig.33 As shown in (a) and 33 (b), the node contact patterning layer may include a second oxide layer 325a and 325b, a third hard mask layer 326a and 326b, a third silicon oxynitride layer 327a and 327b, a fourth hard mask layer 328a and 328b, a fourth silicon oxynitride layer 329a and 329b, and a second photoresist layer 330a and 330b, which are stacked in sequence. The third hard mask layer may be, for example, an ACL layer, and the fourth hard mask layer may be a SOH layer, but the present disclosure is not limited thereto. The second photoresist layer 330b is patterned to perform a patterning process to form an NC pattern, and the remaining second oxide layer 325b is used to form a Fig.34 (b) shows a node contacting dielectric line 3251b. Fig.34 As shown in (a), the third hard mask layer 326a, the third silicon oxynitride layer 327a, the fourth hard mask layer 328a, the fourth silicon oxynitride layer 329a, and the second photoresist layer 330a are removed.

[0058] like Fig.35 As shown in (b), a second dielectric material is deposited between the node contact dielectric lines 3251b, and then the node contact dielectric lines 3251b are removed to form the second dielectric material into a node contact line (NC line) 331. The second dielectric material may be, for example, silicon nitride, but the present disclosure is not limited thereto. Fig.35 As shown in (a), the second oxide layer 325a is removed.

[0059] like Fig.36 As shown in (a), the protection structure at the NC AA Landing Pad position is removed, the remaining bit line insulation layer 324a is represented as 3241a, and the remaining first nitride layer 3141a is represented as 3142a. Fig.36 As shown in (b), the bit line insulating layer 324b is removed.

[0060] like Fig.37 As shown, a first conductive material such as conductive poly is deposited between the groove and the adjacent bit line structure to form a node contact structure 332a. Fig.38 As shown, the first conductive material is filled between adjacent NC lines 331 to form NC 332b. In the disclosed embodiment, since the manufacturing process of BLC is omitted, since BLC needs to dig holes and fill poly, when poly is etched in the holes to form BLC, poly residue is likely to occur, which can easily lead to a short circuit between BLC and NC. In the disclosed embodiment, BL is formed on the same horizontal plane, so when the poly of BL is etched to form BL, it can be etched more cleanly without poly residue, so that no short circuit will occur between BL and NC.

[0061] In the disclosed embodiment, a NC AA Landing Pad is formed by using a BW insulating layer and a mask layer parallel to the BL direction. On the one hand, the contact area between NC and AA is expanded through the NC AA Landing Pad, thereby connecting NC and avoiding NC and AA open. On the other hand, it does not belong to the preparation of BLC, can solve the problem of NC and BLC short, improve the NC AA process window, and improve the chip yield. The preparation method and semiconductor structure provided in the disclosed embodiment can be applied to dynamic random access memory DRAM, but are not limited to this.

[0062] Furthermore, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, comprising: providing a substrate, the substrate forming an array-arranged active area and an isolation structure between the active areas, the active area including a node contact area and a bit line contact area; forming a node contact pad in the isolation structure corresponding to the node contact area, the node contact pad being in contact with the node contact area; and forming a bit line structure in the bit line contact area.

[0063] In an exemplary embodiment, a node contact pad is formed in the isolation structure corresponding to the node contact area, including: forming a mask layer on the surface of the substrate to expose a portion of the node contact area and a portion of the isolation structure corresponding to the node contact area; etching the partially exposed isolation structure to form a node contact groove; filling the node contact groove with a first conductive material; etching back the partially exposed node contact area and the first conductive material to form a groove, and the remaining portion of the first conductive material forms the node contact pad.

[0064] In an exemplary embodiment, the method further includes forming a protection structure in the groove.

[0065] In an exemplary embodiment, forming a node contact structure on the node contact pad and the node contact area includes: after forming the bit line structure in the bit line contact area, removing the protection structure; forming a node contact structure, wherein the node contact structure is at least partially formed in the groove.

[0066] In an exemplary embodiment, the method further includes: forming a node contact structure on the node contact pad and the node contact region.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate includes an isolation structure and an active region located between adjacent isolation structures; Bit line structures are arranged at intervals on the substrate; A node contact pad, wherein the node contact pad is located between the isolation structure and the active region between adjacent bit line structures, and a side surface of the node contact pad contacts at least a portion of a side surface of the corresponding active region; A node contact structure is located between adjacent bit line structures, wherein a lower surface of the node contact structure at least partially contacts an upper surface of the node contact pad.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: A node contact trench is formed between adjacent isolation structures and active regions, and the node contact pad is disposed in the node contact trench.

3. The semiconductor structure according to claim 1, characterized in that: Also includes: A groove is located between adjacent isolation structures, and the node contact structure is at least partially disposed in the groove.

4. The semiconductor structure according to claim 1, characterized in that The node contact pad has a depth of 5 to 15 nm and a width of 3 to 5 nm.

5. The semiconductor structure according to claim 1, characterized in that: The bit line structure includes a self-bit line structure and a passing bit line structure, and the self-bit line structure and the passing bit line structure are arranged on the substrate at intervals; The self-bit line structure includes a self-bit line and a self-bit line isolation structure covering the self-bit line, and the self-bit line is in contact with the corresponding active area; The bit line structure includes a bit line and a bit line isolation structure covering the bit line, and the bit line is located on the corresponding isolation structure; A first surface of the active region in contact with the self-bit line is flush with a first surface of the isolation structure in contact with the through-bit line.

6. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and forming isolation structures and active regions located between adjacent isolation structures in the substrate; forming a node contact pad between at least a portion of the isolation structure and the active region, wherein a side surface of the node contact pad contacts at least a portion of a side surface of the corresponding active region; forming spaced-apart bit line structures on the substrate; A node contact structure is formed between adjacent bit line structures, and a lower surface of the node contact structure is at least partially in contact with an upper surface of the node contact pad.

7. The preparation method according to claim 6, characterized in that: Forming a node contact pad between at least a portion of the isolation structure and the active region, comprising: Forming mask layers spaced apart on the active area and the isolation structure, with at least a portion of the active area exposed between adjacent mask layers; Using the mask layer as a mask, removing a portion of the isolation structure adjacent to the at least partially exposed active region to form a node contact trench between the remaining isolation structure and the at least partially exposed active region; The node contact pad is formed in the node contact trench.

8. The preparation method according to claim 7, characterized in that: The mask layer is disposed at a position corresponding to the bit line structure, and the mask layer has a width greater than a critical dimension of the bit line in the bit line structure.

9. The preparation method according to claim 7, characterized in that: Forming the node contact pad in the node contact groove comprises: filling a first conductive material in the node contact trench; removing a portion of the first conductive material in the node contact groove and a portion of the active area in contact with the first conductive material, and using the remaining first conductive material in the node contact groove as the node contact pad, wherein the first surface of the node contact pad is flush with the first surface of the active area in contact with the node contact pad, and forming a groove between adjacent isolation structures; The mask layer is removed, and a protection structure is filled in the groove.

10. The preparation method according to claim 9, characterized in that: Filling the groove with a protective structure, including: forming a first isolation layer on the groove and the isolation structure; forming a second isolation layer on the first isolation layer; A portion of the first isolation layer and a portion of the second isolation layer are removed to form the protection structure in the groove.

11. The preparation method according to claim 9, characterized in that: The active region in contact with the node contact pad is used as the first active region, the active region not in contact with the node contact pad is used as the second active region, the isolation structure with the node contact pad between the first active region is used as the first isolation structure, and the isolation structure between the two first active regions is used as the second isolation structure; Wherein, the bit line structures arranged at intervals are formed on the substrate, including: exposing the second active region, the second isolation structure, and a portion of the first isolation structure; The bit line structures are formed on the second active region and the second isolation structure so as to be spaced apart from each other.

12. The preparation method according to claim 11, characterized in that: The bit line structure is formed on the second active region and the second isolation structure and is spaced apart from each other, comprising: forming a second conductive material on the second active region, the second isolation structure and a portion of the first isolation structure; forming a bit line insulating protection layer on the second conductive material; Performing a patterning process on the second conductive material and the bit line insulating protection layer to form a bit line and a bit line protection layer on the second active region and the second isolation structure; A bit line insulating layer is formed covering the bit line, the bit line protection layer and the protection structure to form the bit line structure.

13. The preparation method according to claim 12, characterized in that: The substrate also includes a word line and a word line insulating layer located on the word line; The step of forming a bit line insulating layer covering the bit line, the bit line protection layer and the protection structure comprises: forming a bit line insulating layer covering the bit line, the bit line protection layer and the protection structure; forming a node contact patterning layer on the bit line insulating layer and the word line insulating layer; Performing a patterning process on the node contact patterning layer to form a node contact dielectric line between the word line insulating layers; Filling a second dielectric material between the node contact dielectric lines; removing the node contact patterned layer to form the bit line insulating layer, removing the node contact dielectric line to form a node contact line corresponding to the word line insulating layer using the second dielectric material; Wherein, when forming a node contact structure between adjacent bit line structures, the method further includes: A second conductive material is filled between the node contact lines to form the node contact structure.

14. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate is formed with active areas arranged in an array and isolation structures between the active areas, wherein the active areas include node contact areas and bit line contact areas; forming a node contact pad in the isolation structure corresponding to the node contact region, the node contact pad being in contact with the node contact region; A bit line structure is formed in the bit line contact region.

15. The preparation method according to claim 14, characterized in that: Forming a node contact pad in the isolation structure corresponding to the node contact area includes: forming a mask layer on the surface of the substrate to expose a portion of the node contact area and a portion of the isolation structure corresponding to the node contact area; Etching the exposed portion of the isolation structure to form a node contact groove; filling a first conductive material in the node contact trench; The exposed portion of the node contact area and the first conductive material is etched back to form a groove, and the remaining portion of the first conductive material forms the node contact pad.

16. The preparation method according to claim 15, characterized in that: Also includes: A protection structure is formed in the groove.

17. The preparation method according to claim 16, characterized in that: A node contact structure is formed on the node contact pad and the node contact region, comprising: After forming the bit line structure in the bit line contact region, removing the protection structure; A node contact structure is formed, the node contact structure being at least partially formed in the recess.

18. The preparation method according to claim 14, characterized in that: Also includes: A node contact structure is formed on the node contact pad and the node contact region.

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