Memory and its fabrication method, electronic device

Abstract

This application relates to a memory and its fabrication method, as well as an electronic device. The fabrication method includes: providing a substrate; forming a stacked structure on the upper surface of the substrate, the stacked structure including multiple first stacked structures spaced apart along a first direction and a second direction, each first stacked structure including a sacrificial layer and a conductive layer alternately stacked from bottom to top; the first direction and the second direction are both parallel to the substrate and intersect each other; etching each conductive layer within the first stacked structure to partially remove each conductive layer, forming a first gap; forming a first electrode within the first gap, the first electrode covering the surface of the first gap; forming a capacitor dielectric layer, the capacitor dielectric layer at least covering the surface of the first electrode; and forming a second electrode on the surface of the capacitor dielectric layer. This fabrication method can increase the capacitor area and thus increase the capacitor capacity, and can reduce the work function of the metal and the contact resistance, thereby improving the performance of the memory.

Description

Technical Field

[0001] This application relates to the semiconductor field, and in particular to a memory and its fabrication method, and an electronic device. Background Technology

[0002] Three-dimensional dynamic random access memory (3D-DRAM) offers higher integration density and larger storage capacity, and has gradually become one of the important research directions in memory technology. A typical 3D-DRAM usually includes transistors, word lines, bit lines, and capacitors. The capacitor is generally fabricated as follows: First, the insulating dielectric layer in a stacked structure consisting of alternating insulating dielectric layers and metal layers (from bottom to top) is etched away to form gaps; a capacitor dielectric layer and a top electrode are formed within these gaps; the metal layer in the stacked structure serves as the bottom electrode of the capacitor. The channel layer of the transistor in the 3D-DRAM is in contact with the metal layer in the stacked structure. Since the metal layer in the stacked structure is retained as the bottom electrode in the capacitor, the area S of the formed capacitor plate is the outer surface of the metal layer (C = εS / d), and the plate area is limited by the length and thickness of the metal layer. Furthermore, during the formation of trenches for transistor fabrication, the metal layer in the stacked structure that contacts the channel layer of the transistor will be oxidized. This will inevitably lead to an increase in the work function of the metal, which in turn will increase the contact resistance between the transistor and the capacitor, thus affecting the performance of the three-dimensional dynamic random access memory. Summary of the Invention

[0003] Therefore, it is necessary to provide a memory and its fabrication method, as well as an electronic device, to address the aforementioned technical problems. This method can increase the capacitor area, thereby increasing the capacitor capacity, and can also reduce the metal work function and contact resistance, thereby effectively improving the performance of the memory.

[0004] On the one hand, some embodiments of this application provide a method for fabricating a memory, including the following steps.

[0005] Provide substrate;

[0006] A stacked structure is formed on the upper surface of the substrate. The stacked structure includes a plurality of first stacked structures arranged at intervals along a first direction and a second direction. Each first stacked structure includes a sacrificial layer and a conductive layer that are alternately stacked from bottom to top. The first direction and the second direction are both parallel to the substrate and intersect each other.

[0007] Etch each conductive layer within the first stacked structure to partially remove each conductive layer, thereby forming the first gap;

[0008] A first electrode is formed within a first gap, and the first electrode covers the surface of the first gap;

[0009] A capacitor dielectric layer is formed, which at least covers the surface of the first electrode;

[0010] A second electrode is formed on the surface of the capacitor dielectric layer.

[0011] In this embodiment, a first stacked structure consisting of alternating layers of sacrificial and conductive layers is first formed. Then, a first spacer is formed by partially etching each conductive layer within the first stacked structure. Next, a capacitor comprising a first electrode, a dielectric layer, and a second electrode is formed within the first spacer. The first electrode also conformally covers the surface of the first spacer. Compared to electrode structures in related technologies that fill the entire space, the first electrode obtained in this application can have a larger surface area, thereby effectively increasing the capacitance per unit substrate area.

[0012] In some embodiments, forming a first electrode within the first gap includes: forming a first electrode conformally covering the surface of the first gap using an atomic layer deposition process; wherein the material of the first electrode includes one of titanium nitride, tantalum nitride, and molybdenum nitride.

[0013] In this embodiment, atomic layer deposition (ALD) can be used to obtain a first electrode with uniform thickness on the surface of the first gap, thereby ensuring the electrical performance of the first electrode. Furthermore, the material of the first electrode can include metal nitrides such as titanium nitride, tantalum nitride, and molybdenum nitride, effectively preventing accidental oxidation in subsequent processes. Thus, in embodiments where the first electrode needs to be electrically connected to other devices (e.g., transistors) to form a complete memory, the work function and contact resistance can be effectively reduced, further improving the electrical performance of the obtained memory.

[0014] In some embodiments, after forming a stacked structure on the upper surface of the substrate and before etching each conductive layer within the first stacked structure, the fabrication method further includes the following steps.

[0015] A release hole is formed within the first stacked structure, and the release hole penetrates the first stacked structure along the thickness direction;

[0016] Etching each conductive layer within the first stacked structure includes: etching each conductive layer within the first stacked structure based on release holes.

[0017] In some embodiments, after forming the first electrode within the first gap and before forming the capacitor dielectric layer, the fabrication method further includes the following steps.

[0018] Each sacrificial layer within the first stacked structure is etched to partially remove each sacrificial layer, thereby forming a second gap; the length of the second gap along the first direction is less than the length of the first gap along the first direction.

[0019] Forming a capacitor dielectric layer includes: forming a capacitor dielectric layer at least within a release hole, a first gap, and a second gap, wherein the capacitor dielectric layer at least covers the surface of the first electrode, the inner wall of the release hole, and the surface of the second gap.

[0020] In this embodiment, after the first gap is formed, the sacrificial layers in the first stacked structure are etched to form the second gap; this allows the capacitor dielectric layer and the second electrode to cover the second gap, further increasing the capacitor area and thus improving the charge storage capacity of the capacitor.

[0021] In some embodiments, after forming a second electrode on the surface of the capacitor dielectric layer, the preparation method further includes: forming an electrode connection layer on the surface of the second electrode, wherein the electrode connection layer fills the release hole, the first gap, and the second gap.

[0022] In some embodiments, the stacked structure further includes: a second stacked structure extending along a second direction, the second stacked structure including sacrificial layers and conductive layers alternately stacked from bottom to top; the conductive layers in the second stacked structure serve as bit lines, and the sacrificial layers in the second stacked structure serve as bit line isolation layers for adjacent bit lines; and first stacked structures arranged at intervals along a first direction are located on opposite sides of the second stacked structure.

[0023] In some embodiments, the capacitor dielectric layer, the second electrode, and the electrode connection layer are further located on the stacked structure; the first electrode, the capacitor dielectric layer, and the second electrode constitute a capacitor; after the electrode connection layer is formed on the surface of the second electrode, the preparation method further includes the following steps.

[0024] A covering dielectric layer is formed on the upper surface of the electrode connection layer;

[0025] An isolation trench is formed, which penetrates and covers the dielectric layer, electrode connection layer, second electrode and capacitor dielectric layer along the thickness direction; the orthographic projection of the isolation trench on the upper surface of the stacked structure covers the second stacked structure;

[0026] An isolation layer is formed within the isolation groove, which insulates and isolates the capacitors on opposite sides of the second stack structure; multiple capacitors located on the same side of the second stack structure share the second electrode.

[0027] In some embodiments, the fabrication method further includes: forming a plurality of transistors within a first stacked structure, wherein the transistors are connected to a first electrode and a bit line located on the same layer.

[0028] In some embodiments, forming a plurality of transistors within the first stacked structure includes the following steps.

[0029] Multiple first through holes are formed within the first stacked structure. The first through holes are located between the capacitor and the second stacked structure and penetrate the isolation layer and the first stacked structure along the thickness direction.

[0030] The conductive layer retained in the first stacked structure is removed based on the first via to obtain the second via;

[0031] A channel layer is formed at least on the sidewall and bottom of the second via, and the channel layer is in contact with the first electrode and bit line located in the same layer;

[0032] A gate dielectric layer is formed on the surface of the channel layer;

[0033] A gate conductive layer is formed on the surface of the gate dielectric layer; the gate conductive layer also serves as a word line.

[0034] In this embodiment, a plurality of first vias are first formed in the first stacked structure, and the conductive layer retained in the first stacked structure is removed based on the first vias to obtain second vias; then a channel layer, a gate dielectric layer and a gate conductive layer are sequentially formed in the first vias and the second vias to form a transistor, so that the channel layer is in direct contact with the first electrode and bit line located on the same layer, thereby ensuring a reduction in work function and contact resistance.

[0035] In some embodiments, after forming a stacked structure on the upper surface of the substrate and before etching each of the conductive layers within the first stacked structure, the fabrication method further includes: forming a filling dielectric layer that fills the gap between adjacent first stacked structures and covers the upper surface of the stacked structure.

[0036] On the other hand, some embodiments of this application provide a memory as a practical application of the memory fabrication methods described in the foregoing embodiments. This memory also possesses all the technical advantages of the memory fabrication methods described in the foregoing embodiments, and will not be detailed here.

[0037] In some embodiments, the memory includes: a substrate and a plurality of memory cell stacked structures; wherein the plurality of memory cell stacked structures are arranged at intervals along a first direction and a second direction; each memory cell stacked structure includes a capacitor and a plurality of first gaps arranged at intervals from bottom to top; the capacitor includes a first electrode, a capacitor dielectric layer and a second electrode, the first electrode at least covering the surface of the first gap; the capacitor dielectric layer covers the surface of the first electrode, and the second electrode covers the surface of the capacitor dielectric layer; the first direction and the second direction are both parallel to the substrate and intersect each other.

[0038] In some embodiments, the storage cell stack structure further includes: a sacrificial layer, in which a second gap is formed; the sacrificial layer and the second gap are arranged alternately with the first gap from bottom to top; the length of the second gap along the first direction is less than the length of the first gap along the first direction.

[0039] Correspondingly, the memory also includes: a release hole that penetrates the memory cell stack structure along the thickness direction and is connected to both the first gap and the second gap; the capacitor dielectric layer also covers the surface of the release hole and the surface of the second gap.

[0040] In some embodiments, the memory further includes an electrode connection layer located on the surface of the second electrode and filling the release hole, the first gap, and the second gap.

[0041] In some embodiments, the memory further includes: a bit line stack structure and a plurality of transistors, wherein the bit line stack structure extends along a second direction and includes bit line isolation layers and bit lines alternately stacked from bottom to top; memory cell stack structures arranged at intervals along a first direction are located on opposite sides of the bit line stack structure; the plurality of transistors are located on opposite sides of the bit line stack structure, penetrate the memory cell stack structure along the thickness direction, and are connected to the first electrode and bit lines located on the same layer.

[0042] In some embodiments, the capacitor dielectric layer, the second electrode, and the electrode connection layer are also located on the memory cell stack structure and the bit line stack structure; the memory further includes: a cover dielectric layer, an isolation trench, and an isolation layer, wherein the cover dielectric layer is located on the upper surface of the electrode connection layer; the isolation trench penetrates the cover dielectric layer, the electrode connection layer, the second electrode, and the capacitor dielectric layer along the thickness direction; the orthographic projection of the isolation trench onto the upper surface of the stack structure covers the second stack structure; the isolation layer is located within the isolation trench, and the isolation layer insulates and isolates the capacitors on opposite sides of the bit line stack structure; multiple capacitors located on the same side of the bit line stack structure share the second electrode.

[0043] On the other hand, some embodiments of this application provide an electronic device including the memory described in the foregoing embodiments. The electronic device also possesses the technical advantages of the memory described in the foregoing embodiments, and will not be detailed here. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1This is a schematic diagram of the structure of a memory provided in some embodiments;

[0046] Figure 2 For along Figure 1 A cross-sectional view along the AA direction;

[0047] Figure 3 For along Figure 1 Cross-sectional view along the BB direction;

[0048] Figure 4 For along Figure 1 A cross-sectional view along the CC direction;

[0049] Figure 5 For along Figure 1 A cross-sectional view along the DD direction;

[0050] Figure 6 For along Figure 1 A cross-sectional view along the EE direction;

[0051] Figure 7 For along Figure 1 A cross-sectional view along the FF direction;

[0052] Figure 8 This is a schematic flowchart of a method for fabricating a memory provided in some embodiments;

[0053] Figure 9 This is a flowchart illustrating another method for fabricating a memory provided in some embodiments;

[0054] Figure 10 This is a flowchart illustrating yet another method for fabricating a memory provided in some embodiments;

[0055] Figure 11 This is a flowchart illustrating one step S1100 provided in some embodiments;

[0056] Figure 12 This is a schematic diagram of a structure obtained after forming an initial stacked structure, provided in some embodiments;

[0057] Figure 13 This is a top view of the structure obtained after performing step S200, as provided in some embodiments.

[0058] Figure 14 For along Figure 13 A cross-sectional view along the AA direction;

[0059] Figure 15 For along Figure 13 Cross-sectional view along the BB direction;

[0060] Figure 16 For along Figure 13 A cross-sectional view along the CC direction;

[0061] Figure 17 This is a top view of the structure obtained after performing step S250, as provided in some embodiments.

[0062] Figure 18 For along Figure 17 A cross-sectional view along the AA direction;

[0063] Figure 19 For along Figure 17 Cross-sectional view along the BB direction;

[0064] Figure 20 For along Figure 17 A cross-sectional view along the CC direction;

[0065] Figure 21 This is a top view of the structure obtained after performing step S260, as provided in some embodiments.

[0066] Figure 22 For along Figure 21 A cross-sectional view along the AA direction;

[0067] Figure 23 The structure obtained after performing step S300 in some embodiments is provided along... Figure 21 A cross-sectional view along the AA direction;

[0068] Figure 24 The structure obtained after performing step S300 in some embodiments is provided along... Figure 21 A cross-sectional view along the CC direction;

[0069] Figure 25 In some embodiments, a structure obtained after performing step S400 is provided along... Figure 21 A cross-sectional view along the AA direction;

[0070] Figure 26 In some embodiments, a structure obtained after performing step S400 is provided along... Figure 21 A cross-sectional view along the CC direction;

[0071] Figure 27 In some embodiments, a structure obtained after performing step S450 is provided along... Figure 21 A cross-sectional view along the AA direction;

[0072] Figure 28 In some embodiments, a structure obtained after performing step S450 is provided along... Figure 21 A cross-sectional view along the CC direction;

[0073] Figure 29 In some embodiments, a structure obtained after executing step S500 is provided along... Figure 21 A cross-sectional view along the AA direction;

[0074] Figure 30 In some embodiments, a structure obtained after executing step S500 is provided along... Figure 21 A cross-sectional view along the CC direction;

[0075] Figure 31 In some embodiments, a structure obtained after performing step S600 is provided along... Figure 21 A cross-sectional view along the AA direction;

[0076] Figure 32 In some embodiments, a structure obtained after performing step S600 is provided along... Figure 21 A cross-sectional view along the CC direction;

[0077] Figure 33 In some embodiments, a structure obtained after performing step S700 is provided along... Figure 21 A cross-sectional view along the AA direction;

[0078] Figure 34 In some embodiments, a structure obtained after performing step S700 is provided along... Figure 21 A cross-sectional view along the CC direction;

[0079] Figure 35 The structure obtained after performing step S800 in some embodiments is provided along... Figure 21 A cross-sectional view along the AA direction;

[0080] Figure 36 The structure obtained after performing step S800 in some embodiments is provided along... Figure 21 A cross-sectional view along the CC direction;

[0081] Figure 37 The structure obtained after performing step S900 in some embodiments is provided along... Figure 21 A cross-sectional view along the AA direction;

[0082] Figure 38 The structure obtained after performing step S900 in some embodiments is provided along... Figure 21 A cross-sectional view along the CC direction;

[0083] Figure 39 The structure obtained after performing step S1000 in some embodiments is provided along... Figure 21 A cross-sectional view along the AA direction;

[0084] Figure 40 The structure obtained after performing step S1000 in some embodiments is provided along... Figure 21 A cross-sectional view along the CC direction;

[0085] Figure 41 This is a top view of the structure obtained after performing step S1101 in some embodiments;

[0086] Figure 42 For along Figure 41 A cross-sectional view along the AA direction;

[0087] Figure 43 For along Figure 41 A cross-sectional view along the EE direction;

[0088] Figure 44 The structure obtained after performing step S1102 in some embodiments is provided along... Figure 41 A cross-sectional view along the AA direction;

[0089] Figure 45 In some embodiments, a structure obtained after performing step S1102 is provided along... Figure 41 A cross-sectional view along the EE direction;

[0090] Figure 46 The structure obtained after performing step S1103 in some embodiments is provided along... Figure 41 A cross-sectional view along the AA direction;

[0091] Figure 47 The structure obtained after performing step S1103 in some embodiments is provided along... Figure 41 A cross-sectional view along the EE direction;

[0092] Figure 48 In some embodiments, a structure obtained after performing step S1104 is provided along... Figure 41 A cross-sectional view along the AA direction;

[0093] Figure 49 In some embodiments, a structure obtained after performing step S1104 is provided along... Figure 41 A cross-sectional view along the EE direction;

[0094] Figure 50 In some embodiments, a structure obtained after performing step S1105 is provided along... Figure 41 A cross-sectional view along the AA direction;

[0095] Figure 51In some embodiments, a structure obtained after performing step S1105 is provided along... Figure 41 A cross-sectional view along the EE direction;

[0096] Figure 52 In some embodiments, a structure obtained after performing a flattening process is provided along... Figure 41 A cross-sectional view along the AA direction.

[0097] Explanation of reference numerals in the attached figures:

[0098] 10-Substrate, 20-Memory cell stacked structure, 30-Capacitor, 31-First electrode, 32-Capacitor dielectric layer, 33-Second electrode, 40-Stacked structure, 40A-First stacked structure, 40B-Second stacked structure, 41-Sacrificial layer, 42-Conductive layer, 50-Electrode connection layer, 60-Bit line stacked structure, 61-Bit line isolation layer, 62-Bit line, 70-Transistor, 71-Channel layer, 72-Gate dielectric layer, 73-Gate conductive layer, 80-Fill dielectric layer, 90-Cover dielectric layer, 100-Isolation layer, G1-First gap, G2-Second gap, G3-Isolation trench, H1-Release hole, H2-First via, H3-Second via. Detailed Implementation

[0099] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0100] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0101] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is transmission of electrical signals or data between the connected objects.

[0102] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0103] Three-dimensional dynamic random access memory (3D-DRAM) offers higher integration density and larger storage capacity, and has gradually become one of the important research directions in memory technology. A typical 3D-DRAM usually includes transistors, word lines, bit lines, and capacitors. The capacitor is generally fabricated as follows: First, the insulating dielectric layer in a stacked structure consisting of alternating insulating dielectric layers and metal layers (from bottom to top) is etched away to form gaps; a capacitor dielectric layer and a top electrode are formed within these gaps; the metal layer in the stacked structure serves as the bottom electrode of the capacitor, and the capacitor's area is only the surface area of ​​the metal layer. The channel layer of the transistor in the 3D-DRAM is in contact with the metal layer in the stacked structure. Since the metal layer in the stacked structure is retained as the bottom electrode in the capacitor, the area S of the formed capacitor plate is the outer surface of the metal layer (C = εS / d), and the plate area is limited by the length and thickness of the metal layer. Furthermore, during the formation of trenches for transistor fabrication, the metal layer in the stacked structure that contacts the channel layer of the transistor will be oxidized. This will inevitably lead to an increase in the work function of the metal, which in turn will increase the contact resistance between the transistor and the capacitor, thus affecting the performance of the three-dimensional dynamic random access memory.

[0104] Please see Figures 1 to 7 Understood, in some embodiments, a memory is provided. The memory includes: a substrate 10 and a plurality of memory cell stack structures 20; wherein the plurality of memory cell stack structures 20 are arranged at intervals along a first direction and a second direction; each memory cell stack structure 20 includes a plurality of first gaps G1 and a capacitor 30 arranged at intervals from bottom to top; the capacitor 30 includes a first electrode 31, a capacitor dielectric layer 32 and a second electrode 33, the first electrode 31 at least covering the surface of the first gap G1; the material of the first electrode 31 includes a metal nitride; the capacitor dielectric layer 32 covers the surface of the first electrode 31, and the second electrode 33 covers the surface of the capacitor dielectric layer 32; the first direction and the second direction are both parallel to the substrate 10 and intersect each other.

[0105] For example, substrate 10 may be composed of any combination of semiconductor materials, insulating materials, conductive materials, or such materials. Substrate 10 may be a single-layer structure or a multi-layer structure. For example, substrate 10 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, substrate 10 may be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. This application does not impose limitations on the comparison.

[0106] For example, the first direction is, for example, the X direction, and the second direction is, for example, the Y direction. Both the first and second directions are parallel to the substrate 10 and intersect each other. The direction perpendicular to the substrate is the third direction, for example, the Z direction. To more clearly illustrate the structure of the memory provided in this application, unless otherwise specified, the following embodiments and figures will continue the aforementioned definitions of each direction.

[0107] For example, an atomic layer deposition process can be used to form a first electrode 31 that conformally covers the surface of the first gap G1.

[0108] For example, the material of the first electrode 31 may include: titanium nitride, tungsten nitride, molybdenum nitride, aluminum nitride, magnesium nitride, or tantalum nitride.

[0109] For example, the material of the capacitor dielectric layer 32 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0110] For example, the material of the second electrode 33 may include: tungsten, titanium, aluminum, copper, or nickel.

[0111] In some embodiments, the sum of the thicknesses of the first electrode 31, the capacitor dielectric layer 32, and the second electrode 33 is less than or equal to half the height of the first gap G1, so as to facilitate the placement of other related film layers in the first gap G1.

[0112] Please continue reading. Figure 1 and Figure 2In some embodiments, the memory cell stack structure 20 further includes: a sacrificial layer 41, in which a second gap G2 is formed; the sacrificial layer 41 and the second gap G2 are arranged alternately with the first gap G1 from bottom to top; the length of the second gap G2 along a first direction (e.g., the X direction) is less than the length of the first gap G1 along the first direction (e.g., the X direction). Correspondingly, the memory also includes: a release hole H1, which penetrates the memory cell stack structure 20 along the thickness direction (e.g., the Z direction) and is connected to both the first gap G1 and the second gap G2; the capacitor dielectric layer 32 also covers the surface of the release hole H1 and the surface of the second gap G2.

[0113] Here, the sacrificial layer 41 and the second gap G2 located in the same layer are arranged as a whole, alternating with the first gap G1 from bottom to top. It can be understood that, due to the presence of the sacrificial layer 41, the length of the second gap G2 along the X direction is less than the length of the first gap G1 along the X direction.

[0114] For example, the first gap G1 and the second gap G2 extend along the X direction at the same end of the storage cell stack structure 20, and the release hole H1 is adjacent to this end, so that the release hole H1 can be connected to both the first gap G1 and the second gap G2.

[0115] For example, the material of the sacrificial layer 41 may include silicon oxide, silicon nitride, phosphosilicate glass, or borosilicate glass.

[0116] In some embodiments, the memory further includes a filling medium layer 80 that fills the gaps between the memory cell stack structures 20 and covers the surface of the stack structure.

[0117] Please continue reading. Figure 2 In some embodiments, the memory further includes an electrode connection layer 50, which is located on the surface of the second electrode 33 and fills the release hole H1, the first gap G1 and the second gap G2.

[0118] Here, the electrode connection layer 50 is used to connect the second electrodes 33 of each capacitor 30 together to increase the capacitance storage capacity.

[0119] For example, the electrode connection layer 50 may also cover the upper surface of the memory cell stack structure 20 to facilitate corresponding connection of the electrode connection layer 50 with external circuitry.

[0120] For example, the material of the electrode connection layer 50 includes: tungsten metal, copper metal, aluminum metal, or doped polycrystalline silicon.

[0121] Please continue reading. Figures 1 to 3 as well as Figure 7Understandably, in some embodiments, the memory further includes: a bit line stack structure 60 and a plurality of transistors 70, wherein the bit line stack structure 60 extends along a second direction (e.g., the Y direction) and includes bit line isolation layers 61 and bit lines 62 alternately stacked from bottom to top; memory cell stack structures 20 arranged at intervals along a first direction (e.g., the X direction) are located on opposite sides of the bit line stack structure 60; the plurality of transistors 70 are located on opposite sides of the bit line stack structure 60, penetrate the memory cell stack structure 20 along the thickness direction (e.g., the Z direction), and are connected to the first electrode 31 and bit lines 62 located on the same layer.

[0122] For example, the first sacrificial layer 41 and the second gap G2 in the memory cell stack structure 20 are disposed in the same layer as the bit line isolation layer 61 in the bit line stack structure 60; the first gap G1 in the memory cell stack structure 20 is disposed in the same layer as the bit line 62 in the bit line stack structure 60. Alternatively, the memory cell stack structure 20 and the bit line stack structure 60 can also be fabricated separately based on different regions of the same film layer stack structure.

[0123] Please continue reading. Figures 1 to 2 In some embodiments, the capacitor dielectric layer 32, the second electrode 33, and the electrode connection layer 50 are also located on the memory cell stack structure 20 and the bit line stack structure 60; the memory also includes: a cover dielectric layer 90, an isolation trench G3, and an isolation layer 100, wherein the cover dielectric layer 90 is located on the upper surface of the electrode connection layer 50; the isolation trench G3 penetrates the cover dielectric layer 90, the electrode connection layer 50, the second electrode 33, and the capacitor dielectric layer 32 along the thickness direction; the orthographic projection of the isolation trench G3 on the upper surface of the stack structure covers the bit line stack structure 60; the isolation layer 100 is located in the isolation trench G3, and the isolation layer 100 insulates and isolates the capacitors 30 on opposite sides of the bit line stack structure 60; multiple capacitors 30 located on the same side of the bit line stack structure 60 share the second electrode 33.

[0124] It should be noted that, for the sake of clarity in illustrating certain structures, structures located above the filling dielectric layer 80, such as the capacitor dielectric layer 32, the second electrode 33, and the electrode connection layer 50, are not shown. Figure 1 As shown in the image.

[0125] Here, by forming an isolation trench and an isolation layer located in the isolation trench, at least the capacitor dielectric layer 32, the second electrode 33 and the electrode connection layer 50 located on the memory cell stack structure 20 and the bit line stack structure 60 are disconnected, thereby connecting the second electrodes 33 of multiple capacitors 30 located on the same side of the bit line stack structure 60 together, so as to facilitate the regional control of each capacitor 30.

[0126] Please see Figure 8This application also provides a method for fabricating a memory in some embodiments, for fabricating the memory described in the foregoing embodiments. This fabrication method also possesses the technical advantages of the memory described in the foregoing embodiments, and will not be detailed here. The fabrication method includes steps S100 to S600.

[0127] S100 provides a substrate.

[0128] S200, a stacked structure is formed on the upper surface of the substrate. The stacked structure includes a plurality of first stacked structures arranged at intervals along a first direction and a second direction. Each first stacked structure includes a sacrificial layer and a conductive layer that are alternately stacked from bottom to top. The first direction and the second direction are both parallel to the substrate and intersect each other.

[0129] S300, etch each conductive layer in the first stacked structure to remove a portion of each conductive layer to form a first gap.

[0130] S400, a first electrode is formed within a first gap, the first electrode covering the surface of the first gap; the material of the first electrode includes a metal nitride.

[0131] S500, forming a capacitor dielectric layer, the capacitor dielectric layer at least covering the surface of the first electrode.

[0132] S600 forms a second electrode on the surface of the capacitor dielectric layer.

[0133] In this embodiment, a first stacked structure consisting of alternating layers of sacrificial layers and conductive layers is first formed; then, a first gap is formed by partially etching each conductive layer in the first stacked structure; then, a capacitor including a first electrode, a capacitor dielectric layer, and a second electrode is formed in the first gap, and by making the first electrode cover the surface of the first gap, the relative area between the first electrode and the second electrode is effectively increased, thereby improving the charge storage capacity of the capacitor.

[0134] Please see Figure 9 In some embodiments, after step S200 and before step S300, the preparation method further includes step S260.

[0135] S260, a release hole is formed in the first stacked structure, and the release hole penetrates the first stacked structure along the thickness direction.

[0136] Correspondingly, step S300 includes: etching each conductive layer within the first stacked structure based on the release hole.

[0137] Please continue reading. Figure 9 In some embodiments, after step S200 and before step S300, the preparation method further includes step S450.

[0138] S450, etch each sacrificial layer in the first stacked structure to remove a portion of each sacrificial layer to form a second gap; the length of the second gap along the first direction is less than the length of the first gap along the first direction.

[0139] Correspondingly, step S500 includes: forming a capacitor dielectric layer at least in the release hole, the first gap and the second gap, wherein the capacitor dielectric layer at least covers the surface of the first electrode, the inner wall of the release hole and the surface of the second gap.

[0140] Please see Figure 10 In some embodiments, after step S200 and before step S300, the preparation method further includes step S250.

[0141] S250, forming a filling dielectric layer that fills the gap between adjacent first stacked structures and covers the upper surface of the stacked structures.

[0142] Please continue reading. Figure 10 In some embodiments, after step S600, the preparation method further includes step S700.

[0143] S700, an electrode connection layer is formed on the surface of the second electrode, and the electrode connection layer fills the release hole, the first gap and the second gap.

[0144] In some embodiments, the stacked structure further includes: a second stacked structure extending along a second direction, the second stacked structure including a sacrificial layer and a conductive layer alternately stacked from bottom to top; the conductive layer in the second stacked structure serves as a bit line, and the sacrificial layer in the second stacked structure serves as a bit line isolation layer for adjacent bit lines; and a first stacked structure arranged at intervals along a first direction is located on opposite sides of the second stacked structure.

[0145] Please continue reading. Figure 11 In some embodiments, the capacitor dielectric layer, the second electrode, and the electrode connection layer are also located on the stacked structure; the first electrode, the capacitor dielectric layer, and the second electrode constitute a capacitor; after step S700, the preparation method further includes steps S800 to S1000.

[0146] S800 forms a covering dielectric layer on the upper surface of the electrode connection layer.

[0147] S900, forming an isolation trench that penetrates and covers the dielectric layer, electrode connection layer, second electrode and capacitor dielectric layer along the thickness direction; the orthographic projection of the isolation trench on the upper surface of the stacked structure covers the second stacked structure.

[0148] S1000, an isolation layer is formed in the isolation groove, the isolation layer insulates and isolates the capacitors on opposite sides of the second stack structure; multiple capacitors located on the same side of the second stack structure share the second electrode.

[0149] Please continue reading. Figure 10 In some embodiments, after step S1000, the preparation method further includes step S1100.

[0150] S1100, a plurality of transistors are formed within the first stacked structure, and the transistors are connected to the first electrode and bit line located on the same layer.

[0151] For example, please refer to Figure 11 Step S1100 includes steps S1101 to S1105.

[0152] S1101, a plurality of first through holes are formed in the first stacked structure. The first through holes are located between the capacitor and the second stacked structure and penetrate the isolation layer and the first stacked structure along the thickness direction.

[0153] S1102, based on the first via, remove the conductive layer retained in the first stacked structure to obtain the second via.

[0154] S1103, a channel layer is formed at least on the sidewall and bottom of the second via, and the channel layer is in contact with the first electrode and bit line located in the same layer.

[0155] S1104 forms a gate dielectric layer on the surface of the channel layer.

[0156] S1105, a gate conductive layer is formed on the surface of the gate dielectric layer; the gate conductive layer also serves as a word line.

[0157] Furthermore, in the above embodiments of this application, unless otherwise expressly stated herein, the execution order of the steps in the method is not strictly limited. These steps may not necessarily be executed in the described order, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0158] To more clearly illustrate the memory fabrication methods in some of the above embodiments, the following embodiments are combined with... Figures 10 to 52 The fabrication methods of some memory devices are described in detail.

[0159] In step S100, please refer to Figure 10S100 and Figure 12 Substrate 10 is provided.

[0160] For example, substrate 10 may be composed of any combination of semiconductor materials, insulating materials, conductive materials, or such materials. Substrate 10 may be a single-layer structure or a multi-layer structure. For example, substrate 10 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, substrate 10 may be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. This application does not impose limitations on the comparison.

[0161] In step S200, please refer to Figure 10 S200 and Figures 13 to 16 A stacked structure is formed on the upper surface of the substrate 10. The stacked structure includes a plurality of first stacked structures 40A arranged at intervals along a first direction (e.g., the X direction) and a second direction (e.g., the Y direction). Each first stacked structure 40A includes a sacrificial layer 41 and a conductive layer 42 stacked alternately from bottom to top. The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) are both parallel to the substrate and intersect each other.

[0162] For example, an initial stacked structure consisting of multiple sacrificial layers 41 and conductive layers 42 alternately stacked can be formed on the substrate 10 first, and by patterning the initial stacked structure, a stacked structure 40 containing multiple first stacked structures 40A can be obtained.

[0163] For example, the material of the sacrificial layer 41 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0164] For example, the material of the conductive layer 42 includes: tungsten, titanium, aluminum, copper, or nickel.

[0165] In one example, the material of the sacrificial layer 41 is, for example, silicon oxide; and the material of the conductive layer 42 is, for example, tungsten metal.

[0166] In some embodiments, a second stacked structure 40B is formed simultaneously with the formation of the first stacked structure 40A. The second stacked structure 40B extends along a second direction (e.g., the Y direction) and includes sacrificial layers 41 and conductive layers 42 alternately stacked from bottom to top. The conductive layers 42 in the second stacked structure 40B serve as bit lines 62, and the sacrificial layers 41 in the second stacked structure 40B serve as bit line isolation layers 61 for adjacent bit lines 62. The first stacked structures 40A, spaced apart along a first direction (e.g., the X direction), are located on opposite sides of the second stacked structure 40B.

[0167] Here, the conductive layer 42 located in the second stacked structure 40B and the same layer located in the first stacked structure 40A are integrally connected; the sacrificial layer 41 located in the second stacked structure 40B and the same layer located in the first stacked structure 40A are integrally connected.

[0168] In step S250, please refer to Figure 10 S250 and Figures 17 to 20 A filling dielectric layer 80 is formed, which fills the gap between adjacent first stacked structures 40A and covers the upper surface of the stacked structure 40.

[0169] For example, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, evaporation growth, molecular beam epitaxy, or vapor phase film formation can be used to form a filling medium layer 80 that fills the gap between adjacent first stacked structures 40A and covers the upper surface of the stacked structure 40.

[0170] For example, the material filling the dielectric layer 80 includes silicon oxide, silicon nitride, or silicon oxynitride. In one example, the material filling the dielectric layer 80 is, for example, silicon nitride.

[0171] In step S260, please refer to Figure 10 S260 and Figures 21 to 22 A release hole H1 is formed within the first stacked structure 40A, and the release hole H1 penetrates the first stacked structure 40A along the thickness direction (e.g., the Z direction).

[0172] Here, the release hole H1 can be formed at one end of the first stacked structure 40A away from the second stacked structure 40B to expose the conductive layer 42 located in the first stacked structure 40A.

[0173] For example, a patterned mask layer can be formed on the surface of the filling dielectric layer 80 opposite to the stacked structure 40. The patterned mask layer has an opening pattern that defines the location of the release hole H1. The filling dielectric layer 80 and the first stacked structure 40A are etched based on the patterned mask layer to obtain the release hole H1.

[0174] For example, the number of release holes H1 is set to match the number of the first stacked structure 40A, but this application does not limit this.

[0175] For example, a dry etching process can be used, and the formation direction and depth of the release hole H1 can be accurately controlled by adjusting parameters such as etching direction and etching time.

[0176] It should be noted that since this step does not involve further direct processing of the filling dielectric layer 80 located between adjacent first stacked structures 40A, the cross-sectional schematic diagram of the structure obtained after performing this step along the BB direction can be referred to Figure 19 Understanding; a cross-sectional diagram along the CC direction can be referenced. Figure 20 understand.

[0177] In step S300, please refer to Figure 10 S300 and Figures 23 to 24 The conductive layers 42 within the first stacked structure 40A are etched to partially remove each conductive layer 42, thereby forming the first gap G1.

[0178] For example, a wet etching process can be used to etch and remove one end of the exposed conductive layer 42, and by adjusting parameters such as etching time, the extension length of the obtained first gap G1 along the first direction (e.g., the X direction) can be controlled.

[0179] It should be noted that since this step does not involve further direct processing of the filling dielectric layer 80 located between adjacent first stacked structures 40A, the cross-sectional schematic diagram of the structure obtained after performing this step along the BB direction can be referred to Figure 19 understand.

[0180] In step S400, please refer to Figure 10 S400 and Figures 25 to 26 A first electrode 31 is formed within the first gap G1, and the first electrode 31 covers the surface of the first gap G1; the material of the first electrode 31 includes metal nitride.

[0181] For example, the first electrode 31 covering the surface of the first gap G1 can be formed using processes such as chemical vapor deposition, physical vapor deposition, evaporation, electroplating, or atomic layer deposition. In one example, the first electrode 31 is prepared using an atomic layer deposition process.

[0182] The material of the first electrode 31 may include: titanium nitride, tungsten nitride, molybdenum nitride, aluminum nitride, magnesium nitride, or tantalum nitride.

[0183] It should be noted that since this step does not involve further direct processing of the filling dielectric layer 80 located between adjacent first stacked structures 40A, the cross-sectional schematic diagram of the structure obtained after performing this step along the BB direction can be referred to Figure 19 understand.

[0184] In step S450, please refer to Figure 10 S450 and Figures 27 to 28 The sacrificial layers 41 within the first stacked structure 40A are etched to partially remove each sacrificial layer 41, thereby forming a second gap G2. The length of the second gap G2 along the first direction (e.g., the X direction) is less than the length of the first gap G1 along the first direction (e.g., the X direction).

[0185] Here, the orthographic projection of the second gap G2 onto the substrate falls into the orthographic projection of the first gap G1 onto the substrate.

[0186] For example, a wet etching process can be used to etch and remove one end of the exposed sacrificial layer 41, and by adjusting parameters such as etching time, the extension length of the obtained second gap G2 along the first direction (e.g., the X direction) can be controlled.

[0187] In step S500, please refer to Figure 10 S500 and Figures 29 to 30 A capacitor dielectric layer 32 is formed, which at least covers the surface of the first electrode 31.

[0188] For example, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation can be used to cover the surface of the first electrode 31 to form a capacitor dielectric layer 32.

[0189] For example, the capacitor dielectric layer 301 includes silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0190] For example, in some embodiments, the capacitor dielectric layer 32 also covers the second spacer G1, the release hole H1, and the surface of the filling dielectric layer 80.

[0191] In step S600, please refer to Figure 10 S600 and Figures 31 to 32 A second electrode 33 is formed on the surface of the capacitor dielectric layer 32.

[0192] For example, processes such as chemical vapor deposition, physical vapor deposition, evaporation, electroplating, or atomic layer deposition can be used to form the second electrode 33 covering the surface of the capacitor dielectric layer 32.

[0193] For example, the material of the second electrode 33 may include: tungsten, titanium, aluminum, copper, or nickel.

[0194] In step S700, please refer to Figure 10 S700 and Figures 33 to 34 An electrode connection layer 50 is formed on the surface of the second electrode 33, and the electrode connection layer 50 fills the release hole H1, the first gap G1 and the second gap G2.

[0195] For example, processes such as chemical vapor deposition, physical vapor deposition, evaporation, electroplating, or atomic layer deposition can be used to form an electrode connection layer 50 that fills the release hole H1, the first gap G1, and the second gap G2 and covers the surface of the second electrode 33.

[0196] For example, the material of the electrode connection layer 50 may include: tungsten metal, copper metal, aluminum metal, or doped polycrystalline silicon.

[0197] For example, the electrode connection layer 50 also covers the filling dielectric layer 80.

[0198] In step S800, please refer to Figure 10 S800 and Figures 35 to 36 A covering dielectric layer 90 is formed on the upper surface of the electrode connection layer 50.

[0199] For example, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation can be used to form a covering dielectric layer 90 on the upper surface of the electrode connection layer 50.

[0200] For example, the material covering the dielectric layer 90 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0201] In step S900, please refer to Figure 10 S900 and Figures 37 to 38 An isolation trench G3 is formed, which penetrates and covers the dielectric layer 90, the electrode connection layer 50, the second electrode 33 and the capacitor dielectric layer 32 along the thickness direction (e.g., the Z direction); the orthographic projection of the isolation trench G3 on the upper surface of the stacked structure 40 covers the second stacked structure 40B.

[0202] For example, an etching process can be used to etch the surface of the covering dielectric layer 90 toward the substrate, and the filling dielectric layer 80 can be used as an etching stop layer to obtain the isolation trench G3.

[0203] In step S1000, please refer to Figure 10 S1000 and Figures 39 to 40An isolation layer 100 is formed in the isolation groove G3, which insulates and isolates the capacitors 30 on opposite sides of the second stacked structure 40B; multiple capacitors 30 located on the same side of the second stacked structure 40B share the second electrode 33.

[0204] For example, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation can be used to form the isolation layer 100 that fills the isolation trench G3.

[0205] For example, the material of the insulating layer 100 may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borosilicate glass.

[0206] In step S1100, please refer to Figure 10 S1100 and Figures 41 to 48 Multiple transistors 70 are formed within the first stacked structure 40A, and the transistors 70 are connected to the first electrode 31 and bit line 62 located on the same layer.

[0207] For example, step S1100 includes steps S1101 to S1105.

[0208] In step S1101, please refer to Figure 11 S1101 and Figures 41 to 43 Multiple first through holes H2 are formed in the first stacked structure 40A. The first through holes H2 are located between the capacitor 30 and the second stacked structure 40B, and penetrate the isolation layer 100 and the first stacked structure 40A along the thickness direction (e.g., the Z direction).

[0209] For example, a patterned mask layer is first formed on the overlay dielectric layer 90 and the isolation layer 100. The patterned mask layer has an opening pattern that defines the location of the first via H2. The isolation layer 100 and the first stacked structure 40A are etched based on the patterned mask layer to obtain the first via H2.

[0210] For example, a dry etching process can be used, and the formation direction and depth of the first via H2 can be accurately controlled by adjusting parameters such as etching direction and etching time.

[0211] In step S1102, please refer to Figure 10 S1102 and Figures 44 to 45 The conductive layer 42 retained in the first stacked structure 40A is removed based on the first via H2 to obtain the second via H3.

[0212] For example, a wet etching process can be used to selectively etch the conductive layer 42 retained in the first stacked structure 40A using an etching solution with a selectivity ratio, and to use the second electrode 33 as an etching stop layer to obtain the second via H3.

[0213] For example, in some embodiments, a portion of the bit lines 62 located in the second stacked structure 40B are removed simultaneously with the removal of the conductive layer 42.

[0214] In step S1103, please refer to Figure 10 S1103 and Figures 46 to 47 A channel layer 71 is formed at least on the sidewall and bottom of the second through hole H3, and the channel layer 71 is in contact with the first electrode 31 and the bit line 62 located in the same layer.

[0215] For example, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation can be used to cover the sidewalls and bottom of the second via H3 to form a channel layer 71.

[0216] For example, the material of the channel layer 71 includes monocrystalline silicon, polycrystalline silicon, germanium silicon, or indium tin zinc oxide. In one example, the material of the channel layer 71 is, for example, indium tin zinc oxide.

[0217] For example, in some embodiments, the channel layer 71 also covers the sidewalls and bottom of the first via H2 and the surface of the covering dielectric layer 90.

[0218] Optionally, in some embodiments, after forming the channel layer 71, the method further includes removing a portion of the channel layer 71 that covers the surface of the sacrificial layer 41. Here, by removing a portion of the channel layer 71, the formation of parasitic transistors can be avoided, thereby further ensuring and improving the electrical performance of the memory.

[0219] In step S1104, please refer to Figure 10 S1104 and Figures 48 to 49 A gate dielectric layer 72 is formed on the surface of the channel layer 71.

[0220] For example, processes such as chemical vapor deposition, physical vapor deposition, thermal oxidation, atomic layer deposition, evaporation growth, molecular beam epitaxy, or vapor phase film formation can be used to cover the surface of the channel layer 71 to form the gate dielectric layer 72.

[0221] For example, the material of the gate dielectric layer 72 includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, or hafnium dioxide.

[0222] In step S1105, please refer to Figure 10 S1105 and Figures 50 to 51 A gate conductive layer 73 is formed on the surface of the gate dielectric layer 72; the gate conductive layer 73 also serves as a word line.

[0223] Here, the gate conductive layer 73 also fills the second via H3; the channel layer 71, the gate dielectric layer 72, and the gate conductive layer 73 together constitute the transistor 70.

[0224] For example, a gate conductive layer 73 covering the surface of the channel layer 71 and filling the second via H3 can be formed using processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, or evaporation.

[0225] For example, the material of the gate conductive layer 73 includes: tungsten, titanium, aluminum, copper, or nickel.

[0226] Please see Figure 52 In some embodiments, planarization may also be performed on the semiconductor structure after the transistor 70 is formed.

[0227] In some embodiments, an electronic device is provided, including the memory described in some of the foregoing embodiments. The electronic device also possesses the technical advantages of the memory described in some of the foregoing embodiments, and will not be detailed here.

[0228] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0229] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0230] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a memory, characterized in that, The method includes: Provide substrate; A stacked structure is formed on the upper surface of the substrate. The stacked structure includes a plurality of first stacked structures arranged at intervals along a first direction and a second direction. Each first stacked structure includes a sacrificial layer and a conductive layer alternately stacked from bottom to top. The first direction and the second direction are both parallel to the substrate and intersect each other. A release hole is formed within the first stacked structure, and the release hole penetrates the first stacked structure along the thickness direction; Based on the release hole, each of the conductive layers in the first stacked structure is etched to remove a portion of each conductive layer to form a first gap; A first electrode is formed within the first gap, and the first electrode covers the surface of the first gap; The sacrificial layers within the first stacked structure are etched to partially remove each sacrificial layer, thereby forming a second gap; the length of the second gap along the first direction is less than the length of the first gap along the first direction. A capacitor dielectric layer is formed at least within the release hole, the first gap, and the second gap, and the capacitor dielectric layer at least covers the surface of the first electrode, the inner wall of the release hole, and the surface of the second gap; A second electrode is formed on the surface of the capacitor dielectric layer.

2. The method for fabricating a memory according to claim 1, characterized in that, The formation of the first electrode within the first gap includes: forming a first electrode conformally covering the surface of the first gap using an atomic layer deposition process; wherein... The material of the first electrode includes one of titanium nitride, tantalum nitride, and molybdenum nitride.

3. The method for fabricating a memory according to claim 1, characterized in that, After forming the second electrode on the surface of the capacitor dielectric layer, the method further includes: An electrode connection layer is formed on the surface of the second electrode, and the electrode connection layer fills the release hole, the first gap and the second gap.

4. The method for fabricating a memory according to claim 3, characterized in that, The stacked structure further includes: The second stacked structure extends along the second direction and includes sacrificial layers and conductive layers stacked alternately from bottom to top. The conductive layers in the second stacked structure serve as bit lines, and the sacrificial layers in the second stacked structure serve as bit line isolation layers between adjacent bit lines. The first stacked structures, arranged at intervals along the first direction, are located on opposite sides of the second stacked structure.

5. The method for fabricating a memory according to claim 4, characterized in that, The capacitor dielectric layer, the second electrode, and the electrode connection layer are also located on the stacked structure; the first electrode, the capacitor dielectric layer, and the second electrode constitute a capacitor; After forming the electrode connection layer on the surface of the second electrode, the method further includes: A covering dielectric layer is formed on the upper surface of the electrode connection layer; An isolation trench is formed, which penetrates the covering dielectric layer, the electrode connection layer, the second electrode, and the capacitor dielectric layer along the thickness direction; the orthographic projection of the isolation trench on the upper surface of the stacked structure covers the second stacked structure; An isolation layer is formed within the isolation groove, which insulates and isolates the capacitors on opposite sides of the second stacked structure; the plurality of capacitors located on the same side of the second stacked structure share a second electrode.

6. The method for fabricating a memory according to claim 5, characterized in that, Multiple transistors are formed within the first stacked structure, and the transistors are connected to the first electrode and the bit line located on the same layer.

7. The method for fabricating a memory according to claim 6, characterized in that, The formation of multiple transistors within the first stacked structure includes: A plurality of first through holes are formed within the first stacked structure. The first through holes are located between the capacitor and the second stacked structure and penetrate the isolation layer and the first stacked structure along the thickness direction. The conductive layer retained in the first stacked structure is removed based on the first via to obtain the second via; A channel layer is formed at least on the sidewall and bottom of the second through hole, and the channel layer is in contact with the first electrode and the bit line located in the same layer; A gate dielectric layer is formed on the surface of the channel layer; A gate conductive layer is formed on the surface of the gate dielectric layer; the gate conductive layer also serves as a word line.

8. The method for fabricating a memory according to claim 1, characterized in that, After forming a stacked structure on the upper surface of the substrate, and before etching each of the conductive layers within the first stacked structure, the method further includes: A filling medium layer is formed, which fills the gap between adjacent first stacked structures and covers the upper surface of the stacked structures.

9. A memory, characterized in that, include: Substrate; A stacked structure of multiple storage cells, arranged at intervals along a first direction and a second direction; Each of the aforementioned memory cell stack structures includes a capacitor and a plurality of first gaps arranged at intervals from bottom to top; the capacitor includes a first electrode, a capacitor dielectric layer and a second electrode, the first electrode at least covers the surface of the first gap, and the material of the first electrode includes a metal nitride; the capacitor dielectric layer covers the surface of the first electrode, and the second electrode covers the surface of the capacitor dielectric layer; Both the first direction and the second direction are parallel to the substrate and intersect each other; The storage cell stack structure further includes: a sacrificial layer, in which a second gap is formed; the sacrificial layer and the second gap are arranged alternately with the first gap from bottom to top; the length of the second gap along the first direction is less than the length of the first gap along the first direction. The memory also includes a release hole that penetrates the memory cell stack structure along the thickness direction and is connected to both the first gap and the second gap; the capacitor dielectric layer also covers the surface of the release hole and the surface of the second gap.

10. The memory according to claim 9, characterized in that, It also includes an electrode connection layer, which is located on the surface of the second electrode and fills the release hole, the first gap and the second gap.

11. The memory according to claim 10, characterized in that, Also includes: The bit line stacking structure extends along the second direction and includes bit line isolation layers and bit lines that are alternately stacked from bottom to top. The memory cell stack structure, which is spaced apart along the first direction, is located on opposite sides of the bit line stack structure; Multiple transistors are located on opposite sides of the bit line stack structure, extending through the memory cell stack structure along the thickness direction, and are connected to the first electrode and the bit line located on the same layer.

12. The memory according to claim 11, characterized in that, The capacitor dielectric layer, the second electrode, and the electrode connection layer are also located on the memory cell stack structure and the bit line stack structure; the memory cell stack structure and the bit line stack structure constitute a stack structure; the memory further includes: A covering dielectric layer is located on the upper surface of the electrode connection layer; An isolation trench extends along the thickness direction through the cover dielectric layer, the electrode connection layer, the second electrode, and the capacitor dielectric layer; the orthographic projection of the isolation trench onto the upper surface of the stacked structure covers the bit line stacked structure. An isolation layer, located within the isolation groove, insulates and isolates the capacitors on opposite sides of the bit line stack structure; multiple capacitors located on the same side of the bit line stack structure share a second electrode.

13. An electronic device, characterized in that, include: The memory as described in any one of claims 9 to 12.

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