Semiconductor device and method of manufacturing the same

Abstract

The present inventive concept relates to a semiconductor device and a method of manufacturing the same, the semiconductor device according to some example embodiments comprising: a substrate comprising an active region defined by a device isolation layer; a word line intersecting and overlapping the active region; a bit line crossing the active region in a different direction from the word line; a direct contact connecting the active region and the bit line and including a metal material; a buried contact connected to the active region; and a bit line spacer between the bit line and the buried contact, where a width of the direct contact is different from a width of the bit line, and the bit line spacer is on an upper surface of the direct contact.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0101036 filed in the Korean Intellectual Property Office on August 2, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0003] As semiconductor devices become more and more highly integrated, circuit patterns are becoming finer to implement more semiconductor devices in the same area. That is, as the integration of semiconductor devices increases, design rules for constituent elements of semiconductor devices decrease.

[0004] In highly scaled semiconductor devices, the process of forming multiple bit lines and direct contacts connected thereto is becoming increasingly complex and difficult. Summary of the invention

[0005] Some example embodiments provide a semiconductor device having improved reliability and productivity and / or a method for manufacturing the semiconductor device.

[0006] Some example embodiments provide a semiconductor device, which may include: a substrate including an active region defined by a device isolation layer; a word line intersecting and overlapping the active region; a bit line intersecting the active region in a direction different from the word line; a direct contact connecting the active region and the bit line and including a metal material; a buried contact connected to the active region; and a bit line spacer located between the bit line and the buried contact. The width of the direct contact may be different from that of the bit line, and the bit line spacer may be located on an upper surface of the direct contact.

[0007] Some example embodiments provide a semiconductor device, which may include: a substrate, including an active area defined by a device isolation layer; a word line, which crosses and overlaps the active area; a bit line, which crosses the active area in a direction different from the word line; a direct contact, which connects the active area and the bit line and includes a metal material; a silicide layer, which is located between the active area and the direct contact; a buried contact, which is connected to the active area; a first bit line spacer, which is located on an upper surface of the direct contact; a second bit line spacer, which is located between the first bit line spacer and the buried contact; and a bonding pad, which is connected to the active area through the buried contact, wherein the width of the direct contact is larger than the width of the bit line.

[0008] Some example embodiments provide a method for manufacturing a semiconductor device, wherein the method may include the following steps: forming a device isolation layer in a substrate to define an active area; forming an insulating layer on the substrate, and then patterning the insulating layer to form a direct contact groove to expose the upper surface of the active area; forming a trench spacer in the direct contact groove on the exposed upper surface of the active area; forming a first material layer including a metal material in the direct contact groove; sequentially stacking a second material layer, a third material layer, and a fourth material layer on the insulating layer and the first material layer; forming a bit line based on patterning at least some of the second material layer, the third material layer, and the fourth material layer; forming a first bit line spacer to cover the side surface of the bit line; patterning the trench spacer and the first material layer using the first bit line spacer as an etching mask to form a direct contact connected to the active area and the bit line; forming a second bit line spacer covering the first bit line spacer and the direct contact; forming a buried contact connected to the active area; and forming a bonding pad connected to the active area through the buried contact.

[0009] According to some example embodiments, since a bit line spacer including a low dielectric material is disposed on a side surface of a bit line, a semiconductor device having improved electrical characteristics may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A top plan view of a semiconductor device according to some example embodiments is illustrated.

[0011] Figure 2 Shown along Figure 1 A cross-sectional view taken along line II'.

[0012] Figure 3 Shown along Figure 1 A cross-sectional view taken along line II-II'.

[0013] Figure 4 According to some example embodiments Figure 2 A local enlarged view of area R1.

[0014] Figure 5 , Figure 6 and Figure 7 A partially enlarged view of a cross section of a semiconductor device according to some example embodiments is shown.

[0015] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 and Fig. 20 A cross-sectional view for explaining a method for manufacturing a semiconductor device according to some example embodiments is shown. DETAILED DESCRIPTION

[0016] The inventive concept will be described more fully below with reference to the accompanying drawings, in which some example embodiments of the inventive concept are shown. As will be appreciated by those skilled in the art, the described example embodiments may be modified in various different ways without departing from the spirit or scope of the inventive concept.

[0017] In order to clearly describe the inventive concept, parts or portions irrelevant to the description are omitted, and the same or similar constituent elements are denoted by the same reference numerals throughout the specification.

[0018] In addition, in the drawings, the size and thickness of each element are arbitrarily shown for ease of description, and the inventive concept is not necessarily limited to the size and thickness of each element shown in the drawings. In the drawings, the thickness of layers, films, plates, regions, areas, etc. are exaggerated for clarity. In the drawings, the thickness of some layers, regions, and areas are exaggerated for ease of description.

[0019] It will be understood that when an element such as a layer, film, zone, region, or substrate is referred to as being "on" or "over" another element, the element may be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, in the specification, the words "on" or "above" mean disposed on or below an object portion, and do not necessarily mean disposed on the upper side of an object portion based on the direction of gravity.

[0020] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0021] Furthermore, throughout the specification, the phrase "in a plan view" or "on a plane" means viewing a target portion from the top, and the phrase "in a cross-sectional view" or "on a section" means viewing a section formed by vertically cutting the target portion from the side.

[0022] It will be understood that elements and / or their properties (e.g., structures, surfaces, directions, etc.) that may be referred to as being "perpendicular", "parallel", "coplanar", etc., relative to other elements and / or their properties (e.g., structures, surfaces, directions, etc.) may be "perpendicular", "parallel", "coplanar", etc., respectively, relative to the other elements and / or their properties, or may be "substantially perpendicular", "substantially parallel", "substantially coplanar", etc., respectively, relative to the other elements and / or their properties.

[0023] Elements and / or properties (e.g., structures, surfaces, directions, etc.) that are “substantially perpendicular,” “substantially parallel,” or “substantially coplanar” relative to other elements and / or properties thereof will be understood to be “perpendicular,” “parallel,” or “coplanar,” respectively, relative to the other elements and / or properties thereof within manufacturing tolerances and / or material tolerances, and / or have an amplitude deviation and / or an angular deviation equal to or less than 10% (e.g., a tolerance of ±10%) from being “perpendicular,” “parallel,” or “coplanar,” respectively, relative to the other elements and / or properties thereof.

[0024] It will be understood that elements and / or their properties may be described herein as being "the same" or "equal" to other elements, and it will also be understood that elements and / or their properties described herein as being "equivalent", "identical" or "equal" to other elements may be "equivalent", "identical" or "equal" or "substantially equivalent", "substantially identical" or "substantially equivalent" to the other elements and / or their properties. Elements and / or their properties that are "substantially equivalent", "substantially identical" or "substantially equivalent" to other elements and / or their properties will be understood to include elements and / or their properties that are equivalent, identical or equal to the other elements and / or their properties within manufacturing tolerances and / or material tolerances. Elements and / or their properties that are equivalent or substantially equivalent and / or identical or substantially identical to other elements and / or their properties may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition. Although the terms "same", "equal" or "equivalent" may be used in the description of some example embodiments, it will be understood that some imprecision may exist. Thus, when a first element, property, or value is referred to as being “the same,” “equal,” or “equivalent” to a second element, property, or value, and regardless of whether the first element, property, or value is modified to be “substantially” the same, equal, or equivalent to the second element, property, or value, it should be understood that the first element, property, or value is “the same,” “equal,” or “equivalent” to the second element, property, or value within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0025] It will be understood that elements and / or properties thereof described herein as being "substantially" the same, equal, and / or equivalent include elements and / or properties thereof having a relative magnitude difference of 10% or less. Furthermore, regardless of whether elements and / or properties thereof are qualified as "substantially," it will be understood that these elements and / or properties thereof should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated elements and / or properties thereof.

[0026] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but rather that the tolerance of the shape is within the disclosed range. In addition, regardless of whether a numerical value or shape is modified as "approximately" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape. When a range is specified, the range includes all values ​​therebetween (such as in increments of 0.1%).

[0027] As described herein, when an operation is described as being performed “by” or “via” performing additional operations, or an effect such as a structure is described as being established “by” or “via” performing additional operations, it will be understood that the operation may be performed “based on” the additional operations and / or the effect / structure may be established “based on” the additional operations, which may include performing the additional operations alone or in combination with other further additional operations.

[0028] As described herein, an element described as being "spaced apart" from another element in general and / or in a specific direction (e.g., vertically spaced apart, laterally (or referred to as lateral) spaced apart, etc.) and / or described as "separated from" the other element may be understood as being isolated from the other element in general and / or in the specific direction without direct contact (e.g., isolated from the other element in the vertical direction without direct contact, isolated from the other element in the lateral or horizontal direction without direct contact, etc.). Similarly, elements described as being "spaced apart" from each other in general and / or in a specific direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and / or described as "separated from" each other may be understood as being isolated from each other in general and / or in the specific direction without direct contact (e.g., isolated from each other in the vertical direction without direct contact, isolated from each other in the lateral or horizontal direction without direct contact, etc.). Similarly, a structure described herein as being located between two other structures to separate the two other structures from each other may be understood as being constructed to isolate the two other structures from each other without direct contact.

[0029] In the following, reference will be made to Figures 1 to 3 Semiconductor devices according to some example embodiments are described.

[0030] Figure 1 A top plan view of a semiconductor device according to some example embodiments is illustrated. Figure 2 Shown along Figure 1 A cross-sectional view taken along line II'. Figure 3 Shown along Figure 1 A cross-sectional view taken along line II-II'.

[0031] Reference Figures 1 to 3 , a semiconductor device according to some example embodiments may include an active region AR, a word line WL crossing and overlapping the active region AR, a bit line BL crossing and overlapping the active region AR in a direction different from the direction of the word line WL, a direct contact DC connecting the active region AR and the bit line BL, a buried contact BC connected to the active region AR, and a bit line spacer structure 620 disposed between the bit line BL and the buried contact BC. The semiconductor device according to some example embodiments may further include a bonding pad LP connected to the buried contact BC. The buried contact BC may connect the active region AR and the bonding pad LP.

[0032] The substrate 100 may include a cell array region and a peripheral circuit region. The cell array region is a region where a plurality of memory cells are formed, and a plurality of active regions AR may be disposed in the cell array region. The peripheral circuit region may be disposed to surround the cell array region, and elements driving the memory cells may be disposed in the peripheral circuit region. For convenience, Figures 1 to 3A cell array region is shown, and illustration of a peripheral circuit region is omitted.

[0033] The active region AR may be defined by a device isolation layer 112 disposed in the substrate 100. A plurality of active regions AR may be disposed in the substrate 100, and the plurality of active regions AR may be separated from each other by the device isolation layer 112. The device isolation layer 112 may be disposed on both sides of each active region AR.

[0034] The substrate 100 may have an upper surface parallel to the first and second directions X and Y, and may have a thickness parallel to a third direction Z that is perpendicular to the first and second directions X and Y.

[0035] The substrate 100 may include a semiconductor material. The substrate 100 may include a group IV semiconductor, a group III-V compound semiconductor, and / or a group II-VI compound semiconductor. For example, the substrate 100 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. However, the material of the substrate 100 is not limited thereto, but may be changed variously.

[0036] The active region AR may have a rod (bar) shape extending along a fourth direction DR4, and the fourth direction DR4 is inclined to the first direction X and the second direction Y. The fourth direction DR4 may be parallel to the upper surface of the substrate 100, and may be disposed on substantially the same plane as the first direction X and the second direction Y. For example, the fourth direction DR4 may make an acute angle with the first direction X and the second direction Y, respectively.

[0037] The plurality of active regions AR may extend in directions parallel to each other. The plurality of active regions AR may be arranged to be spaced apart from each other by a predetermined interval along the fourth direction DR4 and the first direction X. A central portion of one active region AR may be adjacent to an end of another active region AR in the first direction X. One end of one active region AR may be adjacent to another end of another active region AR in the first direction X. However, the shape or arrangement form of the active region AR is not limited thereto, but may be variously changed.

[0038] The device isolation layer 112 may have a shallow trench isolation (STI) structure with excellent device isolation characteristics. The device isolation layer 112 may include silicon oxide, silicon nitride, or any combination thereof. However, the material and configuration of the device isolation layer 112 are not limited thereto, but may be changed differently. For example, the device isolation layer 112 may be formed as a single layer or multiple layers.

[0039] Furthermore, the device isolation layer 112 may be made of a single material, or may include two or more types of insulating materials.

[0040] A semiconductor device according to some example embodiments may include a plurality of word lines WL. The plurality of word lines WL may extend along a first direction X and may be spaced apart from each other along a second direction Y at regular intervals.

[0041] Each of the plurality of word lines WL may extend along the first direction X and may cross the active region AR. The plurality of word lines WL may overlap the active region AR and may serve as gate electrodes.

[0042] One word line WL may overlap a plurality of active regions AR adjacent to the first direction X (eg, overlap in the third direction Z). Each of the plurality of active regions AR may cross-overlap two word lines WL. Each active region AR may be divided into three parts by the two word lines WL.

[0043] Here, the central portion of the active region AR disposed between the two word lines WL may be a portion connected to the bit line BL, and both ends of the active region AR disposed outside the two word lines WL may be portions connected to the capacitor (not shown). The bit line BL may be connected to the active region AR through a direct contact DC. The capacitor may be connected to the active region AR through a bonding pad LP and a buried contact BC.

[0044] The substrate 100 may include a word line trench WLT, and the word line structure WLS may be disposed in the word line trench WLT. That is, the word line structure WLS may have a form embedded in the substrate 100. A portion of the word line trench WLT may be disposed on the active region AR, and another portion may be disposed on the device isolation layer 112.

[0045] The word line structure WLS may include a gate insulating layer 132, a word line WL disposed on the gate insulating layer 132, and a word line capping layer 134 disposed on the word line WL. However, the location and configuration of the word line structure WLS are not limited thereto but may be variously changed.

[0046] The gate insulating layer 132 may be disposed in the word line trench WLT. The gate insulating layer 132 may be conformally disposed on the inner sidewall of the word line trench WLT.

[0047] The gate insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or any combination thereof. However, the position, shape, and material of the gate insulating layer 132 are not limited thereto but may be variously changed.

[0048] The word line WL may be disposed on the gate insulating layer 132. The side surface and the bottom surface of the word line WL may be surrounded by the gate insulating layer 132. The gate insulating layer 132 may be disposed between the word line WL and the active region AR. Therefore, the word line WL may not directly contact the active region AR.

[0049] The word line WL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or any combination thereof However, the position, shape, and material of the word line WL are not limited thereto but may be variously changed.

[0050] The word line capping layer 134 may be disposed on the word line WL. The word line capping layer 134 may completely cover the upper surface of the word line WL. The lower surface of the word line capping layer 134 may contact the word line WL. The side surface of the word line capping layer 134 may be covered by the gate insulating layer 132.

[0051] The word line capping layer 134 may include silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof However, the position, shape, and material of the word line capping layer 134 are not limited thereto but may be variously changed.

[0052] A semiconductor device according to some example embodiments may include a plurality of bit lines BL.

[0053] Each of the plurality of bit lines BL may extend along a second direction Y crossing the first direction X, and may be spaced apart from each other along the first direction X at regular intervals.

[0054] Each of the plurality of bit lines BL may cross the active region AR and the word line WL. The plurality of bit lines BL may be disposed on the word line WL. In some example embodiments, the bit line BL may cross the active region AR in a direction different from that of the word line WL. For example, the word line WL may cross the active region AR in a first direction X, and the bit line BL may cross the active region AR in a second direction Y.

[0055] One bit line BL may overlap a plurality of active regions AR adjacent to each other along the second direction Y (eg, overlap in the third direction Z). Each of the plurality of bit lines BL may be connected to the active region AR through a direct contact DC.

[0056] One bit line BL may be connected to a plurality of active regions AR adjacent along the second direction Y. Each of the plurality of active regions AR may be connected to one bit line BL. A central portion of the active region AR may be connected to the bit line BL. However, this is an example, and the connection form of the bit line BL to the active region AR may be variously changed.

[0057] The substrate 100 may include a direct contact trench DCT. The direct contact trench DCT may be disposed on the active region AR.

[0058] The trench spacer 650 may be conformally disposed on a portion of an inner sidewall of the direct contact trench DCT. The trench spacer 650 is disposed on an inner sidewall of the direct contact trench DCT overlapping the bit line BL in the third direction Z and may be spaced apart along the second direction Y within the direct contact trench DCT.

[0059] That is, the trench spacer 650 overlaps the bit line BL on the inner sidewall of the direct contact trench DCT in the third direction Z, and may be disposed only on the inner sidewalls of the direct contact trench DCT on one side and the other side disposed in the second direction Y.

[0060] In other words, the trench spacer 650 overlaps the bit line BL in the third direction Z, but may not be disposed on inner sidewalls directly contacting the trench DCT on one side and the other side disposed in the first direction X.

[0061] Will refer to it later Fig.15 and Fig.16 In the process step of forming the direct contact DC, the trench spacer 650 may be a portion of the trench spacer 650 disposed on the inner sidewall of the direct contact trench DCT that remains after being etched together with the first material layer 150a. Detailed description of this will be described later.

[0062] The trench spacer 650 may include a metal, a metal nitride, or any combination thereof. For example, the trench spacer 650 may include a metal such as Ti or Ta and / or a metal nitride such as TiN or TaN.

[0063] As another example, the trench spacer 650 may include a metal such as W, Mo, Au, Cu, Al, Ni, or Co. However, the material included in the trench spacer 650 is not limited thereto but may be variously changed.

[0064] The direct contact DC may be disposed within the direct contact trench DCT. The direct contact DC may be disposed substantially at a center portion of the direct contact trench DCT.

[0065] A side surface of the direct contact DC in the direct contact trench DCT disposed in the second direction Y may directly contact the trench spacer 650. A side surface of the direct contact DC in the direct contact trench DCT disposed in the first direction X may be spaced apart from an inner surface of the direct contact trench DCT and the trench spacer 650.

[0066] The word line WL may be disposed on both sides (eg, opposite sides) of the direct contact DC, and the direct contact DC may overlap the word line WL in the third direction Z. A lower surface DC_B of the direct contact DC may be disposed at a level higher than that of an upper surface WL_U of the word line WL.

[0067] As used herein, the "level" of an element (e.g., a surface thereof) may be understood to refer to the distance of the element from a reference position (e.g., the lower surface 100b of the substrate 100) in the third direction Z. When one element is described as being at a level higher than the level of another element, the one element may be understood to be positioned farther from the reference position than the other element in the positive third direction +Z.

[0068] The trench spacer 650 and the word line capping layer 134 may be disposed between the direct contact DC and the word line WL. One side surface of the trench spacer 650 may contact the direct contact DC, and the other side surface of the trench spacer 650 may contact the word line capping layer 134 .

[0069] Therefore, the word line WL and the direct contact DC may be insulated by the trench spacer 650 and the word line capping layer 134 .

[0070] The silicide layer 140 may be disposed between the direct contact DC and the active region AR (eg, at least Figure 4 The direct contact DC may be connected to the active region AR by the silicide layer 140 disposed between the direct contact DC. That is, the upper surface of the silicide layer 140 may contact the direct contact DC, and the lower surface of the silicide layer 140 may contact the active region AR.

[0071] The silicide layer 140 may include a metal silicide material. For example, the silicide layer 140 may include a metal silicide material such as titanium silicide, cobalt silicide, nickel silicide, and manganese silicide. However, the material included in the silicide layer 140 is not limited thereto, but may be variously changed.

[0072] The direct contact DC may include a metal material. The metal material may include a metal, a metal nitride, or any combination thereof. For example, the direct contact DC may include a metal such as Ti or Ta and / or a metal nitride such as TiN or TaN.

[0073] As another example, the direct contact DC may include a metal such as W, Mo, Au, Cu, Al, Ni, or Co. However, the material included in the direct contact DC is not limited thereto but may be variously changed.

[0074] As described above, when the silicide layer 140 is disposed between the active region AR and the direct contact DC including different materials, electrical contact between the active region AR and the direct contact DC may be improved.

[0075] The bit lines BL may be disposed on the substrate 100 and the direct contact DC. That is, some of the bit lines BL may be disposed on the device isolation layer 112, and the remaining bit lines BL may be disposed on the direct contact DC.

[0076] In a semiconductor device according to some example embodiments, the bit line BL may include a metal material different from a metal material of the direct contact DC. The bit line BL may include a plurality of layers stacked sequentially, and at least one of the plurality of layers constituting the bit line BL may include a metal material different from the metal material of the direct contact DC. For example, the bit line BL may include a first conductive layer 151 and a second conductive layer 153, and at least one of the first conductive layer 151 and the second conductive layer 153 may include a metal material different from the metal material of the direct contact DC.

[0077] Specifically, the first conductive layer 151 and the second conductive layer 153 may include a conductive material. For example, the first conductive layer 151 may include a metal such as Ti or Ta and / or a metal nitride such as TiN or TaN. The second conductive layer 153 may include a metal such as W, Mo, Au, Cu, Al, Ni, or Co. However, the number and material of the conductive layers constituting the bit line BL are not limited thereto, but may be variously changed.

[0078] For example, the bit line BL may include a conductive layer other than the first conductive layer 151 and the second conductive layer 153, and the bit line BL may include three conductive layers or four conductive layers. As another example, the first conductive layer 151 may include a metal such as W, Mo, Au, Cu, Al, Ni, and Co, and the second conductive layer 153 may include a metal such as Ti and Ta and / or a metal nitride such as TiN and TaN.

[0079] The first conductive layer 151 of the bit line BL disposed on the device isolation layer 112 may be disposed at a level higher than that of the upper surface of the direct contact DC.

[0080] The bit line BL disposed on the direct contact DC may directly contact the direct contact DC. That is, the first conductive layer 151 of the bit line BL may directly contact the upper surface of the direct contact DC.

[0081] The bit line cover layer 155 may be disposed on the bit line BL. The bit line BL and the bit line cover layer 155 may form a bit line structure BLS. The bit line cover layer 155 may overlap the bit line BL and the direct contact DC in the third direction Z.

[0082] The bit line BL and the direct contact DC may be patterned by using the bit line capping layer 155 as a mask. A plan shape of the bit line BL may be substantially the same as a plan shape of the bit line capping layer 155.

[0083] The bit line capping layer 155 is shown to be in contact with the second conductive layer 153 of the bit line BL, but is not limited thereto. Another layer may be further provided between the bit line capping layer 155 and the second conductive layer 153 of the bit line BL.

[0084] The bit line capping layer 155 may include silicon nitride. However, the material of the bit line capping layer 155 is not limited thereto but may be variously changed.

[0085] The bit line spacer structure 620 may be disposed on both sides of the bit line structure BLS. The bit line spacer structure 620 may cover side surfaces of the bit line capping layer 155, side surfaces of the bit lines BL, and side surfaces of the direct contacts DC.

[0086] The bit line spacer structure 620 may extend substantially along a side surface of the bit line structure BLS in the third direction Z. At least a portion of the bit line spacer structure 620 may be disposed within the direct contact trench DCT. In the direct contact trench DCT, the bit line spacer structure 620 may be disposed on both sides of the direct contact DC.

[0087] The bit line spacer structure 620 may be formed of multiple layers made of a combination of various types of insulating materials.

[0088] The bit line spacer structure 620 may include first, second, third, fourth, and fifth bit line spacers 621, 623, 625, 627, and 629. However, it is not limited thereto, and the number and structure of layers constituting the bit line spacer structure 620 may be variously changed.

[0089] In addition, the bit line spacer structure 620 may be formed of a single layer. In some cases, the bit line spacer structure 620 may be formed as an air spacer structure surrounded by spacers and having an air space.

[0090] The first bit line spacer 621 may be disposed on the upper surface of the direct contact member DC. The first bit line spacer 621 may cover the side surface of the bit line structure BLS. The first bit line spacer 621 may cover the upper surface of the direct contact member DC. That is, the first bit line spacer 621 may cover the upper surface of the direct contact member DC that does not overlap with the bit line structure BLS in the third direction Z among the upper surfaces of the direct contact member DC. For example, referring to Figure 4The first bit line spacer 621 may cover (e.g., directly contact) a side surface BL_S of the bit line BL, and may also cover (e.g., directly contact) at least a portion DC_Ua of an upper surface DC_U of the direct contact member DC, which portion DC_Ua does not overlap with (e.g., is exposed from) the bit line BL in a third direction Z.

[0091] Therefore, the upper surface of the direct contact DC may directly contact the first conductive layer 151 of the bit line BL and the first bit line spacer 621 , and the upper surface of the direct contact DC may be completely covered by the first conductive layer 151 of the bit line BL and the first bit line spacer 621 .

[0092] The second bit line spacer 623 may be disposed on the first bit line spacer 621. The second bit line spacer 623 may cover the side surface of the first bit line spacer 621 and the side surface of the direct contact DC. A portion of the second bit line spacer 623 is disposed in the direct contact trench DCT and may cover the upper surface of the silicide layer 140 and the side and bottom surfaces of the direct contact trench DCT.

[0093] The third bit line spacer 625 may be disposed on the second bit line spacer 623. The lower surface and the side surface of the third bit line spacer 625 may be surrounded by the second bit line spacer 623. The third bit line spacer 625 may be disposed in the direct contact trench DCT. The third bit line spacer 625 may fill the direct contact trench DCT. The third bit line spacer 625 may be disposed on both sides of the direct contact DC in the direct contact trench DCT.

[0094] The fourth bit line spacer 627 may be disposed on the second bit line spacer 623 and the third bit line spacer 625. That is, the fourth bit line spacer 627 may be disposed on a side surface of the second bit line spacer 623 and an upper surface of the third bit line spacer 625.

[0095] The fourth bit line spacer 627 may overlap the second bit line spacer 623 in the first direction X, and may overlap the third bit line spacer 625 in the third direction Z. The fourth bit line spacer 627 may extend in the third direction Z substantially along side surfaces of the second bit line spacer 623 .

[0096] The fifth bit line spacer 629 may be disposed on the third bit line spacer 625 and the fourth bit line spacer 627. The fifth bit line spacer 629 may be disposed on an upper surface of the third bit line spacer 625 and a side surface of the fourth bit line spacer 627.

[0097] The fifth bit line spacer 629 may overlap the third bit line spacer 625 in the third direction Z, and may overlap the third bit line spacer 625 and the fourth bit line spacer 627 in the first direction X. The fifth bit line spacer 629 may extend substantially along a side surface of the fourth bit line spacer 627 in the third direction Z. The fifth bit line spacer 629 may extend parallel to the first bit line spacer 621, the second bit line spacer 623, and the fourth bit line spacer 627. A lower surface and a side surface of the fifth bit line spacer 629 may contact the third bit line spacer 625 and the fourth bit line spacer 627.

[0098] The bit line spacer structure 620 may include an insulating material. At least one of the first bit line spacer 621, the second bit line spacer 623, the third bit line spacer 625, the fourth bit line spacer 627, and the fifth bit line spacer 629 may include different materials.

[0099] Each of the first bit line spacer 621, the second bit line spacer 623, the third bit line spacer 625, the fourth bit line spacer 627 and the fifth bit line spacer 629 may include at least one of silicon oxide, silicon nitride, silicon oxynitride and a low-k material with a low dielectric constant (such as SiOCN, SiOC, SiBN, SiBCN and / or SiBCON).

[0100] For example, the first bit line spacer 621 may include a low-k material having a low dielectric constant (such as SiOCN, SiOC, SiBN, SiBCN and SiBCON), the second bit line spacer 623, the third bit line spacer 625 and the fifth bit line spacer 629 may include silicon nitride, and the fourth bit line spacer 627 may include silicon oxide.

[0101] As another example, the first bit line spacer 621 may include silicon oxide or silicon nitride, the second bit line spacer 623, the third bit line spacer 625, and the fifth bit line spacer 629 may include silicon nitride, and the fourth bit line spacer 627 may include silicon oxide. However, the material included in the bit line spacer structure 620 is not limited thereto but may be variously changed.

[0102] The insulating layer 640 may be disposed under the bit line BL. The insulating layer 640 may be disposed between the bit line BL and the device isolation layer 112. The silicide layer 140 and the direct contact DC are disposed between the bit line BL and the active region AR, but the insulating layer 640 may not be disposed between the bit line BL and the active region AR.

[0103] The insulating layer 640 may be disposed on the word line structure WLS. The insulating layer 640 may be disposed between the word line structure WLS and the bit line BL. The insulating layer 640 may include a first insulating layer 642, a second insulating layer 644, and a third insulating layer 646 sequentially stacked from below.

[0104] At least some of the first insulating layer 642, the second insulating layer 644, and the third insulating layer 646 may have different widths. For example, the width of the first insulating layer 642 and the width of the second insulating layer 644 may be substantially the same, and the width of the third insulating layer 646 may be smaller than the width of the first insulating layer 642 and the width of the second insulating layer 644. The width of the third insulating layer 646 may be greater than the width of the bit line BL and the width of the bit line capping layer 155. In addition, the width of the first insulating layer 642 and the width of the second insulating layer 644 may be greater than the width of the bit line BL and the width of the bit line capping layer 155.

[0105] The insulating layer 640 may be covered by the bit line spacer structure 620. For example, the upper surface of the third insulating layer 646 may be covered by the first bit line spacer 621, and the side surface of the third insulating layer 646 may be covered by the second bit line spacer 623. The upper surface of the second insulating layer 644 may be covered by the second bit line spacer 623 and the fifth bit line spacer 629.

[0106] The insulating layer 640 may include an insulating material. That is, each of the first insulating layer 642, the second insulating layer 644, and the third insulating layer 646 may include an insulating material. For example, the first insulating layer 642 may include silicon oxide. The second insulating layer 644 may include a material whose etching selectivity is different from that of the first insulating layer 642. For example, the second insulating layer 644 may include silicon nitride. For example, the third insulating layer 646 may include silicon oxide or silicon nitride. However, the configuration, width, and material of the insulating layer 640 are not limited thereto, but may be changed differently.

[0107] The semiconductor device according to some example embodiments may include a plurality of buried contacts BC. The buried contacts BC may be disposed between a plurality of bit lines BL (eg, between bit lines BL adjacent to each other along at least a first direction X, such as Figure 2 ).

[0108] The plurality of buried contacts BC may be arranged to be spaced apart from each other along the first direction X and the second direction Y. For example, the plurality of buried contacts BC may be arranged to be spaced apart from each other in the second direction Y between adjacent two bit lines BL.

[0109] Furthermore, the plurality of buried contacts BC may be arranged to be spaced apart from each other between adjacent two word lines WL in the first direction X. However, the arrangement form of the plurality of buried contacts BC is not limited thereto but may be variously changed.

[0110] At least a portion of the buried contact BC may overlap the active region AR in the third direction Z, and another portion of the buried contact BC may overlap the device isolation layer 112 in the third direction Z.

[0111] The buried contact BC may be electrically connected to the active region AR. The buried contact BC may directly contact the active region AR. At least some of the lower surface and the side surface of the buried contact BC may be surrounded by the active region AR. However, it is not limited thereto, but another layer may be further provided between the buried contact BC and the active region AR, and the buried contact BC may be connected to the active region AR through another layer.

[0112] The bit line spacer structure 620 may be disposed on both sides of the buried contact BC. That is, the bit line spacer structure 620 may be disposed between the buried contact BC and the bit line BL.

[0113] For example, one side surface of the buried contact BC may contact the active region AR, the insulating layer 640, and the fifth bit line spacer 629, and the other side surface of the buried contact BC may contact the third bit line spacer 625 and the fifth bit line spacer 629. The lower surface of the buried contact BC may contact the device isolation layer 112 and the first bit line spacer 621. However, the arrangement relationship between the buried contact BC and the bit line spacer structure 620 is not limited thereto, but may be variously changed.

[0114] The upper surface of the buried contact BC may be disposed at a level higher than that of the upper surface of the bit line BL, and the lower surface of the buried contact BC may be disposed at a level between the upper surface and the lower surface of the direct contact DC. However, the arrangement relationship between the buried contact BC and the bit line BL and between the buried contact BC and the direct contact DC is not limited thereto, but may be changed variously.

[0115] The buried contact BC may include a conductive material, for example, polysilicon doped with impurities, but is not limited thereto.

[0116] A semiconductor device according to some example embodiments may include a plurality of bonding pads LP.

[0117] The bonding pad LP may be disposed on the buried contact BC.

[0118] The plurality of bonding pads LP may be arranged to be spaced apart from each other along the first direction X and the second direction Y. The plurality of bonding pads LP may be arranged in a row along the first direction X. The plurality of bonding pads LP may be arranged in a zigzag form along the second direction Y. For example, the plurality of bonding pads LP may be alternately arranged on the left and right sides of the bit line BL. However, the arrangement form of the plurality of bonding pads LP is not limited thereto, but may be changed variously.

[0119] The bonding pad LP may cover the upper surface of the buried contact BC and may overlap the buried contact BC in the third direction Z. At least a portion of the bonding pad LP may overlap the bit line spacer structure 620 in the third direction Z and may overlap the bit line BL in the third direction Z.

[0120] The upper surface of the bonding pad LP may be disposed at a level higher than that of the upper surface of the bit line capping layer 155. The bit line spacer structure 620 may be disposed on both sides of the bonding pad LP. The bit line spacer structure 620 may be disposed between the bonding pad LP and the bit line capping layer 155.

[0121] The bonding pad LP may be electrically connected to the buried contact BC. The bonding pad LP may directly contact the buried contact BC. The bonding pad LP may be electrically connected to the active region AR through the buried contact BC.

[0122] The bonding pad LP may include a metal silicide layer 171 , a conductive barrier layer 173 , and a conductive layer 175 .

[0123] The metal silicide layer 171 may be disposed on the buried contact BC, the conductive barrier layer 173 may be disposed on the metal silicide layer 171 , and the conductive layer 175 may be disposed on the conductive barrier layer 173 .

[0124] The metal silicide layer 171 may directly contact the buried contact BC. The metal silicide layer 171 may completely cover the upper surface of the buried contact BC. The upper surface of the buried contact BC may be formed to have a shape concave toward the buried contact BC, and the metal silicide layer 171 may have a shape concave along the upper surface of the buried contact BC.

[0125] The bit line spacer structure 620 may be disposed on both sides of the metal silicide layer 171. For example, the metal silicide layer 171 may contact the fifth bit line spacer 629.

[0126] The metal silicide layer 171 may include a metal silicide material such as cobalt silicide, nickel silicide, manganese silicide, etc. However, the shape and material of the metal silicide layer 171 are not limited thereto but may be variously changed. In addition, in some example embodiments, the metal silicide layer 171 may be omitted.

[0127] The conductive barrier layer 173 may be disposed between the metal silicide layer 171 and the conductive layer 175. A lower surface of the conductive barrier layer 173 may contact the metal silicide layer 171. The bit line spacer structure 620 may be disposed on both side surfaces of the conductive barrier layer 173. For example, the conductive barrier layer 173 may cover an upper surface of the first bit line spacer 621, an upper surface of the second bit line spacer 623, an upper surface of the fourth bit line spacer 627, and an upper surface of the fifth bit line spacer 629.

[0128] The conductive barrier layer 173 may include Ti, TiN, or any combination thereof However, the shape and material of the conductive barrier layer 173 are not limited thereto but may be variously changed.

[0129] A lower surface of the conductive layer 175 may contact the conductive barrier layer 173. At least some of the lower surface and side surfaces of the conductive layer 175 may be surrounded by the conductive barrier layer 173. The conductive barrier layer 173 may be disposed between the conductive layer 175 and the metal silicide layer 171. The conductive barrier layer 173 may be disposed between the conductive layer 175 and the bit line spacer structure 620.

[0130] The conductive layer 175 may include metal, metal nitride, polysilicon doped with impurities, or any combination thereof. For example, the conductive layer 175 may include W. However, the shape and material of the conductive layer 175 are not limited thereto but may be variously changed.

[0131] The insulating pattern 660 may be disposed between the plurality of bonding pads LP. The insulating pattern 660 may fill the space between the plurality of bonding pads LP. Therefore, the plurality of bonding pads LP may be separated from each other by the insulating pattern 660.

[0132] The insulating pattern 660 may include silicon nitride, silicon oxynitride, silicon oxide, or any combination thereof. The insulating pattern 660 may be formed of a single layer or a plurality of layers.

[0133] For example, the insulating pattern 660 may include a first insulating pattern layer and a second insulating pattern layer stacked. The first insulating pattern layer may include silicon oxide or a low-k material with a low dielectric constant (such as SiOCH or SiOC), and the second insulating pattern layer may include silicon nitride or silicon oxynitride. However, the shape and material of the insulating pattern 660 are not limited thereto, but may be changed variously.

[0134] Although not shown, the capacitor structure may be disposed on the bonding pad LP. The capacitor structure may include a first capacitor electrode, a second capacitor electrode, and a dielectric layer disposed between the first capacitor electrode and the second capacitor electrode.

[0135] The first capacitor electrode may contact the bonding pad LP and may be electrically connected to the bonding pad LP. The capacitor structure may be electrically connected to the active region AR through the bonding pad LP and the buried contact BC.

[0136] The first capacitor electrode may be disposed on each bonding pad LP, and the plurality of first capacitor electrodes may be disposed to be separated from each other. The second capacitor electrodes of the plurality of capacitor structures may be applied with the same voltage and may be integrally formed. The dielectric layers of the plurality of capacitor structures may be integrally formed.

[0137] In the following, in reference to Figures 4 to 7 In a semiconductor device according to some example embodiments, the arrangement relationship between a direct contact DC and components disposed around the direct contact DC, the relationship between the width of the direct contact DC and the width of the bit line BL, and the relationship between the widths of spacers constituting the bit line spacer structure 620 will be described.

[0138] Figure 4 According to some example embodiments Figure 2 A local enlarged view of area R1. Figure 5 , Figure 6 and Figure 7 A partially enlarged view of a cross section of a semiconductor device according to some example embodiments is shown.

[0139] Specifically, Figures 5 to 7 According to some example embodiments, Figure 2 Region R1 corresponds to region R2, region R3 and region R4.

[0140] Reference Figure 4 As described above, the direct contact DC and the bit line BL may be sequentially disposed on the silicide layer 140. That is, the direct contact DC may be disposed on the silicide layer 140, and the bit line BL (e.g., the lower surface thereof) may be disposed on the direct contact DC (e.g., the upper surface DC_U thereof) (e.g., directly or indirectly disposed on the direct contact DC (e.g., the upper surface DC_U thereof)).

[0141] Therefore, the lower surface DC_B of the direct contact DC may directly contact the silicide layer 140, and the upper surface DC_U of the direct contact DC may directly contact the first conductive layer 151 of the bit line BL. However, it is not limited thereto, and in some example embodiments, other layers may be further provided between the direct contact DC and the upper silicide layer 140 and between the direct contact DC and the bit line BL.

[0142] In some example embodiments, the bit line BL may have a first width W1, the direct contact DC may have a second width W2, and the silicide layer 140 may have a third width W3. Here, the width may mean a width along the first direction X. As shown, the width of the direct contact DC (e.g., the second width W2 in the first direction X) may be different from (e.g., greater than) the width of the bit line BL (e.g., the first width W1 in the first direction X).

[0143] The first conductive layer 151 and the second conductive layer 153 of the bit line BL may extend in the third direction Z, and may have a constant width along the first direction X. That is, the first conductive layer 151 and the second conductive layer 153 may have a first width W1 according to the first direction X. However, it is not limited thereto, and in some example embodiments, the first conductive layer 151 and the second conductive layer 153 of the bit line BL may have different widths along the first direction X.

[0144] The direct contact DC may extend in the third direction Z and may have a constant width along the first direction X. The widths of the upper surface DC_U and the lower surface DC_B of the direct contact DC may be substantially the same. That is, the upper surface DC_U and the lower surface DC_B of the direct contact DC may have a second width W2 in the first direction X.

[0145] In some example embodiments, the first width W1 and the second width W2 may be different. For example, the second width W2 may be greater than the first width W1. That is, the width of the direct contact DC along the first direction X may be greater than the width of the bit line BL along the first direction X.

[0146] Therefore, at least a portion of the upper surface of the direct contact DC may not be covered by the bit line BL. As described above, the upper surface of the portion of the direct contact DC not covered by the bit line BL may be covered by the first bit line spacer 621. The first bit line spacer 621 may directly contact both the side surface BL_S of the bit line BL and the upper surface DC_U of the direct contact DC.

[0147] Therefore, the width of the direct contact DC may be the same as or substantially the same as the sum of the width of the bit line BL and the width of the first bit line spacer 621. That is, the width of the first bit line spacer 621 may be the same as or substantially the same as the difference between the width of the direct contact DC and the width of the bit line BL (e.g., equal to or substantially equal to the difference between the width of the direct contact DC and the width of the bit line BL). Here, the width of each constituent element may represent the width along the first direction X.

[0148] In some example embodiments, the second width W2 (e.g., the width of the direct contact DC in the first direction X) and the third width W3 (e.g., the width of the silicide layer 140 in the first direction X) may be different. For example, the third width W3 may be greater than the second width W2. That is, the width of the direct contact DC along the first direction X may be less than the width of the silicide layer 140 along the first direction X.

[0149] The relationship among the first width W1 , the second width W2 , and the third width W3 has been described above, but is not limited thereto but may be variously changed.

[0150] Therefore, since the silicide layer 140 , the direct contact DC, and the bit line BL have different widths, their side surfaces may be aligned at different boundaries.

[0151] Specifically, the side surface DC_S of the direct contact DC may be disposed on the upper surface of the silicide layer 140. That is, the side surface 140S of the silicide layer 140 may protrude more than the side surface DC_S of the direct contact DC toward the first direction X. In other words, the side surface DC_S of the direct contact DC may be disposed between the two side surfaces 140S of the silicide layer 140.

[0152] The side surface BL_S of the bit line BL may be disposed on the upper surface DC_U of the direct contact DC. That is, the side surface DC_S of the direct contact DC may protrude more toward the first direction X than the side surface BL_S of the bit line BL. For example, the side surface DC_S of the direct contact DC may protrude outward (e.g., in the first direction X) from the side surface BL_S of the bit line BL. In other words, the side surface BL_S of the bit line BL may be disposed between two side surfaces DC_S of the direct contact DC.

[0153] In addition, the side surface 140S of the silicide layer 140 may be disposed to protrude more than the side surface BL_S of the bit line BL toward the first direction X. In other words, the side surface BL_S of the bit line BL may be disposed between both side surfaces 140S of the silicide layer 140 .

[0154] In addition, the side surface 621S of the first bit line spacer 621 disposed on the side surface of the bit line BL may be aligned at substantially the same boundary with the side surface DC_S of the direct contact DC. That is, the side surface 621S of the first bit line spacer 621 that covers the upper surface of the direct contact DC together with the bit line BL may be aligned at substantially the same boundary with the side surface DC_S of the direct contact DC in the third direction Z. For example, the side surface 621S of the first bit line spacer 621 may be coplanar or substantially coplanar with the side surface DC_S of the direct contact DC at the interface between the first bit line spacer 621 and the direct contact DC. In other words, the side surface 621S of the first bit line spacer 621 and the side surface DC_S of the direct contact DC may extend continuously along the third direction Z.

[0155] The first bit line spacer 621, the second bit line spacer 623, the fourth bit line spacer 627, and the fifth bit line spacer 629 may have a first thickness D1, a second thickness D2, a third thickness D3, and a fourth thickness D4, respectively. Here, each of the first thickness D1, the second thickness D2, the third thickness D3, and the fourth thickness D4 may mean a thickness along the first direction X. In some example embodiments, the first bit line spacer 621 may have a thickness of about 0.5 nm to about 1 nm, for example, the first thickness D1 (e.g., the first thickness D1 in the first direction X).

[0156] At least one of the first thickness D1, the second thickness D2, the third thickness D3, and the fourth thickness D4 may be different. For example, the first thickness D1 may be thicker than the second thickness D2 and thinner than the third thickness D3 and the fourth thickness D4. The second thickness D2 may be thinner than the first thickness D1, the third thickness D3, and the fourth thickness D4. The third thickness D3 may be thicker than the first thickness D1, the second thickness D2, and the fourth thickness D4. The fourth thickness D4 may be thicker than the first thickness D1 and the second thickness D2 and thinner than the third thickness D3. That is, the second thickness D2 of the bit line spacer structure 620 may be the thinnest, and the third thickness D3 of the bit line spacer structure 620 may be the thickest. However, the relationship between the first thickness D1 of the first bit line spacer 621, the second thickness D2 of the second bit line spacer 623, the third thickness D3 of the fourth bit line spacer 627, and the fourth thickness D4 of the fifth bit line spacer 629 included in the bit line spacer structure 620 is not limited thereto, but may be changed differently.

[0157] According to include Figure 5 Some example embodiments of the example embodiments include Figure 4Unlike some example embodiments shown in FIG. 1 , a side surface DC_1S of the direct contact DC_1 and a side surface 621S of the first bit line spacer 621 may be aligned at different boundaries. Therefore, the shape of the bit line spacer structure 620 disposed between the direct contact DC_1 and the buried contact BC may vary.

[0158] Specifically, the side surface DC_1S of the direct contact DC_1 may protrude farther in the first direction X than the side surface 621S of the first bit line spacer 621. For example, the side surface DC_1S of the direct contact DC_1 may protrude outward (e.g., in the first direction X) from the side surface 621S of the first bit line spacer 621. Therefore, the side surface DC_1S of the direct contact DC_1 may be aligned at a boundary different from the side surface 621S of the first bit line spacer 621. That is, the side surface 621S of the first bit line spacer 621 may be disposed on the upper surface DC_1U of the direct contact DC_1 between the two side surfaces DC_1S of the direct contact DC_1. As shown, the width of the lower surface DC_1B of the direct contact DC (e.g., the width in the first direction X) may be greater than the width of the bit line BL (e.g., the width in the first direction X).

[0159] The first bit line spacer 621 and the second bit line spacer 623 may be disposed on the upper surface DC_1U of the direct contact DC_1. Figure 4 Unlike some example embodiments shown in FIG. 1 , in which only the first bit line spacer 621 is disposed on the upper surface DC_1U of the direct contact DC, in some example embodiments, the first bit line spacer 621 and the second bit line spacer 623 may be disposed on the upper surface DC_1U of the direct contact DC_1. In other words, the upper surface DC_1U of the direct contact DC_1 may be covered by the bit line BL, the first bit line spacer 621, and the second bit line spacer 623.

[0160] When the side surface DC_1S of the direct contact DC_1 protrudes farther than the side surface 621S of the first bit line spacer 621 in the first direction X, the second bit line spacer 623 may be conformally disposed on the upper surface DC_1U and the side surface DC_1S of the direct contact DC_1 .

[0161] In addition, when the side surface DC_1S of the direct contact DC_1 protrudes farther in the first direction X than the side surface 621S of the first bit line spacer 621, the arrangement shape of the third bit line spacer 625 disposed on the second bit line spacer 623 may be the same as that according to Figure 4 An arrangement shape of the third bit line spacer 625 of some example embodiments shown in FIG. 1 is different.

[0162] according to Figure 6 and Figure 7 The cross-sectional shape of the direct contacts DC_2 and DC_3 of the embodiment shown in FIG. Figure 4 The cross-sectional shape of the direct contact DC of some example embodiments shown in FIG. 6 is different. Therefore, the shape of the bit line spacer structure 620 disposed between the direct contacts DC_2 and DC_3 and the buried contact BC may vary.

[0163] according to Figure 6 In some example embodiments shown in FIG. 1 , the width of the direct contact DC_2 along the first direction X may decrease from the upper surface DC_2U and the lower surface DC_2B of the direct contact DC_2 toward the central portion of the direct contact DC_2. That is, the width along the first direction X may decrease from the upper surface DC_2U to the central portion of the direct contact DC_2, and the width along the first direction X may increase from the central portion of the direct contact DC_2 to the lower surface DC_2B of the direct contact DC_2.

[0164] In addition, the side surface DC_2S of the direct contact DC_2 according to some example embodiments may include a curve. That is, the two side surfaces DC_2S of the direct contact DC_2 may have a shape that is concave toward the central axis of the direct contact DC_2. However, the shape of the side surface DC_2S of the direct contact DC_2 is not limited thereto, but may be changed differently. For example, the side surface DC_2S of the direct contact DC_2 may include a straight line shape in addition to the curve.

[0165] Therefore, the side surface of the second bit line spacer 623 disposed between the direct contact DC_2 and the buried contact BC along the contour of the side surface DC_2S of the direct contact DC_2 may include a curve. In addition, the side surface of the third bit line spacer 625 disposed on the second bit line spacer 623 between the direct contact DC_2 and the buried contact BC may also include a curve.

[0166] The bit line BL may have a first width W1 along the first direction X, the upper surface DC_2U and the lower surface DC_2B of the direct contact DC_2 may have a second width W2 along the first direction X, the silicide layer 140 may have a third width W3 along the first direction X, and the central portion of the direct contact DC_2 may have a fourth width W4 along the first direction X.

[0167] In some example embodiments, at least one of the first width W1, the second width W2, the third width W3, and the fourth width W4 may be different. For example, the second width W2 may be greater than the first width W1, and the third width W3 may be greater than the second width W2. In addition, the fourth width W4 may be greater than the first width W1 and less than the second width W2 and the third width W3. However, it is not limited thereto, and the relationship between the first width W1, the second width W2, the third width W3, and the fourth width W4 may be changed variously.

[0168] According to include Figure 7 Some example embodiments of the example embodiments shown in Figure 6 Unlike the side surface DC_2S of the direct contact DC_2 shown in FIG, the side surface DC_3S of the direct contact DC_3 may include both a curve and a straight line. That is, a portion of the side surface DC_3S of the direct contact DC_3 disposed on the direct contact DC_3 (e.g., disposed at the upper portion of the direct contact DC_3) and connected to the upper surface DC_3U of the direct contact DC_3 includes a curve, and the remaining side surface DC_3S of the direct contact DC_3 may include a straight line.

[0169] The width of the direct contact DC_3 along the first direction X may decrease from the upper surface DC3_U of the direct contact DC_3 to the lower surface DC_3B, and then may remain constant. That is, the width of the direct contact DC_3 portion including the curve in the side surface DC_3S of the direct contact DC_3 along the first direction X may decrease from the upper surface DC_3U of the direct contact DC_3 to the lower surface DC_3B, and the width of the direct contact DC_3 portion including the straight line in the side surface DC_3S of the direct contact DC_3 along the first direction X may remain constant.

[0170] Therefore, the upper surface DC_3U and the lower surface DC_3B of the direct contact DC_3 may have different widths in the first direction X. As shown, the width of the upper surface DC_3U of the direct contact DC (e.g., the second width W2 in the first direction X) may be greater than the width of the lower surface DC_3B of the direct contact DC (e.g., the fourth width W4 in the first direction X). In addition, the side surface of the second bit line spacer 623 and the side surface of the third bit line spacer 625, which are disposed along the contour of the side surface DC_3S of the direct contact DC_3 between the direct contact DC_3 and the buried contact BC, may have a shape substantially corresponding to (e.g., substantially complementary to) the side surface DC_3S of the direct contact DC_3.

[0171] The bit line BL may have a first width W1 along the first direction X, the upper surface DC_3U of the direct contact DC_3 may have a second width W2 along the first direction X, the silicide layer 140 may have a third width W3 along the first direction X, and the lower surface DC_3B of the direct contact DC_3 may have a fourth width W4 along the first direction X.

[0172] In some example embodiments, at least one of the first width W1, the second width W2, the third width W3, and the fourth width W4 may be different. For example, the first width W1 may be smaller than the second width W2, the third width W3, and the fourth width W4. The second width W2 may be larger than the first width W1 and the fourth width W4 and smaller than the third width W3. The third width W3 may be larger than the first width W1, the second width W2, and the fourth width W4. The fourth width W4 may be larger than the first width W1 and smaller than the second width W2 and the third width W3.

[0173] That is, the width of the upper surface DC_3U of the direct contact DC_3 along the first direction X may be greater than the width of the lower surface DC_3B of the direct contact DC_3 along the first direction X, and the width of the lower surface DC_3B of the direct contact DC_3 along the first direction X may be greater than the width of the bit line BL along the first direction X. However, it is not limited thereto, and the relationship between the first width W1, the second width W2, the third width W3, and the fourth width W4 may be changed differently. For example, the fourth width W4 may be greater than the second width W2.

[0174] According to the semiconductor device according to some example embodiments, when the first bit line spacer 621 is disposed on the side surface of the bit line BL disposed on the direct contacts DC, DC_1, DC_2, and DC_3, the side surface of the bit line BL may be prevented from being exposed during a manufacturing process of the semiconductor device.

[0175] Therefore, the bit line BL may be prevented from being damaged due to galvanic corrosion between the bit line BL including a conductive material and the direct contacts DC, DC_1, DC_2, and DC_3 including a conductive material caused by a cleaning material during a manufacturing process of the semiconductor device. Detailed description of this will be described later.

[0176] Furthermore, when the first bit line spacer 621 disposed on the side surface of the bit line BL includes a low-k material, it is possible to prevent the bit line BL from being damaged and reduce parasitic capacitance that may occur between the bit line BL and the buried contact BC.

[0177] In the following, reference will be made to Figures 8 to 20 A semiconductor device according to some example embodiments is described. Figures 8 to 20In some example embodiments of the example embodiments shown in FIG. 1 , components identical to those in the previously described example embodiments are denoted by the same reference numerals, and redundant descriptions thereof will be omitted or simplified, and differences will be mainly described.

[0178] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 and Fig. 20 A cross-sectional view for explaining a method for manufacturing a semiconductor device according to some example embodiments is shown.

[0179] Specifically, Figures 8 to 20 The corresponding manufacturing process steps are shown along Figure 1 , to explain a method for fabricating a semiconductor device according to some example embodiments.

[0180] First, refer to Figure 8 A trench for isolating a plurality of devices may be formed in the substrate 100 , and a device isolation layer 112 may be formed to fill the trench. A plurality of active regions AR may be defined by the device isolation layer 112 .

[0181] A plurality of active regions AR may be disposed within the substrate 100, and the plurality of active regions AR may be isolated from each other by the device isolation layer 112. The device isolation layer 112 may be disposed on both sides (eg, opposite sides) of each active region AR.

[0182] Then, refer to Fig. 9 , a first insulating layer 642 , a second insulating layer 644 , and a third insulating layer 646 of the insulating layer 640 may be sequentially stacked on the substrate 100 to cover the active region AR and the device isolation layer 112 .

[0183] Thus, the first insulating layer 642, the second insulating layer 644, and the third insulating layer 646 may constitute the insulating layer 640. However, the structure of the insulating layer 640 is not limited thereto, and the insulating layer 640 may be formed as a single layer, a double layer, or four or more insulating layers.

[0184] The first insulating layer 642, the second insulating layer 644, and the third insulating layer 646 may each be made of an insulating material. For example, the first insulating layer 642 may include silicon oxide. The second insulating layer 644 may include a material whose etching selectivity is different from that of the first insulating layer 642. For example, the second insulating layer 644 may include silicon nitride. For example, the third insulating layer 646 may include silicon oxide or silicon nitride. However, the material of the insulating layer 640 is not limited thereto, but may be changed variously.

[0185] Next, refer to Fig.10 , a direct contact trench DCT exposing at least a portion of the active region AR may be formed by patterning the insulating layer 640 , the device isolation layer 112 , and a portion of the active region AR.

[0186] The direct contact trench DCT may be formed by forming a hard mask layer on the insulating layer 640 , patterning the hard mask layer using photo and etching processes, and then using the hard mask pattern.

[0187] That is, the third insulating layer 646, the second insulating layer 644, and the first insulating layer 642 may be sequentially etched using the hard mask pattern. When the first insulating layer 642 is etched, the upper surfaces of the active region AR and the device isolation layer 112 of the substrate 100 may be exposed. Subsequently, a direct contact trench DCT may be formed by etching the active region AR and the device isolation layer 112.

[0188] The active region AR may be disposed approximately at the center portion of the direct contact trench DCT. The active region AR and the device isolation layer 112 may constitute the bottom surface of the direct contact trench DCT. The device isolation layer 112 and the insulating layer 640 may constitute the sidewalls of the direct contact trench DCT.

[0189] In a cross-sectional view, the direct contact trench DCT may have a substantially quadrilateral shape. However, the shape of the direct contact trench DCT is not limited thereto but may be changed variously. For example, the direct contact trench DCT may have a shape whose width narrows toward the bottom surface. However, the formation method and shape of the direct contact trench DCT are not limited thereto but may be changed variously.

[0190] Then, refer to Fig.11 , a trench spacer 650 may be formed in the direct contact trench DCT. That is, the trench spacer 650 may be conformally formed along the contours of the sidewall and bottom surface of the direct contact trench DCT. Therefore, the trench spacer 650 may be disposed on the active region AR (e.g., the exposed upper surface of the active region AR), the device isolation layer 112, and the insulating layer 640.

[0191] The trench spacer 650 may include a metal, a metal nitride, or any combination thereof. For example, the trench spacer 650 may include a metal such as Ti or Ta and / or a metal nitride such as TiN or TaN. As another example, the trench spacer 650 may include a metal such as W, Mo, Au, Cu, Al, Ni, or Co. However, the material included in the trench spacer 650 is not limited thereto, but may be formed according to the first material layer (in the embodiment of the present invention) to be described later. Fig.15 150a) and in some example embodiments, the trench spacer 650 may be omitted.

[0192] Then, refer to Fig.12 , the upper surface of the active region AR may be exposed by etching a portion of the trench spacer 650. That is, the upper surface of the active region AR may be exposed by etching a portion of the trench spacer 650 disposed on the bottom surface directly contacting the trench DCT.

[0193] In some example embodiments, a process step of etching a portion of the trench spacer 650 may be simultaneously performed in a patterning step after forming the trench spacer 650 .

[0194] Subsequently, a first material layer 150a may be formed in the direct contact trench DCT. That is, the first material layer 150a may be formed on the trench spacer 650 and the active region AR.

[0195] First, a trench spacer 650 is formed in the direct contact trench DCT of the substrate 100 , and then, in a state where the trench spacer 650 is etched so that the upper surface of the active region AR is exposed, a first material layer 150 a may be formed to fill the inside of the direct contact trench DCT.

[0196] Subsequently, when a planarization process is performed until the upper surface of the insulating layer 640 is exposed, the upper surface of the first material layer 150a and the upper surface of the insulating layer 640 may be planarized. That is, the upper surface of the first material layer 150a and the upper surface of the third insulating layer 646 may be disposed at substantially the same level.

[0197] A lower surface of the first material layer 150a may contact the active region AR and the trench spacer 650. A side surface of the first material layer 150a may contact the trench spacer 650. An upper surface of the first material layer 150a and an upper surface of the insulating layer 640 may be flat.

[0198] The first material layer 150a may include a metal material. For example, the first material layer 150a may include a metal, a metal nitride, or any combination thereof. For example, the first material layer 150a may include a metal such as Ti or Ta and / or a metal nitride such as TiN or TaN.

[0199] As another example, the first material layer 150a may include a metal such as W, Mo, Au, Cu, Al, Ni, or Co. However, the material included in the direct contact DC is not limited thereto but may be variously changed.

[0200] The silicide layer 140 may be formed between the upper surface of the active region AR exposed by the trench spacer 650 and the first material layer 150a. That is, the silicide layer 140 may be formed by reacting the metal included in the first material layer 150a with the silicon included in the active region AR. In other words, after the first material layer 150a is formed on the active region AR exposed by the trench spacer 650 so that the active region AR and the first material layer 150a contact each other, when an annealing process is performed, the material included in the first material layer 150a and the material included in the active region AR may react to form the silicide layer 140 at the interface between the first material layer 150a and the active region AR.

[0201] The silicide layer 140 may include a metal silicide material. For example, the silicide layer 140 may include a metal silicide material such as titanium silicide, cobalt silicide, nickel silicide, and manganese silicide. However, the materials included in the silicide layer 140 and the method for forming the silicide layer 140 are not limited thereto, but may be variously changed.

[0202] Subsequently, a second material layer 150 b , a third material layer 150 c , and a fourth material layer 150 d may be sequentially stacked on the first material layer 150 a .

[0203] The lower surface of the second material layer 150b may contact the insulating layer 640, the first material layer 150a, and the trench spacer 650. The second material layer 150b may be disposed between the first material layer 150a and the third material layer 150c, and may be disposed between the insulating layer 640 and the third material layer 150c. The upper surface of the second material layer 150b may contact the third material layer 150c, and the upper surface of the third material layer 150c may contact the fourth material layer 150d.

[0204] The second material layer 150b and the third material layer 150c may include a conductive material. For example, the second material layer 150b may include a metal such as Ti or Ta and / or a metal nitride such as TiN or TaN. The third material layer 150c may include a metal such as W, Mo, Au, Cu, Al, Ni or Co. The fourth material layer 150d may include an insulating material. For example, the fourth material layer 150d may include silicon nitride. However, the materials included in the second material layer 150b, the third material layer 150c and the fourth material layer 150d are not limited thereto, but may be changed variously.

[0205] Then, refer to Fig.13 , the fourth material layer 150d, the third material layer 150c, and the second material layer 150b may be patterned. That is, at least some of the fourth material layer 150d, the third material layer 150c, and the second material layer 150b may be removed by performing a photo and etching process. The bit line structure BLS may be formed by a patterning process. In addition, in the step of patterning the fourth material layer 150d, the third material layer 150c, and the second material layer 150b, the upper surface of the bit line structure BLS may be patterned to have a curved shape.

[0206] Specifically, the bit line structure BLS may be formed by patterning the second material layer 150 b , the third material layer 150 c , and the fourth material layer 150 d . The bit line structure BLS may include a bit line BL and a bit line capping layer 155 .

[0207] The first conductive layer 151 of the bit line BL may be formed by patterning the second material layer 150b, and the second conductive layer 153 of the bit line BL may be formed by patterning the third material layer 150c. In addition, the bit line capping layer 155 may be formed by patterning the fourth material layer 150d.

[0208] The second conductive layer 153 may be disposed on the first conductive layer 151 of the bit line BL, and the bit line capping layer 155 may be disposed on the second conductive layer 153. In addition, the first conductive layer 151, the second conductive layer 153, and the bit line capping layer 155 of the bit line BL may be sequentially disposed on the upper surface of the first material layer 150a.

[0209] When the second material layer 150b is removed, the third insulating layer 646 disposed under the second material layer 150b may be exposed to the outside. When the third insulating layer 646 includes a material having an etching selectivity different from that of the second material layer 150b, the third insulating layer 646 may be used as an etching stop film in the step of patterning the fourth material layer 150d, the third material layer 150c, and the second material layer 150b.

[0210] In some example embodiments, when the fourth material layer 150d, the third material layer 150c, and the second material layer 150b are patterned, the third insulating layer 646 may be etched together, and the second insulating layer 644 disposed below the third insulating layer 646 and having an etching selectivity different from that of the third insulating layer 646 may be exposed.

[0211] In some example embodiments, when the fourth material layer 150d, the third material layer 150c, and the second material layer 150b are patterned, the second insulating layer 644 and the third insulating layer 646 may be etched together, and the first insulating layer 642 disposed under the second insulating layer 644 and having an etching selectivity different from that of the second insulating layer 644 may be exposed.

[0212] Then, refer to Fig.14 , a first bit line spacer 621 may be formed on the bit line structure BLS using an insulating material. The first bit line spacer 621 may be conformally formed to cover an upper surface and side surfaces of the bit line structure BLS.

[0213] In addition, the first bit line spacer 621 may conformally cover an upper surface of the insulating layer 640 , an upper surface of the trench spacer 650 , and an upper surface of the first material layer 150 a .

[0214] The first bit line spacer 621 may include an insulating material. For example, the first bit line spacer 621 may include at least one of silicon oxide, silicon nitride, and a low-k material having a low dielectric constant such as SiOCN, SiOC, SiBN, SiBCN, or SiBCON. However, the material included in the first bit line spacer 621 is not limited thereto, but may be variously changed.

[0215] Then, refer to Fig.15 , the first bit line spacer 621 may be patterned. That is, by patterning the first bit line spacer 621, at least a portion of the first bit line spacer 621 may be removed.

[0216] Specifically, the first bit line spacer 621 disposed between the bit line structures BLS and on the upper surface of the bit line structure BLS may be removed. That is, the first bit line spacer 621 disposed on the upper surface of the bit line structure BLS, the upper surface of the insulating layer 640, the upper surface of the trench spacer 650, and the upper surface of the first material layer 150a may be removed.

[0217] Therefore, the first bit line spacer 621 may be disposed on the side surface of the bit line structure BLS. When a portion of the first bit line spacer 621 is removed, the upper surface of the bit line structure BLS disposed below the first bit line spacer 621, the upper surface of the insulating layer 640, the upper surface of the trench spacer 650, and the upper surface of the first material layer 150a may be exposed.

[0218] In addition, in the step of patterning the first bit line spacer 621 , the thickness of the first bit line spacer 621 may be reduced. Here, the thickness may mean the thickness of the first bit line spacer 621 along the first direction X.

[0219] Then, refer to Fig.16 , the first material layer 150a may be patterned. That is, at least a portion of the first material layer 150a disposed in the direct contact trench DCT may be removed by performing a photo and etching process. The trench spacer 650 and the first material layer 150a may be patterned using the first bit line spacer 621 as an etching mask. Through the patterning process, a direct contact DC disposed in the direct contact trench DCT may be formed. The direct contact DC may be substantially disposed at a central portion of the direct contact trench DCT.

[0220] The bit line structure BLS may be disposed on the direct contact DC. That is, the first conductive layer 151 and the second conductive layer 153 of the bit line BL may be sequentially disposed on the direct contact DC, and the bit line capping layer 155 may be disposed on the second conductive layer 153 .

[0221] Furthermore, after forming the first bit line spacer 621 on the side surface of the bit line structure BLS, when the first material layer 150 a is patterned, the first bit line spacer 621 may be disposed on the upper surface of the direct contact DC.

[0222] That is, since the first bit line spacer 621 disposed on the side surface of the bit line BL is used as a mask in the process step of patterning the first material layer 150a, the first material layer 150a can be overlapped with the first bit line spacer 621 in the third direction Z, and the first material layer 150a disposed under the first bit line spacer 621 may not be etched.

[0223] Therefore, the width of the direct contact DC of the first material layer 150a along the first direction X may be different from the width of the bit line BL along the first direction X. For example, the width of the direct contact DC along the first direction X may be greater than the width of the bit line BL along the first direction X. In addition, the side surface of the first bit line spacer 621 may be aligned with the side surface of the direct contact DC in the third direction Z at substantially the same boundary.

[0224] In the step of patterning the first material layer 150 a disposed within the direct contact trench DCT, the trench spacer 650 conformally formed along the sidewall of the direct contact trench DCT may be removed together.

[0225] When the trench spacer 650 including the same material as the first material layer 150a is formed in the direct contact trench DCT, the first material layer 150a disposed within the direct contact trench DCT may be smoothly etched in a process step of forming the direct contact DC by patterning the first material layer 150a.

[0226] That is, by forming a trench spacer 650 including the same material as the first material layer 150a along the side surfaces of the insulating layer 640 and the device isolation layer 112 (which include a material different from that of the first material layer 150a), etching defects can be prevented from occurring at the interfaces between the first material layer 150a and the insulating layer 640 and between the first material layer 150a and the device isolation layer 112.

[0227] Furthermore, in the step of patterning the first material layer 150 a disposed in the direct contact trench DCT, when a portion of the third insulating layer 646 is removed together, the upper surface of the second insulating layer 644 disposed under the third insulating layer 646 may be exposed to the outside.

[0228] That is, when the first bit line spacer 621 disposed on the upper surface of the third insulating layer 646 is used as a mask, the first bit line spacer 621 may overlap with the third insulating layer 646 in the third direction Z, and the third insulating layer 646 disposed under the first bit line spacer 621 may not be etched.

[0229] Therefore, the third insulating layer 646 that does not overlap the first bit line spacer 621 in the third direction Z may be etched, and an upper surface of the second insulating layer 644 disposed below the third insulating layer 646 may be exposed. When the second insulating layer 644 includes a material having an etching selectivity different from that of the third insulating layer 646, the second insulating layer 644 may function as an etching stop film.

[0230] The method of manufacturing a semiconductor device according to some example embodiments may further include a cleaning process step for removing residues remaining in the direct contact trench DCT after patterning the first material layer 150 a to form the direct contact DC.

[0231] As described above, since the first bit line spacer 621 is formed on the side surface of the bit line BL and then the first material layer 150a is patterned to form the direct contact DC, in the cleaning process step for removing the residues remaining in the direct contact trench DCT, the side surface of the bit line BL including the conductive material may not be exposed by the first bit line spacer 621, but it may be covered by the first bit line spacer 621.

[0232] As described above, in the semiconductor device according to some example embodiments, the bit line BL may include a metal material different from the metal material of the direct contact DC. The bit line BL may include a plurality of layers, and at least one of the plurality of layers constituting the bit line BL may include a metal material different from the metal material of the direct contact DC. For example, the bit line BL may include a first conductive layer 151 and a second conductive layer 153, and at least one of the first conductive layer 151 and the second conductive layer 153 may include a metal material different from the metal material of the direct contact DC.

[0233] Therefore, when the side surface of the bit line BL is exposed in the cleaning process of removing the residue in the direct contact trench DCT, galvanic corrosion may occur due to a potential difference between the direct contact DC and the bit line BL including different conductive materials.

[0234] In the semiconductor device according to some example embodiments, since the side surface of the bit line BL is covered by the first bit line spacer 621 in the step of performing the cleaning process for removing the residue in the direct contact trench DCT, the bit line BL can be prevented from being damaged by galvanic corrosion by blocking the bit line BL from being exposed to the cleaning material.

[0235] Then, refer to Fig.17 , the second bit line spacer 623 may be formed on the bit line structure BLS using an insulating material. For example, the insulating material may include silicon nitride. However, the insulating material is not limited thereto but may be variously changed.

[0236] The second bit line spacer 623 may be conformally formed on the bit line structure BLS. The second bit line spacer 623 may cover the side surface of the bit line structure BLS and the side surface of the direct contact DC. The second bit line spacer 623 may cover the side surface of the third insulating layer 646, the upper surface and the side surface of the second insulating layer 644, and the side surface of the first insulating layer 642. In addition, the second bit line spacer 623 may cover the bottom surface and the side wall of the direct contact trench DCT.

[0237] In some example embodiments, the thickness of the second bit line spacer 623 may be thinner than the thickness of the first bit line spacer 621. Here, the thickness of the first bit line spacer 621 and the thickness of the second bit line spacer 623 may mean a thickness along the first direction X. However, the thickness relationship between the first bit line spacer 621 and the second bit line spacer 623 is not limited thereto but may be variously changed.

[0238] Then, refer to Fig.18 , a third bit line spacer 625 disposed within the direct contact trench DCT may be formed, and a fourth bit line spacer 627 may be formed on the second bit line spacer 623 and the third bit line spacer 625 .

[0239] Specifically, the third bit line spacer 625 may be formed on the second bit line spacer 623 using an insulating material. For example, the insulating material may include silicon nitride. However, the insulating material is not limited thereto but may be variously changed.

[0240] The third bit line spacer 625 may be conformally formed on the first bit line spacer 621. The third bit line spacer 625 may be formed to fill the direct contact trench DCT. The thickness of the third bit line spacer 625 may be thicker than the thickness of the first bit line spacer 621 and the thickness of the second bit line spacer 623.

[0241] Here, the thickness of the first bit line spacer 621, the thickness of the second bit line spacer 623, and the thickness of the third bit line spacer 625 may mean the thickness along the first direction X. However, the relationship between the thickness of the first bit line spacer 621, the thickness of the second bit line spacer 623, and the thickness of the third bit line spacer 625 is not limited thereto but may be variously changed.

[0242] Next, the third bit line spacer 625 may be patterned to leave portions of the third bit line spacer 625 disposed in the direct contact trench DCT, and the remaining portions of the third bit line spacer 625 may be removed. Portions of the third bit line spacer 625 covering the bit line structure BLS may be removed.

[0243] Subsequently, a fourth bit line spacer 627 may be formed on the second bit line spacer 623 and the third bit line spacer 625 by using an insulating material. For example, the insulating material may include silicon oxide. However, the insulating material is not limited thereto but may be variously changed.

[0244] The fourth bit line spacer 627 may be conformally formed on the second bit line spacer 623 and the third bit line spacer 625. The fourth bit line spacer 627 may have a thickness thicker than the first bit line spacer 621 and the second bit line spacer 623, and may be thinner than the third bit line spacer 625.

[0245] Here, the thickness of the first bit line spacer 621, the thickness of the second bit line spacer 623, the thickness of the third bit line spacer 625, and the thickness of the fourth bit line spacer 627 may mean the thickness along the first direction X. However, the relationship between the thickness of the first bit line spacer 621, the thickness of the second bit line spacer 623, the thickness of the third bit line spacer 625, and the thickness of the fourth bit line spacer 627 is not limited thereto but may be variously changed.

[0246] Subsequently, the second and fourth bit line spacers 623 and 627 may be patterned. That is, the second and fourth bit line spacers 623 and 627 disposed between the bit line structures BLS and on the upper surfaces of the bit line structures BLS may be partially removed.

[0247] When the second and fourth bit line spacers 623 and 627 are partially removed, the upper surface of the bit line structure BLS may be exposed. That is, the upper surface and the side surface of the bit line capping layer 155 may be partially exposed.

[0248] In addition, when the second bit line spacer 623 and the fourth bit line spacer 627 are partially removed, the upper surface of the second insulating layer 644 and the upper surface of the third bit line spacer 625 may be partially exposed. That is, the upper surface of the second insulating layer 644 and the upper surface of the third bit line spacer 625 disposed between the bit line structures BLS may be partially exposed.

[0249] Then, refer to Fig.19 , a fifth bit line spacer 629 may be formed on the fourth bit line spacer 627 by using an insulating material. For example, the insulating material may include silicon nitride. However, the insulating material is not limited thereto but may be variously changed.

[0250] The fifth bit line spacer 629 may be conformally formed on the upper surface of the bit line structure BLS, the fourth bit line spacer 627, and the upper surface of the second insulating layer 644. The first bit line spacer 621, the second bit line spacer 623, the third bit line spacer 625, the fourth bit line spacer 627, and the fifth bit line spacer 629 may constitute a bit line spacer structure 620.

[0251] Then, refer to Fig. 20, the fifth bit line spacer 629 may be patterned. By removing a portion of the fifth bit line spacer 629, the upper surface of the bit line structure BLS may be exposed. That is, the upper surface and the side surface of the bit line structure BLS may be partially exposed. In addition, by removing a portion of the fifth bit line spacer 629, the upper surface of the second insulating layer 644 disposed between the bit line structures BLS may be exposed.

[0252] Thus, the fifth bit line spacer 629 may be disposed on the side surface of the bit line structure BLS and may contact the fourth bit line spacer 627 and the third bit line spacer 625. In addition, the fifth bit line spacer 629 may contact the upper surface of the second insulating layer 644.

[0253] The thickness of the fifth bit line spacer 629 may be thicker than the thickness of the first bit line spacer 621 and the thickness of the second bit line spacer 623, and may be thinner than the thickness of the third bit line spacer 625 and the thickness of the fourth bit line spacer 627. The thickness of the fifth bit line spacer 629 may be reduced during patterning of the fifth bit line spacer 629.

[0254] Here, the thickness of the first bit line spacer 621, the thickness of the second bit line spacer 623, the thickness of the third bit line spacer 625, the thickness of the fourth bit line spacer 627, and the thickness of the fifth bit line spacer 629 may mean the thickness along the first direction X. However, the relationship between the thickness of the first bit line spacer 621, the thickness of the second bit line spacer 623, the thickness of the third bit line spacer 625, the thickness of the fourth bit line spacer 627, and the thickness of the fifth bit line spacer 629 is not limited thereto but may be variously changed.

[0255] Subsequently, an etching process may be performed to remove at least a portion of the active region AR, thereby forming a buried contact trench BCT. When at least a portion of the active region AR is removed, at least some of the device isolation layer 112, the second bit line spacer 623, the third bit line spacer 625, the second insulating layer 644, and the third insulating layer 646 disposed around the active region AR may be removed together.

[0256] Furthermore, at least some of the first bit line spacer 621 , the second bit line spacer 623 , the fourth bit line spacer 627 , and the fifth bit line spacer 629 disposed around the bit line capping layer 155 may be removed together.

[0257] Subsequently, a conductive material layer 170 may be formed on the bit line structures BLS. The conductive material layer 170 may be formed between the bit line structures BLS. The buried contact trench BCT may be filled with the conductive material layer 170.

[0258] Therefore, the conductive material layer 170 may contact the active region AR. The conductive material layer 170 may include a conductive material. For example, the conductive material layer 170 may include polysilicon doped with impurities, but is not limited thereto.

[0259] like Figure 2 As shown in FIG. 1 , the buried contact BC may be formed by patterning the conductive material layer 170. The buried contact BC may be electrically connected to the active region AR.

[0260] Subsequently, a bonding pad LP connected to the buried contact BC may be formed, and an insulating pattern 660 may be formed to isolate the bonding pad LP. Although not shown, a capacitor structure may be further formed on the bonding pad LP. The capacitor structure may be electrically connected to the active region AR through the bonding pad LP and the buried contact BC.

[0261] While certain example embodiments of the inventive concept have been described in connection with what are presently considered to be practical embodiments, it is to be understood that the inventive concept is not limited to such example embodiments, but, on the contrary, the inventive concept is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a substrate including an active region defined by a device isolation layer; word lines, crossing and overlapping the active area; A bit line intersecting the active area in a different direction than the word line; A direct contact, connecting the active area and the bit line, the direct contact comprising a metal material; a buried contact connected to the active area; and A bit line spacer, located between the bit line and the buried contact, wherein the width of the direct contact is different from the width of the bit line, and The bit line spacer is located on the upper surface of the direct contact.

2. The semiconductor device according to claim 1, wherein The width of the direct contact is greater than the width of the bit line.

3. The semiconductor device according to claim 2, wherein: A side surface of the direct contact protrudes outward from a side surface of the bit line.

4. The semiconductor device according to claim 3, wherein: A side surface of the bit line spacer is coplanar with a side surface of the direct contact.

5. The semiconductor device according to claim 3, wherein: A side surface of the direct contact protrudes outward from a side surface of the bit line spacer.

6. The semiconductor device according to claim 1, wherein The bit line spacer directly contacts a side surface of the bit line and an upper surface of the direct contact.

7. The semiconductor device according to claim 6, wherein: The bit line spacer covers the side surface of the bit line, and The bit line spacer covers at least a portion of an upper surface of the direct contact that does not overlap the bit line in a vertical direction.

8. The semiconductor device according to claim 1, wherein The width of the upper surface of the direct contact member is greater than the width of the lower surface of the direct contact member.

9. The semiconductor device according to claim 8, wherein: The width of the lower surface of the direct contact is greater than the width of the bit line.

10. The semiconductor device according to claim 1, further comprising: A silicide layer between the upper surface of the active area and the direct contact, The width of the silicide layer is greater than the width of the direct contact.

11. The semiconductor device according to claim 1, wherein The thickness of the bit line spacer is 0.5 nm to 1 nm.

12. The semiconductor device according to claim 1, wherein The bit line spacer includes at least one of SiO2, SiN, SiOCN, SiOC, SiBN, SiBCN, and SiBCON.

13. A semiconductor device, comprising: a substrate including an active region defined by a device isolation layer; word lines, crossing and overlapping the active area; A bit line intersecting the active area in a different direction than the word line; A direct contact, connecting the active area and the bit line, the direct contact comprising a metal material; a silicide layer between the active area and the direct contact; a buried contact connected to the active area; a first bit line spacer, located on the upper surface of the direct contact; a second bit line spacer disposed between the first bit line spacer and the buried contact; as well as Bond pads, connected to the active area through buried contacts, The width of the direct contact is greater than the width of the bit line.

14. The semiconductor device according to claim 13, wherein: The width of the first bit line spacer is equal to the difference between the width of the direct contact and the width of the bit line.

15. The semiconductor device according to claim 14, wherein: A first bit line spacer covers both the side surface of the bit line and the upper surface of the direct contact, and The second bit line spacer covers both a side surface of the first bit line spacer and a side surface of the direct contact.

16. The semiconductor device according to claim 15, wherein: The first bit line spacer includes at least one of SiO 2 , SiN, SiOCN, SiOC, SiBN, SiBCN, and SiBCON.

17. The semiconductor device according to claim 16, further comprising: a third bit line spacer disposed between the second bit line spacer and the buried contact; as well as a fourth bit line spacer, located between the second bit line spacer and the third bit line spacer, Wherein, the first bit line spacer comprises at least one of SiOCN, SiOC, SiBN, SiBCN and SiBCON, Wherein, the second bit line spacer and the third bit line spacer both comprise SiN, and The fourth bit line spacer includes SiO2.

18. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a device isolation layer in the substrate to define an active area; forming an insulating layer on the substrate, and then patterning the insulating layer to form a direct contact trench to expose the upper surface of the active area; forming trench spacers in the direct contact trenches on the exposed upper surface of the active area; forming a first material layer including a metal material in the direct contact trench; sequentially stacking a second material layer, a third material layer, and a fourth material layer on the insulating layer and the first material layer; forming a bit line based on patterning at least some of the second material layer, the third material layer, and the fourth material layer; forming a first bit line spacer to cover a side surface of the bit line; patterning the trench spacers and the first material layer using the first bitline spacers as an etch mask to form direct contacts connected to the active area and the bitline; forming a second bit line spacer covering the first bit line spacer and the direct contact; forming a buried contact connected to the active area; as well as Bond pads are formed that are connected to the active region through buried contacts.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: Based on patterning the first material layer using the first bit line spacer as an etch mask, The side surface of the first line spacer is coplanar with the side surface of the direct contact, and The width of the direct contact is greater than the width of the bit line.

20. The method for manufacturing a semiconductor device according to claim 18, wherein: The first bit line spacer includes at least one of SiO2, SiN, SiOCN, SiOC, SiBN, SiBCN and SiBCON, and The thickness of the first bit line spacer is 0.5 nm to 1 nm.

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