Memory and method of manufacturing the same

Abstract

This disclosure belongs to the field of semiconductor technology, specifically relating to a memory and its manufacturing method. The memory includes a substrate and at least one storage layer formed on the substrate, and the storage layer includes storage cells. Each storage cell includes: a read transistor comprising a first gate, a first semiconductor layer at least horizontally surrounding the outer periphery of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer. The first gate includes a gate bottom wall and a gate sidewall, the gate sidewall being horizontally disposed around the gate bottom wall and extending in a direction away from the substrate, the gate sidewall and the gate bottom wall forming a gate trench; and a write transistor comprising a second gate, a second semiconductor layer at least horizontally surrounding the outer periphery of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer, a portion of the second semiconductor layer being embedded in the gate trench and in contact with at least a portion of the gate trench. This solution improves storage density while reducing process technology difficulty.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, and specifically relates to a memory and its manufacturing method. Background Technology

[0002] As technology nodes shrink, DRAM (Dynamic Random Access Memory) memory cells are gradually shifting from a 1T1C (a combination of one transistor and one capacitor) structure to a planar 2T0C structure (i.e., a structure with two horizontally arranged transistors and no capacitor). However, this design results in a still low storage density for DRAM and a more complex manufacturing process. Summary of the Invention

[0003] This disclosure provides a memory and a method for manufacturing the same, which can increase storage density while reducing the difficulty of the manufacturing process.

[0004] A first aspect of this disclosure provides a memory that may include a substrate and at least one storage layer formed on the substrate, the storage layer including storage cells, wherein the storage cells include:

[0005] A read transistor includes a first gate, a first semiconductor layer at least horizontally surrounding the outer periphery of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer. The first gate includes a gate bottom wall and a gate side wall. The gate side wall is horizontally disposed around the gate bottom wall and extends in a direction away from the substrate. The gate side wall and the gate bottom wall form a gate trench.

[0006] The write transistor includes a second gate, a second semiconductor layer at least horizontally surrounding the outer periphery of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer, wherein a portion of the second semiconductor layer is embedded in the gate trench and in contact with at least a portion of the gate trench.

[0007] A second aspect of this disclosure provides a method for manufacturing a memory, the method comprising:

[0008] Provide a base;

[0009] At least one storage layer is formed on the substrate, wherein the step of forming the storage layer includes:

[0010] A read transistor is formed on the substrate. The read transistor includes a first gate, a first semiconductor layer that is at least horizontally surrounding the outer periphery of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer. The first gate includes a gate bottom wall and a gate side wall. The gate side wall is horizontally disposed around the gate bottom wall and extends in a direction away from the substrate. The gate side wall and the gate bottom wall form a gate trench.

[0011] A write transistor is formed at the gate trench to form a memory cell. The write transistor includes a second gate, a second semiconductor layer at least horizontally surrounding the outer periphery of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer. A portion of the second semiconductor layer is embedded in the gate trench and in contact with at least a portion of the gate trench.

[0012] The technical solutions provided in this disclosure have at least the following advantages:

[0013] In this disclosure, by vertically nesting a portion of the CAA-type write transistor within the CAA-type read transistor of the memory cell, compared to a planar 2TOC type memory cell, while maintaining the memory cell storage density, it can not only reduce the horizontal area occupied by the memory cell, but also reduce the vertical height of the memory cell. In other words, it can reduce the overall volume of the memory cell, i.e., reduce the space occupied by the memory cell. Thus, more memory cells can be arranged in a memory of a certain volume, thereby increasing the memory storage density.

[0014] Furthermore, this disclosure enables the connection between the write transistor and the read transistor by placing the semiconductor layer of the write transistor at the gate trench of the gate in the read transistor, allowing direct contact with the gate of the read transistor. Compared to planar 2T0C type memory cells, there is no need to design additional connection patterns to connect the write transistor and the read transistor together, thereby reducing the requirements for photolithography during the manufacturing process, which in turn can improve product yield and reduce production costs. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] Figures 1 to 6 Schematic diagrams of the memory structure under different embodiments of this disclosure are shown respectively.

[0017] Figures 7 to 24The diagrams show the structure of the memory manufacturing method disclosed herein after each of the different steps has been performed. Detailed Implementation

[0018] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0019] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0020] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0021] This disclosure provides a memory that may include a substrate and at least one storage layer.

[0022] The memory of the present disclosure embodiments will now be described in detail with reference to the accompanying drawings.

[0023] refer to Figure 1 As shown, the substrate 1 can be a stacked structure. For example, the substrate 1 may include a semiconductor substrate layer 10 and an insulating substrate layer 11 formed on the semiconductor substrate layer 10. The semiconductor substrate layer 10 may include semiconductor materials such as single crystal silicon, but is not limited to this, and may also include semiconductor materials such as germanium (Ge). The insulating substrate layer 11 may include insulating materials such as silicon dioxide, but is not limited to this. The insulating substrate layer 11 may also be made of other materials with insulating properties, depending on the actual situation.

[0024] It should be understood that the substrate 1 in this embodiment is not limited to... Figure 1 The stacked structure shown can also be a single-layer structure. For example, the substrate 1 can be a single-layer structure made of semiconductor material or a single-layer structure made of insulating material, depending on the specific situation.

[0025] refer to Figure 1 As shown, the storage layer 2 can be formed on the substrate 1. For example, when the substrate 1 is a stacked structure including a semiconductor substrate layer 10 and an insulating substrate layer 11, the storage layer 2 can be formed on the top surface of the insulating substrate layer 11 away from the semiconductor substrate layer 10.

[0026] Continue to refer to Figure 1 As shown, storage layer 2 may include storage cells. Each storage cell may include two transistors, for example, a read transistor 201 and a write transistor 202. Both read transistor 201 and write transistor 202 may be CAA (Channel-All-Around) type. Specifically, read transistor 201 may include a first gate 2011, a first semiconductor layer 2012 at least horizontally surrounding the outer periphery of the first gate 2011, and a first gate insulating layer 2013 formed between the first gate 2011 and the first semiconductor layer 2012. Write transistor 202 may include a second gate 2021, a second semiconductor layer 2022 at least horizontally surrounding the outer periphery of the second gate 2021, and a second gate insulating layer 2023 formed between the second gate 2021 and the second semiconductor layer 2022.

[0027] For example, the materials of the first semiconductor layer 2012 and the second semiconductor layer 2022 can be the same. For instance, both the first semiconductor layer 2012 and the second semiconductor layer 2022 can be made of IGZO (indium gallium zinc oxide). By using IGZO to make the semiconductor layers, it is not necessary to dope the first semiconductor layer 2012 and the second semiconductor layer 2022 to form source and drain regions, and the leakage current is small, thereby increasing the storage time and improving the storage performance. However, it is not limited to this. The first semiconductor layer 2012 and the second semiconductor layer 2022 can also be made of other semiconductor materials such as IAZO (indium aluminum zinc oxide), as long as the storage time and storage performance of the transistor can be guaranteed. In addition, the materials of the first semiconductor layer 2012 and the second semiconductor layer 2022 can also be different, depending on the specific situation.

[0028] For example, the first gate 2011 and the second gate 2021 can be made of the same material. For instance, the first gate 2011 and the second gate 2021 can both be made of conductive materials such as tungsten metal, but are not limited to this. Other materials with good conductivity can also be used, depending on the specific requirements. In addition, the first gate 2011 and the second gate 2021 can also be made of different materials, depending on the specific situation.

[0029] For example, the first gate insulating layer 2013 and the second gate insulating layer 2023 may be made of the same material. For instance, both the first gate insulating layer 2013 and the second gate insulating layer 2023 may be made of insulating materials such as silicon dioxide, but they are not limited to this and may also be made of other insulating materials. In addition, the materials of the first gate insulating layer 2013 and the second gate insulating layer 2023 may also be different, depending on the specific circumstances.

[0030] In this embodiment, the first gate 2011 of the read transistor 201 may be designed in a groove shape. Specifically, in the read transistor 201: the first gate 2011 may include a gate sidewall 2011a and a gate bottom wall 2011b. The gate sidewall 2011a is horizontally disposed around the gate bottom wall 2011b and extends in a direction away from the substrate 1. The gate sidewall 2011a and the gate bottom wall 2011b form a gate groove. A portion of the write transistor 202 may be vertically nested in the read transistor 201. Specifically, a portion of the second semiconductor layer 2022 in the write transistor 202 is embedded in the gate groove of the first gate 2011 and contacts at least a portion of the gate groove in the first gate 2011, that is: it may contact at least one of the gate sidewall 2011a and the gate bottom wall 2011b.

[0031] In this disclosure, by vertically nesting a portion of the CAA-type write transistor 202 inside the CAA-type read transistor 201 in the memory cell, compared to the planar 2TOC type memory cell, while ensuring the storage density of the memory cell, not only can the horizontal area occupied by the memory cell be reduced, but also the vertical height of the memory cell can be reduced, that is, the overall volume of the memory cell can be reduced, thereby reducing the space occupied by the memory cell. In this way, more memory cells can be arranged in a memory of a certain volume, so as to improve the storage density of the memory.

[0032] Furthermore, by placing the semiconductor layer of the write transistor 202 at the gate trench of the gate in the read transistor 201, the write transistor 202 can directly contact the gate of the read transistor 201, thereby achieving the connection between the write transistor 202 and the read transistor 201. Compared with planar 2TOC type memory cells, there is no need to design additional connection patterns to connect the write transistor 202 and the read transistor 201 together, thereby reducing the requirements for photolithography process during manufacturing, thereby improving product yield and reducing production costs.

[0033] It should be understood that the location where the gate trench in the first gate 2011 contacts the second semiconductor layer 2022 can be understood as the storage node of the memory cell, for example: Figure 1 The location where the bottom wall 2011b of the middle gate contacts the second semiconductor layer 2022 can be understood as a memory node.

[0034] In some embodiments, reference Figure 1As shown, in the write transistor 202: the second semiconductor layer 2022, the second gate 2021, and the second gate insulating layer 2023 may each have an embedded portion and an extension portion. The embedded portion may be the portion of the second semiconductor layer 2022, the second gate 2021, and the second gate insulating layer 2023 embedded in the gate trench. It should be understood that the embedded portion of the second semiconductor layer 2022 is in contact with at least a portion of the gate trench to realize the connection between the write transistor 202 and the read transistor 201. The extension portion may be the portion of the second semiconductor layer 2022, the second gate 2021, and the second gate insulating layer 2023 located on the side of the embedded portion away from the substrate 1. This extension portion protrudes in a direction away from the substrate 1 relative to the read transistor 201.

[0035] In this embodiment, by embedding the bottom of the second semiconductor layer 2022, the second gate 2021, and the second gate insulating layer 2023 in the write transistor 202 into the gate trench of the first gate 2011, the vertical height of the memory cell can be further reduced while ensuring the storage density.

[0036] For example, see reference Figure 1 As shown, the embedding portion of the second semiconductor layer 2022 may include a second semiconductor sidewall 2022a and a second semiconductor bottom wall 2022b. The second semiconductor sidewall 2022a is horizontally disposed around the second semiconductor bottom wall 2022b and extends in a direction away from the substrate 1. The second semiconductor sidewall 2022a and the second semiconductor bottom wall 2022b form a second semiconductor trench. The embedding portion of the second gate 2021 and the embedding portion of the second gate insulating layer 2023 are located in the second semiconductor trench.

[0037] refer to Figure 1 As shown, the bottom surface of the second semiconductor bottom wall 2022b and the bottom surface of the second semiconductor side wall 2022a are both in contact with the gate bottom wall 2011b. This design can ensure the contact area between the second semiconductor layer 2022 and the first gate 2011, and the manufacturing process is also less difficult.

[0038] In some embodiments, reference Figure 1As shown, the memory cell may further include an insulating dielectric sidewall 203a, which is embedded in the gate trench and horizontally surrounds the outer periphery of the embedded portion in the second semiconductor layer 2022. The outer periphery of the embedded portion in the second semiconductor layer 2022 is insulated from the gate sidewall 2011a by the insulating dielectric sidewall 203a. The bottom surface of the embedded portion in the second semiconductor layer 2022 is in contact with the bottom gate wall 2011b. This design enables the connection between the write transistor 202 and the read transistor 201, while also allowing the embedded portion of the second semiconductor layer 2022 to be part of the channel in the write transistor 202. This reduces the height of the second semiconductor layer 2022 protruding from the read transistor 201 while ensuring that the channel length of the write transistor 202 meets the requirements. In other words, it reduces the height of the extension in the second semiconductor layer 2022, thereby further reducing the vertical height of the memory cell.

[0039] In some embodiments, the insulating dielectric sidewall 203a may include a low-dielectric material portion, which is made of a material with a dielectric constant of less than 3.0. This low-dielectric material portion may be horizontally surrounded around the outer periphery of the embedded portion of the second semiconductor layer 2022 to reduce the parasitic capacitance generated between the second semiconductor layer 2022 and the first gate 2011.

[0040] In other embodiments, the insulating dielectric sidewall 203a may also include a silicon dioxide material layer that horizontally surrounds the outer periphery of the embedded portion of the second semiconductor layer 2022, so as to reduce material costs while achieving insulation between the embedded portion of the second semiconductor layer 2022 and the gate sidewall 2011a of the first gate 2011.

[0041] In some other embodiments, the insulating dielectric sidewall 203a may include a stacked structure in which a low dielectric material portion and a silicon dioxide material layer are nested together, thereby reducing material costs and parasitic capacitance.

[0042] In some embodiments of this disclosure, reference is made to Figure 1 As shown, in addition to memory cells, storage layer 2 may also include a first signal line 204 and a second signal line 205. Combined with... Figures 1 to 3As shown, a first signal line 204 is formed on the substrate 1, extends in the first horizontal direction X, and contacts the bottom surface of the first semiconductor layer 2012 and / or the bottom region of the outer peripheral surface of the first semiconductor layer 2012; a second signal line 205 is formed on the side of the first signal line 204 away from the substrate 1, a first interlayer insulating layer 206 is formed between the layer containing the second signal line 205 and the layer containing the first signal line 204, the second signal line 205 extends in the second horizontal direction Y intersecting the first horizontal direction X, the second signal line 205 and the first interlayer insulating layer 206 horizontally surround the outer peripheral side of the first semiconductor layer 2012, and the second signal line 205 contacts the top region of the outer peripheral surface of the first semiconductor layer 2012, wherein one of the first signal line 204 and the second signal line 205 is a read bit line and the other is a read word line.

[0043] For example, the first signal line 204 and the second signal line 205 can be made of the same material, such as conductive materials like tungsten, but are not limited to this; other conductive materials can also be used. Furthermore, the first signal line 204 and the second signal line 205 can be signal lines made of a single material, but are not limited to this; they can also be composite signal lines made of multiple stacked materials, depending on the specific circumstances. The first interlayer insulation layer 206 can be made of materials like silicon dioxide, but is not limited to this; other insulating materials can also be used, depending on the specific circumstances.

[0044] refer to Figure 1 As shown, the first semiconductor layer 2012 of the read transistor 201 is formed on the side of the first signal line 204 away from the substrate 1, and both the first semiconductor layer 2012 and the first gate insulating layer 2013 of the read transistor 201 can be designed in a trench shape. In this embodiment, the first gate insulating layer 2013 and the first gate 2011 can be designed according to the shape of the first semiconductor layer 2012 and cooperate with each other, so as to simplify the process steps, reduce the process cost, and ensure the channel length of the read transistor 201.

[0045] For detailed explanation, please refer to the following: Figure 1 As shown, the first semiconductor layer 2012 may include a first semiconductor sidewall 2012a and a first semiconductor bottom wall 2012b. The first semiconductor sidewall 2012a is horizontally disposed around the first semiconductor bottom wall 2012b and extends in a direction away from the substrate 1. The first semiconductor sidewall 2012a and the first semiconductor bottom wall 2012b form a first semiconductor trench. The bottom surfaces of the first semiconductor sidewall 2012a and the first semiconductor bottom wall 2012b are in contact with the first signal line 204.

[0046] refer to Figure 1As shown, the first gate insulating layer 2013 includes a first gate insulating sidewall 2013a and a first gate insulating bottom wall 2013b. The first gate insulating bottom wall 2013b is located within the first semiconductor trench and contacts the top surface of the first semiconductor bottom wall 2012b. The first gate insulating sidewall 2013a is located at least within the first semiconductor trench and is horizontally arranged around the first gate insulating bottom wall 2013b. The first gate insulating sidewall 2013a extends in a direction away from the substrate 1 and forms a first gate insulating trench with the first gate insulating bottom wall 2013b. The outer peripheral surface of the first gate insulating sidewall 2013a contacts the inner peripheral surface of the first semiconductor sidewall 2012a. The gate bottom wall 2011b is located within the first gate insulating trench and contacts the top surface of the first gate insulating bottom wall 2013b. The gate sidewall 2011a is located at least within the first gate insulating trench, and the outer peripheral surface of the gate sidewall 2011a contacts the inner peripheral surface of the first gate insulating sidewall 2013a.

[0047] In some embodiments, reference Figure 1 As shown, the top surface of the first semiconductor sidewall 2012a, the top surface of the first gate insulating sidewall 2013a, and the top surface of the gate sidewall 2011a may be flush with the top surface of the second signal line 205; however, this is not the limitation. In other embodiments, refer to Figure 4 As shown, the top of the first semiconductor sidewall 2012a has a first semiconductor overlap portion 2012c extending horizontally outward, and the first semiconductor overlap portion 2012c is formed on the top surface of the second signal line 205. The top of the first gate insulating sidewall 2013a has a first gate insulating overlap portion 2013c extending horizontally outward, and the first gate insulating overlap portion 2013c is formed on the top surface of the first semiconductor overlap portion 2012c. The top of the gate sidewall 2011a has a gate overlap portion 2011c extending horizontally outward, and the gate overlap portion 2011c is formed on the top surface of the first gate insulating overlap portion 2013c.

[0048] In some embodiments of this disclosure, reference is made to Figure 1 As shown, in addition to memory cells, first signal line 204, and second signal line 205, memory layer 2 may also include write bit line 207 and write word line 208. Write bit line 207 may be formed on the side of second signal line 205 away from substrate 1. A second interlayer insulating layer 209 is formed between the layer containing write bit line 207 and the layer containing second signal line 205. Write bit line 207 and second interlayer insulating layer 209 horizontally surround the outer periphery of the extension of the second semiconductor layer 2022, and write bit line 207 is in contact with the outer periphery of the first semiconductor layer 2012. Write word line 208 may be formed on the side of the extension of write bit line 207 and second gate 2021 away from substrate 1. A third interlayer insulating layer 210 is formed between the layer containing write word line 208 and the layer containing write bit line 207. Write word line 208 is connected to the top surface of the extension of the second gate 2021.

[0049] Among them, combined Figure 2 and Figure 3 As shown, the write bit line 207 can extend in the first horizontal direction X, and the write word line 208 can extend in the second horizontal direction Y. This can reduce the area of ​​the overlapping region between the write bit line 207 and the second signal line 205, thereby reducing the generation of parasitic capacitance between them. However, it is not limited to this. The write bit line 207 can also extend in the second horizontal direction Y, and the write word line 208 can extend in the first horizontal direction X, depending on the specific situation.

[0050] For example, the write word line 208 and the write bit line 207 can be made of the same material, such as conductive materials like tungsten, but are not limited to this; other conductive materials can also be used. Furthermore, the write word line 208 and the write bit line 207 can be signal lines made of a single material, but are not limited to this; they can also be composite signal lines made of multiple stacked materials, depending on the specific situation. The second interlayer insulation layer 209 and the third interlayer insulation layer 210 can be made of materials like silicon dioxide, but are not limited to this; other insulating materials can also be used, depending on the specific situation.

[0051] In some embodiments, reference Figure 1 and Figure 4 As shown, the top of the extension in the second semiconductor layer 2022 has a second semiconductor overlap portion 2022c extending outward horizontally. The second semiconductor overlap portion 2022c is formed on the top surface of the write word line 208. The top of the extension in the second gate insulating layer 2023 has a second gate insulating overlap portion 2023c extending outward horizontally. The second gate insulating overlap portion 2023c is formed on the top surface of the second semiconductor overlap portion 2022c. The top surface of the extension in the second gate 2021 is flush with the top surface of the second gate insulating overlap portion 2023c. The storage layer 2 also includes a conductive contact pad 2024. The bottom surface of the conductive contact pad 2024 contacts the top surface of the second gate insulating overlap portion 2023c and the top surface of the extension in the second gate 2021. The top surface of the conductive contact pad 2024 contacts the bottom surface of the write word line 208. This design can increase the contact area between the write transistor 202 and the write word line 208, thereby ensuring connection stability.

[0052] For example, the conductive contact pad 2024 in this embodiment can be integrally formed with the second gate 2021 to reduce process costs, but it is not limited to this and can also be manufactured separately, depending on the specific situation.

[0053] In embodiments of this disclosure, combined with Figure 2 and Figure 3As shown, the storage layer 2 may include multiple storage cells, which are arranged in an array along a first horizontal direction X and a second horizontal direction Y. The number of first signal lines 204 is equal to the number of rows in the storage cell array structure, and the number of second signal lines 205 is equal to the number of rows in the storage cell array structure. The first signal lines 204 are spaced apart along the second horizontal direction Y, and each first signal line 204 is connected to the first semiconductor layer 2012 of the read transistors 201 in all storage cells of its corresponding row. The second signal lines 205 are spaced apart along the first horizontal direction X, and each second signal line 205 is connected to the first semiconductor layer 2012 of the read transistors 201 in all storage cells of its corresponding column.

[0054] refer to Figure 2 and Figure 3 As shown, if the write bit lines 207 extend in the first horizontal direction X and the write word lines 208 extend in the second horizontal direction Y, then the number of write bit lines 207 is equal to the number of rows in the memory cell array structure, and the number of write word lines 208 is equal to the number of rows in the memory cell array structure. The write bit lines 207 are arranged at intervals in the second horizontal direction Y, and each write bit line 207 is connected to the second semiconductor layer 2022 of the write transistors 202 in all memory cells in its corresponding row. The write word lines 208 are arranged at intervals in the first horizontal direction X, and each write word line 208 is connected to the second gate 2021 of the write transistors 202 in all memory cells in its corresponding column.

[0055] If the write bit lines 207 extend in the second horizontal direction Y and the write word lines 208 extend in the first horizontal direction X, then the number of write bit lines 207 is equal to the number of columns in the memory cell array structure, and the number of write word lines 208 is equal to the number of rows in the memory cell array structure. The write bit lines 207 are spaced apart in the first horizontal direction X, and each write bit line 207 is connected to the second semiconductor layer 2022 of the write transistors 202 in all memory cells in its corresponding column. The write word lines 208 are spaced apart in the second horizontal direction Y, and each write word line 208 is connected to the second gate 2021 of the write transistors 202 in all memory cells in its corresponding row.

[0056] In this embodiment, the use of vertically nested storage cells can reduce their horizontal area, thereby reducing the space occupied by the storage cells and allowing more storage cells to be arranged in each storage layer 2, thus increasing the storage density of storage layer 2.

[0057] In embodiments of this disclosure, reference is made to Figure 5 and Figure 6As shown, the number of storage layers 2 can be multiple, and multiple storage layers 2 can be stacked along the direction perpendicular to the base 1. In this embodiment, by using vertical nested storage cells, the vertical height of storage layers 2 can be reduced, so that more storage layers 2 can be arranged when the height of the memory is constant, thereby increasing the storage density of the memory.

[0058] In some embodiments, in two adjacent storage layers 2, the storage layer 2 closer to the substrate 1 is defined as the bottom storage layer, and the storage layer 2 farther from the substrate 1 is defined as the top storage layer. (Refer to...) Figure 5 As shown, in at least two adjacent storage layers 2, a fourth interlayer insulating layer 211 is formed between the layer where the first signal line 204 of the top storage layer is located and the layer where the write line 208 of the bottom storage layer is located. This design allows for more flexible control of each storage layer 2.

[0059] In other embodiments, reference is made to Figure 6 As shown, in at least two adjacent storage layers 2, the write word line 208 of the bottom storage layer can be shared as the first signal line 204 of the top storage layer. This design allows for the arrangement of more storage layers 2 at a given height, thereby further increasing the storage density of the memory.

[0060] This disclosure also provides a method for manufacturing a memory, used to produce the memory described in any of the foregoing embodiments. The structure of the memory will not be described again below; the method for manufacturing the memory will be described in detail.

[0061] In embodiments of this disclosure, the method for manufacturing the memory may include steps S100 and S102.

[0062] In step S100: A substrate 1 is provided. For example, an insulating substrate layer 11 may be formed on the semiconductor substrate layer 10 to form the substrate 1, see reference. Figure 7 As shown.

[0063] In step S102: at least one storage layer 2 is formed on the substrate 1. The step of forming the storage layer 2 may include at least:

[0064] Step S1021: A read transistor 201 is formed on the substrate 1. In this embodiment, the read transistor 201 has a gate trench.

[0065] In step S1022, a write transistor 202 is formed at the gate trench of the read transistor 201 to form a memory cell.

[0066] The following is combined with Figures 1 to 24 The manufacturing method of forming a storage layer on substrate 1 is described in detail below.

[0067] In some embodiments of this disclosure, the step of forming the storage layer 2 before step S1021 may further include steps S10200, S10201, S10202, and S10203.

[0068] In step S10200: a first signal line 204 is formed on the substrate 1, the first signal line 204 extending in the first horizontal direction X, referenced Figure 8 As shown. For example, a first metal thin film covering the entire surface can be deposited on the insulating substrate layer 11 of the substrate 1, and then the first metal thin film can be patterned to form a plurality of first signal lines 204 spaced apart in the second horizontal direction Y, as shown in the figure. Figure 9 As shown.

[0069] Among them, continue to refer to Figure 9 As shown, a first insulating isolation post 212 may be formed between adjacent first signal lines 204 to achieve mutual insulation between adjacent first signal lines 204. The top surface of the first insulating isolation post 212 may be flush with the top surface of the first signal line. It should be noted that the first insulating isolation post 212 may be formed on the substrate 1 before the first signal line 204, or the first signal line 204 may be formed on the substrate 1 before the first insulating isolation post 212.

[0070] In step S10201: A first interlayer insulating layer 206 is formed on the top surface of the first signal line 204. For example, after forming multiple first signal lines 204 spaced apart in the second horizontal direction Y, a first interlayer insulating layer 206 covering the entire surface can be deposited. In addition to covering the top surface of the first signal lines 204, the first interlayer insulating layer 206 can also cover the top surface of the first insulating isolation pillar 212. Afterwards, a chemical mechanical polishing process can be used to polish the top surface of the first interlayer insulating layer 206 into a plane.

[0071] It should be noted that if the first insulating isolation post 212 is formed after the first signal line 204, the first interlayer insulation layer 206 can be integrally formed with the first insulating isolation post 212, but it is not limited to this and can also be formed separately, that is: the first insulating isolation post 212 is formed first, and then the first interlayer insulation layer 206 is formed.

[0072] In step S10202: a second signal line 205 is formed on the top surface of the first interlayer insulating layer 206. The second signal line 205 extends in the second horizontal direction Y, and the orthographic projection of the second signal line 205 on the substrate 1 has a first overlapping area with the orthographic projection of the first signal line 204 on the substrate 1.

[0073] For example, step S10202 may include steps S102021 and S102022. Specifically, in step S102021: a second metal thin film 205a covering the entire surface of the first interlayer insulating layer 206 is first deposited, referring to… Figure 10 As shown. In step S102022: the second metal thin film 205a is patterned to form a plurality of second signal lines 205 spaced apart in the first horizontal direction X.

[0074] In step S10203: a first receiving hole 213 is formed. The orthographic projection of the first receiving hole 213 on the substrate 1 is located in the first overlapping region. The first receiving hole 213 penetrates the second signal line 205 and the first interlayer insulating layer 206, and exposes the first signal line 204.

[0075] Among them, reference Figure 11 As shown, step S10203 can be executed after step S102021 and before step S102022. In this case, the first receiving hole 213 mentioned in step S10203 penetrating the second signal line 205 can be understood as the first receiving hole 213 penetrating the portion of the second metal film 205a used to form the second signal line 205. It should be understood that step S10203 can also be executed after step S102022, depending on the specific circumstances.

[0076] For example, refer to Figure 11 As shown, the first receiving hole 213 can extend into the interior of the first signal line 204, thus ensuring the contact area between the subsequently formed read transistor 201 and the first signal line 204. However, it is not limited to this; the first receiving hole 213 can also extend just to the top surface of the first signal line 204, or the first receiving hole 213 can penetrate through the first signal line 204, depending on the specific situation. Furthermore, this embodiment may have multiple first receiving holes 213, arranged in an array in the first horizontal direction X and the second horizontal direction Y, as shown in the reference. Figure 12 As shown.

[0077] In some embodiments of this disclosure, the step of forming the read transistor 201 may include: forming a first semiconductor layer 2012, a first gate insulating layer 2013, and a first gate 2011 in a first receiving hole 213, wherein the first semiconductor layer 2012 at least horizontally surrounds the outer peripheral side of the first gate 2011, the first gate insulating layer 2013 is formed between the first gate 2011 and the first semiconductor layer 2012, the first gate 2011 includes a gate bottom wall 2011b and a gate side wall 2011a, the gate side wall 2011a is horizontally disposed around the gate bottom wall 2011b and extends in a direction away from the substrate 1, and the gate side wall 2011a and the gate bottom wall 2011b form a gate trench; wherein, the first signal line 204 may contact the bottom surface of the first semiconductor layer 2012 and / or the bottom region of the outer peripheral surface of the first semiconductor layer 2012, and the second signal line 205 surrounds the outer peripheral side of the first semiconductor layer 2012 and contacts the top region of the outer peripheral surface of the first semiconductor layer 2012.

[0078] It should be noted that step S102022 can be performed after the read transistor 201 is formed, but is not limited to this. It can also be performed before the read transistor 201 is formed, depending on the specific circumstances.

[0079] The steps for forming the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011 include steps S10210, S10211, S10212, S10213, and S10214.

[0080] In step S10210: A first semiconductor thin film 214 is formed on the substrate 1, with reference to... Figure 13 As shown, the first semiconductor thin film 214 completely covers the top surface of the second signal line 205, the wall surface of the first receiving hole 213, and the exposed surface of the first signal line 204 exposed by the first receiving hole 213. For example, the first semiconductor thin film 214 can be deposited using an atomic layer deposition process, and the first semiconductor thin film 214 can be fabricated conformally to the shape of the underlying structural layer. It should be understood that the portion of the first semiconductor thin film 214 located in the first receiving hole 213 belongs to the aforementioned first semiconductor layer 2012.

[0081] It should be noted that if step S102022 is executed after the formation of the read transistor 201, then the fact that the first semiconductor thin film 214 can completely cover the top surface of the second signal line 205 in step S10210 can be understood as the first semiconductor thin film 214 covering the second metal thin film 205a. (Refer to...) Figure 13 As shown.

[0082] In step S10211: A first gate insulating film 215 is formed on the first semiconductor thin film 214, the first gate insulating film 215 completely covering the first semiconductor thin film 214, as referenced. Figure 13 As shown. For example, an atomic layer deposition process can be used to deposit the first gate insulating film 215, which can be fabricated to conform to the shape of the underlying structural layer. It should be understood that the portion of the first gate insulating film 215 located at the first receiving hole 213 belongs to the aforementioned first gate insulating layer 2013.

[0083] In step S10212: A first conductive film 216 is formed on the first gate insulating film 215, the first conductive film 216 completely covering the first gate insulating film 215, as shown in the reference. Figure 13 As shown. For example, an atomic layer deposition process can be used to deposit a first conductive thin film 216, which can be fabricated conformally to the shape of the underlying structural layer. It should be understood that the portion of the first conductive thin film 216 located in the first receiving hole 213 belongs to the first gate 2011.

[0084] In step S10213: a filling film layer 217 is formed on the first conductive film 216, the filling film layer 217 completely covers the first conductive film 216, and fills the first receiving hole 213. The filling film layer 217 may include an insulating dielectric film 217a and a sacrificial material film 217b formed on the insulating dielectric film 217a, the insulating dielectric film 217a completely covering the first conductive film 216.

[0085] The portion of the insulating dielectric film 217a located at the gate trench belongs to the insulating dielectric section 203. The insulating dielectric section 203 may include an insulating dielectric sidewall 203a and an insulating dielectric bottom wall 203b. The insulating dielectric sidewall 203a is horizontally disposed around the insulating dielectric bottom wall 203b and extends in a direction away from the substrate 1. The insulating dielectric sidewall 203a and the insulating dielectric bottom wall 203b form an insulating dielectric trench. The sacrificial material film 217b completely covers the insulating dielectric film 217a and fills the first receiving hole 213.

[0086] For example, after the deposited sacrificial material film 217b completely covers the insulating dielectric film 217a and fills the first receiving hole 213, the sacrificial material film 217b can be ground using a chemical mechanical polishing process to make the top surface of the sacrificial material film 217b a flat plane, which is beneficial to the accuracy of subsequent processes.

[0087] In some embodiments, the material of the insulating dielectric film 217a may be a low dielectric material, and the material of the sacrificial material film 217b may be a polycrystalline silicon material or a silicon dioxide material. It can also be understood that the insulating dielectric portion 203 may include a low dielectric material portion, and the sacrificial material portion may include a polycrystalline silicon material layer or a silicon dioxide material layer.

[0088] In step S10214: The portions of the filling film layer 217, the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214 located outside the target range of the first receiving hole 213 are completely removed to expose the second signal line 205, and at the same time the first semiconductor layer 2012, the first gate insulating layer 2013 and the first gate 2011 are formed.

[0089] It should be noted that if step S102022 is performed after the read transistor 201 is formed, the exposure of the second signal line 205 mentioned in step S10214 can be understood as exposing at least a portion of the second metal thin film 205a used to form the second signal line 205.

[0090] In some embodiments, the step of completely removing the portions of the filling film 217, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 located outside the target range of the first receiving hole 213 may include: steps S102140, S102141, S102142, S102143, S102144, and S102145.

[0091] In step S102140: the portion of the filling film layer 217 above the top surface of the first conductive film 216 is removed to expose the top surface of the first conductive film 216. (Refer to...) Figure 14 As shown.

[0092] In step S102141: the portion of the filler film 217 above the top surface of the second signal line 205 is further etched away, so that the top surface of the remaining filler portion in the filler film 217 is flush with the top surface of the second signal line 205. (Refer to...) Figure 15 As shown.

[0093] It should be noted that if step S102022 is performed after the read transistor 201 is formed, the top surface of the fill retention portion retained in the fill film layer 217 mentioned in step S10214 being flush with the top surface of the second signal line 205 can be understood as making the top surface of the fill retention portion retained in the fill film layer 217 being flush with the top surface of the second metal thin film 205a.

[0094] Among them, reference Figure 15 As shown, the filling retention portion may include an insulating medium portion 203 and a sacrificial material portion 218. The insulating medium portion 203 may be located at the gate trench of the first gate 2011, and the sacrificial material portion 218 fills the insulating medium trench of the insulating medium portion 203.

[0095] For example, when the insulating dielectric film 217a in the filling film layer 217 is made of a low dielectric material and the sacrificial material film 217b is made of polycrystalline silicon, in steps S102140 and S102141, Cl2 (chlorine) and CHF3 (trifluoromethane) can be used to etch the filling film layer 217. It should be understood that attention should be paid to the flatness of the filling retention portion retained in the filling film layer 217 during etching.

[0096] In step S102142: A protective film layer 219 is formed on the top surface of the first conductive film 216 and the top surface of the filling retention portion, as shown in the reference. Figure 16 As shown. The protective film layer 219 is used to protect the filled portion during subsequent etching. It should be understood that the top surface of the formed protective film layer 219 can be understood as a horizontal plane, which can be a plane parallel or approximately parallel to the substrate 1.

[0097] Under the same etching conditions, the etching rate of the protective film layer 219 is lower than that of the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214. For example, the protective film layer 219 in this embodiment can be a carbon coating (Spin-On-Carbon, or SOC for short), but it is not limited to this, as long as the etching rate of the protective film layer 219 can be lower than that of the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214.

[0098] In step S102143: the portion of the protective film layer 219 above the top surface of the first conductive film 216 is etched away using a first etchant, so that the remaining protective portion 2190 in the protective film layer 219 at the filling retention portion is flush with the top surface of the first conductive film 216. (Refer to...) Figure 17 As shown. In embodiments of this disclosure, the first etchant may be an etching gas; for example, when the protective film layer 219 is a carbon coating, the first etchant may include a mixture of CF4 (carbon tetrafluoride) and O2 (oxygen).

[0099] In step S102144: the portions of the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 above the top surface of the second signal line 205 are completely removed using a second etchant to form the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011. Simultaneously, a portion of the remaining protective portion 2190 is etched away by the second etchant, leaving a portion of the remaining protective portion covering the filler portion. (Refer to...) Figure 18 As shown.

[0100] In this embodiment of the disclosure, the second etchant may be an etching gas; for example, the second etchant may include a mixed gas containing fluorine, chlorine and oxygen, such as a mixed gas of CF4, Cl2 (chlorine) and O2, which has a relatively low etching selectivity for the first conductive thin film material, the first gate insulating thin film material and the first semiconductor thin film material, which can improve the etching uniformity and make the top surfaces of the first semiconductor layer 2012, the first gate insulating layer 2013 and the first gate 2011 flush.

[0101] In step S102145: the remaining portion of the residual protective portion 2190 on the filler retention portion is completely removed using a third etchant, refer to... Figure 19 As shown, the top surface of the first semiconductor layer 2012, the first gate insulating layer 2013, the first gate 2011, and the filling retention portion is flush with the top surface of the second signal line 205, and the target range is located outside the first receiving hole 213.

[0102] It should be noted that if step S102022 is performed after the read transistor 201 is formed, the fact that the top surfaces of the first semiconductor layer 2012, the first gate insulating layer 2013, the first gate 2011, and the fill retention portion mentioned in step S10215 are flush with the top surface of the second signal line 205 can be understood as the top surfaces of the first semiconductor layer 2012, the first gate insulating layer 2013, the first gate 2011, and the fill retention portion being flush with the top surface of the second metal thin film 205a.

[0103] In this embodiment of the disclosure, either ashing or wet cleaning methods can be used to completely remove the portion of the remaining protective portion 2190 remaining on the filler film layer 217. When using the ashing method, the third etchant can be an asher gas, for example, the asher gas may include oxygen.

[0104] It should be noted that if the material of the insulating dielectric part 203 is a low dielectric material, then in step S102145, care should be taken to select the Asher gas ratio to reduce the oxidation of the low dielectric material, thereby reducing the possibility of defects forming in the insulating dielectric part 203.

[0105] In some other embodiments, the step of completely removing the portions of the filling film 217, the first conductive film 216, the first gate insulating film 215 and the first semiconductor film 214 located outside the target range of the first receiving hole 213 may include steps S102146 and S102147.

[0106] In step S102146: The portion of the sacrificial material film 217b that is above the top surface of the insulating dielectric film 217a is removed to expose the top surface of the insulating dielectric film 217a. The sacrificial material film 217b retained inside the insulating dielectric groove is divided into a sacrificial material section 218, the top surface of which is flush with the top surface of the insulating dielectric film 217a. (Refer to...) Figure 20 As shown.

[0107] In step S102147: the portions of the insulating dielectric film 217a, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 located outside the target area of ​​the first receiving hole 213 are etched away to form the insulating dielectric portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011. (Refer to...) Figure 21 As shown. The area outside the target range is the region where the distance between the target range and the boundary of the first receiving hole 213 exceeds a target value, where the target value is greater than 0. This results in the formation of an outwardly horizontally extending first semiconductor overlap portion 2012c on the top of the first semiconductor layer 2012, the first semiconductor overlap portion 2012c being formed on the top surface of the second signal line 205, the top of the first gate insulating layer 2013 having an outwardly horizontally extending first gate insulating overlap portion 2013c, the first gate insulating overlap portion 2013c being formed on the top surface of the first semiconductor overlap portion 2012c, the top of the gate sidewall 2011a having an outwardly horizontally extending gate overlap portion 2011c, the gate overlap portion 2011c being formed on the top surface of the first gate insulating overlap portion 2013c, and the top of the insulating dielectric sidewall 203a having an outwardly horizontally extending insulating dielectric overlap portion 203c, the insulating dielectric overlap portion 203c being formed on the top surface of the gate overlap portion 2011c.

[0108] It should be noted that if step S102022 is performed after the read transistor 201 is formed, the first semiconductor overlap portion 2012c mentioned in step S10214 being formed on the top surface of the second signal line 205 can be understood as the first semiconductor overlap portion 2012c being formed on the top surface of the second metal thin film 205a.

[0109] For example, in step S102147: a photolithography process can be used to etch away portions of the insulating dielectric film 217a, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 located outside the target area of ​​the first receiving hole 213, to form the insulating dielectric portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011; specifically, after step S102146, a full-surface-covering BARC material layer and a photoresist layer can be formed sequentially, and then... The photomask is used to pattern the BARC material layer and the photoresist layer to form a mask structure with the target pattern. Then, the etching process is performed using this mask structure to etch away the portions of the insulating dielectric film 217a, the first conductive film 216, the first gate insulating film 215, and the first semiconductor film 214 that are outside the target range of the first receiving hole 213, thereby forming the insulating dielectric portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013, and the first gate 2011.

[0110] The BARC (Bottom Anti-Reflection Coating) material layer is mainly used to reduce the amount of light reflected back to the photoresist layer during exposure, thereby reducing the standing wave effect and improving the accuracy of the photolithography process. The BARC material layer can be formed by spin coating, and its main components include cross-linkable resin, thermo-acid generator, surfactant, and solvent to reduce light interference.

[0111] It should be understood that after the insulating dielectric portion 203, the first semiconductor layer 2012, the first gate insulating layer 2013 and the first gate 2011 are formed, the mask structure formed by the BARC material layer and the photoresist layer can be removed.

[0112] For example, step S102022 of this embodiment can be executed after step S102147.

[0113] In some embodiments of this disclosure, the step of forming the write transistor 202 may include steps S10220, S10221, S10222 and S10223.

[0114] In step S10220: A second interlayer insulating layer 209 is formed on the top surface of the read transistor 201, the insulating dielectric portion 203, and the sacrificial material portion 218. It should be understood that the second interlayer insulating layer 209 can completely cover the structural layer located below it, and the top surface of the second interlayer insulating layer 209 can be a plane parallel or approximately parallel to the substrate 1 to ensure the flatness of the subsequent film layer formation.

[0115] In step S10221: A write bit line 207 is formed on the side of the second interlayer insulating layer 209 away from the substrate 1. The orthogonal projection of the write bit line 207 on the substrate 1 completely covers the orthogonal projection of the sacrificial material portion 218 on the substrate 1. (Refer to...) Figure 22 As shown. For example, a third metal film covering the entire surface of the second interlayer insulating layer 209 can be deposited, and then the third metal film can be patterned to form multiple write lines 207 spaced apart in the second horizontal direction Y (or the first horizontal direction X). A second insulating isolation pillar can also be provided between adjacent write lines 207, the top surface of which can be flush with the top surface of the write line 207 to ensure the flatness of subsequent film layer formation.

[0116] In this embodiment, the second insulating isolation post may be formed before the write bit line 207, or the write bit line 207 may be formed before the second insulating isolation post, depending on the specific situation.

[0117] In step S10222: the bottom wall 203b of the insulating dielectric layer 203 of the sacrificial material portion 218 and the insulating dielectric layer 203 is completely etched, and the portion of the second interlayer insulating layer 209 and the write line 207 located on the sacrificial material portion 218 is completely etched to form a second receiving hole 220, which exposes a portion of the gate bottom wall 2011b. The insulating dielectric sidewall 203a of the insulating dielectric layer 203 is retained. For example, the second receiving hole 220 may extend just into the interior of the gate bottom wall 2011b, thus ensuring the area at the subsequent formation of the memory node and thereby ensuring the storage capacitance, but is not limited thereto; see reference... Figure 23 As shown, the second receiving hole 220 may extend just to the top surface of the gate bottom wall 2011b, or the second receiving hole 220 may penetrate through the gate bottom wall 2011b, depending on the specific situation. In addition, it should be understood that there may be multiple second receiving holes 220 in this embodiment, and they may be arranged in an array in the first horizontal direction X and the second horizontal direction Y.

[0118] In step S10223: a second semiconductor layer 2022, a second gate insulating layer 2023, and a second gate 2021 are formed in the second receiving hole 220, with reference to... Figure 24 As shown. For example, the second semiconductor layer 2022, the second gate insulating layer 2023, and the second gate 2021 can be manufactured in the same manner as the first semiconductor layer 2012, the second gate insulating layer 2023, and the second gate 2021, which will not be described in detail here.

[0119] It should be noted that after forming the write transistor 202, the step of forming the memory layer 2 may further include sequentially forming the third interlayer insulating layer 210 and the write word line 208, as shown in the reference. Figure 3 As shown, I will not go into too much detail here.

[0120] Among them, if reference Figure 5 As shown, in two adjacent memory layers 2, the first signal line 204 of the top memory layer is not shared with the write word line 208 of the bottom memory layer. Therefore, it is possible to form the first signal line 204 of the top memory layer before forming the first signal line 208 of the bottom memory layer. Figure 5 The fourth interlayer insulating layer 211 shown will not be described in detail here. (Refer to...) Figure 6 As shown, in two adjacent storage layers 2, the first signal line 204 of the top storage layer is shared with the write line 208 of the bottom storage layer. Therefore, the fabrication of an insulating layer and a signal line can be omitted. That is, the steps of fabricating the fourth interlayer insulating layer 211 and the first signal line 204 in the top storage layer are omitted, so as to reduce the manufacturing cost and increase the storage density.

[0121] Furthermore, the terms "first," "second," "third," and "fourth," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," "third," or "fourth" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0122] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0123] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A memory comprising a substrate and at least one memory layer formed on the substrate, the memory layer comprising memory cells, characterized in that, The storage unit includes: A read transistor includes a first gate, a first semiconductor layer at least horizontally surrounding the outer periphery of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer. The first gate includes a gate bottom wall and a gate side wall. The gate side wall is horizontally disposed around the gate bottom wall and extends in a direction away from the substrate. The gate side wall and the gate bottom wall form a gate trench. The write transistor includes a second gate, a second semiconductor layer at least horizontally surrounding the outer periphery of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer, wherein a portion of the second semiconductor layer is embedded in the gate trench and in contact with at least a portion of the gate trench.

2. The memory according to claim 1, characterized in that, The second semiconductor layer, the second gate, and the second gate insulating layer each have an embedded portion embedded in the gate trench and an extension portion located on the side of the embedded portion away from the substrate, the extension portion being disposed to protrude away from the substrate relative to the read transistor.

3. The memory according to claim 2, characterized in that, The memory cell further includes an insulating dielectric sidewall, which is embedded in the gate trench and horizontally surrounds the outer periphery of the embedded portion in the second semiconductor layer. In this configuration, the outer peripheral surface of the embedded portion in the second semiconductor layer is insulated from the gate sidewall by the insulating dielectric sidewall, and the bottom surface of the embedded portion in the second semiconductor layer is in contact with the gate bottom wall.

4. The memory according to claim 3, characterized in that, The insulating dielectric sidewall includes a low-dielectric material portion, which horizontally surrounds the outer periphery of the embedding portion of the second semiconductor layer; and / or The insulating dielectric sidewall includes a silicon dioxide material layer, which horizontally surrounds the outer periphery of the embedded portion of the second semiconductor layer.

5. The memory according to claim 3, characterized in that, The embedding portion of the second semiconductor layer includes a second semiconductor sidewall and a second semiconductor bottom wall. The second semiconductor sidewall is horizontally disposed around the second semiconductor bottom wall and extends in a direction away from the substrate. The second semiconductor sidewall and the second semiconductor bottom wall form a second semiconductor trench. The embedding portion of the second gate and the embedding portion of the second gate insulating layer are located in the second semiconductor trench. The bottom surface of the second semiconductor bottom wall and the bottom surface of the second semiconductor side wall are both in contact with the bottom surface of the gate trench.

6. The memory according to claim 1, characterized in that, The storage layer also includes: A first signal line is formed on the substrate, the first signal line extends in a first horizontal direction and contacts the bottom surface of the first semiconductor layer and / or the bottom region of the outer peripheral surface of the first semiconductor layer; A second signal line is formed on the side of the first signal line away from the substrate. A first interlayer insulating layer is formed between the layer containing the second signal line and the layer containing the first signal line. The second signal line extends in a second horizontal direction that intersects with the first horizontal direction. The second signal line and the first interlayer insulating layer horizontally surround the outer periphery of the first semiconductor layer, and the second signal line contacts the top region of the outer periphery of the first semiconductor layer. In this configuration, one of the first signal line and the second signal line is a bit line, and the other is a word line.

7. The memory according to claim 6, characterized in that, The first semiconductor layer is formed on the side of the first signal line away from the substrate. The first semiconductor layer includes a first semiconductor sidewall and a first semiconductor bottom wall. The first semiconductor sidewall is horizontally disposed around the first semiconductor bottom wall and extends in a direction away from the substrate. The first semiconductor sidewall and the first semiconductor bottom wall form a first semiconductor trench. The first gate insulating layer includes a first gate insulating sidewall and a first gate insulating bottom wall. The first gate insulating bottom wall is located in the first semiconductor trench and is in contact with the top surface of the first semiconductor bottom wall. The first gate insulating sidewall is located at least in the first semiconductor trench and is horizontally arranged around the first gate insulating bottom wall. The first gate insulating sidewall extends in a direction away from the substrate and forms a first gate insulating trench with the first gate insulating bottom wall. The outer peripheral surface of the first gate insulating sidewall is in contact with the inner peripheral surface of the first semiconductor sidewall. The bottom wall of the gate is located within the first gate insulating groove and is in contact with the top surface of the first gate insulating bottom wall. The side wall of the gate is located at least within the first gate insulating groove, and the outer peripheral surface of the side wall of the gate is in contact with the inner peripheral surface of the first gate insulating side wall.

8. The memory according to claim 7, characterized in that, The top surface of the first semiconductor sidewall, the top surface of the first gate insulating sidewall, and the top surface of the gate sidewall are flush with the top surface of the second signal line; or The top of the first semiconductor sidewall has a first semiconductor overlap portion extending horizontally outward, the first semiconductor overlap portion being formed on the top surface of the second signal line. The top of the first gate insulating sidewall has a first gate insulating overlap portion extending horizontally outward, the first gate insulating overlap portion being formed on the top surface of the first semiconductor overlap portion. The top of the gate sidewall has a gate overlap portion extending horizontally outward, the gate overlap portion being formed on the top surface of the first gate insulating overlap portion.

9. The memory according to claim 6, characterized in that, The storage layer also includes: A write bit line is formed on the side of the second signal line away from the substrate. A second interlayer insulating layer is formed between the layer where the write bit line is located and the layer where the second signal line is located. The write bit line and the second interlayer insulating layer are horizontally surrounded around the outer periphery of the extension of the second semiconductor layer, and the write bit line is in contact with the outer periphery of the first semiconductor layer. A write word line is formed on the side away from the substrate of the extension of the write bit line and the second gate. A third interlayer insulating layer is formed between the layer where the write word line is located and the layer where the write bit line is located. The write word line is connected to the top surface of the extension of the second gate. Wherein, one of the write position line and the write character line extends in the first horizontal direction, and the other extends in the second horizontal direction.

10. The memory according to claim 9, characterized in that, The write line extends in the first horizontal direction, and the write character line extends in the second horizontal direction; and / or The top of the extension in the second semiconductor layer has a second semiconductor overlap extending horizontally outward, the second semiconductor overlap being formed on the top surface of the write bit line. The top of the extension in the second gate insulating layer has a second gate insulating overlap extending horizontally outward, the second gate insulating overlap being formed on the top surface of the second semiconductor overlap. The top surface of the extension in the second gate is flush with the top surface of the second gate insulating overlap. The storage layer also includes a conductive contact pad, the bottom surface of which contacts the top surface of the second gate insulating overlap and the top surface of the extension in the second gate. The top surface of the conductive contact pad is in contact with the bottom surface of the write bit line.

11. The memory according to claim 9, characterized in that, The storage layers are multiple, stacked perpendicular to the substrate. In adjacent storage layers, the layer closer to the substrate is defined as the bottom storage layer, and the layer farther from the substrate is defined as the top storage layer. In at least two adjacent memory layers: a fourth interlayer insulating layer is formed between the layer containing the first signal line of the top memory layer and the layer containing the write line of the bottom memory layer; and / or In at least two adjacent storage layers: the write line of the lower storage layer is shared as the first signal line of the upper storage layer.

12. A method for manufacturing a memory, characterized in that, The manufacturing method includes: Provide a base; At least one storage layer is formed on the substrate, wherein the step of forming the storage layer includes: A read transistor is formed on the substrate. The read transistor includes a first gate, a first semiconductor layer that is at least horizontally surrounding the outer periphery of the first gate, and a first gate insulating layer formed between the first gate and the first semiconductor layer. The first gate includes a gate bottom wall and a gate side wall. The gate side wall is horizontally disposed around the gate bottom wall and extends in a direction away from the substrate. The gate side wall and the gate bottom wall form a gate trench. A write transistor is formed at the gate trench to form a memory cell. The write transistor includes a second gate, a second semiconductor layer at least horizontally surrounding the outer periphery of the second gate, and a second gate insulating layer formed between the second gate and the second semiconductor layer. A portion of the second semiconductor layer is embedded in the gate trench and in contact with at least a portion of the gate trench.

13. The manufacturing method according to claim 12, characterized in that, Prior to the step of forming the read transistor, the step of forming the memory layer further includes: A first signal line is formed on the substrate, and the first signal line extends in a first horizontal direction; A first interlayer insulation layer is formed on the top surface of the first signal line; A second signal line is formed on the top surface of the first interlayer insulating layer. The second signal line extends in the second horizontal direction, and the orthographic projection of the second signal line on the substrate and the orthographic projection of the first signal line on the substrate have a first overlapping area. A first receiving hole is formed, the orthographic projection of the first receiving hole on the substrate is located in the first overlapping area, the first receiving hole penetrates the second signal line and the first interlayer insulation layer, and exposes the first signal line.

14. The manufacturing method according to claim 13, characterized in that, The steps for forming the read transistor include: A first semiconductor layer, a first gate insulating layer, and a first gate are formed in the first receiving hole. The first semiconductor layer is at least horizontally surrounding the outer periphery of the first gate. The first gate insulating layer is formed between the first gate and the first semiconductor layer. The first gate includes a gate bottom wall and a gate side wall. The gate side wall is horizontally disposed around the gate bottom wall and extends in a direction away from the substrate. The gate side wall and the gate bottom wall form a gate trench. The first signal line is in contact with the bottom surface of the first semiconductor layer and / or the bottom region of the outer peripheral surface of the first semiconductor layer, and the second signal line is wrapped around the outer peripheral side of the first semiconductor layer and in contact with the top region of the outer peripheral surface of the first semiconductor layer.

15. The manufacturing method according to claim 14, characterized in that, The steps of forming the first semiconductor layer, the first gate insulating layer, and the first gate include: A first semiconductor thin film is formed on the substrate, the first semiconductor thin film completely covering the top surface of the second signal line, the hole wall surface of the first receiving hole and the exposed surface of the first signal line exposed by the first receiving hole, wherein the portion of the first semiconductor thin film located in the first receiving hole belongs to the first semiconductor layer. A first gate insulating film is formed on the first semiconductor thin film, the first gate insulating film completely covering the first semiconductor thin film, wherein the portion of the first gate insulating film located at the first receiving hole belongs to the first gate insulating layer; A first conductive film is formed on the first gate insulating film, the first conductive film completely covering the first gate insulating film, wherein the portion of the first conductive film located at the first receiving hole belongs to the first gate; A filling film layer is formed on the first conductive film, the filling film layer completely covers the first conductive film and fills the first receiving hole; The portions of the filler film, the first conductive film, the first gate insulating film, and the first semiconductor film located outside the target range of the first receiving hole are completely removed to expose the second signal line, while simultaneously forming the first semiconductor layer, the first gate insulating layer, and the first gate.

16. The manufacturing method according to claim 15, characterized in that, The step of completely removing the portions of the filler film, the first conductive film, the first gate insulating film, and the first semiconductor film located outside the target range of the first receiving hole includes: Remove the portion of the filler layer that is above the top surface of the first conductive film to expose the top surface of the first conductive film; The portion of the filler film layer that is higher than the top surface of the second signal line is etched away, so that the top surface of the remaining filler portion in the filler film layer is flush with the top surface of the second signal line; A protective film layer is formed on the top surface of the first conductive film and the top surface of the filling retention portion. The top surface of the protective film layer is a horizontal plane. Under the same etching conditions, the etching rate of the protective film layer is less than the etching rate of the first conductive film, the first gate insulating film and the first semiconductor film. The portion of the protective film layer above the top surface of the first conductive film is etched away using a first etchant, so that the remaining protective portion in the protective film layer at the filling retention portion is flush with the top surface of the first conductive film. The portion of the first conductive film, the first gate insulating film, and the first semiconductor film above the top surface of the first signal line is completely removed by the second etchant to form the first semiconductor layer, the first gate insulating layer, and the first gate. At the same time, the remaining protective portion is etched away by a portion of its height under the action of the second etchant, and a portion of the remaining protective portion still covers the filling and retention portion. The remaining portion of the protective portion remaining on the filled and retained portion is completely removed using a third etchant. Wherein, the top surface of the first semiconductor layer, the first gate insulating layer, the first gate, and the top surface of the filling retention portion are flush with the top surface of the second signal line, and the target range is located outside the first receiving hole.

17. The manufacturing method according to claim 16, characterized in that, The filling retention portion includes: An insulating dielectric portion is located at the gate trench of the first gate. The insulating dielectric portion includes an insulating dielectric bottom wall and an insulating dielectric side wall. The insulating dielectric side wall is horizontally disposed around the insulating dielectric bottom wall and extends in a direction away from the substrate. The insulating dielectric side wall and the insulating dielectric bottom wall form an insulating dielectric trench. The sacrificial material section is filled into the insulating medium tank.

18. The manufacturing method according to claim 15, characterized in that, The filling film layer includes an insulating dielectric film and a sacrificial material film formed on the insulating dielectric film. The insulating dielectric film completely covers the first conductive film, and the portion of the insulating dielectric film located at the gate trench belongs to the insulating dielectric portion. The insulating dielectric portion includes an insulating dielectric bottom wall and an insulating dielectric side wall. The insulating dielectric side wall is horizontally disposed around the insulating dielectric bottom wall and extends in a direction away from the substrate. The insulating dielectric side wall and the insulating dielectric bottom wall form an insulating dielectric trench. The sacrificial material film completely covers the insulating dielectric film and fills the first receiving hole. The step of completely removing the portions of the filling film, the first conductive film, the first gate insulating film, and the first semiconductor film located outside the target range of the first receiving hole includes: The portion of the sacrificial material film that is above the top surface of the insulating dielectric film is etched away to expose the top surface of the insulating dielectric film. The sacrificial material film is divided into sacrificial material portions inside the insulating dielectric groove, and the top surface of the sacrificial material portions is flush with the top surface of the insulating dielectric film. The portions of the insulating dielectric film, the first conductive film, the first gate insulating film, and the first semiconductor film located outside the target range of the first receiving hole are etched away to form the insulating dielectric portion, the first semiconductor layer, the first gate insulating layer, and the first gate. Wherein, the area outside the target range is the region where the distance between the first receiving hole and the hole boundary exceeds a target value, the target value being greater than 0, so that a first semiconductor overlap portion extending horizontally outward is formed on the top of the first semiconductor layer, the first semiconductor overlap portion is formed on the top surface of the second signal line, the top of the first gate insulating layer has a first gate insulating overlap portion extending horizontally outward, the first gate insulating overlap portion is formed on the top surface of the first semiconductor overlap portion, the top of the gate sidewall has a gate overlap portion extending horizontally outward, the gate overlap portion is formed on the top surface of the first gate insulating overlap portion, the top of the insulating dielectric sidewall has an insulating dielectric overlap portion extending horizontally outward, the insulating overlap portion is formed on the top surface of the gate overlap portion.

19. The manufacturing method according to claim 17 or 18, characterized in that, The insulating dielectric sidewall includes a low dielectric material portion, and the sacrificial material portion includes a polycrystalline silicon material layer or a silicon dioxide material layer.

20. The manufacturing method according to claim 17 or 18, characterized in that, The steps for forming the write transistor include: A second interlayer insulating layer is formed on the top surface of the read transistor, the insulating dielectric portion, and the sacrificial material portion; A write bit line is formed on the side of the second interlayer insulating layer away from the substrate, and the orthogonal projection of the write bit line on the substrate completely covers the orthogonal projection of the sacrificial material portion on the substrate; The sacrificial material portion and the bottom wall of the insulating medium are completely etched, and the portion of the second interlayer insulating layer and the write line located on the sacrificial material portion are completely etched to form a second receiving hole, the second receiving hole exposing a portion of the gate bottom wall; The second semiconductor layer, the second gate insulating layer, and the second gate are formed in the second receiving hole.

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