Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device includes: forming a stack including a recessed target layer over a lower structure; forming a sacrificial isolation opening in the stack; forming a sacrificial isolation layer including a barrier layer in the sacrificial isolation opening; forming sacrificial vertical openings in the stack between the sacrificial isolation layers; forming a preliminary horizontal layer by recessing a recessing target layer of the stack via the sacrificial vertical opening; forming a first dielectric layer covering the preliminary horizontal layer; forming a second dielectric layer over the first dielectric layer; forming a cell isolation opening by removing the sacrificial isolation layer; and trimming the first dielectric layer through the cell isolation opening.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0099009, filed on July 28, 2023, and Korean Patent Application No. 10-2023-0112730, filed on August 28, 2023, both of which are incorporated herein by reference in their entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a three-dimensionally arranged memory cell and a method for manufacturing the semiconductor device. Background Art

[0004] Recently, in order to cope with demands for large capacity and miniaturization of memory devices, a technology for providing a 3D memory device in which a plurality of memory cells are stacked has been proposed. Summary of the invention

[0005] Embodiments of the present invention relate to a semiconductor device including a highly integrated memory cell and a method for manufacturing the semiconductor device.

[0006] According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack including a recessed target layer above a lower structure; forming a sacrificial isolation opening in the stack; forming a sacrificial isolation layer including a barrier layer in the sacrificial isolation opening; forming a sacrificial vertical opening in the stack between the sacrificial isolation layers; forming a preliminary horizontal layer by recessing the recessed target layer of the stack through the sacrificial vertical opening; forming a first dielectric layer covering the preliminary horizontal layer; forming a second dielectric layer above the first dielectric layer; forming a cell isolation opening by removing the sacrificial isolation layer; and trimming the first dielectric layer through the cell isolation opening.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack including a single crystal silicon layer; forming a sacrificial isolation opening in the stack; forming a blocking structure for blocking the single crystal silicon layer above the sacrificial isolation opening; forming a sacrificial isolation layer filling the sacrificial isolation opening above the blocking structure; forming a sacrificial vertical opening adjacent to the sacrificial isolation layer in the stack; and recessing the single crystal silicon layer through the sacrificial vertical opening.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a stack including multiple single crystal silicon layers and multiple silicon germanium layers; forming multiple sacrificial isolation openings in the stack; forming a blocking structure for blocking the single crystal silicon layer above the sacrificial isolation openings; forming multiple sacrificial isolation layers filling the sacrificial isolation openings above the blocking structure; forming a sacrificial vertical opening adjacent to the sacrificial isolation layer in the stack; and recessing the single crystal silicon layer through the sacrificial vertical openings.

[0009] According to still another embodiment of the present invention, the sacrificial isolation layer may be prevented from being exposed during a recessing process (or a trimming process) of recessing the target layer by forming a barrier layer.

[0010] These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments of the present invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention.

[0012] Figure 1B It is shown Figure 1A Schematic cross-sectional view of a memory cell shown in FIG.

[0013] Figure 1C It is shown Figure 1A A plan view of the switching element shown in FIG.

[0014] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present invention.

[0015] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention.

[0016] Figure 3A It is shown Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown in FIG.

[0017] Figure 3B is along Figure 2 A cross-sectional view taken along the line AA′ shown in FIG.

[0018] Figure 3C is along Figure 2 A cross-sectional view taken along line BB' shown in FIG.

[0019] Figure 3D is along Figure 2 A cross-sectional view taken along line CC' shown in FIG.

[0020] FIG. 4A to FIG. 26BAn example of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0021] FIG. 27A to FIG. 28B is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0022] Figures 29A to 29C is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0023] Figure 30 to Figure 32 is a perspective view showing a memory cell array according to another embodiment of the present invention. DETAILED DESCRIPTION

[0024] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout the disclosure, in multiple figures and embodiments of the present invention, the same reference numerals refer to the same parts.

[0025] The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer exists between the first layer and the second layer or between the substrate.

[0026] The following embodiments of the present invention relate to three-dimensional memory cells, and memory cells can be stacked vertically to increase memory cell density and reduce parasitic capacitance.

[0027] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention. Figure 1B It is shown Figure 1A Schematic cross-sectional view of a memory cell shown in FIG. Figure 1C It is shown Figure 1A A plan view of the switching element shown in FIG.

[0028] refer to Figures 1A to 1C , the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0029] The first conductive line BL may be oriented in a first direction D1. The first direction may be a vertical direction. In some embodiments, the first conductive line BL may be a bit line or include a bit line. The first conductive line BL may be referred to as a vertical conductive line, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first conductive line BL may include a conductive material. The first conductive line BL may include a silicon-based material, a metal-based material, or a combination thereof. The first conductive line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductive line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductive line BL may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The first conductive line BL may include a stack of titanium nitride and tungsten (TiN / W).

[0030] The switching element TR may have a function of controlling the supply of voltage (or current) to the data storage element CAP in a data write or data read operation of the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second conductive line DWL. The second conductive line DWL may include a horizontal conductive line or a word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, in which case the second conductive line DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second conductive line DWL may be referred to as a horizontal gate electrode or a horizontal word line.

[0031] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. It should be understood that although the second direction D2 and the third direction D3 are shown and referred to as horizontal directions, and the elements extending in the second direction and / or the third direction may be referred to as horizontal elements, this is only one embodiment of the present invention, and generally the second direction and the third direction may be referred to as second lateral and third lateral directions, and the elements extending in the second direction and / or the third direction may be referred to as lateral elements. The lateral direction may include a horizontal direction, but may not be limited to only a horizontal direction. Similarly, the lateral element may be a horizontal element, but may not be limited to only a horizontal element. The second conductive line DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. In the illustrated embodiment, the first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in a first horizontal direction (i.e., D2), and the second conductive line DWL may extend in a second horizontal direction (i.e., D3).

[0032] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first conductive line BL. The second conductive line DWL may have a dual structure. For example, the second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other, with the horizontal layer HL interposed therebetween. The interlayer dielectric layer GD may be formed on the top surface and the bottom surface of the horizontal layer HL. The upper horizontal line G1 may be disposed above the horizontal layer HL, and the lower horizontal line G2 may be disposed below the horizontal layer HL. The second conductive line DWL may include a pair of upper horizontal lines G1 and lower horizontal lines G2. In the second conductive line DWL, the same driving voltage may be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 may form a pair to be coupled to one memory cell MC. In some embodiments, different driving voltages may be applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, one of the upper horizontal line G1 and the lower horizontal line G2 may be used as a back gate or a shield gate.

[0033] Return to reference Figure 1C , each of the upper horizontal line G1 and the lower horizontal line G2 may have a width in the second direction D2, for example, a width of an overlapping portion overlapping with the horizontal layer HL, which is greater than a width of a portion not overlapping with the horizontal layer HL. Due to the width difference, the second conductive line DWL may have a sidewall in a notch shape. The second conductive line DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP refers to a portion overlapping with the channel CH of the horizontal layer HL, and the channel non-overlapping portion NOL refers to a portion not overlapping with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape. The second conductive line may have a cross shape or a diamond shape.

[0034] From a top view perspective, the horizontal layer HL may have a cross shape or a diamond shape. In some embodiments, a side surface of the horizontal layer HL may have a curved shape or a rounded shape.

[0035] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polycrystalline silicon, single crystal silicon, germanium, or silicon germanium. In some embodiments, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). In some embodiments, the horizontal layer HL may include a conductive metal oxide.

[0036] The top surface and the bottom surface of the horizontal layer HL may have flat surfaces. The top surface and the bottom surface of the horizontal layer may also be referred to as an upper surface and a lower surface. The top surface and the bottom surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0037] The horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP. When the horizontal layer HL may be formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first doping region SR and the second doping region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body. The channel CH and the channel overlap portion WLP of the second conductive line DWL may overlap each other. The channel CH may have a cross shape or a diamond shape. The size of the channel overlap portion WLP of the second conductive line DWL may be greater than the size of the channel CH. The channel overlap portion WLP of the second conductive line DWL may completely overlap with the channel CH.

[0038] The first doping region SR and the second doping region DR may be doped with impurities of the same conductivity type. The first doping region SR and the second doping region DR may be doped with N-type impurities or P-type impurities. The first doping region SR and the second doping region DR may include at least one impurity selected from the following: arsenic (As), phosphorus (P), boron (B), indium (In), and a combination thereof. The first doping region SR may be coupled to the first conductive line BL, and the second doping region DR may be coupled to the data storage element CAP. The first doping region SR and the second doping region DR may be referred to as a first source / drain region and a second source / drain region.

[0039] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second conductive line DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer dielectric layer GD may be formed by thermal oxidation of a semiconductor material.

[0040] The second conductive line DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second conductive line DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second conductive line DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked sequentially. The second conductive line DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or greater. The second conductive line DWL may include a stack of a low work function material and a high work function material.

[0041] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally arranged in the second direction D2 from the switching element TR. The data storage element CAP may include a first electrode SN, which extends horizontally in the second direction D2 from the horizontal layer HL. The data storage element CAP may also include a second electrode PN located above the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged horizontally in the second direction D2. The first electrode SN may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode SN may include a plurality of inner surfaces. The outer surface of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically in the first direction D1, and the horizontal outer surface of the first electrode SN may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be arranged in the inner space of the first electrode SN above the dielectric layer DE. Some of the outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL.

[0042] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a 3D structure, and the first electrode SN of the 3D structure may have a horizontal 3D structure oriented in the second direction D2. As an example of a 3D structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0043] In some embodiments, the first electrode SN may have a column shape or a cylindrical barrel shape. The cylindrical barrel shape refers to a structure in which a column shape and a barrel shape are combined together.

[0044] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the first electrode SN, titanium nitride (TiN) may be used as a second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0045] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In some embodiments, the dielectric layer DE may be formed by a composite layer including two or more layers of the above-mentioned high-k materials.

[0046] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO2). The dielectric layer DE may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack may be referred to as layers based on zirconium oxide (ZrO2). In some embodiments, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a stacked structure including hafnium oxide (HfO2). The dielectric layer DE may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked in sequence. The HA stack and the HAH stack may be referred to as layers based on hafnium oxide (HfO2). In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a band gap energy greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a dielectric constant lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-band gap material having a band gap energy greater than that of the high-k material. The dielectric layer DE may include silicon oxide (SiO2) instead of aluminum oxide (Al2O3) as a high band gap material. Since the dielectric layer DE includes a high bandgap material, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. In some embodiments, the dielectric layer DE may include a stacking structure in which the high-k material and the high bandgap material are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O2 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above stacking structure, aluminum oxide (Al2O3) may be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0047] In some embodiments, the dielectric layer DE may include a high-k material and a high bandgap material, and may include a stacked structure in which a plurality of high-k materials and a plurality of high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0048] In some embodiments, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof For example, the dielectric layer DE may include hafnium zirconium oxide (HfZrO).

[0049] In some embodiments, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of a ferroelectric material and an antiferroelectric material.

[0050] In some embodiments, an interface control layer for improving leakage current may be further formed between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN) or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0051] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0052] For example, the memory cell MC may include a thyristor, the first conductive line BL may be a cathode line, and the data storage element CAP may include an anode line. Therefore, the horizontal layer HL may include four semiconductor layers stacked in the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a large amount of current flows or a low conductance state in which a small amount of current flows or no current flows. Each memory cell MC according to an embodiment of the present invention may have a "1" state or a "0" state based on the high conductance state and the low conductance state of the thyristor.

[0053] Return to reference Figure 1A and Figure 1B , the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and each of the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0054] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present invention. Figure 1D The memory cell MC1 shown may be similar to Figures 1A to 1C The memory cell MC shown in FIG. 1 may be omitted in the following description. Figures 1A to 1C Detailed description of the components in .

[0055] The memory cell MC1 may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second conductive line DWL. The horizontal layer HL may include a first doped region SR, a second doped region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.

[0056] The memory cell MC1 may further include a first contact node BLC between the first conductive line BL and the horizontal layer HL and a second contact node SNC between the horizontal layer HL and the data storage element CAP. The first contact node BLC and the second contact node SNC may include doped polysilicon. Each of the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0057] The second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2. Each of the upper horizontal line G1 and the lower horizontal line G2 may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be horizontally arranged along the second direction D2. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be in direct contact with each other. The second work function electrode G12 may be arranged adjacent to the first conductive line BL, and the third work function electrode G13 may be arranged adjacent to the data storage element CAP. The thickness of the horizontal layer HL may be thinner than the thickness of each of the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0058] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be formed of materials having different work functions. The work function of the first work function electrode G11 may be higher than the work function of the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function higher than the mid-bandgap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may include a low work function material. The second work function electrode G12 and the third work function electrode G13 may have a work function lower than the mid-bandgap work function of silicon. The high work function material may have a work function higher than about 4.5 eV, and the low work function material may have a work function lower than about 4.5 eV. The first work function electrode G11 may include a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may include a semiconductor material.

[0059] The second work function electrode G12 and the third work function electrode G13 may include doped polysilicon doped with an N-type dopant (polysilicon doped with an N-type dopant). The first work function electrode G11 may include a metal, a metal nitride, or a combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may be further formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0060] According to this embodiment of the present invention, each of the upper horizontal line G1 and the lower horizontal line G2 of the second conductive line DWL may include a second work function electrode G12-a first work function electrode G11-a third work function electrode G13 horizontally arranged in the second direction D2. The first work function electrode G11 may include metal, and the second work function electrode G12 and the third work function electrode G13 may include polysilicon.

[0061] Each of the upper horizontal line G1 and the lower horizontal line G2 of the second conductive line DWL may have a PMP (polysilicon-metal-polysilicon) structure, in which polysilicon, metal, and polysilicon are horizontally arranged in the second direction D2. In the PMP structure, the first work function electrode G11 may be a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may be polysilicon doped with an N-type dopant, which is polysilicon doped with an N-type dopant. The N-type dopant may include phosphorus or arsenic.

[0062] The first barrier layer G12L may be disposed between the first work function electrode G11 and the second work function electrode G12. The second barrier layer G13L may be disposed between the first work function electrode G11 and the third work function electrode G13. The first barrier layer G12L and the second barrier layer G13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G13L may cover the upper surface, the lower surface, and one side surface of the first work function electrode G11.

[0063] The first work function electrode G11 may have a larger volume than the second work function electrode G12 and the third work function electrode G13, so the second conductive line DWL will have a low resistance. The first work function electrode G11 of the upper horizontal line G1 and the lower horizontal line G2 may overlap vertically in the first direction D1, with the horizontal layer HL interposed therebetween. The second work function electrode G12 and the third work function electrode G13 of the upper horizontal line G1 and the lower horizontal line G2 may overlap vertically in the first direction D1, with the horizontal layer HL interposed therebetween. The overlapping area between the first work function electrode G11 and the horizontal layer HL may be greater than the overlapping area between the second work function electrode G12 and the third work function electrode G13 and the horizontal layer HL. The second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11 may extend in the third direction D3, and the second work function electrode G12 and the third work function electrode G13 and the first work function circuit electrode G11 may be in direct contact with each other.

[0064] As described above, each of the upper horizontal line G1 and the lower horizontal line G2 may have a three-electrode structure including a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second conductive line DWL may include a pair of first work function electrodes G11, a pair of second work function electrodes G12, and a pair of third work function electrodes G13, which extend in a third direction D3 intersecting the horizontal layer HL, with the horizontal layer HL interposed therebetween. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may vertically overlap the channel CH.

[0065] like Figure 1CAs shown, each second conductive line DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or a rhombus shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductive line DWL extending in the third direction D3 through the channel overlap portion WLP and the channel non-overlap portion NOL may have a notched sidewall. From the perspective of the top view, the notched sidewall may be provided by a protruding portion of the channel overlap portion WLP and a recessed portion of the channel non-overlap portion NOL. The channel overlap portion WLP may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13, and the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may overlap vertically with the channel CH.

[0066] In the second direction D2, the first work function electrode G11 having a high work function may be arranged at the center of the second conductive line DWL, and the second work function electrode G12 and the third work function electrode G13 having a low work function may be disposed at both ends of the second conductive line DWL. In this way, leakage current problems such as gate induced drain leakage (GIDL) may be improved.

[0067] Since the first work function electrode G11 having a high work function is disposed at the center of the second conductive line DWL, the threshold voltage of the switching element TR can be increased. Since the second work function electrode G12 of the second conductive line DWL has a low work function, a low electric field can be formed between the first conductive line BL and the second conductive line DWL. Since the third work function electrode G13 of the second conductive line DWL has a low work function, a low electric field can be formed between the data storage element CAP and the second conductive line DWL.

[0068] As described above, the memory cell MC1 may include a second conductive line DWL having a three-work function electrode structure. Each of the upper horizontal line G1 and the lower horizontal line G2 of the second conductive line DWL may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11 may overlap the channel CH, and the second work function electrode G12 may be disposed adjacent to the first conductive line BL and the first doping region SR. The third work function electrode G13 may be disposed adjacent to the data storage element CAP and the second doping region DR. Due to the low work function of the second work function electrode G12, a low electric field may be formed between the second conductive line DWL and the first conductive line BL, thereby reducing leakage current. Due to the low work function of the third work function electrode G13, a low electric field may be formed between the second conductive line DWL and the data storage element CAP, thereby reducing leakage current. Due to the high work function of the first work function electrode G11, a high threshold voltage of the switching element TR may be formed, and the formation of the low electric field may reduce the height of the memory cell MC1, which is advantageous in terms of integration.

[0069] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention. Figure 3A It is shown Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown in FIG. Figure 3B is along Figure 2 A cross-sectional view taken along line AA′ shown in FIG. Figure 3C is along Figure 2 A cross-sectional view taken along line BB' shown in FIG. Figure 3D is along Figure 2 A cross-sectional view taken along the line CC' shown in FIG.

[0070] refer to Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. Regarding the memory cells MC, reference may be made to Figures 1A to 1C Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0071] The memory cell array MCA may include a three-dimensional array of memory cells MC. The 3D array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may have a plurality of memory cells MC stacked in a first direction D1, and the row array of memory cells MC may have a plurality of memory cells MC horizontally arranged in a second direction D2 and a third direction D3. The memory cell array MCA may include a sub-memory cell array MCA1 arranged adjacent to each other in the second direction D2. The sub-memory cell array MCA1 may have a mirror-type structure in which two memory cells MC share a first conductive line BL. In some embodiments, the semiconductor device 100 may further include a sub-memory cell array of a mirror-type structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 in which the memory cells MC are vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 arranged horizontally in the third direction D3.

[0072] In some embodiments, the memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 arranged along the second direction. For example, the data storage element CAP, the switching element TR, the first conductive line BL and the switching element TR may be alternately arranged in the second direction D2 in the stated order.

[0073] The inter-cell dielectric layer IL may be disposed between the memory cells MC stacked along the first direction D1. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may be referred to as a horizontal inter-cell dielectric layer.

[0074] The cell isolation layers ISOA and ISOB may be disposed between adjacent memory cells MC in the third direction D3. The cell isolation layers ISOA and ISOB may be referred to as vertical inter-cell dielectric layers. The cell isolation layers ISOA and ISOB may include silicon oxide, silicon oxycarbide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers ISOA and ISOB may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may have a columnar structure extending vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately and repeatedly disposed in the second direction D2. The first cell isolation layer ISOA may be disposed between the data storage elements CAP along the third direction D3. The second cell isolation layer ISOB may be disposed between the first conductive lines BL along the third direction D3. The second conductive line DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB in the second direction D2. Each of the first cell isolation layer ISOA and the second cell isolation layer ISOB may include a stack of a cell isolation liner layer ISOL and a cell isolation gap-filling layer ISOG. The cell isolation liner layer ISOL may include silicon oxycarbide, and the cell isolation gap-filling layer ISOG may include silicon oxide.

[0075] The memory cell array MCA may be disposed on the lower structure LS.

[0076] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked in a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked in the first direction D1. The memory cell array MCA may include a plurality of first conductive lines BL spaced apart from each other in a third direction D3.

[0077] like Figure 1C As shown, each second conductive line DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may have a cross shape or a diamond shape. The channel overlapping portion WLP may completely overlap with the channel CH. The second conductive line DWL extending in the third direction D3 may include a plurality of channel overlapping portions WLP. Since the channel overlapping portion WLP and the channel non-overlapping portion NOL are alternately repeated in the third direction D3, the second conductive line DWL may have a notched sidewall.

[0078] A plurality of first passivation layers BF1 may be disposed between the lowermost second conductive line DWL among the second conductive lines DWL and the lower structure LS. The second passivation layer BF2 may be disposed between the first conductive line BL and the lower structure LS. The third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include silicon oxide. The first to third passivation layers BF1, BF2, and BF3 may electrically disconnect the first conductive line BL, the second conductive line DWL, and the data storage element CAP from the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may be referred to as a bottom dielectric layer or a bottom passivation layer. The lowermost inter-cell dielectric layer LIL may be disposed between the first passivation layer BF1 and the data storage element CAP.

[0079] The first conductive line BL may extend vertically from the upper portion of the lower structure LS in the first direction D1. The horizontal layer HL may extend in the second direction D2 crossing the first direction D1. The second conductive line DWL may extend in the third direction D3 crossing the first direction D1 and the second direction D2.

[0080] From the perspective of the top view, the horizontal layer HL may have a cross shape or a diamond shape. In some embodiments, the side surface of the horizontal layer HL may have a curved shape or a round shape. Figure 1B As shown, the horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP.

[0081] The first cover layer BC may be disposed between the second conductive line DWL and the first conductive line BL. The second cover layer CC may be disposed between the second conductive line DWL and the first electrode SN of the data storage element. The first cover layer BC may be disposed between the upper horizontal line G1 and the first conductive line BL, and the first cover layer BC may be disposed between the lower horizontal line G2 and the first conductive line BL. The second cover layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC may be disposed between the lower horizontal line G2 and the first electrode SN of the data storage unit CAP. One memory cell MC may include a pair of first cover layers BC and a pair of second cover layers CC.

[0082] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround an outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BL may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BL and the second contact node SNC, respectively.

[0083] The first cover layer BC and the second cover layer CC may include a dielectric material. The first cover layer BC and the second cover layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, an air gap or a combination thereof. The first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride.

[0084] The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may share one second conductive line DWL. The horizontal layers HL of the switching elements TR horizontally arranged in the third direction D3 may be coupled to different first conductive lines BL. The switching elements TR stacked in the first direction D1 may share one first conductive line BL. The switching elements TR horizontally arranged in the third direction D3 may share one second conductive line DWL.

[0085] The first cell isolation layer ISOA may be disposed between the first electrodes SN of the data storage element CAP along the third direction D3. The first electrodes SN may be isolated from each other by the first cell isolation layer ISOA. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0086] The lower structure LS may include a semiconductor substrate, a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, and other memory or peripheral circuit units.

[0087] For example, the lower structure LS may include a structure in which a peripheral circuit unit, a metal interconnection structure, and a bonding pad structure are sequentially stacked. The memory cell array MCA and the peripheral circuit unit of the lower structure LS may be coupled by wafer bonding.

[0088] The peripheral circuit unit of the lower structure LS may be arranged at a level lower than the memory cell array MCA. This may be referred to as a peripheral upper unit (COP) structure. The peripheral circuit unit may include at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit unit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit unit may include an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit of the peripheral circuit unit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0089] For example, the peripheral circuit unit may include a sub word line driver and a sense amplifier. The second conductive line DWL may be coupled to the sub word line driver. The first conductive line BL may be coupled to the sense amplifier.

[0090] In some embodiments, the peripheral circuit unit may be disposed at a higher level than the memory cell array MCA. This may be referred to as a peripheral-on-cell (POC) structure.

[0091] In some embodiments, the memory cell array MCA may include dynamic random access memory (DRAM), embedded DRAM, NAND memory, ferroelectric RAM (FeRAM), spin transfer torque RAM (STTRAM), phase change RAM (PCRAM), or resistive RAM (ReRAM).

[0092] In some embodiments, Figure 1D The memory cell MC1 shown in FIG. 1 is used instead of the individual memory cells MC.

[0093] FIG. 4A to FIG. 26B An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0094] Figure 4A is a plan view of the fourth level 14 showing a method for forming the stacked body SB and the sacrificial isolation openings 15A and 15B, Figure 4B is along Figure 4A A cross-sectional view taken along line AA′ shown in FIG. Figure 4C is along Figure 4A A cross-sectional view taken along line BB' is shown.

[0095] Reference FIG. 4A to FIG. 4C, the stack SB may be formed on the lower structure 11. The lower structure 11 may be a material suitable for semiconductor processing. The lower structure 11 may include at least one of a conductive material, a dielectric material, and a semiconductor material. A variety of materials may be formed on the lower structure 11. The lower structure 11 may include a semiconductor substrate. The lower structure 11 may be formed of a material containing silicon. The lower structure 11 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The lower structure 11 may also include other semiconductor materials such as germanium. The lower structure 11 may include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The lower structure 11 may include a silicon-on-insulator (SOI) substrate.

[0096] In the stack SB, a plurality of sub-stacks SB1, SB2 and SB3 may be alternately stacked. Each sub-stack may include a first layer 12A, a second layer 13 and a third layer 12B. A fourth layer 14 may be disposed between adjacent sub-stacks. The first layer 12A and the third layer 12B may be formed of the same material and may include silicon germanium. The second layer 13 and the fourth layer 14 may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B and the fourth layer 14 may be formed by an epitaxial growth process. The first layer 12A of the lowermost layer may be used as a seed layer during the epitaxial growth process. The first layer 12A may be thinner than the second layer 13, and the fourth layer 14 may be thicker than the third layer 13.

[0097] The stack SB may include a plurality of fourth layers 14, a first sub-stack SB1, a second sub-stack SB2, and a third sub-stack SB3. In the stack SB, the first sub-stack SB1, the fourth layer 14, the second sub-stack SB2, the fourth layer 14, and the third sub-stack SB3 may be stacked in the order described. The second layer 13 may be disposed on the uppermost layer of the stack SB. Each of the first sub-stack SB1, the second sub-stack SB2, and the third sub-stack SB3 may be a three-layer stack of the first layer 12A / the second layer 13 / the third layer 12B. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 includes a single crystal silicon layer, the first sub-stack SB1, the second sub-stack SB2, and the third sub-stack SB3 may include a stack of a first silicon germanium / single crystal silicon / a second silicon germanium (SiGe / Si / SiGe).

[0098] The second layer 13 may include a first single crystal silicon layer, and the fourth layer 14 may include a second single crystal silicon layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer. Therefore, in the stack SB, the first sub-stack SB1 may be disposed below the second single crystal silicon layer, and the second sub-stack SB2 may be disposed above the second single crystal silicon layer. Each of the first sub-stack SB1 and the second sub-stack SB2 may include a stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer, and the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0099] The first layer 12A, the second layer 13, and the third layer 12B may be referred to as a "sacrificial layer", and the fourth layer 14 may be referred to as a "depressed target layer". The stack SB may be referred to as a "vertical stack". The stack SB may include a plurality of sacrificial layers and a depressed target layer alternately stacked. The sacrificial layer may include a first sub-stack SB1, a second sub-stack SB2, and a third sub-stack SB3, and each of the first sub-stack SB1, the second sub-stack SB2, and the third sub-stack SB3 may include a three-layer stack of the first layer 12A / the second layer 13 / the third layer 12B. The depressed target layer may include a fourth layer 14. Each sacrificial layer may include a three-layer stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer. Each depressed target layer may include a single-layer second single crystal silicon layer, and the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0100] As above reference Figures 2 to 3D As described above, when the memory cells MC are vertically stacked, the first sub-stack SB1 , the fourth layer 14 , the second sub-stack SB2 , the fourth layer 14 , and the third sub-stack SB3 may be alternately stacked several times.

[0101] Subsequently, a portion of the stack SB may be etched to form a plurality of sacrificial isolation openings 15A and 15B. The sacrificial isolation openings 15A and 15B may be initial openings for cell isolation, and the sacrificial isolation openings 15A and 15B may include a large opening 15A and a small opening 15B. The size of the large opening 15A may be greater than the size of the small opening 15B. From the perspective of the top view, the large opening 15A and the small opening 15B may have a rectangular shape. In some embodiments, the large opening 15A and the small opening 15B may have a circular shape. According to another embodiment of the present invention, the large opening 15A and the small opening 15B may have an elliptical shape. In some embodiments, the sacrificial isolation openings 15A and 15B may be referred to as "sacrificial isolation trenches". The large opening 15A and the small opening 15B may extend vertically in the first direction D1. The large opening 15A and the small opening 15B may be alternately arranged in the second direction D2. A plurality of large openings 15A may be arranged in the third direction D3. A plurality of small openings 15B may be arranged in the third direction D3. The large opening 15A and the small opening 15B may penetrate the stacked body SB in the first direction D1.

[0102] After forming the sacrificial isolation openings 15A and 15B, the portion of the lower structure 11 exposed below the sacrificial isolation openings 15A and 15B may be etched. Therefore, the bottom surfaces of the sacrificial isolation openings 15A and 15B may extend into the lower structure 11. The bottom surfaces of the sacrificial isolation openings 15A and 15B may include a U-shaped profile. Due to the sacrificial isolation openings 15A and 15B, the fourth layer 14 may have a mesh pattern.

[0103] Figure 5A is a plan view of a fourth level 14 showing a method for forming sacrificial isolation layers 16A and 16B, Figure 5B is along Figure 5A A cross-sectional view taken along line BB' is shown.

[0104] Reference Figure 5A and Figure 5B , sacrificial isolation layers 16A and 16B filling the sacrificial isolation openings 15A and 15B may be formed. The sacrificial isolation layers 16A and 16B may include a first sacrificial isolation layer 16A and a second sacrificial isolation layer 16B. The first sacrificial isolation layer 16A may fill the large opening 15A, and the second sacrificial isolation layer 16B may fill the small opening 15B.

[0105] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. For example, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. Forming the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include forming a sacrificial isolation material on the stack SB to fill the sacrificial isolation openings 15A and 15B, and flattening the sacrificial isolation material to expose the top layer of the stack SB. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may have different sizes or different volumes. For example, the size (or volume) of the first sacrificial unit isolation layer 16A may be greater than the size (or volume) of the second sacrificial isolation layer 16B.

[0106] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may extend vertically in the first direction D1. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be alternately arranged in the second direction D2. A plurality of first sacrificial isolation layers 16A may be arranged in the third direction D3. A plurality of second sacrificial isolation layers 16B may be arranged in the third direction D3. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may pass through the stack SB in the first direction D1.

[0107] Each of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include a stack of a barrier layer L1, a sacrificial liner layer L2, a sacrificial gap filling layer L3, and a sacrificial cover layer L4. The barrier layer L1 may include silicon nitride, polysilicon, or a combination thereof. The sacrificial liner layer L2 may include silicon oxide, and the sacrificial gap filling layer L3 may include amorphous carbon. The sacrificial cover layer L4 may include titanium nitride. The barrier layer L1 may prevent the sacrificial liner layer L2, the sacrificial gap filling layer L3, and the sacrificial cover layer L4 from being trimmed or lost in a subsequent recessing process of recessing the fourth layer 14.

[0108] Forming the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include sequentially forming a barrier layer L1, a sacrificial liner layer L2, a sacrificial gap-filling layer L3, and a sacrificial cover layer L4 on the stacked body SB to fill the sacrificial isolation openings 15A and 15B, and planarizing the barrier layer L1, the sacrificial liner layer L2, and the sacrificial gap-filling layer L3 to expose the uppermost layer of the stacked body SB. After planarizing the sacrificial gap-filling layer L3, the upper region of the sacrificial gap-filling layer L3 may be recessed, and subsequently, the sacrificial cover layer L4 may be deposited and planarized.

[0109] Fig. 6A is a plan view of the fourth level 14 showing a method for forming sacrificial vertical openings V1' and V2', Figure 6B is along Fig. 6A A cross-sectional view taken along line AA' is shown.

[0110] refer to Fig. 6A and Figure 6B A hard mask layer pattern 17 may be formed over the stacked body SB, the first sacrificial isolation layer 16A, and the second sacrificial isolation layer 16B. The hard mask layer pattern 17 may include silicon nitride. The hard mask layer pattern 17 may be formed by an etching process using a hard mask material of a mask layer. A plurality of hole-type openings may be defined in the hard mask layer pattern 17.

[0111] Subsequently, a portion of the stacked body SB may be etched using the hard mask layer pattern 17 as an etching barrier. As a result, a plurality of sacrificial vertical openings V1' and V2' may be formed in the stacked body SB. The sacrificial vertical openings V1' and V2' may include a first sacrificial vertical opening V1' and a second sacrificial vertical opening V2'. From the perspective of a top view, the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be hole-type openings. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may extend vertically in the first direction D1. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be formed by etching the stacked body SB between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. The first sacrificial vertical opening V1' may be formed by etching the stacked body SB between the first sacrificial isolation layers 16A. The second sacrificial vertical opening V2' may be formed by etching the stacked body SB between the second sacrificial isolation layers 16B. The first sacrificial vertical opening V1' may be disposed between the second sacrificial isolation layers 16B in the third direction D3. The second sacrificial vertical openings V2' may be disposed between the first sacrificial isolation layers 16A in the third direction D3. From a top view perspective, cross-sections of the first sacrificial vertical openings V1' and the second sacrificial vertical openings V2' may have a rectangular shape, a circular shape, or an elliptical shape.

[0112] Fig. 7A is a plan view showing a method for forming the preliminary horizontal layer 14A, Figure 7B is along Fig. 7A A cross-sectional view taken along line AA' is shown. Figure 7C is along Fig. 7A A cross-sectional view taken along line BB' is shown.

[0113] refer to FIG. 7A to FIG. 7C , a portion of the hard mask layer pattern 17 (refer to reference numeral 17T) may be trimmed.

[0114] Subsequently, the first layer 12A and the third layer 12B may be selectively removed through the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' by using the difference between the etching selectivity of the second layer 13 and the fourth layer 14 and the etching selectivity of the first layer 12A and the third layer 12B. The first layer 12A and the third layer 12B may be removed by a wet etching process or a dry etching process. In some embodiments, the first layer 12A and the third layer 12B may include a silicon germanium layer, the second layer 13 and the fourth layer 14 may include a silicon layer, and the silicon germanium layer may be etched using an etching solution or an etching gas that is selective to the silicon layer.

[0115] Subsequently, the second layer 13 and the fourth layer 14 may be recessed using, for example, a wet etching process or a dry etching process. According to the illustrated embodiment, the fourth layer 14 may be partially etched, and the second layer 13 may be removed. As a result, the second layer 13 may be removed, and the fourth layer 14 may be thinned, as shown in the reference numeral '14A'. The recessing process for forming the thin fourth layer 14A (i.e., the preliminary horizontal layer 14A) may be referred to as a thinning process or a trimming process of the fourth layer 14. In order to form the preliminary horizontal layer 14A, the upper surface, the lower surface, and the side surface of the fourth layer 14 may be recessed. The preliminary horizontal layer 14A may be referred to as a thin-body active layer. The preliminary horizontal layer 14A may include a single crystal silicon layer. The recessing process for forming the preliminary horizontal layer 14A may use, for example, HSC1 (Hot SC-1). HSC1 may include a mixed solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a ratio of 1:4:20. The second layer 13 and the fourth layer 14 may be selectively etched using HSC1.

[0116] The preliminary horizontal layer 14A may be formed by the above-described recessing process for recessing the fourth layer 14, and the horizontal recesses 18 may be formed between the preliminary horizontal layers 14. Each of the top and bottom surfaces of the preliminary horizontal layer 14A may include a flat surface.

[0117] The preliminary horizontal layer 14A may have a cross shape from a top view perspective. A side surface of the preliminary horizontal layer 14A may have a curved shape or a rounded shape.

[0118] After forming the preliminary horizontal layer 14A, the first sacrificial vertical opening and the second sacrificial vertical opening may be enlarged, as shown in reference numerals "V1" and "V2". The preliminary horizontal layers 14A may be spaced apart from each other along a second direction D2 separated by the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A may have a shape in which a plurality of cross shapes are merged in a third direction D3.

[0119] When the preliminary horizontal layer 14A is formed, the surface of the lower structure 11 may be recessed to a certain depth indicated by reference numeral ' 11A' As a result, the depths of the first sacrificial vertical openings V1 and the second sacrificial vertical openings V2 may be increased.

[0120] The first sacrificial vertical openings V1 and the second sacrificial vertical openings V2 may be alternately disposed between the preliminary horizontal layers 14A in the second direction D2. The first sacrificial vertical openings V1 may be disposed between the second sacrificial isolation layers 16B in the third direction D3. The second sacrificial vertical openings V2 may be disposed between the first sacrificial isolation layers 16A in the third direction D3.

[0121] When forming the preliminary horizontal layer 14A, the barrier layer L1 may prevent the sacrificial liner layer L2 , the sacrificial gap-filling layer L3 , and the sacrificial cover layer L4 from being trimmed or lost.

[0122] As a comparative example, when the barrier layer L1 is omitted, the sacrificial liner layer L2 , the sacrificial gap-filling layer L3 , and the sacrificial capping layer L4 may be lost when the recess process is performed using the HSC1 .

[0123] Fig. 8A is a plan view showing a method for forming the first dielectric layer 19 and the second dielectric layer 20, Figure 8B is along Fig. 8A A cross-sectional view taken along line AA' is shown. Figure 8C is along Fig. 8A A cross-sectional view taken along line BB' is shown.

[0124] Reference FIG. 8A to FIG. 8C , a first dielectric layer 19 covering the preliminary horizontal layer 14A may be formed. The first dielectric layer 19 may include silicon nitride. The first dielectric layer 19 may completely cover the top surface, the bottom surface, and the side surface of the preliminary horizontal layer 14A.

[0125] When the first dielectric layer 19 is formed, a dummy dielectric layer 19D may be formed on the surface of the lower structure 11. Some of the first dielectric layer 19 may completely cover the top surface, the bottom surface, and the side surface of the hard mask layer pattern 17.

[0126] Subsequently, a second dielectric layer 20 may be formed on the first dielectric layer 19. The second dielectric layer 20 may fill the space between the first dielectric layers 19 disposed vertically adjacent to each other. The second dielectric layer 20 may include silicon oxide. Portions of the second dielectric layer 20 may be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The horizontal recess ( Figure 7B and Figure 7C 18) in the embodiment may be filled with a first dielectric layer 19 and a second dielectric layer 20.

[0127] Subsequently, a sacrificial column 21 may be formed on the second dielectric layer 20 disposed in the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The sacrificial column 21 may be made of a sacrificial material and may include amorphous carbon. In some embodiments, a column cover layer may be further formed on the sacrificial column 21. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. Forming the sacrificial column 21 may include depositing a sacrificial material and planarizing the sacrificial material. A planarization process for forming the sacrificial column 21 may be performed until the uppermost first dielectric layer 19 is exposed. Subsequently, the uppermost second dielectric layer 20 may also be planarized until the uppermost first dielectric layer 19 is exposed. The sacrificial column 21 may not be formed between the vertically stacked first dielectric layers 19.

[0128] The second dielectric layer 20 and the sacrificial column 21 may form a first sacrificial column structure SV1 and a second sacrificial column structure SV2 filling the first sacrificial vertical opening V1 and the second sacrificial column structure SV2. The first sacrificial column structure SV1 may fill the first sacrificial vertical opening V1, and the second sacrificial column structure SV2 may fill the second sacrificial vertical opening V2. In some embodiments, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. In some embodiments, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From the perspective of the top view, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be hole-type sacrificial columns. In some embodiments, a portion of the first dielectric layer 19 may be conformally formed on the surface of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2, and therefore, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may also include a portion of the first dielectric layer 19.

[0129] Return to reference Figure 8C , the first dielectric layer 19 may be formed between the preliminary horizontal layers 14A. The second dielectric layer 20 may be disposed in the first dielectric layer 19 such that the first dielectric layer 19 surrounds the second dielectric layer 20. The first dielectric layer 19 may include a first surrounding portion and a second surrounding portion. The first surrounding portion may surround the preliminary horizontal layer 14A in the A-A' direction. The second surrounding portion may surround the second dielectric layer 20 in the B-B' direction. The first dielectric layer 19 may directly contact the barrier layer L1. The barrier layer L1 may prevent the first dielectric layer 19 and the sacrificial liner layer L2 from contacting each other. Therefore, the first dielectric layer 19 may not extend into the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B, and after a subsequent trimming process of the first dielectric layer 19, the first dielectric layer 19 may prevent the first dielectric layer ( Fig. 10B 19A) between the bridge.

[0130] As described above, a unit mold structure may be formed by forming a preliminary horizontal layer 14A, a first dielectric layer 19, and a second dielectric layer 20. The unit mold structure may include a plurality of unit molds. Each unit mold may include a plurality of mold layers. The mold layer refers to the preliminary horizontal layer 14A, the first dielectric layer 19, and the second dielectric layer 20. Each unit mold may include an ONSN (oxide-nitride-siliconide-nitride) stack. Here, the ONSN stack refers to a structure in which silicon oxide, a first silicon nitride, a single crystal silicon layer, and a second silicon nitride are stacked in sequence. Silicon oxide may correspond to the second dielectric layer 20, and the first silicon nitride and the second silicon nitride may correspond to the first dielectric layer 19. The single crystal silicon layer may correspond to the preliminary horizontal layer 14A. The unit mold structure may be referred to as a vertical stack. In some embodiments, each unit mold may include an ONSNO (oxide-nitride-silicon-nitride-oxide) stack. Here, the ONSNO stack refers to a structure in which the first silicon oxide, the first silicon nitride, the single crystal silicon layer, the second silicon nitride, and the second silicon oxide are stacked in sequence. The first silicon oxide and the second silicon oxide may correspond to the second dielectric layer 20, and the first silicon nitride and the second silicon nitride may correspond to the first dielectric layer 19. The single crystal silicon layer may correspond to the preliminary horizontal layer 14A.

[0131] As described above, the sub-stacks of the stack SB can be formed by FIG. 4A to FIG. 8C The series of processes shown are replaced by a unit mold. The first layer 12A, the second layer 13, and the third layer 12B can be replaced by the first dielectric layer 19 and the second dielectric layer 20. The fourth layer 14 can be made into a preliminary horizontal layer 14A by a recess process. The first dielectric layer 19 can be referred to as a trimming target layer.

[0132] Fig.9A is a plan view showing a method for forming cell isolation openings 22A and 22B and a horizontal layer 14B, Fig. 9B is along Fig.9A A cross-sectional view taken along line BB' is shown.

[0133] refer to Fig.9A and Fig. 9B , in order to form the cell isolation openings 22A and 22B, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be removed. The cell isolation openings 22A and 22B may include the first cell isolation opening 22A and the second cell isolation opening 22B. The first cell isolation opening 22A may be formed by removing the first sacrificial isolation layer 16A. The second cell isolation opening 22B may be formed by removing the second sacrificial isolation layer 16B. When the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B are removed, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be covered by a mask layer (not shown). The cell isolation openings 22A and 22B may expose the side surfaces of the preliminary horizontal layer 14A and the first dielectric layer 19 in the BB' direction.

[0134] Subsequently, the side surface of the preliminary horizontal layer 14A of the cell mold may be trimmed in the second direction D2 and the third direction D3 by the cell isolation openings 22A and 22B. As a result, a trimmed horizontal layer 14B may be formed. A horizontal level gap 14R may be formed on the side surface of the horizontal layer 14B. The horizontal level gap 14R and the horizontal layer 14B may be disposed between the first dielectric layer 19. The horizontal layer 14B may be referred to as a "trimmed horizontal layer pattern".

[0135] When the horizontal layer 14B is formed, the surface of the lower structure 11 (eg, the bottom surface of the cell isolation openings 22A and 22B) may be recessed to a predetermined depth.

[0136] The horizontal layer 14B may be disposed between the first sacrificial column structure SV1 and the second sacrificial column structure SV2 in the second direction D2. From the perspective of the top view, the horizontal layer 14B may have a cross shape. The horizontal layer 14B may have a cross shape that is smaller in size than the preliminary horizontal layer 14A. The preliminary horizontal layer 14A may have a shape in which a plurality of cross shapes are merged. The horizontal layer 14B may have a shape in which the cross shapes are separated separately in the third direction D3. A horizontal level gap 14R may be formed between the horizontal layers 14B disposed along the third direction D3. The first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be disposed between the horizontal layers 14B in the second direction D2.

[0137] Fig. 10A 2 is a plan view illustrating a method for forming the horizontal-level spacer 23 and the first dielectric layer 19A. Fig. 10B is along Fig. 10A A cross-sectional view taken along line BB' is shown.

[0138] Reference now Fig. 10A and Fig. 10B , the horizontal level spacers 23 may be formed on the side surfaces of the horizontal layers 14B. Forming the horizontal level spacers 23 may include first forming a spacer material on the side surfaces of the horizontal layers 14B, and then trimming the spacer material by etching to a desired thickness. The horizontal level spacers 23 may be made of any suitable dielectric material, including, for example, silicon oxide. The horizontal level spacers 23 may fill the horizontal level gaps 14R. The horizontal layers 14B arranged in the third direction D3 may be isolated from each other by the horizontal level spacers 23.

[0139] Subsequently, a portion of the first dielectric layer 19 may be horizontally trimmed through the cell isolation openings 22A and 22B. After the trimming process, the first dielectric layer 19 may remain, as indicated by reference numeral '19A'. As a result, from the perspective of line BB', a pair of first dielectric layers 19A may be disposed between the horizontal layer 14B, and one second dielectric layer 20 may be disposed between the pair of first dielectric layers 19A.

[0140] Reference 9A to 10B The width of the first dielectric layer 19A in the third direction D3 between the cell isolation openings 22A and 22B may be greater than the width of the horizontal layer 14B. The trimming depth of the first dielectric layer 19 in the third direction D3 may be less than the trimming depth of the preliminary horizontal layer 14A.

[0141] A pair of first dielectric layers 19A may vertically overlap one horizontal layer 14B. The first dielectric layer 19A remaining after the trimming process may be referred to as a trimmed first dielectric layer.

[0142] Fig.11A is a plan view showing a method for forming cell isolation layers 24A and 24B, Fig. 11B is along Fig.11A A cross-sectional view taken along line BB' is shown. Fig.11A is a plan view of the first dielectric layer 19A level illustrating a method for forming the cell isolation layers 24A and 24B.

[0143] Reference Fig.11A and Fig. 11B , cell isolation layers 24A and 24B filling the cell isolation openings 22A and 22B may be formed. The cell isolation layers 24A and 24B may include a first cell isolation layer 24A and a second cell isolation layer 24B. The first cell isolation layer 24A and the second cell isolation layer 24B may be formed of the same material. The first cell isolation layer 24A and the second cell isolation layer 24B may be formed of a dielectric material. For example, the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. From the perspective of the top view, the outermost layer material of the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxycarbide.

[0144] Forming the first cell isolation layer 24A and the second cell isolation layer 24B may include forming a cell isolation material filling the cell isolation openings 22A and 22B, and planarizing the cell isolation material and the uppermost first dielectric layer 19A to expose the surface of the hard mask layer pattern 17. The first cell isolation layer 24A and the second cell isolation layer 24B may have different sizes or different volumes. The first cell isolation layer 24A and the second cell isolation layer 24B may have a dual structure of silicon oxide and silicon oxycarbide. For example, silicon oxycarbide may be deposited after silicon oxide is deposited. In some embodiments, the first cell isolation layer 24A and the second cell isolation layer 24B may include an embedded air gap, and an embedded air gap may be provided when silicon oxycarbide is deposited. The second sacrificial column structure SV2 may be disposed between the first cell isolation layer 24A in the third direction D3, and the first sacrificial column structure SV1 may be disposed between the second cell isolation layer 24B in the third direction D3. The first cell isolation layer 24A and the second cell isolation layer 24B may extend vertically in the first direction D1.

[0145] The cell isolation layers 24A and 24B may correspond to Figures 2 to 3B The cell isolation layers ISOA and ISOB are shown. Figure 3C and 3D As shown, each of the first cell isolation layer 24A and the second cell isolation layer 24B may include a stack of a cell isolation liner layer ISOL and a cell isolation gap filling layer ISOG. The cell isolation liner layer ISOL may include silicon oxide, and the cell isolation gap filling layer ISOG may include silicon oxycarbide. In some embodiments, the first cell isolation layer 24A and the second cell isolation layer 24B may include an embedded air gap, and the embedded air gap may be provided when the cell isolation gap filling layer ISOG is formed.

[0146] The cell isolation layers 24A and 24B and the first dielectric layer 19A may be in direct contact with each other. A horizontal level spacer 23 may be disposed between the horizontal layer 14B and the cell isolation layers 24A and 24B.

[0147] Fig.12 is a plan view showing a method for forming a first dielectric layer pattern 19B, FIG. 13A to FIG. 13D is a diagram showing a method for forming the first dielectric layer pattern 19B. Fig.12 A cross-sectional view taken along the line AA′ shown in FIG.

[0148] First, refer to Fig.13A , the hard mask layer 17 and the uppermost first dielectric layer 19A may be removed to form a hard mask level recess 25 .

[0149] Reference Fig. 13B, a top dielectric layer 26 filling the hard mask level recess 25 may be formed. The top dielectric layer 26 may include silicon oxide.

[0150] Reference Fig. 13C , an initial vertical opening 27 may be formed by removing the second sacrificial pillar structure SV2.

[0151] Subsequently, the second dielectric layer 20 may be horizontally recessed. The first dielectric layer 19A and the dummy dielectric layer 19D may be exposed by the initial vertical opening 27 .

[0152] Reference Fig.13D , the first dielectric layer 19A and the dummy dielectric layer 19D may be selectively horizontally recessed. As a result, the first dielectric layer pattern 19B and the dielectric level recess 28 may be formed. Portions of the horizontal layer 14B may be exposed by the dielectric level recess 28.

[0153] Fig.14A is a plan view showing a method for forming a vertical sacrificial structure 29, Fig. 14B is along Fig.14A A cross-sectional view taken along line AA′ shown in FIG.

[0154] refer to Fig.14A and Fig. 14B A vertical sacrificial structure 29 filling the dielectric level recess 28 and the initial vertical opening 27 may be formed. The vertical sacrificial structure 29 may include a sacrificial material. The vertical sacrificial structure 29 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0155] Fig.15A is a plan view showing a method for forming the vertical stage path 30, Fig. 15B is along Fig.15A A cross-sectional view taken along line AA' is shown.

[0156] refer to Fig.15A and Fig. 15B In order to form the vertical stage path 30 , the sacrificial pillar 21 of the first sacrificial pillar structure SV1 may be removed.

[0157] Subsequently, in order to form the lower-level gap 19D′, the dummy dielectric layer 19D below the vertical level path 30 may be removed.

[0158] Fig.16A is a plan view showing a method for forming a first hole-type vertical opening 32, Fig. 16B is along Fig.16A A cross-sectional view taken along line AA' is shown.

[0159] Reference Fig.16A and Fig. 16BTo form a first hole-type vertical opening 32 , the second dielectric layer 20 may be cut (indicated by arrow 31 ) through a vertical step path 30 .

[0160] Subsequently, a first passivation layer BF1 filling the lower gap 19D' may be formed. The first passivation layer BF1 may include silicon oxide. Forming the first passivation layer BF1 may include depositing silicon oxide to fill the lower gap 19D' and etching the silicon oxide.

[0161] Subsequently, the surface of the lower structure 11 may be oxidized to form a second passivation layer BF2 in a lower region of the first hole-type vertical opening 32 .

[0162] Fig.17A is a plan view showing a method for forming a horizontal step recess 33, Fig. 17B is along Fig.17A A cross-sectional view taken along line AA' is shown. Fig. 17C is along Fig.17A A cross-sectional view taken along line BB' is shown.

[0163] Reference FIG. 17A to FIG. 17C , the first dielectric layer pattern 19B can be removed through the first hole-type vertical opening 32 to form a horizontal level recess 33 that exposes a portion of the horizontal layer 14B. Fig. 17C , the horizontal level recess 33 may be disposed between the second dielectric layer 20 and the horizontal layer 14B. Two horizontal level recesses 33 may face each other with one horizontal layer 14B located therebetween.

[0164] Fig.18A is a plan view showing a method for forming the horizontal conductive line 35 . Fig.18B is along Fig.18A A cross-sectional view taken along line AA' is shown. Fig. 18C is along Fig.18A A cross-sectional view taken along line BB' is shown.

[0165] Reference 18A to 18C , an interlayer dielectric layer 34 may be formed on the exposed portion of the horizontal layer 14B. The interlayer dielectric layer 34 may be referred to as a gate dielectric layer. The interlayer dielectric layer 34 may correspond to Figures 1A to 3B The interlayer dielectric layer GD is shown.

[0166] The interlayer dielectric layer 34 may be formed by oxidizing the surface of the horizontal layer 14B. In some embodiments, the interlayer dielectric layer 34 may be formed by a deposition process of depositing silicon oxide. The interlayer dielectric layer 34 may be formed of silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer 34 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiO2, or a combination thereof.

[0167] Subsequently, a horizontal conductive line 35 filling the horizontal level recess 33 may be formed on the interlayer dielectric layer 34. Forming the horizontal conductive line 35 may include depositing a conductive material filling the horizontal level recess 33 on the interlayer dielectric layer 34, and performing an etch-back process on the conductive material. The horizontal conductive line 35 may include a pair of first horizontal conductive lines 35A and second horizontal conductive lines 35B facing each other, with the semiconductor layer pattern 14A located between them. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal conductive line 35A and the second horizontal conductive line 35B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more.

[0168] The horizontal conductive lines 35 may correspond to Figures 1A to 1D , and the first horizontal conductive line 35A and the second horizontal conductive line 35B may correspond to the upper horizontal line G1 and the lower horizontal line G2. Figures 1A to 1D , each of the first horizontal conductive line 35A and the second horizontal conductive line 35B may have a cross shape and include a channel overlap portion WLP and a channel non-overlap portion NOL.

[0169] Fig.19A is a plan view showing a method for forming a vertical conductive line 39, Fig.19B is along Fig.19A A cross-sectional view along line AA' is shown.

[0170] Reference Fig.19A and Fig.19B, a first capping layer 36 may be formed on one side surface of the horizontal conductive line 35. The first capping layer 36 may include silicon oxide, silicon nitride, silicon oxycarbide, an embedded air gap, or a combination thereof. The capping material may be deposited and etched back to form the first capping layer 36. When or after forming the first capping layer 36, a portion of the interlayer dielectric layer 34 may be removed to expose a first edge portion of each horizontal layer 14B.

[0171] Subsequently, a vertical conductive line 39 coupled to a first edge portion of each horizontal layer 14B may be formed. The vertical conductive line 39 may fill the first hole-type vertical opening 32. Each vertical conductive line 39 may be commonly coupled to a plurality of horizontal layers 14B arranged in the first direction D1. The vertical conductive line 39 may include titanium nitride, tungsten, or a combination thereof. The vertical conductive line 39 may be referred to as a bit line or a vertical bit line. The vertical conductive lines 39 adjacent to each other in the third direction D3 may be spaced apart from each other by the second cell isolation layer 24B.

[0172] Before forming the vertical conductive line 39, a first doped region 37 and a first contact node 38 may be formed. The first doped region 37 may be formed in a first edge portion of the horizontal layer 14B. Forming the first doped region 37 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The first doped region 37 may include impurities diffused from the doped polysilicon. In some embodiments, the first doped region 37 may be formed by a process of doping impurities.

[0173] The first contact node 38 may include doped polysilicon. The first doping region 37 may include impurities diffused from the first contact node 38. An ohmic contact layer such as metal silicide may be formed between the vertical conductive line 39 and the first contact node 38.

[0174] The vertical conductive lines 39 may correspond to Figures 1A to 1D The first conductive line BL is shown in FIG.

[0175] Fig. 20A is a plan view showing a method for forming a preliminary second hole type vertical opening 29V, Fig. 20B is along Fig. 20A A cross-sectional view taken along line AA' is shown.

[0176] refer to Fig. 20A and Fig. 20B , a portion of the vertical sacrificial structure 29 may be removed to form a preliminary second hole type vertical opening 29V. One side surface (i.e., the second edge portion) of the horizontal layer 14B may be exposed through the preliminary second hole type vertical opening 29V. After forming the preliminary second hole type vertical opening 29V, a preliminary second cover layer 29A may be formed on the top and bottom surfaces of the horizontal layer 14B.

[0177] When the preliminary second capping layer 29A is formed, a lowermost dielectric layer 29L may be formed on the side surface of the first passivation layer BF1 by removing a portion of the vertical sacrificial structure 29 .

[0178] Fig.21A is a plan view showing a recessing method of the horizontal layer HL, Fig. 21B is along Fig.21A A cross-sectional view taken along line AA' is shown.

[0179] refer to Fig.21A and Fig. 21B , a third passivation layer BF3 may be formed on the surface of the lower structure 11. The third passivation layer BF3 may include silicon oxide.

[0180] Subsequently, the second edge portion of the horizontal layer 14B may be horizontally recessed in the second direction D2 (refer to reference numeral ' 14C'). As a result, the horizontal layer may remain as shown by reference numeral 'HL'.

[0181] After forming the horizontal layer HL, the preliminary second hole type vertical opening may be enlarged, as indicated by reference numeral “ 40 .” Hereinafter, the enlarged preliminary second hole type vertical opening may be simply referred to as “second hole type vertical opening 40 .”

[0182] Fig.22A is a plan view showing a method for forming the storage opening 41, Fig. 22B is along Fig.22A A cross-sectional view taken along line AA' is shown.

[0183] refer to Fig.22A and Fig. 22B In order to form the second capping layer 29C, the preliminary second capping layer 29A may be selectively recessed. The second capping layer 29C may include silicon oxide, silicon nitride, or a combination thereof.

[0184] After forming the second capping layer 29C, a storage opening 41 horizontally extending from the second hole-type vertical opening 40 may be formed. The storage opening 41 may be referred to as a "capacitor opening."

[0185] The horizontal layer HL may include a first edge and a second edge. The first edge refers to a portion coupled to the first contact node 38 and the vertical conductive line 39 , and the second edge refers to a portion exposed by the storage opening 41 .

[0186] The storage opening 41 may be disposed between the second dielectric layers 20. The second capping layers 29C may be disposed in lower and upper portions of the horizontal layer HL, respectively.

[0187] As described above, forming the horizontal layer HL and the storage opening 41 may include forming the second hole-type vertical opening 40 , recessing the horizontal layer 14B, and forming the second cover layer 29C.

[0188] Fig.23A is a plan view showing a method for forming the second contact node 42, Fig. 23B is along Fig.23A A cross-sectional view taken along line AA' is shown.

[0189] Reference Fig.23A and Fig. 23B , the second doped regions 43 may be formed in the second edges of the horizontal layer HL, respectively. Forming the second doped regions 43 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The second doped regions 43 may include impurities diffused from the doped polysilicon. In some embodiments, the doped polysilicon may remain after performing the heat treatment.

[0190] Subsequently, a second contact node 42 may be formed on the second edge of the horizontal layer HL. The second contact node 42 may include doped polysilicon. The second doping region 43 may include impurities diffused from the second contact node 42.

[0191] Each horizontal layer HL may include a first doping region 37, a second doping region 43, and a channel 44 horizontally disposed in the second direction D2. The channel 44 may be defined between the first doping region 37 and the second doping region 43. The channel 44 may vertically overlap the horizontal conductive line 35. Figures 1A to 1D As shown, the horizontal layer HL may have a cross shape, and the channel 44 may also have a cross shape.

[0192] Fig.24A is a plan view showing a method for forming the first electrode 45, Fig. 24B is along Fig.24A A cross-sectional view taken along line AA' is shown.

[0193] refer to Fig.24A and Fig. 24B , the first electrode 45 of the data storage element may be formed on the second contact node 42. The first electrode 45 may have a horizontally oriented cylindrical shape. The first electrodes 45 may be respectively disposed in the storage openings 41. The first electrodes 45 adjacent to each other in the second direction D2 may be spaced apart from each other by the second hole-type vertical opening 40. The first electrodes 45 adjacent to each other in the third direction D3 may be spaced apart from each other by the first cell isolation layer 24A.

[0194] Fig.25A is a plan view showing a method of exposing the outer wall of the first electrode 45, Fig.25B is along Fig.25AA cross-sectional view taken along line AA' is shown.

[0195] Reference Fig.25A and Fig.25B , the second dielectric layer 20 may be horizontally recessed (reference numeral '46'). As a result, the outer wall of the first electrode 45 may be exposed. The recessed second dielectric layer 20 may correspond to Figure 3B The inter-cell dielectric layer IL is shown.

[0196] Fig.26A is a plan view showing a method for forming the dielectric layer 47 and the second electrode 48, Fig.26B is along Fig.26A A cross-sectional view taken along line AA' is shown.

[0197] Reference Fig.26A and Fig.26B , a dielectric layer 47 and a second electrode 48 may be sequentially formed on the first electrode 45. The first electrode 45, the dielectric layer 47, and the second electrode 48 may become a data storage element CAP.

[0198] Each first electrode 45 may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode 45 may include a plurality of inner surfaces. The outer surface of the first electrode 45 may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode 45 may extend vertically in the first direction D1, and the horizontal outer surface of the first electrode 45 may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode 45 may be a three-dimensional space. The dielectric layer 47 may conformally cover the inner and outer surfaces of the first electrode 45. The second electrode 48 may be disposed in the inner space of the first electrode 45 on the dielectric layer 47. Some outer surfaces of the first electrode 45 may be electrically connected to the second doping region 43 of the horizontal layer HL.

[0199] The first electrode 45 may have a cylindrical shape. The cylindrical shape of the first electrode 45 may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surface of the first electrode 45 may be electrically connected to the second doping region 43 of the horizontal layer HL. The dielectric layer 47 and the second electrode 48 may be disposed on the cylindrical inner surface of the first electrode 45. The second electrode 48 may extend vertically in the first direction D1.

[0200] The first electrode 45 and the second electrode 48 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 45 and the second electrode 48 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode 48 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 48 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling an inner space of the first electrode 45 , titanium nitride (TiN) may be used as a data storage element CAP, and tungsten nitride may be a low resistance material.

[0201] The dielectric layer 47 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 47 may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 47 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). The dielectric layer 45 may include a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HA (HfO2 / Al2O3) stack, a HAH (HfO2 / Al2O3 / HfO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.

[0202] In some embodiments, an interface control layer for improving leakage current may be further formed between the first electrode 45 and the dielectric layer 47. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) and niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode 45 and the dielectric layer 47.

[0203] FIG. 27A to FIG. 28B is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0204] Reference FIG. 4A to FIG. 4C , sacrificial isolation openings 15A and 15B may be formed in the stacked body SB.

[0205] Fig.27A is a plan view showing a method for forming sacrificial isolation layers 16A and 16B, Fig.27B is along Fig.27A A cross-sectional view taken along line BB' is shown.

[0206] Reference Fig.27A and Fig.27B , sacrificial isolation layers 16A and 16B filling the sacrificial isolation openings 15A and 15B may be formed.

[0207] The sacrificial isolation layers 16A and 16B may include an additional barrier layer L5, a barrier layer L1, a sacrificial liner layer L2, a sacrificial gap-filling layer L3, and a sacrificial cover layer L4. Forming the sacrificial isolation layers 16A and 16B may include forming an additional barrier layer L5, sequentially forming a barrier layer L1, a sacrificial liner layer L2, and a sacrificial gap-filling layer L3 on the additional barrier layer L5, planarizing the additional barrier layer L5, the barrier layer L1, the sacrificial liner layer L2, and the sacrificial gap-filling layer L3, recessing an upper region of the sacrificial gap-filling layer L3, and forming a sacrificial cover layer L4 on the recessed sacrificial gap-filling layer L3.

[0208] The additional barrier layer L5 and the barrier layer L1 may be formed of different materials. For example, the additional barrier layer L5 may include polysilicon, while the barrier layer L1 may include silicon nitride. The additional barrier layer L5 may directly contact the first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 of the stack SB.

[0209] By forming a double barrier structure, the sacrificial liner layer L2, sacrificial gap filling layer L3 and sacrificial capping layer L4 can be further protected from being trimmed or lost during a subsequent trimming process of the fourth layer 14. In addition, the additional barrier layer L5 can protect the barrier layer L1 from being trimmed or lost.

[0210] Fig.28A is a plan view showing a method for forming the preliminary horizontal layer 14A, Fig.28B is along Fig.28A A cross-sectional view taken along line BB' is shown.

[0211] Reference Fig.28A and Fig.28B, the first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 may be recessed (or trimmed) to form a preliminary horizontal layer 14A and a horizontal recess 18. When forming the preliminary horizontal layer 14A, the additional barrier layer L5 and the barrier layer L1 may protect the sacrificial liner layer L2, the sacrificial gap-filling layer L3, and the sacrificial cover layer L4 from being trimmed or lost.

[0212] Furthermore, even if the additional barrier layer L5 is removed during the formation of the preliminary horizontal layer 14A, the barrier layer L1 may remain sufficiently thick after the recess process for forming the preliminary horizontal layer 14 is completed. Therefore, the barrier layer L1 can prevent the sacrificial liner layer L2, the sacrificial gap-filling layer L3, and the sacrificial cover layer L4 from being trimmed or lost.

[0213] In some embodiments, the sacrificial liner layer L2 may also be used as a barrier layer. Thus, a triple barrier structure of the additional barrier layer L5, the barrier layer L1, and the sacrificial liner layer L2 may be formed. The sacrificial liner layer L2 may be used as an inner barrier layer, and the additional barrier layer L5 may be used as an outer barrier layer.

[0214] Then, you can execute FIG. 8A to FIG. 26B A series of processes shown in .

[0215] FIG. 29A to FIG. 29C is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0216] Reference Fig.29A The stack SB10 may be formed on the lower structure 11. The stack SB10 may include an alternating stack of first semiconductor layers and second semiconductor layers. For example, in the alternating stack, a plurality of silicon germanium layers 12 and a plurality of single crystal silicon layers 14' may be alternately stacked by an epitaxial growth process. The plurality of silicon germanium layers 12 and the plurality of single crystal silicon layers 14' may be formed by an epitaxial growth process. The silicon germanium layer 12 may be a sacrificial layer, and the single crystal silicon layer 14' may be a recessed target layer. The silicon germanium layer 12 may correspond to Figure 4B The first layer 12A or the third layer 12B shown in FIG. 1 , the single crystal silicon layer 14 ′ may correspond to Figure 4B The fourth layer 14 shown in FIG. Figure 4B Different from the stacked body SB shown in FIG. 1 , the stacked body SB10 may be formed by alternating stacks of silicon germanium layers 12 and single crystal silicon layers 14 ′.

[0217] Then, you can execute FIG. 4A to FIG. 5B For example, sacrificial isolation openings 15A and 15B and sacrificial isolation layers 16A and 16B may be formed in the stacked body SB10. The sacrificial isolation layers 16A and 16B may include a barrier layer L1, a sacrificial liner layer L2, a sacrificial gap-filling layer L3, and a sacrificial capping layer L4.

[0218] Then, refer to Fig.29B , a hard mask layer pattern 17 may be formed over the stacked body SB10.

[0219] Subsequently, the stacked body SB may be etched by using the hard mask layer pattern 17 as an etch barrier. As a result, a plurality of first sacrificial vertical openings V1 ′ and a plurality of second sacrificial vertical openings V2 ′ may be formed in the stacked body SB10 .

[0220] Reference Fig.29C , a preliminary horizontal layer 14A' and a horizontal depression 18 can be formed. The preliminary horizontal layer 14A' and the horizontal depression 18 can be formed by Fig.29B The recessing process of the silicon germanium layer 12 and the single crystal silicon layer 14' shown in FIG. After removing the silicon germanium layer 12, the recessing process of the single crystal silicon layer 14' can be performed. The preliminary horizontal layer 14A' can correspond to Figure 7B The preliminary horizontal layer 14A is shown in FIG.

[0221] A wet etching process may be used to recess the silicon germanium layer 12. In some embodiments, a dry etching process may be used to recess the silicon germanium layer 12. For example, an etchant or etching gas having selectivity with respect to the single crystal silicon layer 14' may be used to etch the silicon germanium layer 12.

[0222] The recessing process of the single crystal silicon layer 14' for forming the preliminary horizontal layer 14A' may use, for example, HSC1 (Hot SC-1). HSC1 may include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) mixed in a ratio of 1:4:20. HSC1 may be used to selectively etch the single crystal silicon layer 14'.

[0223] After forming the preliminary horizontal layer 14A', the first sacrificial vertical opening and the second sacrificial vertical opening may be enlarged, as shown in the reference numerals V1 and V2. The preliminary horizontal layer 14A' may be spaced apart from each other in the second direction D2 by the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A' may have a shape in which a plurality of crosses are merged in the third direction D3. When forming the preliminary horizontal layer 14A', the surface of the lower structure 11 may be recessed to a predetermined depth (see reference numeral '11A'). As a result, the depths of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be increased.

[0224] Then, you can execute FIG. 8A to FIG. 26B A series of processes shown in .

[0225] Figure 30 to Figure 32 1 is a perspective view showing a memory cell array according to another embodiment of the present invention. The memory cell arrays MCA100, MCA200 and MCA300 may be similar to Figure 3AIn the following, for the memory cell array MCA that also appears Figure 3A In Figure 30 to Figure 32 The components of Figure 3A Description.

[0226] refer to Fig.30 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0227] The memory cell array MCA100 may include a three-dimensional (3D) array of memory cells MC10. The 3D array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked in a first direction D1. The row array of memory cells MC10 may include a plurality of memory cells MC10 horizontally arranged in a second direction D2 and a third direction D3.

[0228] Each memory cell MC10 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the aforementioned embodiments.

[0229] The switching element TR may include a horizontal layer HL and a second conductive line DWL. The horizontal layer HL may extend in the second direction D2. The second conductive line DWL may extend in the third direction D3.

[0230] The second conductive line DWL may have a double structure. For example, the second conductive line DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other with a horizontal layer HL interposed therebetween. Figure 3B As shown, an interlayer dielectric layer GD may be formed on top and bottom surfaces of the horizontal layer HL.

[0231] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS refer to vertical sidewalls. The flat sidewalls FS may have a linear shape extending in the third direction D3.

[0232] refer to Fig.31 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0233] The memory cell array MCA200 may include a 3D array of memory cells MC20. The 3D array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked in a first direction D1, and the row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged in a second direction D2 and a third direction D3.

[0234] Each memory cell MC20 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the aforementioned embodiments.

[0235] The switching element TR may include a horizontal layer HL and a second conductive line SWL. The horizontal layer HL may extend in the second direction D2. The second conductive line SWL may extend in the third direction D3.

[0236] The second conductive line SWL may have a single structure. For example, the second conductive line SWL may be disposed on the upper surface of the horizontal layer HL. Figure 3B As shown, the interlayer dielectric layer GD may be formed between the upper surface of the horizontal layer HL and the second conductive line SWL. In some embodiments, the second conductive line SWL may be disposed on the lower surface of the horizontal layer HL.

[0237] The second conductive line SWL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may also be referred to as "vertical sidewalls".

[0238] In some embodiments, Figure 1C As shown, the second conductive line SWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL.

[0239] Reference Fig.32 , the memory cell array MCA300 may include a plurality of memory cells MC30.

[0240] The memory cell array MCA300 may include a 3D array of memory cells MC30. The 3D array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may include a plurality of memory cells MC30 stacked in a first direction D1, and the row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged in a second direction D2 and a third direction D3.

[0241] Each memory cell MC30 may include a first conductive line BL, a switching element TR, and a data storage element CAP. For detailed description of the first conductive line BL and the data storage element CAP, reference may be made to the aforementioned embodiments.

[0242] The switching element TR may include a horizontal layer HL and a second conductive line GAA-WL. The horizontal layer HL may extend in the second direction D2. The second conductive line GAA-WL may extend in the third direction D3.

[0243] The second conductive line GAA-WL may have a gate full ring structure GAA. For example, the second conductive line GAA-WL may extend in the third direction D3 while surrounding the horizontal layer HL. An interlayer dielectric layer GD may be formed between the horizontal layer HL and the second conductive line GAA-WL. The interlayer dielectric layer GD may surround each horizontal layer HL.

[0244] The second conductive line GAA-WL may include a pair of flat sidewalls FS extending in the third direction D3. The flat sidewalls FS may also be referred to as "vertical sidewalls".

[0245] Although the present invention has been described with respect to the above specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a stack including a recessed target layer over the lower structure; forming a sacrificial isolation opening in the stack; forming a sacrificial isolation layer including a barrier layer in the sacrificial isolation opening; forming a sacrificial vertical opening in the stack between the sacrificial isolation layers; forming a preliminary horizontal layer by recessing the recess target layer of the stack through the sacrificial vertical opening; forming a first dielectric layer covering the preliminary horizontal layer; forming a second dielectric layer over the first dielectric layer; forming a cell isolation opening by removing the sacrificial isolation layer; as well as The first dielectric layer is trimmed through the cell isolation opening.

2. The method according to claim 1, wherein: The barrier layer includes a material having an etch selectivity with respect to the recessed target layer.

3. The method according to claim 1, wherein: The barrier layer includes silicon nitride, polysilicon, or a combination thereof.

4. The method according to claim 1, wherein: Forming the sacrificial isolation layer including the barrier layer comprises: conformally forming the barrier layers on the sacrificial isolation openings, respectively; forming a sacrificial liner layer over the barrier layer; and A sacrificial gap-filling layer filling the sacrificial isolation opening is formed over the sacrificial liner layer.

5. The method according to claim 4, wherein: The sacrificial liner layer includes silicon oxide, and The sacrificial gap-fill layer includes amorphous carbon.

6. The method according to claim 1, wherein: The recessed target layer includes a single crystal silicon layer.

7. The method according to claim 1, further comprising: Before trimming the first dielectric layer, a horizontal layer is formed by trimming a side surface of the preliminary horizontal layer.

8. The method according to claim 7, further comprising: After forming the horizontal layer, replacing a portion of the trimmed first dielectric layer with a horizontal conductive line; forming a vertical conductive line coupled to one side surface of the horizontal layer; as well as A data storage element coupled to the other side surface of the horizontal layer is formed.

9. The method according to claim 7, wherein: The cross section of the horizontal layer has a cross shape.

10. The method according to claim 1, wherein: The barrier layer is formed in a double structure of polysilicon and silicon nitride.

11. The method according to claim 1, wherein: Forming the stack including the recessed target layer includes: A first sacrificial layer stack, the recess target layer, and a second sacrificial layer stack are sequentially formed.

12. The method according to claim 11, wherein: Each of the first sacrificial layer stack and the second sacrificial layer stack is formed by sequentially stacking a first silicon germanium layer, a first single crystal silicon layer, and a second silicon germanium layer; as well as The recessed target layer includes a second single crystal silicon layer, and the second single crystal silicon layer is thicker than the first single crystal silicon layer.

13. A method for manufacturing a semiconductor device, the method comprising: forming a stack including a single crystal silicon layer; forming a sacrificial isolation opening in the stack; forming a blocking structure for blocking the single crystal silicon layer on the sacrificial isolation opening; forming a sacrificial isolation layer filling the sacrificial isolation opening on the blocking structure; forming a sacrificial vertical opening in the stack adjacent to the sacrificial isolation layer; as well as The single crystal silicon layer is recessed through the sacrificial vertical opening.

14. The method according to claim 13, wherein: Forming the blocking structure includes: A barrier layer is conformally formed over the sacrificial isolation opening to cover the single crystal silicon layer.

15. The method according to claim 13, wherein: Forming the blocking structure includes: forming a first blocking layer over the sacrificial isolation opening to block the single crystal silicon layer; and A second barrier layer is formed over the first barrier layer.

16. The method according to claim 13, wherein: Forming the blocking structure includes: forming a polysilicon layer over the sacrificial isolation opening to block the single crystal silicon layer; and Silicon nitride is formed over the polysilicon layer.

17. The method according to claim 13, wherein: Forming the blocking structure includes: forming a polysilicon layer blocking the single crystal silicon layer on the sacrificial isolation opening; forming silicon nitride over the polysilicon layer; and Silicon oxide is formed on the silicon nitride.

18. The method according to claim 13, wherein: The sacrificial isolation layer includes silicon oxide, amorphous carbon, a metal-based material or a combination thereof.

19. The method according to claim 13, further comprising: After recessing the single crystal silicon layer, forming a cell isolation opening by removing the sacrificial isolation layer; forming a single crystal silicon layer pattern by horizontally trimming the recessed single crystal silicon layer through the cell isolation opening; as well as A cell isolation layer filling the cell isolation opening is formed.

20. The method according to claim 19, further comprising: After forming the cell isolation layer, forming horizontal conductive lines facing each other vertically, with the single crystal silicon layer pattern being interposed between the horizontal conductive lines; forming a vertical conductive line coupled to a side surface of the single crystal silicon layer pattern; as well as A data storage element coupled to the other side surface of the single crystal silicon layer pattern is formed.

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