Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device may include: a gate structure including a gate line extending in a first direction; a first source pattern on the gate structure; a second source pattern on the first source pattern and extending in a second direction crossing the first direction; and a channel structure extending through the gate structure and protruding into the first source pattern.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to an electronic device and a method for manufacturing the electronic device, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device for forming a memory cell in a single layer on a substrate has reached its limit, a three-dimensional semiconductor device in which memory cells are stacked in a three-dimensional array over a substrate has been proposed. In addition, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods continue to be developed. Summary of the invention

[0003] In an embodiment of the present disclosure, a semiconductor device may include: a gate structure including a gate line extending in a first direction; a first source pattern located on the gate structure; second source patterns spaced apart from each other along the first direction, the second source pattern being located on the first source pattern and extending in a second direction intersecting the first direction; and channel structures spaced apart from each other along the first direction, each channel structure extending through the gate structure and protruding into the first source pattern.

[0004] In an embodiment of the present disclosure, a semiconductor device may include: a gate structure including a cell region and a contact region, and including a gate line extending in a first direction; a first source pattern located on the cell region of the gate structure; a second source pattern located on the first source pattern and extending in a second direction intersecting the first direction; a first insulating layer located between the second source patterns, respectively; and a second insulating layer located on the contact region.

[0005] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a stack on a substrate, the stack including a second material layer extending in a first direction; forming a channel structure extending through the stack into the substrate; exposing the channel structure by removing the substrate; forming a first source layer on the exposed channel structure; and forming a second source pattern on the first source layer, the second source pattern extending in a second direction intersecting the first direction.

[0006] In an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include the following steps: forming a gate structure, the gate structure including a cell region and a contact region and including a gate line extending in a first direction; forming contact plugs in the contact region, the contact plugs being respectively connected to the gate lines; forming a first source layer on a rear surface of the gate structure, the first source layer being located on the cell region and the contact region; forming a second source pattern in the cell region of the gate structure, the second source pattern being located on the first source layer and extending in a second direction intersecting the first direction; and forming a first insulating layer between the second source patterns.

[0007] These and other features and advantages of the present disclosure will become better understood from the following drawings and detailed description of embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1C is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] FIG. 2A to FIG. 2C is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 is a diagram for describing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A and Fig. 10B is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] Various embodiments of the present disclosure are directed to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0013] According to the present technology, a semiconductor device can have a stable structure and improved reliability.

[0014] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0015] Figures 1A to 1C is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1A It is a floor plan. Figure 1B It is along Figure 1AA cross-sectional view taken along line A-A', Figure 1C It is along Figure 1A A cross-sectional view taken along line BB'.

[0016] For reference, Figure 1A is a schematic plan view for describing relative positions of structures included in a semiconductor device. Figure 1A Can be omitted Figure 1B and Figure 1C Some structures or Figure 1B and Figure 1C Some areas of the Figures 1A to 1C The semiconductor device may include a gate structure 110, a channel structure 120, and a first source pattern 160 or a second source pattern 170 or a combination thereof. The semiconductor device may also include a contact plug 130, a first insulating layer 180, a second insulating layer 190, an interlayer insulating layer IL, and a separation insulating layer SI or a slit structure SLS or a combination thereof.

[0017] The gate structure 110 may include an insulating layer 110A and a gate line 110B alternately stacked. The gate line 110B may extend in a first direction I. The gate structure 110 may include a cell region CR and a contact region CTR adjacent to each other in the first direction I. The gate structure 110 may include Figure 4 Each gate line 110B may be exposed through the step structure. For reference, although Figures 1A to 1C Not shown in the figure, the gate structure 110 may not include a step structure. The gate line 110B may be a source selection line, a drain selection line, a word line or a bit line. The insulating layer 110A may each include an insulating material such as oxide. The gate line 110B may each include a conductive material such as tungsten, molybdenum or polysilicon.

[0018] The channel structure 120 may be located in the gate structure 110. The channel structure 120 may be located in the cell region CR of the gate structure 110. Each channel structure 120 may include a channel layer 120A or a memory layer 120B or a combination thereof. Each channel structure 120 may also include an insulating core 120C. The memory layer 120B may surround the channel layer 120A. The insulating core 120C may be located in the channel layer 120A.

[0019] The contact plugs 130 may be connected to the gate lines 110B of the gate structure 110 through the interlayer insulating layer IL, respectively. For example, the contact plugs 130 may be connected to the gate lines 110B, respectively, in the contact regions CTR. For reference, when the gate structure 110 does not include a step structure, the contact plugs 130 may extend through the gate structure 110, respectively, and be connected to the gate lines 110B. The contact plugs 130 may each include a conductive material such as tungsten.

[0020] The first source pattern 160 may be located on the gate structure 110. For example, the first source pattern 160 may be located on the cell region CR. The first source pattern 160 may be connected to the channel structure 120. For example, the first source pattern 160 may be connected to the channel structure 120 protruding into the first source pattern 160 through the gate structure 110. Here, the channel layer 120A of each channel structure 120 and the first source pattern 160 may be connected to each other. The first source pattern 160 may include polysilicon.

[0021] The second source patterns 170 may be located on the first source patterns 160. The second source patterns 170 may be located on the cell region CR of the gate structure 110. The second source patterns 170 may each include a material having a lower specific resistance than the first source patterns 160. For example, the second source patterns 170 may each include a metal. The second source patterns 170 may each include tungsten.

[0022] The second source patterns 170 may each extend in a second direction II intersecting the first direction I. For example, the second source pattern 170 may extend in the second direction II intersecting the gate line 110B extending in the first direction I. When the second source pattern 170 extends in a direction intersecting the gate line 110B, stress may be generated in different directions in the second source pattern 170 and the gate line 110B. For example, stress may be generated in the first direction I in the gate line 110B, and stress may be generated in the second source pattern 170 in the second direction II intersecting the first direction I. Therefore, the warpage of the semiconductor device may be reduced by the gate line 110B and the second source pattern 170 intersecting each other in different directions.

[0023] The first insulating layer 180 may be located between the second source patterns 170. The first insulating layer 180 may be located on the cell region CR of the gate structure 110. The first insulating layer 180 may extend in a second direction II crossing the gate line 110B extending in the first direction I. The first insulating layers 180 may each include an insulating material such as oxide.

[0024] The second insulating layer 190 may be located on the gate structure 110. For example, the second insulating layer 190 may be located on the contact region CTR of the gate structure 110. The height of the lower surface of the second insulating layer 190 may be substantially the same as or different from the height of the lower surface of each first insulating layer 180. For example, the height of the lower surface of the second insulating layer 190 may be located below the height of the lower surface of each first insulating layer 180. This is because the source patterns 160 and 170 are not located on the contact region CTR. The second insulating layer 190 may extend in a second direction II intersecting the gate line 110B extending in the first direction I. The second insulating layer 190 may include an insulating material such as an oxide.

[0025] The separation insulating layer SI may be located in the gate structure 110. For example, the separation insulating layer SI may be located in the cell region CR. The separation insulating layers SI may each extend in the first direction I. For example, the separation insulating layers SI may each extend in the first direction I through the cell region CR and extend to the contact region CTR. The separation insulating layer SI may be located between the channel structures 120. The separation insulating layer SI may partially penetrate the channel structure 120. For example, the separation insulating layer SI may insulate some gate lines 110B by partially penetrating the channel structure 120. Here, the insulated gate line 110B may be a drain selection line. The channel structure 120 partially penetrated by the separation insulating layer SI may be used as a real channel structure or as a dummy channel structure. The separation insulating layer SI may include an insulating material such as an oxide.

[0026] The slit structure SLS may be located in the gate structure 110. For example, the slit structure SLS may be located in the cell region CR. The slit structures SLS may each extend in the first direction I. For example, the slit structures SLS may each extend through the cell region CR in the first direction I and extend to the contact region CTR. A separation insulating layer SI may be located between the slit structures SLS. The slit structure SLS may be formed as a slit used as a channel for replacing a sacrificial layer (not shown) with a gate line 110B. The slit structures SLS may each include an insulating material such as an oxide or include a source contact structure.

[0027] According to the above structure, the gate lines 110B may each extend in a first direction I. The second source patterns 170 may each extend in a second direction II intersecting the first direction I. Therefore, warpage of the semiconductor device may be reduced by forming the second source patterns 170 in a direction intersecting the gate lines 110B.

[0028] In addition, a first source pattern 160 including polysilicon and a second source pattern 170 including a material having a lower specific resistance than the first source pattern 160 may be located on the cell region CR of the gate structure 110. That is, a source structure including a first source pattern 160 and a second source pattern 170 configured in multiple layers may be formed. Therefore, compared with a case where the source structure is formed as a single layer of polysilicon, the resistance of the source structure may be reduced, and source jumping may be reduced. The threshold voltage distribution of the memory cell may be reduced, the programming speed may be improved, and the operating characteristics may be improved. Since the resistance of the source structure is reduced, the layout of the upper wiring may be changed, and the wiring conventionally connected to the source structure may be used as a data wiring or a power wiring.

[0029] FIG. 2A to FIG. 2C is a simplified diagram illustrating a semiconductor device according to an embodiment of the present disclosure. FIG. 2A to FIG. 2C Hereinafter, any contents that are repeated with the previously described contents may be omitted.

[0030] Now refer to FIG. 2A to FIG. 2C , the second source pattern 270, the first insulating layer 280 and the second insulating layer 290 may extend in the second direction II. Figure 1A , the gate line 110B may extend in the first direction I. That is, the second source pattern 270, the first insulating layer 280, and the second insulating layer 290 may extend in the second direction II crossing the gate line 110B extending in the first direction I. Therefore, the stress generated in the first direction I and the stress generated in the second direction II may offset each other, so that the warpage of the semiconductor device may be reduced.

[0031] The shape, thickness, width, etc. of the second source pattern 270 may be various. Figure 2A , each of the second source patterns 270 may have a straight line shape extending in a second direction II crossing the first direction I. The first insulating layer 280 located between the second source patterns 270 may also have a straight line shape.

[0032] Reference Figure 2B , each of the second source patterns 270 may extend in an oblique direction that crosses the first direction I at an acute angle. The first insulating layer 280 located between the second source patterns 270 may also have a shape extending in the oblique direction.

[0033] Reference Figure 2C , each second source pattern 270 may extend in a zigzag shape. Alternatively, each second source pattern 270 may extend in a wavy shape. The first insulating layer 280 located between the second source patterns 270 may also extend in a wavy shape.

[0034] According to the above structure, the second source pattern 270 and the first insulating layer 280 may have various shapes. For example, each second source pattern 270 may extend in a straight line shape, an oblique line shape, or a zigzag shape. The first insulating layer 280 located between the second source patterns 270 may also extend in a straight line shape, an oblique line shape, or a zigzag shape. However, the shapes of the second source pattern 270 and the first insulating layer 280 are not limited thereto. The second source pattern 270 and the first insulating layer 280 may have any shape as long as they can extend in the second direction II to reduce the stress of the gate line 110B extending in the first direction I.

[0035] Figure 3 1 is a diagram for describing a semiconductor device according to an embodiment of the present disclosure.

[0036] Reference Figure 3, the semiconductor device may include a first structure WF1 or a second structure WF2 or a combination thereof. The first structure WF1 may refer to a first structure that does not include a substrate, but includes a gate structure 310, a channel structure 320, and a first source pattern 360 or a second source pattern 370 or a combination thereof. The first structure WF1 may also include a contact plug 330, a first insulating layer 380, a second insulating layer 390, an interlayer insulating layer IL1, and a first interconnect structure 340 or a first bonding pad 350 or a combination thereof.

[0037] The first interconnect structure 340 may be located below the gate structure 110. The first interconnect structure 340 may include a first contact via 340A or a first wiring 340B or a combination thereof. The first interconnect structure 340 may be connected to the channel structure 320 or the contact plug 330. For example, the first contact via 340A may be connected to the channel structure 320 or the contact plug 330, respectively. Each first wiring 340B may be connected to the first contact via 340A. The first contact via 340A or the first wiring 340B may each include a conductive material such as tungsten.

[0038] The first bonding pads 350 may be located below the first interconnect structure 340. Each of the first bonding pads 350 may be connected to the first interconnect structure 340. For example, each of the first bonding pads 350 may be connected to at least one first wiring 340B. The channel structure 320 and the contact plug 330 may be electrically connected to the second structure WF2 through the first interconnect structure 340 and the first bonding pads 350.

[0039] The second structure WF2 may include a substrate 1, a peripheral circuit PC, and a second interconnect structure 3 or a second bonding pad 4 or a combination thereof. The second structure WF2 may further include an interlayer insulating layer IL2 or an element isolation layer ISO or a combination thereof.

[0040] The peripheral circuit PC may be located on the substrate 1, and the element isolation layer ISO may be located in the substrate 1. The active region may be defined by the element isolation layer ISO. The peripheral circuit PC may include a transistor 2, a capacitor, a resistor, etc. For example, the transistor 2 may include a first junction 2A, a second junction 2B, a gate insulating layer 2C, or a gate electrode 2D. The gate insulating layer 2C may be located between the gate electrode 2D and the substrate 1. The gate insulating layer 2C and the element isolation layer ISO may each include an insulating material such as an oxide or a nitride.

[0041] The second interconnect structure 3 may include a second contact via 3A or a second wiring 3B or a combination thereof. The interlayer insulating layer IL2 may be located on the substrate 1. The second interconnect structure 3 may be located in the interlayer insulating layer IL2. The second interconnect structure 3 may be connected to the peripheral circuit PC. Each second contact via 3A may connect the junctions 2A and 2B of the transistor 2 to the second wiring 3B, or may connect the second wirings 3B to each other. Each second wiring 3B may be connected to the second contact via 3A, connect the second contact vias 3A to each other, or connect the second bonding pad 4 to the second contact via 3A. The second contact via 3A or the second wiring 3B may each include a conductive material such as tungsten.

[0042] The second bonding pads 4 may be located on the second interconnect structure 3. Each second bonding pad 4 may be connected to the second interconnect structure 3. For example, each second bonding pad 4 may be connected to at least one second wiring 3B. The peripheral circuit PC may be electrically connected to the first structure WF1 through the second interconnect structure 3 and the second bonding pads 4.

[0043] A bonding structure BS that electrically connects the first interconnect structure 340 and the second interconnect structure 3 to each other may be defined. The bonding structure BS may include a first bonding pad 350 and a second bonding pad 4. The first structure WF1 and the second structure WF2 may be bonded to each other. For example, the first structure WF1 and the second structure WF2 may be bonded to each other through the bonding structure BS. That is, the first bonding pad 350 of the first structure WF1 and the second bonding pad 4 of the second structure WF2 may be bonded to each other. Therefore, the first structure WF1 may be located on the second structure WF2. Here, in a state where the first structure WF1 is rotated, the upper portion of the second structure WF2 and the upper portion of the first structure WF1 may be bonded to each other.

[0044] For reference, here, the upper part and the lower part are relative concepts for convenience of description. The source patterns 360 and 370 may be located below the gate structure 310. Alternatively, the second structure WF2 may be located on the first structure WF1. Therefore, in a state where the second structure WF2 is rotated, the upper part of the second structure WF2 and the upper part of the first structure WF1 may be joined to each other.

[0045] According to the above structure, by separately forming the first structure WF1 including the cell array and the second structure WF2 including the peripheral circuit PC, the integration degree of the memory of the semiconductor device can be increased.

[0046] In addition, warpage of the first structure WF1 may be reduced in the first structure WF1 by the second source pattern 370 extending in the second direction II crossing the gate line 310B extending in the first direction I. Therefore, stress at a bonding interface between the first structure WF1 and the second structure WF2 may be reduced, and delamination at the bonding interface may be reduced.

[0047] Figures 4 to 10B 1 is a simplified diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0048] Reference Figure 4 , a first wafer WF1 may be formed. First, a stack 410D may be formed on a substrate 400. The stack 410D may include first material layers 410A and second material layers 410C that are alternately stacked. The first material layers 410A may each include an insulating material such as an oxide. The second material layers 410C may each include a sacrificial material such as a nitride. Alternatively, the first material layers 410A may each include an insulating material such as an oxide. The second material layers 410C may each include a conductive material such as polysilicon. Subsequently, a channel structure 420 extending into the stack 410D may be formed. Each channel structure 420 may include a channel layer 420A and a memory layer 420B surrounding the channel layer 420A or an insulating core 420C located in the channel layer 420A, or a combination thereof.

[0049] A step structure may be formed in the stack 410D. Each second material layer 410C of the stack 410D may be exposed through the step structure. After the step structure is formed, an interlayer insulating layer IL1 may be formed on the stack 410D. For reference, the process of forming the step structure in the stack 410D may be omitted. Contact plugs 430 respectively connected to the second material layers 410C of the stack 410D may be formed. For example, contact plugs 430 extending through the interlayer insulating layer IL1 and respectively connected to the second material layers 410C may be formed. For reference, when the stack 410D does not include the step structure, contact plugs 430 extending through the stack 410D and respectively connected to the second material layers 410C may be formed.

[0050] The gate structure 410 may be formed by replacing the second material layer 410C of the stack 410D with a gate line 410B. For example, the sacrificial material of the second material layer 410C may be replaced with a conductive material through a slit (not shown). Here, the gate lines 410B may each include a conductive material such as tungsten, molybdenum or polysilicon. The gate line 410B may be a selection line, a word line or a bit line. The gate structure 410 may include a cell region CR and a contact region CTR. The channel structure 420 may be formed in the cell region CR of the gate structure 410. The contact plug 430 may be formed in the contact region CTR of the gate structure 410. Therefore, the contact plug 430 may be connected to the gate line 410B of the gate structure 410 in the contact region CTR, respectively.

[0051] For reference, when the second material layers 410C each include a conductive material, the process of replacing the second material layers 410C with the gate lines 410B may be omitted. In this case, the second material layers 410C may be used as the gate lines 410B. The stack 410D may be used as the gate structure 410.

[0052] Subsequently, a first interconnection structure 440 may be formed on the gate structure 410. For example, a first interconnection structure 440 connected to the channel structure 420 and the contact plug 430 may be formed. The first interconnection structure 440 may include a first contact via 440A and a first wiring 440B. Each first contact via 440A may be connected to at least one channel structure 420. Alternatively, each contact via 440A may be connected to at least one contact plug 430. The first wirings 440B may be connected to the first contact vias 440A, respectively, or the first contact vias 440A may be connected to each other.

[0053] Subsequently, a first bonding pad 450 may be formed on the first interconnect structure 440. At least one first contact via 440A may be connected to the at least one first bonding pad 450. The first bonding pad 450 may be electrically connected to the channel structure 420 and the contact plug 430 through the first interconnect structure 440.

[0054] Reference Figure 5 , a second wafer WF2 may be formed. First, a peripheral circuit PC may be formed on a substrate 1. An element isolation layer ISO may be located in the substrate 1, and an active region may be defined by the element isolation layer ISO. The peripheral circuit PC may include a transistor 2, a resistor, a capacitor, and the like. The transistor 2 may include at least one of a first junction 2A, a second junction 2B, a gate insulating layer 2C, and a gate electrode 2D. The gate insulating layer 2C may be formed between the substrate 1 and the gate electrode 2D. The gate insulating layer 2C and the element isolation layer ISO may each include an insulating material such as an oxide or a nitride. An interlayer insulating layer IL2 may be formed on the substrate 1, and a second interconnect structure 3 may be formed in the interlayer insulating layer IL2.

[0055] A second bonding pad 4 may be formed on the second interconnect structure 3. The second interconnect structure 3 may include a second contact via 3A and a second wiring 3B. The second contact via 3A may connect the peripheral circuit PC and the second wiring 3B to each other. The second wiring 3B may connect the second contact vias 3A to each other or connect the second contact via 3A to the second bonding pad 4. The second bonding pad 4 may be electrically connected to the peripheral circuit PC through the second interconnect structure 3. Thus, a second wafer WF2 including the peripheral circuit PC may be formed.

[0056] Subsequently, the second wafer WF2 and the first wafer WF1 may be bonded to each other. The upper surface of the second wafer WF2 and the upper surface of the first wafer WF1 may be bonded to each other. For example, the first bonding pad 450 of the first wafer WF1 and the second bonding pad 4 of the second wafer WF2 may be connected to each other. Therefore, the peripheral circuit PC of the second wafer WF2 may be electrically connected to the channel structure 420 and the contact plug 430 through the bonding pads 4 and 450. By separately forming the first wafer WF1 including the cell array and the second wafer WF2 including the peripheral circuit PC, the integration of the memory of the semiconductor device may be improved.

[0057] Reference Figure 6 After the first wafer WF1 and the second wafer WF2 are bonded to each other, the substrate 400 may be removed. The channel structure 420 may be exposed by removing the substrate 400. Subsequently, the channel layer 420A of each channel structure 420 may be exposed. For example, the channel layer 420A may be exposed by etching the memory layer 420B exposed by removing the substrate 400.

[0058] Subsequently, a first source layer 460A may be formed on the exposed channel structure 420. The first source layer 460A may be formed on the back surface 410BS of the gate structure 410. For example, the first source layer 460A may be formed on the cell region CR and the contact region CTR of the gate structure 410, and on the back surface 410BS of the gate structure 410. The first source layer 460A may include polysilicon.

[0059] Subsequently, a second source layer 470A may be formed on the first source layer 460A. The second source layer 470A may include a material having a lower specific resistance than the first source layer 460A. For example, the second source layer 470A may include tungsten. A multilayer source structure is formed by forming a second source layer 470A including a material having a lower specific resistance than the first source layer 460A including polysilicon (e.g., tungsten) on the first source layer 460A, and thus, the resistance of the source structure may be reduced. Therefore, source jumps of the source structure may be reduced, and the characteristics of the memory cell may be improved.

[0060] Reference Fig. 7A and Figure 7B, a second source pattern 470 may be formed. For example, the second source pattern 470 may be formed on the cell region CR of the gate structure 410. First, a mask pattern may be formed by forming a mask layer (not shown) on the second source layer 470A, and then patterning the mask layer (not shown) to be spaced apart from each other in the first direction I. For example, a mask pattern exposing a portion corresponding to a portion of the contact region CTR of the gate structure 410 and a portion corresponding to a portion of the cell region CR of the gate structure 410 may be formed on the second source layer 470A. Subsequently, the second source layer 470A may be etched using the mask pattern as an etching barrier. Thus, a first opening OP1 may be formed. Therefore, a first opening OP1 extending in a second direction II intersecting the first direction I and exposing the first source layer 460A may be formed in the second source layer 470A. Here, the first opening OP1 may be formed on the cell region CR. The second source layer 470A may be separated into the second source pattern 470 by the first opening OP1.

[0061] The shape, width, thickness, etc. of the first opening OP1 for forming the second source pattern 470 may be various. Figure 7B , each first opening OP1 may have a straight line shape extending in the second direction II intersecting the first direction I. However, the present disclosure is not limited thereto, and each first opening OP1 may have a shape extending in an oblique line direction intersecting the first direction I at an acute angle, a sawtooth shape, etc. Therefore, each second source pattern 470 may also have a straight line shape, an oblique line shape, a sawtooth shape, etc.

[0062] When the first opening OP1 is formed on the cell region CR, the second opening OP2 exposing the first source layer 460A may be formed on the contact region CTR. The second opening OP2 exposing the first source layer 460A may be formed by etching a portion of the second source layer 470A formed on the contact region CTR.

[0063] The gate lines 410B may each extend in a first direction I. The second source patterns 470 may each extend in a second direction II intersecting the first direction I. The gate lines 410B may generate stress in the first direction I. The second source patterns 470 may generate stress in the second direction II. Therefore, in the gate lines 410B and the second source patterns 470, stresses are generated in different directions and thus may offset each other. Therefore, warpage of the semiconductor device may be reduced.

[0064] Reference Fig. 8A and Figure 8B, a first preliminary insulating layer 480A may be formed. The first preliminary insulating layer 480A may be formed on the first opening OP1 and the second opening OP2. The first preliminary insulating layer 480A may be formed to partially fill the second opening OP2 while being formed to fill the first opening OP1. The first preliminary insulating layer 480A may include an insulating material such as oxide.

[0065] Reference Fig. 9A and Fig. 9B , a first insulating layer 480 may be formed. The first preliminary insulating layer 480A may be etched so that the second source pattern 470 is exposed. Therefore, the first insulating layer 480 may be formed in the first opening OP1, respectively. That is, the first insulating layer 480 may extend along the first source layer 460A exposed by removing the second source layer 470A. The first insulating layer 480 may be formed between the second source patterns 470. Here, the first preliminary insulating layer 480A formed on the contact region CTR of the gate structure 410 may partially remain.

[0066] Subsequently, the contact region CTR of the gate structure 410 may be exposed. For example, the contact region CTR of the gate structure 410 may be exposed by etching a portion of the first source layer 460A formed on the contact region CTR through the second opening OP2. Here, the partially remaining first preliminary insulating layer 480A may also be etched and removed. Therefore, the first source pattern 460 located on the cell region CR may be formed by etching a portion of the first source layer 460A formed on the contact region CTR. In this case, the back surface 410BS of the contact region CTR of the gate structure 410 may be exposed.

[0067] Reference Fig. 10A and Fig. 10B , a second insulating layer 490 may be formed on the contact region CTR of the gate structure 410. For example, the second insulating layer 490 may be formed in the second opening OP2. First, a second preliminary insulating layer (not shown) may be formed in the second opening OP2. Here, the second preliminary insulating layer (not shown) may also be formed on the cell region CR. Subsequently, the second insulating layer 490 may be formed in the second opening OP2 by etching the second preliminary insulating layer (not shown) so that the second source pattern 470 is exposed. Therefore, the second insulating layer 490 located on the contact region CTR may be formed on the back surface 410BS of the gate structure 410.

[0068] Here, the height of the lower surface of the second insulating layer 490 may be substantially the same as or different from the height of the lower surface of each first insulating layer 480. For example, the height of the lower surface of the second insulating layer 490 may be formed below the height of the lower surface of each first insulating layer 480. This is because the second insulating layer 490 is formed after the source layers 460A and 470A formed on the contact region CTR are removed.

[0069] According to the above-described manufacturing method, the gate line 410B may be formed to extend in the first direction I. In addition, the source pattern 470 may be formed to extend in the second direction II intersecting the first direction I. Therefore, in the gate line 410B and the second source pattern 470, stresses are generated in different directions and thus may offset each other. Therefore, warpage of the semiconductor device may be reduced.

[0070] In addition, after the first wafer WF1 and the second wafer WF2 are bonded to each other, the substrate 400 of the first wafer WF1 may be removed. In subsequent processes, since stresses may be offset by forming the second source pattern 470 in a direction intersecting the gate line 410B, stresses at the bonding interface may also be reduced. Therefore, delamination at the bonding interface may be prevented, minimized, or reduced.

[0071] In addition, a multi-layer source structure may be formed by forming a first source pattern 460 including polysilicon and a second source pattern 470 including a material having a lower specific resistance than the first source pattern 460. Therefore, the resistance of the source structure may be reduced compared to a case where the source structure is a single layer including polysilicon. Therefore, source jumping may be reduced. In addition, the characteristics of the memory cell may be improved.

[0072] Although the embodiments according to the technical concept of the present disclosure are described above with reference to the accompanying drawings, this is only for the purpose of describing the embodiments according to the concepts of the present disclosure. The present disclosure is not limited to the above embodiments. Without departing from the technical concept of the present disclosure defined in the following claims, a person skilled in the art to which the present disclosure belongs may make various types of substitutions, modifications and changes to the embodiments, and these substitutions, modifications and changes should be interpreted as belonging to the scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

[0073] CROSS-REFERENCE TO RELATED APPLICATIONS

[0074] This application claims priority to Korean Patent Application No. 10-2023-0101390, filed on August 3, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a gate structure comprising a gate line extending in a first direction; a first source pattern, the first source pattern being located on the gate structure; second source patterns, the second source patterns being spaced apart from each other along the first direction, the second source patterns being located on the first source patterns and extending in a second direction crossing the first direction; as well as Channel structures are spaced apart from each other along the first direction, each channel structure extending through the gate structure and protruding into the first source pattern.

2. The semiconductor device according to claim 1, wherein The second source pattern includes a material having a lower specific resistance than that of the first source pattern.

3. The semiconductor device according to claim 1, wherein The first source pattern includes polysilicon, and the second source pattern includes metal.

4. The semiconductor device according to claim 1, wherein Each of the second source patterns extends in an oblique direction that intersects the first direction at an acute angle.

5. The semiconductor device according to claim 1, wherein Each of the second source patterns extends in a zigzag shape.

6. The semiconductor device according to claim 1, wherein The gate structure includes a cell region and a contact region, and the channel structure is located in the cell region. 7 . The semiconductor device according to claim 6 , further comprising contact plugs respectively connected to the gate lines in the contact regions.

8. The semiconductor device according to claim 6, wherein: The first source pattern and the second source pattern are located on the cell region.

9. The semiconductor device according to claim 1, further comprising: a first interconnect structure located below the gate structure and connected to the channel structure; Peripheral circuits; a second interconnect structure connected to the peripheral circuit; as well as A bonding structure electrically connects the first interconnect structure and the second interconnect structure to each other. 10 . The semiconductor device of claim 1 , further comprising first insulating layers respectively located between the second source patterns and extending in the second direction.

11. The semiconductor device according to claim 10, wherein The gate structure includes a cell region and a contact region, and the semiconductor device further includes a second insulating layer located on the contact region.

12. The semiconductor device according to claim 11, wherein The height of the lower surface of the second insulating layer is lower than the height of the lower surface of each of the first insulating layers.

13. A semiconductor device, comprising: a gate structure including a cell region and a contact region, and including a gate line extending in a first direction; a first source pattern, the first source pattern being located on the cell region of the gate structure; a second source pattern, the second source pattern being located on the first source pattern and extending in a second direction intersecting the first direction; a first insulating layer, wherein the first insulating layer is respectively located between the second source patterns; as well as A second insulating layer is located on the contact region.

14. The semiconductor device according to claim 13, wherein: The second source pattern includes a material having a lower specific resistance than that of the first source pattern.

15. The semiconductor device according to claim 13, wherein: Each of the second source patterns extends in an oblique direction crossing the first direction at an acute angle or extends in a zigzag shape.

16. The semiconductor device according to claim 13, wherein: Each of the first insulating layers extends in an oblique direction that intersects the first direction at an acute angle or extends in a zigzag shape.

17. The semiconductor device according to claim 13, further comprising: a channel structure, wherein the channel structure is located in the cell region; as well as Contact plugs are connected to the gate lines in the contact regions, respectively.

18. The semiconductor device according to claim 17, further comprising: a first interconnect structure located below the gate structure and connected to the channel structure; Peripheral circuits; a second interconnect structure connected to the peripheral circuit; as well as A bonding structure electrically connects the first interconnect structure and the second interconnect structure to each other.

19. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a stack on a substrate, the stack comprising a second material layer extending in a first direction; forming a channel structure extending through the stack into the substrate; exposing the channel structure by removing the substrate; forming a first source layer on the exposed channel structure; as well as A second source pattern is formed on the first source layer, the second source pattern extending in a second direction crossing the first direction.

20. The manufacturing method according to claim 19, wherein: The step of forming the second source pattern comprises the following steps: forming a second source layer on the first source layer; forming a first opening in the second source layer, the first opening extending in the second direction and exposing the first source layer; and A first insulating layer is formed in each of the first openings.

21. The manufacturing method according to claim 20, wherein: The stack includes first material layers and second material layers alternately stacked, and The manufacturing method further comprises the following steps: A gate structure is formed by replacing the second material layer with a gate line.

22. The manufacturing method according to claim 21, wherein: The gate structure includes a cell region and a contact region, and the first opening is formed on the cell region.

23. The manufacturing method according to claim 22, wherein: When the first opening is formed, a second opening exposing the first source layer is formed by etching a portion of the second source layer formed on the contact region.

24. The manufacturing method according to claim 23, further comprising the following steps: exposing the contact region of the gate structure by etching a portion of the first source layer formed on the contact region through the second opening; as well as A second insulating layer is formed on the exposed contact region of the gate structure.

25. The manufacturing method according to claim 24, wherein: A first source pattern located on the cell region is formed by etching the portion of the first source layer formed on the contact region.

26. The manufacturing method according to claim 21, wherein: The gate structure includes a cell region and a contact region, and The manufacturing method further includes the step of forming contact plugs respectively connected to the gate lines in the contact regions.

27. The manufacturing method according to claim 26, further comprising the following steps: A first wafer is bonded to a second wafer, the first wafer including the substrate, the gate structure, and the channel structure, and the second wafer including a peripheral circuit.

28. The manufacturing method according to claim 27, wherein: After the first wafer is bonded to the second wafer, the substrate is removed.

29. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a gate structure including a cell region and a contact region and including a gate line extending in a first direction; forming contact plugs in the contact regions, the contact plugs being connected to the gate lines respectively; forming a first source layer on the rear surface of the gate structure, the first source layer being located on the cell region and the contact region; forming a second source pattern in the cell region of the gate structure, the second source pattern being located on the first source layer and extending in a second direction intersecting the first direction; as well as A first insulating layer is formed between the second source patterns.

30. The manufacturing method according to claim 29, further comprising the following steps: removing a portion of the first source layer formed on the contact region; as well as A second insulating layer is formed on the rear surface of the gate structure, the second insulating layer being located on the contact region.

31. The manufacturing method according to claim 29, wherein: The step of forming the second source pattern comprises the following steps: forming a second source layer on the first source layer; and A first opening is formed in the second source layer, the first opening extending in the second direction and exposing the first source layer.

32. The manufacturing method according to claim 31, wherein: The first opening is formed on the cell region, and when the first opening is formed, a second opening exposing the first source layer is formed by etching a portion of the second source layer formed on the contact region.

33. The manufacturing method according to claim 29, wherein: The step of forming the gate structure comprises the following steps: forming a stack including a second material layer extending in the first direction; forming a channel structure extending into the stack; and The gate structure is formed by replacing the second material layer with the gate line.

34. The manufacturing method according to claim 33, further comprising the following steps: bonding a first wafer to a second wafer, the first wafer including the gate structure and the channel structure, and the second wafer including a peripheral circuit, Wherein, after the first wafer is bonded to the second wafer, the first source layer is formed to be connected to the channel structure.

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