Semiconductor device, manufacturing method thereof and storage system

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and a storage system. The semiconductor device comprises an alignment mark structure, and the alignment mark structure comprises a supporting layer, a plurality of supporting columns and a plurality of filling columns. The supporting layer comprises a first mark area, a second mark area and a spacer area adjacent to the first mark area and the second mark area; the plurality of support columns are distributed in the support layer, are arranged outside the first mark area and are positioned in the second mark area and the spacing area; the plurality of packed columns are distributed in the supporting layer and are arranged in the second marking area; wherein a supporting layer is arranged between the adjacent supporting column and filling column. The stability and the alignment accuracy of the alignment mark structure can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] Photolithography is usually required in the manufacturing process of semiconductor devices. Photolithography is a process of transferring the pattern on the mask to the surface of a substrate coated with photoresist through alignment, exposure, development and other steps. The photolithography process will form a patterned photoresist layer on the surface of the substrate, and then perform etching or ion implantation.

[0003] The current manufacturing process of semiconductor devices such as NAND memory usually requires dozens of lithography steps. In addition to the lithography machine, the factors that affect the lithography process error are also the accuracy of alignment. Overlay accuracy (OVL) is the measurement of the alignment accuracy between a lithography pattern placed on a substrate and a previously defined pattern. Since semiconductor devices are stacked with multiple layers of materials, the alignment accuracy of each layer with the previous layer must be guaranteed. During the manufacturing process of each layer, the alignment accuracy of each layer with the previous layer must be measured.

[0004] However, the existing process for measuring the overlay precision pattern is not stable, resulting in large defects in the obtained overlay precision pattern. Summary of the invention

[0005] The embodiments of the present application provide a semiconductor device and a manufacturing method thereof, and a storage system, which can improve the stability and alignment accuracy of an alignment mark structure.

[0006] An embodiment of the present application provides a semiconductor device, wherein the semiconductor device includes an alignment mark structure, and the alignment mark structure includes:

[0007] A support layer, comprising a first marking area, a second marking area, and a spacer area adjacent to the first marking area and the second marking area;

[0008] A plurality of support columns are distributed in the support layer, wherein the support columns are arranged outside the first marking area and located within the second marking area and the spacer area;

[0009] A plurality of filling columns are distributed in the support layer, and the filling columns are arranged in the second marking area;

[0010] Wherein, the supporting layer is spaced between adjacent supporting columns and filling columns.

[0011] In some embodiments of the present application, a boundary of the first marking area is adjacent to the supporting column, and a boundary of the second marking area is adjacent to the filling column.

[0012] In some embodiments of the present application, the support layer includes a plurality of first marking areas arranged along a first direction, and at least one first support column group arranged along the first direction is arranged between adjacent first marking areas, the first support column group includes a plurality of support columns arranged along a second direction, and the first direction intersects with the second direction.

[0013] In some embodiments of the present application, the width of the first marking area along the first direction is greater than the distance between two adjacent first supporting column groups located between two adjacent first marking areas along the first direction.

[0014] In some embodiments of the present application, the support layer includes a plurality of second marking areas arranged along the first direction, and at least one second support column group arranged along the first direction is arranged between adjacent second marking areas, and the second support column group includes a plurality of the support columns arranged along the second direction.

[0015] In some embodiments of the present application, at least one first filling column group arranged along the first direction is disposed in the second marking area, and the first filling column group includes a plurality of the filling columns arranged along the second direction.

[0016] In some embodiments of the present application, the second marking area includes a plurality of the first filling column groups. In the same second marking area, at least one third support column group arranged along the first direction is provided between two adjacent first filling column groups, and the third support column group includes a plurality of the support columns arranged along the second direction.

[0017] In some embodiments of the present application, the number of the third support column groups between two adjacent first filling column groups in the second marking area is different from the number of the second support column groups between two adjacent second marking areas.

[0018] In some embodiments of the present application, the support layer also includes a plurality of first marking areas arranged along the second direction and a plurality of second marking areas arranged along the second direction, and at least one second filling column group arranged along the second direction is provided in the second marking area, and the second filling column group includes a plurality of the filling columns arranged along the first direction.

[0019] In some embodiments of the present application, the support layer includes a plurality of the first marking areas and one second marking area, and the plurality of the first marking areas are arranged around the second marking area;

[0020] Wherein, the second marking area is provided with a plurality of the filling columns arranged in an array along the third direction and the fourth direction, and a plurality of the supporting columns arranged in an array along the third direction and the fourth direction, and the supporting columns are located between adjacent filling columns.

[0021] In some embodiments of the present application, the sidewalls of the support column and the sidewalls of the filling column are both covered with the support layer.

[0022] In some embodiments of the present application, the support layer includes a marking surface, the support column passes through at least a portion of the support layer, one end of the support column is exposed at the marking surface, and the filling column passes through at least a portion of the support layer, one end of the filling column is exposed at the marking surface.

[0023] In some embodiments of the present application, the support layer includes a first material layer and a second material layer that are alternately arranged, and the first material layer is arranged on both opposite sides of the support layer, and one end of the support column and one end of the filling column are exposed on the surface of the first material layer on one side of the support layer.

[0024] In some embodiments of the present application, the material of the first material layer includes silicon nitride material, and the material of the second material layer includes oxide material.

[0025] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a method for manufacturing a semiconductor device, which comprises the following steps:

[0026] Forming a support layer and a plurality of support pillars distributed in the support layer, wherein the support layer includes a first marking area, a second marking area, and a spacer area adjacent to the first marking area and the second marking area, and the support pillars are formed outside the first marking area and are located in the second marking area and the spacer area;

[0027] A plurality of filling columns are formed in the support layer and are located in the second marking area, and the support layer is spaced between adjacent support columns and filling columns.

[0028] In some embodiments of the present application, the step of forming a plurality of filling columns in the supporting layer and located in the second marking area further comprises:

[0029] The support layer comprises a marking surface, and a mask layer is formed on a side of the support layer where the marking surface is provided;

[0030] forming a plurality of mask holes corresponding to the second marking area in the mask layer, wherein the orthographic projections of the mask holes on the marking surface are staggered with the orthographic projections of the support pillars on the marking surface;

[0031] forming a plurality of openings in the second marking area in the support layer through a plurality of the mask holes;

[0032] A plurality of the filling columns are formed in the plurality of the openings.

[0033] In some embodiments of the present application, in the step of forming a plurality of mask holes corresponding to the second marking area in the mask layer:

[0034] The orthographic projection of the mask hole on the marking surface is spaced apart from the orthographic projection of the support column on the marking surface;

[0035] In the step of forming a plurality of openings in the second marking area in the support layer through the plurality of mask holes:

[0036] The support layer is spaced between the opening and the support column.

[0037] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a storage system, which includes the semiconductor device and a controller, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0038] The present application provides a semiconductor device and a manufacturing method and a storage system thereof, wherein a plurality of support columns are formed in a support layer, and no support columns are provided in a first marking area, while filling columns and support columns are provided in a second marking area, so as to distinguish the first marking area from the second marking area; in addition, the support columns and the filling columns are located in the support layer, and in the present application, a support layer is provided between the support columns and the filling columns, thereby avoiding the support columns being independent of the support layer during the hole opening process of the filling columns, thereby improving the phenomenon of the support columns collapsing; at the same time, no support columns are provided in the first marking area, and no hole is required to be opened, thereby improving the phenomenon of the support layer collapsing due to the hole opening and the lack of support columns, and the present application can improve the stability and alignment accuracy of the alignment mark structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0040] Figure 1 A schematic structural diagram of an alignment mark structure provided in some embodiments;

[0041] Figure 2 A schematic structural diagram of an alignment mark structure provided in some embodiments;

[0042] Figures 3 to 6 A schematic diagram of a manufacturing process structure of an alignment mark structure provided in some embodiments;

[0043] Figure 7 A schematic structural diagram of an alignment mark structure in a semiconductor device provided in some embodiments of the present application;

[0044] Figure 8 A schematic diagram of a top view of an alignment mark structure in a semiconductor device provided in some embodiments of the present application;

[0045] Figure 9a Some embodiments of the present application provide corresponding Figure 8 A schematic diagram of the local enlarged structure at position a in the middle;

[0046] Figure 9b Some embodiments of the present application provide corresponding Figure 8 A schematic diagram of the local enlarged structure at position b in the middle;

[0047] Fig.9c Some embodiments of the present application provide corresponding Figure 8 A schematic diagram of the local enlarged structure at position c in the middle;

[0048] Figure 9d Some embodiments of the present application provide corresponding Figure 8 Schematic diagram of the local enlarged structure at the middle d position;

[0049] Fig.10 Another schematic diagram of a top view of an alignment mark structure in a semiconductor device provided in some embodiments of the present application;

[0050] Fig.11 A flow chart of a method for manufacturing an alignment mark structure in a semiconductor device provided in some embodiments of the present application;

[0051] Figure 12 to Figure 14 A schematic diagram of a process structure of an alignment mark structure in a semiconductor device provided in some embodiments of the present application;

[0052] Fig.15 A schematic diagram of a structure of a storage system provided for some embodiments of the present application;

[0053] Fig.16 A schematic structural diagram of a memory card with a storage system provided for some embodiments of the present application;

[0054] Fig.17 A schematic structural diagram of a solid-state drive with a storage system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0056] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0057] Please combine Figure 1 and Figure 2 As shown, the types of alignment mark structures provided in some embodiments may specifically include Figure 1 The raster graphics shown (Advanced Image Measurement, AIM) and Figure 2 The box-in-box (BIB) graphic shown in the figure, wherein the AIM type mark structure includes mark units A and B, and the BIB type alignment mark structure includes mark units C and D, and the mark units A, B, C and D are all formed by the columnar structure of the array, and different columnar structure arrays are used to distinguish the mark units A, B, C and D.

[0058] Specifically, please combine Figures 3 to 6 First, a stacking layer 2 can be formed on the substrate 1, and the stacking layer 2 includes a stacked first sublayer 4 and a second sublayer 5; then, a plurality of first pillars 3 are formed in the stacking layer 2; then, the stacking layer 2 is etched to expose the plurality of first pillars 3, and at the same time, a second pillar 6 is formed at a position where the first pillar 3 is not set, and the second pillar 6 is formed by stacking the stacked first sublayer 4 and the second sublayer 5; then, the array formed by the first pillar 3 and the array formed by the second pillar 6 can correspond to two different marking units for distinction. However, since the first pillar 3 is not covered and supported by the stacking layer 2, it is easy to collapse, and the first sublayer 4 and the second sublayer 5 in the second pillar 6 are exposed, it is easy to peel off and collapse, and then the stability of the first pillar 3 and the second pillar 6 is poor, affecting the alignment accuracy.

[0059] The present application embodiment provides a semiconductor device, please refer to Figure 7 The semiconductor device includes an alignment mark structure, and the alignment mark structure includes a support layer 10, a plurality of support pillars 11 and a plurality of filling pillars 12.

[0060] The support layer 10 includes a first marking area 101, a second marking area 102 and a spacing area 103 adjacent to the first marking area 101 and the second marking area 102; a plurality of support columns 11 are distributed in the support layer 10, the support columns 11 are arranged outside the first marking area 101, and are located in the second marking area 102 and the spacing area 103; a plurality of filling columns 12 are distributed in the support layer 10, and the filling columns 12 are arranged in the second marking area 102.

[0061] Furthermore, a support layer 10 is spaced between adjacent support columns 11 and filling columns 12 .

[0062] The embodiment of the present application forms a plurality of support columns 11 in the support layer 10, but does not provide support columns 11 in the first marking area 101, while providing filling columns 12 and support columns 11 in the second marking area 102 to distinguish the first marking area 101 from the second marking area 102; in addition, the support columns 11 and the filling columns 12 are located in the support layer 10, and in the embodiment of the present application, the support columns 11 and the filling columns 12 are separated by the support layer 10, thereby avoiding the support columns 11 being independent of the support layer 10 during the hole opening process of the filling columns 12, thereby improving the phenomenon of the support columns 11 collapsing; at the same time, the support columns 11 are not provided in the first marking area 101, and no hole is required to be opened, thereby improving the phenomenon of the support layer 10 collapsing due to the hole opening and the lack of support from the support columns 11, and the embodiment of the present application can improve the stability and alignment accuracy of the alignment mark structure.

[0063] For details, please refer to Figure 7 The semiconductor device provided in the embodiment of the present application includes a substrate 20 and an alignment mark structure arranged on the substrate 20.

[0064] In some embodiments, the semiconductor device may include a chip area (not shown in the figure) and a cutting path area, and the semiconductor device also includes a device structure (not shown in the figure) arranged in the chip area, for example, it may be a device structure such as a memory chip, and the alignment mark structure is arranged in the cutting path area, which can be used for mask alignment of the semiconductor device during the manufacturing process.

[0065] It is understandable that the semiconductor device may be an uncut wafer or a cut memory or a partial structure of a memory, and after cutting, some of the alignment mark structures may remain on the semiconductor device.

[0066] like Figure 7As shown, the alignment mark structure includes a support layer 10 disposed on a substrate 20 , a plurality of support columns 11 , and a plurality of filling columns 12 , wherein the plurality of support columns 11 and the plurality of filling columns 12 are distributed in the support layer 10 .

[0067] The support layer 10 includes a first marking area 101, a second marking area 102 and a spacer area 103. The first marking area 101 and the second marking area 102 are used to form two different marking structures. The spacer area 103 is adjacent to the first marking area 101 and the second marking area 102. A plurality of support columns 11 are located outside the first marking area 101 and inside the second marking area 102 and the spacer area 103. A plurality of filling columns 12 are located inside the second marking area 102. Thus, the structure inside the first marking area 101 is different from that inside the second marking area 102, so as to distinguish the first marking area 101 from the second marking area 102. Wherein, no filling column 12 is arranged in the first marking area 101, and no hole is required to be opened, thereby improving the phenomenon that the support layer 10 collapses due to the opening of holes and the lack of support from the support column 11.

[0068] It should be noted that the orthographic projection shape of the support column 11 on the substrate 20 and the orthographic projection shape of the filling column 12 on the substrate 20 may be the same or different, and the orthographic projection size of the support column 11 on the substrate 20 and the orthographic projection size of the filling column 12 on the substrate 20 may be the same or different; and when the orthographic projection shapes and / or orthographic projection sizes of the support column 11 and the filling column 12 are different, the support column 11 and the filling column 12 can be better distinguished, and the specific selection can be made according to actual needs and is not limited here.

[0069] In some embodiments, the material of the support column 11 and the material of the filling column 12 may be different. For example, the material of the support column 11 may include polysilicon material, and the material of the filling column 12 may include silicon material.

[0070] In some embodiments, the alignment mark structure includes a marked surface 104 on a side away from the substrate 20, and one end of the support column 11 and one end of the filling column 12 are both exposed on the marked surface 104 of the support layer 10 to improve the mark recognition effect and accuracy.

[0071] Furthermore, the support layer 10 includes alternating first material layers 13 and second material layers 14, and the first material layers 13 are arranged on opposite sides of the support layer 10, and one end of the support column 11 and one end of the filling column 12 are exposed on the surface of the first material layer 13 on one side of the support layer 10. For example, the support layer 10 may include three layers of first material layers 13 and two layers of second material layers 14, and the stacking structure of the support layer 10 is, from the surface of the substrate 20 to the direction away from the substrate 20, a layer of first material layer 13, a layer of second material layer 14, a layer of first material layer 13, a layer of second material layer 14 and a layer of first material layer 13, and the side of the support layer 10 close to the substrate 20 and the side away from the substrate 20 are both the first material layer 13, and the marking surface 104 is located on the side of the support layer 10 away from the substrate 20; wherein, the support column 11 and the filling column 12 both pass through all the film layers in the support 10 except the layer of first material layer 13 close to the side of the substrate 20, so that one end of the support column 11 and one end of the filling column 12 are exposed on the marking surface 104, that is, one end of the support column 11 and one end of the filling column 12 are both exposed on the surface of the first material layer 13 on the side of the support layer 10 away from the substrate 20, for easy identification.

[0072] In some embodiments, the material of the first material layer 13 may include a silicon nitride material, and the material of the second material layer 14 may include an oxide material.

[0073] In some embodiments, the support column 11 is located outside the first marking area 101 and adjacent to the first marking area 101 to define the first marking area 101 without the support column 11 disposed therein, and the filling column 12 is located in the second marking area 102 and adjacent to the second marking area 102 to define the second marking area 102 with the filling column 12 disposed therein, that is, the boundary of the first marking area 101 can be adjacent to the support column 11 in the spacer area 103, and the boundary of the second marking area 102 can be adjacent to the filling column 12 therein, so that the boundary between the first marking area 101 and the second marking area 102 is more obvious and clear, so as to improve the recognition accuracy.

[0074] Furthermore, the side walls of the support column 11 and the side walls of the filling column 12 are surrounded by the support layer 10, that is, the support column 11 and the filling column 12 are separated by the support layer 10, so that the side walls of the support column 11 and the filling column 12 are all covered in the support layer 10, thereby avoiding the support column 11 from being independent of the support layer 10 when opening a hole, thereby improving the phenomenon of the support column 11 collapsing.

[0075] In some embodiments of this application, please combine Figure 7 , Figure 8 , Figure 9a , Figure 9b , Fig.9c ,as well as Figure 9d , Figure 8 A schematic structural diagram of an alignment mark structure provided in an embodiment of the present application.

[0076] The alignment mark structure includes a plurality of first mark regions 101, a plurality of second mark regions 102 and a spacer region 103. Figure 8 As shown, the alignment mark structure includes a plurality of first mark areas 101 arranged along a first direction X and a plurality of first mark areas 101 arranged along a second direction Y, and the first direction X intersects with the second direction Y, wherein the plurality of first mark areas 101 arranged along the first direction X can be divided into two groups and are centrally symmetrically distributed, and the plurality of first mark areas 101 arranged along the second direction Y can be divided into two groups and are centrally symmetrically distributed. The alignment mark structure also includes a plurality of second mark areas 102 arranged along the first direction X and a plurality of second mark areas 102 arranged along the second direction Y, wherein the plurality of second mark areas 102 arranged along the first direction X can be divided into two groups and are centrally symmetrically distributed, and the plurality of second mark areas 102 arranged along the second direction Y can be divided into two groups and are centrally symmetrically distributed.

[0077] In some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0078] Specifically, please combine Figure 8 and Figure 9a As shown, among the multiple first marking areas 101 arranged along the first direction X, at least one first support column group 111 arranged along the first direction X is provided between adjacent first marking areas 101, for example, two first support column groups 111; and the first support column group 111 is provided with multiple support columns 11 arranged along the second direction Y. It should be noted that the width of the first marking area 101 along the first direction X is greater than the distance between the two adjacent first marking areas 101 and the two adjacent first support column groups 111 along the first direction X, so that the first marking area 101 can be better identified.

[0079] Please combine Figure 8 and Figure 9b As shown, for a plurality of second marking areas 102 arranged along a first direction X, at least one second support column group 112 arranged along the first direction X is provided between adjacent second marking areas 102, for example, two second support column groups 112; the second support column group 112 includes a plurality of support columns 11 arranged along a second direction Y; at least one first filling column group 121 arranged along the first direction X is provided in each second marking area 102, and the first filling column group 121 includes a plurality of filling columns 12 arranged along the second direction Y.

[0080] When the second marking area 102 includes multiple first filling column groups 121, in the same second marking area 102, at least one third support column group 113 arranged along the first direction X is arranged between two adjacent first filling column groups 121, and the third support column group 113 includes multiple support columns 11 arranged along the second direction Y; wherein the number of the third support column group 113 between two adjacent first filling column groups 121 in the second marking area 102 is different from the number of the second support column group 112 between two adjacent second marking areas 102, so that the first marking area 101 can be better identified.

[0081] It should be noted that, in the plurality of second marking areas 102 arranged along the first direction X, in the same first filling column group 121, at least one supporting column 11 may be arranged between two adjacent filling columns 12 along the second direction Y. For example, one supporting column 11, such as Figure 8 shown.

[0082] Please combine Figure 8 and Fig.9c As shown, among the multiple first marking areas 101 arranged along the second direction Y, at least one fourth support column group 114 arranged along the second direction Y is arranged between adjacent first marking areas 101, for example, two fourth support column groups 114; and the fourth support column group 114 is provided with multiple support columns 11 arranged along the first direction X. It should be noted that the width of the first marking area 101 along the second direction Y is greater than the distance between the two adjacent first marking areas 101 and the two adjacent first support column groups 111 along the second direction Y, so that the first marking area 101 can be better identified.

[0083] Please combine Figure 8 and Figure 9d As shown, among the plurality of second marking areas 102 arranged along the second direction Y, at least one fifth support column group 115 arranged along the first direction X is provided between adjacent second marking areas 102, for example, two fifth support column groups 115, such as Figure 8 The fifth support column group 115 includes a plurality of support columns 11 arranged along the first direction X; each second marking area 102 is provided with at least one second filling column group 122 arranged along the second direction Y, and the second filling column group 122 includes a plurality of filling columns 12 arranged along the first direction X.

[0084] When the second marking area 102 includes multiple second filling column groups 122, in the same second marking area 102, at least one sixth support column group 116 arranged along the second direction Y is arranged between two adjacent second filling column groups 122, and the sixth support column group 116 includes multiple support columns 11 arranged along the first direction X; wherein the number of the sixth support column group 116 between two adjacent second filling column groups 122 in the second marking area 102 is different from the number of the fifth support column group 115 between two adjacent second marking areas 102, so that the first marking area 101 can be better identified.

[0085] It should be noted that, in the plurality of second marking areas 102 arranged along the second direction Y, in the same second filling column group 122, at least one supporting column 11 may be arranged between two adjacent filling columns 12 along the first direction X. For example, one supporting column 11, such as Figure 8 shown.

[0086] In other embodiments of the present application, please combine Figure 7 and Fig.10 , Fig.10 A schematic structural diagram of an alignment mark structure provided in an embodiment of the present application.

[0087] The alignment mark structure includes a plurality of first mark regions 101 , a second mark region 102 , and a spacing region 103 , wherein the plurality of first mark regions 101 are located around the second mark region 102 .

[0088] Specifically, the alignment mark structure may include a quadrilateral second mark area 102 and four first mark areas 101 , where the four first mark areas 101 are respectively located at four sides of the second mark area 102 .

[0089] Among them, the second marking area 102 is provided with a plurality of filling columns 12 arranged in an array along the third direction M and the fourth direction N, and a plurality of support columns 11 arranged in an array along the third direction M and the fourth direction N, and the support columns 11 are located between adjacent filling columns 12, that is, the support columns 11 and the filling columns 12 are staggered.

[0090] As mentioned above, in the embodiment of the present application, a plurality of first marking areas 101 and a plurality of second marking areas 102 are arranged to form an alignment mark structure. In this embodiment, a plurality of support columns 11 are formed in the support layer 10, and no support column 11 is provided in the first marking area 101, while a filling column 12 and a support column 11 are provided in the second marking area 102 to distinguish the first marking area 101 from the second marking area 102; in addition, the support column 11 and the filling column 12 are located in the support layer 10, and in the embodiment of the present application, the support column 11 and the filling column 12 are separated by the support layer 10, thereby avoiding the support column 11 being independent of the support layer 10 in the hole-making process of the filling column 12, and improving the phenomenon of the collapse of the support column 11; at the same time, no support column 11 is provided in the first marking area 101, and no hole is required to be made, which improves the phenomenon of the collapse of the support layer 10 due to the hole-making and the lack of support of the support column 11, and the embodiment of the present application can improve the stability and alignment accuracy of the alignment mark structure.

[0091] In addition, an embodiment of the present application further provides a method for manufacturing the semiconductor device described in the above embodiment, and the method for manufacturing the semiconductor device comprises the following steps:

[0092] A support layer 10 and a plurality of support columns 11 distributed in the support layer 10 are formed. The support layer 10 includes a first marking area 101, a second marking area 102, and a spacing area 103 adjacent to the first marking area 101 and the second marking area 102. The support columns 11 are formed outside the first marking area 101 and are located within the second marking area 102 and the spacing area 103.

[0093] A plurality of filling columns 12 are formed in the support layer 10 and located in the second marking region 102 , and the support layer 10 is spaced between adjacent support columns 11 and filling columns 12 .

[0094] Please combine Figure 7 , Fig.11 ,as well as Figure 12 to Figure 14 , the method for manufacturing the semiconductor device comprises the following steps:

[0095] Step S10, forming a support layer 10 and a plurality of support columns 11 distributed in the support layer 10, wherein the support layer 10 includes a first marking area 101, a second marking area 102, and a spacing area 103 adjacent to the first marking area 101 and the second marking area 102, and the support columns 11 are formed outside the first marking area 101 and are located inside the second marking area 102 and the spacing area 103.

[0096] Step S20 , forming a plurality of filling columns 12 in the second marking area 102 in the support layer 10 , with the support layer 10 being spaced between adjacent support columns 11 and filling columns 12 .

[0097] In step S10, a substrate 20 is provided, and a support layer 10 is formed on the substrate 20, specifically, a first material layer 13 and a second material layer 14 are alternately formed on the substrate 20, and the opposite sides of the support layer 10 are both first material layers 13; for example, the support layer 10 may include three layers of first material layers 13 and two layers of second material layers 14, and the stacked structure of the support layer 10 is, in sequence, a layer of first material layer 13, a layer of second material layer 14, a layer of first material layer 13, a layer of second material layer 14 and a layer of first material layer 13 on the substrate 20 to the direction away from the substrate 20, and the side of the support layer 10 close to the substrate 20 and the side away from the substrate 20 are both the first material layer 13, and the side of the support layer 10 away from the substrate 20 is defined as the marking surface 104.

[0098] In some embodiments, the material of the first material layer 13 may include a silicon nitride material, and the material of the second material layer 14 may include an oxide material.

[0099] A first marking area 101, a second marking area 102 and a spacing area 103 adjacent to the first marking area 101 and the second marking area 102 are defined on the support layer 10, and a plurality of support columns 11 are formed in the support layer 10, wherein the support columns 11 pass through all film layers in the support layer 10 except a first material layer 13 on the side close to the substrate 20, so that one end of the support column 11 away from the substrate 20 is exposed on the marking surface 104 for easy identification.

[0100] Furthermore, the support pillars 11 are distributed outside the first marking area 101 and are located in the second marking area 102 and the spacing area 103, so that the support layer 10 in the first marking area 101 does not need to undergo processes such as opening holes, thereby improving the stability of the support layer 10 in the first marking area 101.

[0101] In step S20, a mask layer 30 is formed on the side of the support layer 10 where the marking surface 104 is provided, and the mask layer 30 is patterned to form a plurality of mask holes 31 in the mask layer 30. The orthographic projection of the mask holes 31 on the marking surface 104 is staggered with the orthographic projection of the support column 11 on the marking surface 104, as shown in FIG. Fig.12 shown.

[0102] In some embodiments, the orthographic projection of the mask hole 31 on the marking surface 104 is spaced apart from the orthographic projection of the support column 11 on the marking surface 104 .

[0103] Then, a middle hole 130 is formed in the first material layer 13 on the side of the support layer 10 farthest from the substrate 20 through a plurality of mask holes 31, such as Fig.12 and Fig.13 shown.

[0104] Next, corresponding to the position of the middle hole 130, a plurality of openings 100 are formed in the support layer 10 in the second marking area 102, and the support layer 10 is spaced between the openings 100 and the support pillars 11, such as Fig.14 As shown, the support column 11 can be made independent of the support layer 10 during the process of forming the opening 100, thereby improving the phenomenon of the support column 11 collapsing.

[0105] Next, a plurality of filling columns 12 are formed in the plurality of openings 100, and one end of the filling column 12 away from the substrate 20 is exposed at the marking surface 104, as shown in FIG. Figure 7 As shown, for easy identification. A support layer 10 is provided between the filling column 12 and the support column 11 .

[0106] In summary, in the embodiment of the present application, the alignment mark structure is formed by arranging a plurality of first marking areas 101 and a plurality of second marking areas 102. In this embodiment, a plurality of support columns 11 are formed in the support layer 10, and no support column 11 is provided in the first marking area 101, while a filling column 12 and a support column 11 are provided in the second marking area 102 to distinguish the first marking area 101 from the second marking area 102; in addition, the support column 11 and the filling column 12 are located in the support layer 10, and in the embodiment of the present application, the support column 11 and the filling column 12 are separated by the support layer 10, thereby avoiding the support column 11 being independent of the support layer 10 in the hole-making process of the filling column 12, and improving the phenomenon of the collapse of the support column 11; at the same time, the support column 11 is not provided in the first marking area 101, and no hole is required, which improves the phenomenon of the collapse of the support layer 10 due to the hole-making and the lack of support of the support column 11, and the embodiment of the present application can improve the stability and alignment accuracy of the alignment mark structure.

[0107] In addition, the present application also provides a storage system, please refer to Fig.15 The storage system 40 includes the semiconductor device and a controller 41 . The controller 41 is coupled to the semiconductor device 42 and is used to control the semiconductor device 42 to store data.

[0108] The semiconductor device 42 is the semiconductor device described in the above embodiment or a semiconductor device manufactured by the manufacturing method of the semiconductor device described in the above embodiment.

[0109] In some embodiments, the semiconductor device 42 is a memory, and the following embodiments are described with reference to the memory 42 .

[0110] The storage system can be applied to mobile phones, desktop computers, laptop computers, tablet computers, car computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having a memory device therein. The host 50 can be a processor of an electronic device such as a central processing unit (CPU), or a system on a chip (SoC) such as an application processor (AP). The host 50 can be configured to send data to the memory 42 or receive data from the memory 42. In order to send data to the memory 42 or receive data from the memory 42, in addition to the data, the host 50 can also send instructions to the storage system 40.

[0111] In some embodiments, the controller 41 is coupled to the memory 42 and the host 50, and is configured to control the memory 42. The controller 41 may manage data stored in the memory 42, and communicate with the host 50.

[0112] In some embodiments, the controller 41 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0113] In some embodiments, the controller 41 is designed for operation in a high duty cycle environment SSD or an embedded multimedia card (eMMC) used as a data storage for mobile devices such as smartphones, tablets, laptops, etc., and an enterprise storage array. The controller 41 can be configured to control the operation (e.g., read, erase, and program operations) of the memory 42. For example, based on instructions received from the host 50, the controller 41 can transmit various commands such as program commands, read commands, erase commands, etc. to the memory 42 to control the operation of the memory 42.

[0114] The controller 41 may also be configured to manage various functions regarding data stored or to be stored in the memory 42, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, and the like. In some embodiments, the controller 41 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 42. The controller 41 may also perform any other appropriate functions, such as formatting the memory 42. The controller 41 may communicate with an external device (e.g., the host 50) according to a specific communication protocol. For example, the controller 41 may communicate with an external device through at least one of the following various interface protocols: for example, a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, and the like.

[0115] In some embodiments, please refer to Fig.16 , the above storage system can be applied to the memory card 61, for example, the controller 41 and the single memory 42 can be integrated into the memory card 61. The memory card 61 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 61 may also include a memory card 61 and a host (for example, Fig.15 A memory card connector 611 coupled to the host 50).

[0116] In some embodiments, please refer to Fig.17 The above storage system can also be applied to a solid-state drive 62 (SSD), for example, the controller 41 and the plurality of memories 42 can be integrated into the solid-state drive 62. The solid-state drive 62 can also include a device that connects the solid-state drive 62 to a host (for example, Fig.15 A solid state drive connector 621 coupled to the host 50).

[0117] In some embodiments, Fig.17 The solid state drive 62 in the illustrated embodiment has a storage capacity and / or operating speed greater than Fig.16 The storage capacity and / or operating speed of the memory card 61 in the illustrated embodiment.

[0118] Furthermore, some embodiments of the present application also provide an electronic device, which includes the above-mentioned storage system provided by some embodiments of the present application. Specifically, the electronic device can be a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, or any other device that can store data.

[0119] Some embodiments of the present application provide an electronic device, which has the same beneficial effects as the above-mentioned storage system due to the provision of the storage system provided by some embodiments of the present application.

[0120] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0121] The semiconductor device and its manufacturing method and storage system provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: The semiconductor device includes an alignment mark structure, and the alignment mark structure includes: A support layer, comprising a first marking area, a second marking area, and a spacer area adjacent to the first marking area and the second marking area; A plurality of support columns are distributed in the support layer, wherein the support columns are arranged outside the first marking area and located within the second marking area and the spacer area; A plurality of filling columns are distributed in the support layer, and the filling columns are arranged in the second marking area; Wherein, the supporting layer is spaced between adjacent supporting columns and filling columns.

2. The semiconductor device according to claim 1, wherein: The boundary of the first marking area is adjacent to the supporting column, and the boundary of the second marking area is adjacent to the filling column.

3. The semiconductor device according to claim 1, wherein: The support layer includes a plurality of first marking areas arranged along a first direction, and at least one first support column group arranged along the first direction is arranged between adjacent first marking areas, the first support column group includes a plurality of support columns arranged along a second direction, and the first direction intersects with the second direction.

4. The semiconductor device according to claim 3, characterized in that The width of the first marking area along the first direction is greater than the distance between two adjacent first supporting column groups located between two adjacent first marking areas along the first direction.

5. The semiconductor device according to claim 3, characterized in that The support layer includes a plurality of second marking areas arranged along the first direction, and at least one second support column group arranged along the first direction is disposed between adjacent second marking areas, and the second support column group includes a plurality of support columns arranged along the second direction.

6. The semiconductor device according to claim 5, characterized in that At least one first filling column group arranged along the first direction is disposed in the second marking area, and the first filling column group includes a plurality of the filling columns arranged along the second direction.

7. The semiconductor device according to claim 6, characterized in that The second marking area includes a plurality of the first filling column groups. In the same second marking area, at least one third support column group arranged along the first direction is arranged between two adjacent first filling column groups. The third support column group includes a plurality of the support columns arranged along the second direction.

8. The semiconductor device according to claim 7, characterized in that The number of the third supporting column groups between two adjacent first filling column groups in the second marking area is different from the number of the second supporting column groups between two adjacent second marking areas.

9. The semiconductor device according to claim 1, wherein: The support layer also includes a plurality of first marking areas arranged along the second direction and a plurality of second marking areas arranged along the second direction, wherein at least one second filling column group arranged along the second direction is provided in the second marking area, and the second filling column group includes a plurality of the filling columns arranged along the first direction.

10. The semiconductor device according to claim 1, wherein: The supporting layer includes a plurality of the first marking areas and one second marking area, and the plurality of the first marking areas are arranged around the second marking area; Wherein, the second marking area is provided with a plurality of the filling columns arranged in an array along the third direction and the fourth direction, and a plurality of the supporting columns arranged in an array along the third direction and the fourth direction, and the supporting columns are located between adjacent filling columns.

11. The semiconductor device according to claim 1, wherein: The sidewalls of the support column and the sidewalls of the filling column are both covered with the support layer.

12. The semiconductor device according to claim 1, wherein: The support layer comprises a marking surface, the support column passes through at least a portion of the support layer, one end of the support column is exposed at the marking surface, and the filling column passes through at least a portion of the support layer, one end of the filling column is exposed at the marking surface.

13. The semiconductor device according to claim 12, characterized in that The support layer includes a first material layer and a second material layer which are alternately arranged, and the first material layer is arranged on opposite sides of the support layer. One end of the support column and one end of the filling column are exposed on the surface of the first material layer on one side of the support layer.

14. The semiconductor device according to claim 13, characterized in that The material of the first material layer includes silicon nitride material, and the material of the second material layer includes oxide material.

15. A method for manufacturing a semiconductor device, characterized in that: The following steps are involved: Forming a support layer and a plurality of support columns distributed in the support layer, wherein the support layer includes a first marking area, a second marking area, and a spacer area adjacent to the first marking area and the second marking area, and the support columns are formed outside the first marking area and are located within the second marking area and the spacer area; A plurality of filling columns are formed in the support layer and are located in the second marking area, and the support layer is spaced between adjacent support columns and filling columns.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The step of forming a plurality of filling columns in the support layer and located in the second marking area further comprises: The support layer comprises a marking surface, and a mask layer is formed on a side of the support layer where the marking surface is provided; forming a plurality of mask holes corresponding to the second marking area in the mask layer, wherein the orthographic projections of the mask holes on the marking surface are staggered with the orthographic projections of the support pillars on the marking surface; forming a plurality of openings in the second marking area in the support layer through a plurality of the mask holes; A plurality of the filling columns are formed in the plurality of the openings.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: In the step of forming a plurality of mask holes corresponding to the second marking area in the mask layer: The orthographic projection of the mask hole on the marking surface is spaced apart from the orthographic projection of the support column on the marking surface; In the step of forming a plurality of openings in the second marking area in the support layer through the plurality of mask holes: The support layer is spaced between the opening and the support column.

18. A storage system, characterized in that: The storage system comprises the semiconductor device according to any one of claims 1 to 14 and a controller, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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