Three-dimensional memory device structure and forming method thereof

Abstract

A three-dimensional memory structure is disclosed, comprising: a first semiconductor structure, the first semiconductor structure comprising: a memory stack layer, the memory stack layer comprising interleaved conductive layers and first dielectric layers, the memory stack layer comprising a first side and a second side opposite the first side; the first interconnection layer is located on the first side of the storage stack layer and comprises a stop layer; and the gate gap structure vertically extends to penetrate through the storage stack layer and extends to the stop layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly, to a three-dimensional memory device structure and a method for forming the same. Background Art

[0002] Planar memory cells have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processing and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches its upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells.

[0003] The gate gap structure (GLS) can be used as a source contact for wiring the array common source (ACS) of multiple memory strings formed below the memory stack layer, while the drain is formed at the upper end of the memory string above the memory stack layer. In order to form an electrical connection between the memory string and the ACS, various challenging and costly processes need to be performed, and these are usually completed before the bonding process of the memory array device structure and the peripheral device structure. However, completing the GLS process before bonding may affect subsequent device processes and even cause defects. Summary of the Invention

[0004] Embodiments of a three-dimensional memory device structure and methods of forming the same are described in this disclosure.

[0005] One aspect of the present disclosure provides a three-dimensional memory structure, comprising: a first semiconductor structure, the first semiconductor structure comprising: a memory stack layer, the memory stack layer comprising an interlaced conductive layer and a first dielectric layer, the memory stack layer comprising a first side and a second side opposite to the first side; a first interconnect layer located on the first side of the memory stack layer, the first interconnect layer comprising a stop layer; and a gate gap structure, the gate gap structure extending vertically through the memory stack layer and extending to the stop layer.

[0006] In some examples, the gate gap structure includes a second dielectric layer along a bottom and sidewalls of the gate gap structure and a conductive material surrounded by the second dielectric layer, wherein the bottom of the gate gap structure is in direct contact with the stop layer in the first interconnect layer.

[0007] In some examples, the conductive material includes polysilicon.

[0008] In some examples, the stop layer includes a metal layer.

[0009] In some examples, the first semiconductor structure further includes a semiconductor layer located on the second side of the memory stack layer.

[0010] In some examples, the first semiconductor structure further includes a channel structure extending vertically through the storage stack layer, the channel structure including a channel layer, a tunneling layer, a charge capture layer, and a blocking layer from the inside to the outside, and the semiconductor layer is in contact with the channel layer.

[0011] In some examples, the first semiconductor structure further includes a third dielectric layer located on a side of the semiconductor layer away from the memory stack layer, and the channel structure and the gate gap structure are flush with a top surface of the third dielectric layer.

[0012] In some examples, the three-dimensional memory structure also includes a second semiconductor structure, the second semiconductor structure including a substrate, a peripheral circuit layer above the substrate, and a second interconnect layer above the peripheral circuit layer, wherein the first interconnect layer and the second interconnect layer are connected by hybrid bonding.

[0013] In some examples, the three-dimensional memory structure further includes a peripheral circuit contact extending through the third dielectric layer, the semiconductor layer, and the memory stack layer and extending to the first interconnect layer.

[0014] On the other hand, the present disclosure provides a method for forming a three-dimensional memory structure, comprising: forming a first semiconductor structure, comprising: forming a first substrate; forming a sacrificial stack layer on one side of the first substrate, the sacrificial stack layer comprising an alternating sacrificial layer and a first dielectric layer, and forming a first interconnect layer on a side of the sacrificial stack layer away from the first substrate, the first interconnect layer comprising a stop layer; forming a gate gap opening passing through the sacrificial stack layer and extending to the stop layer; removing the sacrificial layer through the gate gap opening; forming a conductive layer in the space left after removing the sacrificial layer to form a memory stack layer comprising the alternating conductive layer and the first dielectric layer; and forming a gate gap structure in the gate gap opening.

[0015] In some examples, forming the gate slot structure further includes: depositing a second dielectric layer on a bottom and sidewalls of the gate slot opening, and filling the gate slot opening with a conductive material to form the gate slot structure.

[0016] In some examples, the conductive material includes polysilicon.

[0017] In some examples, the stop layer includes a metal layer.

[0018] In some examples, forming the first semiconductor structure further includes: forming a channel structure extending vertically through the storage stack layer, the channel structure including, from inside to outside, a channel layer, a tunneling layer, a charge trapping layer, and a blocking layer.

[0019] In some examples, before forming the gate gap opening, the method further includes: forming a second semiconductor structure, the second semiconductor structure including a second substrate, a peripheral circuit layer above the second substrate, and a second interconnect layer above the peripheral circuit layer; and connecting the first interconnect layer to the second interconnect layer by hybrid bonding.

[0020] In some examples, after connecting the first interconnect layer to the second interconnect layer, the method further includes: removing the first substrate; removing exposed portions of the tunneling layer, the charge trapping layer, and the blocking layer; forming a semiconductor layer on a side of the storage stack layer away from the first interconnect layer, wherein the semiconductor layer is in contact with the channel layer; and forming a third dielectric layer on a side of the semiconductor layer away from the storage stack layer.

[0021] In some examples, forming the gate gap opening further includes: sequentially passing through the third dielectric layer, the semiconductor layer, and the memory stack layer to form the gate gap opening extending to the stop layer.

[0022] In some examples, the method further includes: forming a peripheral circuit contact extending to the first interconnect layer through the third dielectric layer, the semiconductor layer, and the storage stack layer; and forming a lead pad on the third dielectric layer, the lead pad being connected to the peripheral circuit contact.

[0023] In another aspect of the present disclosure, a storage system is also provided, including: a storage device, which is configured to store data, the storage device including: a first semiconductor structure, the first semiconductor structure including: a storage stack layer, the storage stack layer including interleaved conductive layers and a first dielectric layer, the storage stack layer including a first side and a second side opposite to the first side; a first interconnect layer located on the first side of the storage stack layer, the first interconnect layer including a stop layer; a gate gap structure, the gate gap structure extending vertically through the storage stack layer and extending to the stop layer; and a memory controller, the memory controller coupled to the storage device and configured to control the storage device.

[0024] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims, and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one skilled in the relevant art to make and use the present disclosure.

[0026] Figure 1 A cross-sectional view of a three-dimensional memory device according to an embodiment of the present disclosure is shown.

[0027] Figure 2 A cross-sectional view of a peripheral device structure according to an embodiment of the present disclosure is shown.

[0028] Figure 3A-3B A cross-sectional view and a corresponding top view of a memory array device structure according to an embodiment of the present disclosure are shown.

[0029] Figure 3C-3D A cross-sectional view and a corresponding top view of a memory array device structure according to an embodiment of the present disclosure are shown.

[0030] Figure 3E A cross-sectional view of a memory array device structure according to an embodiment of the present disclosure is shown.

[0031] Figure 4 A schematic diagram of bonding a memory array device structure to a peripheral device structure according to an embodiment of the present disclosure is shown.

[0032] Figures 5A-5F Cross-sectional views of a device structure at various stages in a method of forming a GLS structure according to an embodiment of the present disclosure are shown.

[0033] Figure 6 A flow chart of a method for forming a GLS structure according to an embodiment of the present disclosure is shown.

[0034] Figure 7 A block diagram of an exemplary system having a memory device according to an embodiment of the present disclosure is shown.

[0035] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which like reference numerals identify corresponding elements throughout. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The figure in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference numeral.

[0036] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0037] Although specific configurations and arrangements have been discussed, it will be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

[0038] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of persons skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0039] Generally, terms can be understood based, at least in part, on the context of use. For example, depending, at least in part, on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in the singular sense, or can be used to describe a combination of features, structures, or characteristics in the plural sense. Similarly, depending, at least in part, on the context, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage. Additionally, again depending, at least in part, on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can instead allow for the presence of additional factors that are not necessarily explicitly described.

[0040] It should be readily understood that “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only directly on something, but also includes being on something with intervening features or layers therebetween, and such that “over” or “over” includes not only being on or over something, but also includes being on or over something with no intervening features or layers therebetween (i.e., directly on something).

[0041] Additionally, spatially relative terms, such as "below," "beneath," "beneath," "above," and the like, may be used herein for ease of description to describe one element or feature in its relationship to other elements or features as depicted in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0042] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0043] Figure 1 FIG. 1 shows a cross-sectional view of a three-dimensional memory device 100 according to an embodiment of the present disclosure. Figure 1 As shown, the three-dimensional memory device 100 includes a peripheral device structure 101 and a memory array device structure 102 , wherein the peripheral device structure 101 is configured to control the operation of the memory array device structure 102 .

[0044] In some embodiments, the peripheral device structure 101 includes a substrate 106, a peripheral circuit layer 115 located on the substrate 106, and a first interconnect layer 114 located on the peripheral circuit layer. The substrate 106 may include single crystal silicon, Ge, SiGe, SiC, SOI, GOI, polycrystalline silicon, or a III-V compound (e.g., GaAs or InP). The peripheral circuit layer 115 (e.g., including control circuitry) may be fabricated on the substrate 106 and used to facilitate the operation of the memory array device structure 102. For example, the peripheral circuit layer may include metal oxide semiconductor field effect transistors (MOSFETs) and provide functional devices such as page buffers, sense amplifiers, column decoders, and row decoders. The first interconnect layer 114 includes a plurality of interconnect structures and contacts, which may include conductive materials such as W, Co, Cu, Al, or combinations thereof, for bonding to corresponding contacts of the memory array device structure 102, thereby bonding the peripheral device structure 101 and the memory array device structure 102 together via a flip-chip bonding method.

[0045] In some embodiments, the memory array device structure 102 includes a memory stack layer 104, a second interconnect layer 105 located on a side of the memory stack layer 104 close to the peripheral device structure 101, a bonding layer 113 located on the second interconnect layer 105, and a semiconductor layer 103 located on a side of the memory stack layer 104 away from the peripheral device structure 101. In some embodiments, the semiconductor layer 103 can be used as an array common source of the memory array device structure. Figure 1As shown, the memory array device structure 102 further includes a channel structure 111 extending through the memory stack layer and a GLS structure 130. In some embodiments, the channel structure 111 may be cylindrical. In one embodiment, the channel structure 111 includes, from the outer side of the column toward the center, a functional layer and a channel layer. In one embodiment, the functional layer may include a blocking layer on the sidewalls and bottom of the channel structure to block charge outflow, a charge trapping layer on the surface of the blocking layer to store charge during operation of the memory array device, and a tunneling layer on the surface of the charge trapping layer. The blocking layer may include one or more layers, each of which may include one or more materials. Materials for the blocking layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide-bandgap material, etc. The charge trapping layer may include one or more layers, each of which may include one or more materials. Materials for the charge trapping layer may include polycrystalline silicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide-bandgap material, etc. The tunneling layer may include one or more layers, each of which may include one or more materials. The material used for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The channel layer (also referred to as a "semiconductor channel") may be, for example, a polysilicon layer deposited on the tunneling layer. In some other embodiments, the channel layer may include amorphous silicon.

[0046] In some embodiments, the GLS structure 130 includes a dielectric liner 122 and a conductive material 121 filled therein to serve as an array common source contact. Figure 1 As shown, the GLS structure 130 extends through the memory stack layer 104 , and like the channel structure 111 , extends a certain height after passing through the memory stack layer 104 .

[0047] In one embodiment, the GLS structure 130, like the channel structure 111, is fabricated into the memory array device structure 102 before the peripheral device structure 101 and the memory array device structure 102 are bonded together. That is, both the GLS structure 130 and the channel structure 111 extend through the memory stack layer 104 to a relatively deep distance into the sacrificial substrate. As known to those skilled in the art, the formation of the array common source is performed on the back side of the memory array device structure 102, that is, after the formation of structures such as the GLS structure 130 and the channel structure 111, the memory array device structure 102 is turned upside down, and then the sacrificial substrate is removed from the back side and a semiconductor layer serving as the array common source is deposited. However, since the channel structure 111 and the GLS structure 130 extend a relatively deep distance into the sacrificial substrate, and both are narrow and thin columnar structures, especially with reference to FIG. Figure 1Channel structure 111 and GLS structure 130 can be seen protruding a certain height from dielectric layer 108. These narrow and thin protrusions pose considerable challenges to the sacrificial substrate stripping and semiconductor layer deposition processes, potentially introducing defects in the deposited semiconductor layers. Furthermore, since both GLS structure 130 and channel structure 111 are formed from the front side of the array device, and gate metal replacement using the GLS structure introduces significant bowing to the wafer, hindering subsequent bonding processes and potentially preventing some bonding contacts on the bonding surface from forming.

[0048] Therefore, in the present application, a method is proposed to form a GLS structure after bonding the peripheral device structure 101 and the storage array device structure 102 together, which not only solves the problems of process complexity and defects caused by the protrusion of the GLS structure on the back side, but also reduces the warping of the wafer, thereby optimizing the bonding.

[0049] Specifically, if Figure 1 As shown, second interconnect layer 105 includes a metal interconnect 143 that serves as a stop layer, and GLS structure 130 extends through memory stack layer 104 and contacts stop layer 143. In this embodiment, stop layer 143 is formed simultaneously with other interconnect structures in second interconnect layer 105, prior to bonding, and is free of any wiring. Subsequently, after memory array device structure 102 is flipped upside down and bonded to peripheral device structure 101, stop layer 143 can serve as a stop layer for drilling a hole for the GLS structure when processes for forming the ACS and GLS structures are performed on the backside of the device. That is, when a hole for the GLS is formed through memory stack layer 104 from the backside of the device after bonding, etching of the hole will stop on stop layer 143. Thus, this stop layer formed in interconnect layer 105 prior to bonding facilitates stopping the hole for the GLS at the appropriate location when etching the hole from the backside after bonding, thereby enabling the formation of the GLS structure after bonding.

[0050] In an embodiment, Figure 1 As shown, the three-dimensional memory device 100 further includes another dielectric layer 109 located on the dielectric layer 108, and a lead pad 133 is formed in the dielectric layer 109. Furthermore, a peripheral circuit contact 132 is formed through the dielectric layer 108, the semiconductor layer 103, and the memory stack layer 104, and is connected to the peripheral circuit below through the interconnect in the interconnect layer 105, thereby leading the peripheral circuit in the peripheral device structure to the outside of the device through the lead pad 133.

[0051] Figure 2FIG. 2 shows a cross-sectional view of a peripheral device structure 201 according to an embodiment of the present disclosure. Figure 2 As shown, the peripheral device structure 201 includes a substrate 106, a peripheral circuit layer 115 located on the substrate 106, and a first interconnect layer 114 located on the peripheral circuit layer. The substrate 106 may include single crystal silicon, Ge, SiGe, SiC, SOI, GOI, polycrystalline silicon, or a III-V compound (e.g., GaAs or InP). The peripheral circuit layer 115 can be fabricated on the substrate 106 and is used to facilitate the operation of the memory array device structure. For example, the peripheral circuit layer may include metal oxide semiconductor field effect transistors (MOSFETs) and provide functional devices such as page buffers, sense amplifiers, column decoders, and row decoders. The first interconnect layer 114 includes a plurality of interconnect structures and contacts, which may include conductive materials such as W, Co, Cu, Al, or combinations thereof, for bonding to corresponding contacts of the memory array device structure.

[0052] Figures 3A-3E Cross-sectional views of various stages in a method of forming a memory array device structure according to an embodiment of the present disclosure are shown. Figure 4 A schematic diagram of bonding a memory array device structure to a peripheral device structure according to an embodiment of the present disclosure is shown. Figures 5A-5F Cross-sectional views of a device structure at various stages in a method of forming a GLS structure after bonding according to an embodiment of the present disclosure are shown. Figure 6 A flow chart illustrating a method 600 of forming a GLS structure after bonding according to an embodiment of the present disclosure is shown. Figures 5A-5F and Figure 6 Examples of three-dimensional memory devices shown in include Figure 1 The three-dimensional memory device 100 shown in FIG. will be described together Figures 3A-3E 、 Figure 4 、 Figures 5A-5F and Figure 6 It should be understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 6 Execute in different orders as shown in .

[0053] like Figure 6 As shown, the method 600 begins at step 602, wherein a memory array device structure 301 is provided. Figures 3A-3E The steps of providing the memory array device structure 301 are explained in detail.

[0054] Figures 3A-3B A cross-sectional view and corresponding top view of a memory array device structure 301 according to an embodiment of the present disclosure are shown.

[0055] like Figure 3B As shown, a top plan view of a memory array device structure 301 is shown, and in Figure 3A In some embodiments, forming the memory array device structure 301 includes forming a sacrificial substrate 306, a dielectric stack 304 located on the substrate 306, and a channel structure 111 extending through the dielectric stack 304. Figure 3A As shown, the memory array device structure 301 further includes a first conductive layer 303 and a first dielectric layer 313 located between the sacrificial substrate 306 and the dielectric stack layer 304. In an embodiment, the conductive layer 303 may include a conductive material, including but not limited to polysilicon, doped silicon, silicide, or any combination thereof. The dielectric layer 313 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the dielectric stack layer 304 includes a stack of alternating sacrificial layers and dielectric layers. In some embodiments, each dielectric layer may include a silicon oxide layer, and each sacrificial layer may include a silicon nitride layer, but the present disclosure is not limited thereto.

[0056] In an embodiment, the dielectric stack layer 304 can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In some embodiments, the channel structure 111 can be formed as follows. First, an etching mask (not shown) is patterned on the dielectric stack layer 304 by photolithography, development, and etching. Then, the patterned etching mask can be used to etch through the dielectric stack layer 304 by one or more wet etching and / or dry etching processes (e.g., deep reactive ion etching (DRIE)) to form a channel hole using the pattern defined by the etching mask. Subsequently, one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) can be used to sequentially deposit functional layers and channel layers on the sidewalls and bottom surfaces of the channel hole. In an embodiment, the functional layers can include a blocking layer, a charge trapping layer, and a tunneling layer. The material used for the blocking layer can include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The material for the charge trapping layer may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, another wide bandgap material, etc. The material for the tunneling layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material such as aluminum oxide or hafnium oxide, another wide bandgap material, etc. The channel layer (also referred to as a "semiconductor channel") may be a polysilicon layer deposited on the tunneling layer. In some other embodiments, the channel layer may include amorphous silicon.

[0057] like Figure 3AAs shown, the memory array device structure 301 further includes a channel contact contacting one side of the channel structure 111 and a step contact contacting each step of the stepped dielectric stack layer 304. Figure 3B As shown in the plan view of FIG, the small dots on the left represent trench contacts contacting one side of the channel structure 111, and the large dots on the right represent step contacts contacting the steps of the dielectric stack layer 304. In some embodiments, the trench contacts and the step contacts may be formed by etching holes for the contacts using one or more wet etching and / or dry etching processes, and then depositing a conductive material in the holes using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable processes, or any combination thereof).

[0058] like Figures 3C-3D , which shows a cross-sectional view and a corresponding top view of a memory array device structure 301 according to an embodiment of the present disclosure after forming the second interconnect layer 105. Figure 3D shows a top plan view of a memory array device structure 301, and Figure 3C A cross-sectional view taken along line BB' of the plan view is shown.

[0059] In an embodiment, the second interconnect layer 105 may include an interlayer dielectric (ILD) layer and a plurality of interconnect structures formed in the ILD layer. The interconnect structures may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. The ILD layer may include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Figure 3C As can be seen in FIG, a portion of the interconnects in the interconnect layer 105 are connected to the trench contacts, and another portion of the interconnects are connected to the step contacts, thereby providing electrical connections between the two. In addition, the interconnect layer 105 also includes a metal layer 318 used as a stop layer, which is not connected to any other components of the memory array device structure.

[0060] like Figure 3D As shown in the plan view, the cross-shaped pattern on the left represents a portion of the interconnect structure connected to the trench contact, while the linear connection pattern on the right represents a portion of the interconnect structure connected to the step contact and its wiring. The thicker straight line labeled 318 represents the metal stop layer used to form the GLS. This layer is not used for electrical connection and has a straight line shape corresponding to the GLS.

[0061] Figure 3E FIG. 3 shows a cross-sectional view of a memory array device structure 301 according to an embodiment of the present disclosure after forming a bonding layer 113. Figure 3EAs shown, the bonding layer 113 is located on the second interconnect layer 105 and includes an interlayer dielectric (ILD) layer and a plurality of bonding contacts formed in the ILD layer. The bonding contacts may include conductive materials, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. The ILD layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0062] Figure 4 FIG. 1 shows a schematic diagram of bonding a memory array device structure to a peripheral device structure according to an embodiment of the present disclosure. Figure 4 As shown, first Figure 3E The memory array device structure 301 is shown flipped upside down, with the sacrificial substrate 306 facing upward and the bonding layer 113 side facing the peripheral device structure 201 below. Subsequently, the memory array device structure is bonded to the peripheral device structure in a face-to-face manner by bonding contacts in the first interconnect layer 114 in the peripheral device structure 201 to contacts in the bonding layer 113 in the memory array device structure 301. In some embodiments, the substrate 106 of the peripheral device structure 201 remains as the substrate of the bonded non-monolithic three-dimensional memory device, such that in the bonded non-monolithic three-dimensional memory device, the memory array device structure 301 is above the peripheral device structure 201. The peripheral device structure 201 can be bonded to the remainder of the three-dimensional memory device via a bonding interface (not shown) above it. In some embodiments, the bonding interface is the location where the peripheral device structure 201 and the remainder of the three-dimensional memory device meet and bond. In practice, the bonding interface can be a layer having a certain thickness that includes the top surface of the peripheral device structure 201 and the bottom surface of the remainder of the three-dimensional memory device. In some embodiments, one or more peripheral devices are formed in the peripheral device structure 201. The peripheral devices may include any suitable digital, analog, and / or mixed-signal peripheral circuits for facilitating operation of the three-dimensional memory device, such as page buffers, decoders, and latches (not shown).

[0063] Figures 5A-5F Cross-sectional views of a device structure at various stages in a method of forming a GLS structure after bonding according to an embodiment of the present disclosure are shown.

[0064] Figure 5A Shown as Figure 4 The three-dimensional memory device after bonding shown in FIG. includes a peripheral device structure below and a memory array device structure located on the peripheral device structure. Figure 5A As shown, after bonding, the sacrificial substrate 306 of the memory array device structure is located on the upper side of the three-dimensional memory device.

[0065] Figure 5BThe three-dimensional memory device is shown after removing the sacrificial substrate 306. In an embodiment, the substrate 306 can be removed from the back side of the substrate 306 (i.e., the side away from the peripheral device structure). In some embodiments, the substrate can be removed by a process such as wafer grinding, CMP and / or dry / wet etching, or a combination thereof. After removing the sacrificial substrate 306, the first dielectric layer 313 is exposed. In an embodiment, the first dielectric layer 313 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the material of the first dielectric layer 313 may be the same as the material of the dielectric layer in the dielectric stack layer 304.

[0066] Figure 5C FIG. 3 shows a three-dimensional memory device after removing the functional layer of the channel structure located above the upper surface of the first dielectric layer 313 and then depositing a conductive material to form a semiconductor layer. Figure 5C As shown, the functional layers of the channel structure located above the upper surface of the first dielectric layer 313 may first be removed by processes including, but not limited to, wafer grinding, CMP, and / or dry / wet etching, or a combination thereof. In some embodiments, the functional layers may include an ONO dielectric (e.g., a tunneling layer including silicon oxide, a charge trapping layer including silicon nitride, and a blocking layer including silicon oxide). A conductive material is then deposited on the upper surface of the first dielectric layer 313 and on the surface of the channel layer exposed after the functional layers are removed to form a semiconductor layer 503. That is, the semiconductor layer 503 completely covers the surface of the channel structure and the dielectric stack. In some embodiments, the deposited conductive material may include polysilicon. In some embodiments, the deposited conductive material is the same as the conductive material of the first dielectric layer 313. In some embodiments, the conductive material may be deposited using a thin film deposition process such as ALD, CVD, PVD, sputtering, or any other suitable process to form the semiconductor layer 503. In some embodiments, the semiconductor layer 503 may serve as an array common source (ACS) for multiple memory strings formed below the semiconductor layer 503.

[0067] Return Reference Figure 6 The method 600 proceeds to step 604 by forming a GLS opening through the dielectric stack 304 and extending into the stop layer 318 in the second interconnect layer 105 .

[0068] refer to Figure 5D , which shows a three-dimensional memory device after forming an interlayer dielectric layer 108 and forming a GLS opening 518 penetrating the semiconductor layer 503 and the dielectric stack layer 304. In some embodiments, Figure 5CAfter the semiconductor layer 503 is deposited as shown, an interlayer dielectric layer is deposited over the semiconductor layer 503 so that it is flush with the surface of the protruding portion of the channel structure. Then, a GLS opening 518 can be etched through the interlayer dielectric layer 108, the semiconductor layer 503, and the dielectric stack 304 using one or more wet etching and / or dry etching processes (e.g., deep reactive ion etching (DRIE)). In some embodiments, the etching operation stops on the surface of the stop layer 318 in the second interconnect layer 105.

[0069] Return Reference Figure 6 The method 600 proceeds to step 606 where the sacrificial layer in the dielectric stack 304 is removed through the GLS opening 518 to form the cavity 248 .

[0070] In some embodiments, as Figure 5D As shown, the sacrificial layer in the dielectric stack 304 is removed through the GLS opening 518 to leave the cavity 248. In an embodiment, the sacrificial layer may include a silicon nitride layer. In some embodiments, the sacrificial layer in the dielectric stack 304 is removed by wet etching and / or dry etching selectively relative to the dielectric layers in the dielectric stack 304. The etchant used to remove the sacrificial layer can be delivered through the GLS opening 518.

[0071] Return Reference Figure 6 The method 600 proceeds to step 608 where a conductive layer is formed in the cavity 248 remaining after removing the sacrificial layer in the dielectric stack 304 to form the memory stack 504 .

[0072] In some embodiments, as Figure 5EAs shown, a conductive layer 138 is formed along the sidewalls of the GLS opening 518 and fills the cavity 248 left by the etched sacrificial layer, thereby forming a memory stack 504 formed of alternating conductive layers 138 and dielectric layers. In some embodiments, the conductive layer 138 is a composite layer including an adhesion layer and a conductive layer (e.g., a gate conductor / gate line). In some embodiments, a gate dielectric layer is deposited before depositing the conductive layer 138. The gate dielectric layer and the conductive layer 138 can be formed by one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The gate dielectric layer can include a dielectric material including silicon nitride, a high-k dielectric, or any combination thereof. The conductive layer 138 can include a conductive material including, but not limited to, W, Co, Cu, Al, polysilicon, silicide, or any combination thereof. In some embodiments, the gate dielectric layer and the conductive layer 138 are each formed by a CVD process, wherein a reactant gas passes through the GLS opening 518 and reaches the lateral cavity 248 and reacts and deposits along the sidewalls of the GLS opening 518 and the cavity 248. Thus, the conductive layer 138 replaces the sacrificial layer to transform the dielectric stack 304 into the memory stack 504.

[0073] Finally, the method 600 proceeds to step 610 where a GLS structure 530 is formed in the GLS opening 518 .

[0074] In some embodiments, as Figure 5F As shown, the excess conductive layer 518 formed along the sidewalls of the GLS opening 518 is first removed. Subsequently, a dielectric liner 522 may be formed along the sidewalls and bottom of the GLS opening 518 by one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof), and then the opening is filled with a conductive material 521. In embodiments, the dielectric liner 522 may include any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In embodiments, the conductive material 521 may include but not limited to W, Co, Cu, Al, polysilicon, silicide, or any combination thereof.

[0075] Figure 7 A block diagram of an exemplary storage system 700 having a three-dimensional storage device according to an embodiment of the present disclosure is shown. System 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 7As shown, system 700 may include a host 708 and a memory system 702 having one or more memory devices 704 and a memory controller 706. Host 708 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 708 may be configured to send data to or receive data from memory device 704.

[0076] The memory device 704 can be any memory device disclosed herein, such as the three-dimensional memory device 100. In some embodiments, the memory device 704 includes a first semiconductor structure, the first semiconductor structure including: a memory stack layer, the memory stack layer including alternating conductive layers and a first dielectric layer, the memory stack layer including a first side and a second side opposite the first side; a first interconnect layer located on the first side of the memory stack layer, the first interconnect layer including a stop layer; and a gate slit structure, the gate slit structure extending vertically through the memory stack layer and extending to the stop layer.

[0077] According to some embodiments, the memory controller 706 is coupled to the memory device 704 and the host 708 and is configured to control the memory device 704. The memory controller 706 can manage data stored in the memory device 704 and communicate with the host 708. The memory controller 706 can be configured to control operations of the memory device 704, such as read, write, and refresh operations. The memory controller 706 can also be configured to manage various functions related to data stored or to be stored in the memory device 704, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0078] In some embodiments, the memory controller 706 and the one or more memory devices 704 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the storage system 700 can be implemented and packaged into different types of terminal electronic products. The memory controller 706 can communicate with an external device (e.g., a host 708) according to a specific communication protocol. For example, the memory controller 706 can communicate with an external device through at least one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer miniature interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.

[0079] The foregoing descriptions of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0080] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional memory structure, comprising: A first semiconductor structure, the first semiconductor structure comprising: a memory stack layer, the memory stack layer comprising interleaved conductive layers and a first dielectric layer, the memory stack layer comprising a first side and a second side opposite the first side; a first interconnect layer located at the first side of the memory stack layer, the first interconnect layer comprising a stop layer; A gate gap structure vertically extends through the memory stack layer and extends to the stop layer.

2. The three-dimensional memory structure according to claim 1, wherein: The gate slot structure includes a second dielectric layer along a bottom and sidewalls of the gate slot structure and a conductive material surrounded by the second dielectric layer, wherein the bottom of the gate slot structure is in direct contact with the stop layer in the first interconnect layer.

3. The three-dimensional memory structure according to claim 2, wherein: The conductive material includes polysilicon.

4. The three-dimensional memory structure according to claim 1 or 2, wherein: The stop layer includes a metal layer.

5. The three-dimensional memory structure according to claim 1, wherein: The first semiconductor structure further includes a semiconductor layer located on the second side of the memory stack layer.

6. The three-dimensional memory structure according to claim 5, wherein: The first semiconductor structure also includes a channel structure extending vertically through the storage stack layer, the channel structure includes a channel layer, a tunneling layer, a charge trapping layer and a blocking layer from the inside to the outside, and the semiconductor layer is in contact with the channel layer.

7. The three-dimensional memory structure according to claim 5 or 6, wherein: The first semiconductor structure further includes a third dielectric layer located on a side of the semiconductor layer away from the memory stack layer, and the channel structure and the gate gap structure are flush with a top surface of the third dielectric layer.

8. The three-dimensional memory structure according to claim 1, further comprising a second semiconductor structure, the second semiconductor structure comprising a substrate, a peripheral circuit layer above the substrate, and a second interconnect layer above the peripheral circuit layer, wherein: The first interconnect layer and the second interconnect layer are connected by hybrid bonding.

9. The three-dimensional memory structure of claim 1, further comprising a peripheral circuit contact extending through the third dielectric layer, the semiconductor layer, and the memory stack layer and extending to the first interconnect layer.

10. A method of forming a three-dimensional memory structure, comprising: Forming a first semiconductor structure, comprising: forming a first substrate; forming a sacrificial stack layer on one side of the first substrate, the sacrificial stack layer comprising alternating sacrificial layers and a first dielectric layer, and forming a first interconnect layer on a side of the sacrificial stack layer away from the first substrate, wherein the first interconnect layer includes a stop layer; forming a gate gap opening passing through the sacrificial stack layer and extending to the stop layer; removing the sacrificial layer through the gate gap opening; forming a conductive layer in a space left after removing the sacrificial layer to form a storage stack layer including the conductive layer and the first dielectric layer interlaced; and A gate slot structure is formed in the gate slot opening.

11. The method according to claim 10, wherein: Forming the gate gap structure further includes: A second dielectric layer is deposited on the bottom and sidewalls of the gate gap opening, and the gate gap opening is filled with a conductive material to form the gate gap structure.

12. The method according to claim 11, wherein: The conductive material includes polysilicon.

13. The method according to claim 10, wherein: The stop layer includes a metal layer.

14. The method according to claim 10, wherein: Forming the first semiconductor structure also includes: forming a channel structure that vertically extends through the storage stack layer, and the channel structure includes a channel layer, a tunneling layer, a charge trapping layer and a blocking layer from the inside to the outside.

15. The method according to claim 10 or 11, wherein: Before forming the gate gap opening, the method further includes: forming a second semiconductor structure, the second semiconductor structure comprising a second substrate, a peripheral circuit layer over the second substrate, and a second interconnect layer over the peripheral circuit layer; and The first interconnect layer is connected to the second interconnect layer by hybrid bonding.

16. The method according to claim 15, wherein: After connecting the first interconnect layer to the second interconnect layer, the method further comprises: removing the first substrate; removing exposed portions of the tunneling layer, the charge trapping layer, and the blocking layer; forming a semiconductor layer on a side of the memory stack layer away from the first interconnect layer, wherein the semiconductor layer is in contact with the channel layer; and A third dielectric layer is formed on a side of the semiconductor layer away from the memory stack layer.

17. The method according to claim 16, wherein: Forming the gate gap opening further includes: sequentially passing through the third dielectric layer, the semiconductor layer, and the memory stack layer to form the gate gap opening extending to the stop layer.

18. The method according to claim 16, wherein: The method further comprises: forming a peripheral circuit contact extending to the first interconnect layer through the third dielectric layer, the semiconductor layer, and the memory stack layer; and A lead pad is formed on the third dielectric layer, and the lead pad is connected to the peripheral circuit contact.

19. A storage system comprising: A storage device, the storage device being configured to store data, the storage device comprising: A first semiconductor structure, the first semiconductor structure comprising: a memory stack layer, the memory stack layer comprising interleaved conductive layers and a first dielectric layer, the memory stack layer comprising a first side and a second side opposite the first side; a first interconnect layer located at the first side of the memory stack layer, the first interconnect layer comprising a stop layer; A gate gap structure extending vertically through the storage stack layer and extending to the stop layer and A memory controller is coupled to the memory device and is configured to control the memory device.

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