Memory device and manufacturing method of memory device

Abstract

The invention relates to a memory device and a manufacturing method of the memory device. The memory device may include a stack structure including a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked along a first direction, an opening in the stack structure extending from at least one of the plurality of conductive layers in the first direction, and a contact plug in the opening. The opening may include a protruding portion protruding in a second direction intersecting the first direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0102046 filed in the Korean Intellectual Property Office on August 4, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device including a memory block having a three-dimensional structure and a method of manufacturing the memory device. Background Art

[0004] The memory device may include a nonvolatile memory device, and data stored in the nonvolatile memory device is retained even when power is interrupted. According to the structure in which the memory cells are arranged, the nonvolatile memory device can be divided into a two-dimensional structure and a three-dimensional structure. The memory cells of the nonvolatile memory device with a two-dimensional structure can be arranged in a single layer above the substrate, while the memory cells of the nonvolatile memory device with a three-dimensional structure can be stacked in a vertical direction above the substrate. Since the integration of the nonvolatile memory device with a three-dimensional structure is higher than that of the nonvolatile memory device with a two-dimensional structure, electronic devices using nonvolatile memory devices with a three-dimensional structure have become popular. Summary of the invention

[0005] According to one aspect of the present disclosure, a memory device is provided, which includes: a stacking structure including a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked along a first direction; an opening located in the stacking structure and extending from at least one of the plurality of conductive layers in the first direction; and a contact plug located in the opening, wherein the opening includes a protruding portion protruding in a second direction intersecting the first direction.

[0006] According to another aspect of the present disclosure, a method for manufacturing a memory device is provided, the method comprising: forming a preliminary stacking structure including a first material layer set and a second material layer set, the first material layer set and the second material layer set each including at least one first material layer and at least one second material layer, the first material layer set and the second material layer set being stacked on each other; forming a first opening in the second material layer set to expose the first material layer set; forming a protective layer on an inner wall of the first opening while forming the first opening; and forming a second opening in the first material layer set exposed by the first opening, wherein a width of a top end of the second opening is greater than a width of a bottom end of the first opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will be described more fully below with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0008] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout.

[0009] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is a view schematically illustrating a memory device according to an embodiment of the present disclosure.

[0011] Figure 3 is a view showing a cell region and a contact region of a memory device according to an embodiment of the present disclosure.

[0012] Figure 4A and Figure 4B is a view showing a structure of a memory device according to an embodiment of the present disclosure.

[0013] FIG. 5A to FIG. 5M 2 is a view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

[0014] Figure 6 is a view showing a structure of a memory device according to another embodiment of the present disclosure.

[0015] Figure 7 is a diagram showing a memory card system to which the memory device of the present disclosure is applied.

[0016] Figure 8 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0017] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be construed as being limited to the embodiments set forth herein.

[0018] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical spirit of the present disclosure.

[0019] Embodiments provide a memory device and a method of manufacturing the memory device, in which widths of contact plugs respectively connected to gate lines are constantly formed.

[0020] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0021] refer to Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0022] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly connected to the first to i-th memory blocks BLK1 to BLKi.

[0023] The first to i-th memory blocks BLK1 to BLKi may be formed in a three-dimensional structure. The memory block having the three-dimensional structure may include memory cells stacked in a vertical direction over a substrate.

[0024] The memory cell can store one bit or two bits or more of data according to the programming method. For example, the method of storing one bit of data in one memory cell can be called a single-level cell (SLC) method, and the method of storing two bits of data in one memory cell can be called a multi-level cell (MLC) method. The method of storing three bits of data in one memory cell can be called a three-level cell (TLC) method, and the method of storing four bits of data in one memory cell can be called a quad-level cell (QLC) method. In addition, five or more bits of data can be stored in one memory cell.

[0025] The peripheral circuit 170 may be configured to perform a program operation for storing data, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0026] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0027] The programming voltage may be a voltage applied to a selected word line in a word line WL in a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. A precharge voltage may be a voltage higher than 0V, and may be applied to a bit line in a read operation. A verification voltage may be used in a verification operation to determine whether the threshold voltage of a selected memory cell has been increased to a target level. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0028] In a read operation of a selected memory cell, a read voltage may be applied to the selected word line. For example, the read voltage may be set to various levels according to the programming mode of the selected memory cell. The pass voltage may be a voltage applied to an unselected word line in a word line WL in a programming or read operation, and may be used to turn on a memory cell connected to an unselected word line. The erase voltage may be used in an erase operation to erase a memory cell included in a selected memory block, and may be applied to a source line SL.

[0029] The row decoder 130 may be configured to transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the i-th memory block BLKi through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0030] The page buffer group 140 may include a page buffer (not shown) connected to each of the first to i-th memory blocks BLK1 to BLKi. The page buffer (not shown) may be connected to the first to i-th memory blocks BLK1 to BLKi, respectively, through the bit lines BL. In a read operation, in response to a page buffer control signal PBSIG, the page buffer (not shown) may sense a current or voltage of the bit line BL (which varies according to a threshold voltage of a selected memory cell), and may temporarily store the sensed data.

[0031] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL and may transmit an enable signal through the column line. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0032] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller to the control circuit 180 through the input / output line I / O, and may transmit data received from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller through the input / output line I / O.

[0033] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation of a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation of the selected memory block and output the read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation of the selected memory block.

[0034] Figure 2 is a view schematically illustrating a memory device according to an embodiment of the present disclosure.

[0035] refer to Figure 2, the memory device 100 may include a peripheral circuit structure PC and memory blocks BLK1 to BLKi, which are disposed on a substrate SUB. The memory blocks BLK1-BLKi may overlap the peripheral circuit structure PC.

[0036] The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by a selective epitaxial growth process.

[0037] The peripheral circuit structure PC may include a row decoder ( Figure 1 130), column decoder ( Figure 1 150), page buffer group ( Figure 1 140 shown), control circuit ( Figure 1 180 as shown), etc., which constitute a circuit for controlling the operation of the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include an NMOS transistor, a PMOS transistor, a resistor, a capacitor, etc. electrically connected to the memory blocks BLK1 to BLKi. The peripheral circuit structure PC may be disposed between the substrate SUB and the memory blocks BLK1 to BLKi.

[0038] Each of the memory blocks BLK1 to BLKi may include a source structure, a bit line, a cell string electrically connected to the source structure and the bit line, a word line electrically connected to the cell string, and a selection line electrically connected to the cell string. Each of the cell strings may include a memory cell and a selection transistor connected in series through a cell plug. Each of the selection lines may be used as a gate electrode of a selection transistor corresponding thereto, and each of the word lines may be used as a gate electrode of a memory cell corresponding thereto.

[0039] In another embodiment, the substrate SUB, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi may be arranged in the same manner as Figure 2 For example, the peripheral circuit structure PC may be disposed on the memory blocks BLK1 to BLKi.

[0040] In another embodiment, Figure 2 Unlike shown, the peripheral circuit structure PC may be disposed on a partial region of the substrate SUB that does not overlap with the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi may be disposed on regions of the substrate SUB that do not overlap with each other.

[0041] Figure 3 is a view showing a cell region and a contact region of a memory device according to an embodiment of the present disclosure. Figure 3is a plan view showing the layout of the cell region CR and the contact region CTR of the memory device 100 .

[0042] refer to Figure 3 , the memory device may include a cell region CR and a contact region CTR. For example, the contact region CTR may extend from the cell region CR in the X direction. Figure 3 Unlike the illustration of FIG. 1 , the contact region CTC may extend from the cell region CR in the Y direction, or may extend in the X direction and the Y direction. In addition, the cell region CR and the contact region CTR may be differently arranged.

[0043] The cell plug CP may be located in the cell region CR. The cell plug CP may be formed in the cell region CR. The contact plug CT may be located in the contact region CTR. The contact plug CT may be formed in the contact region CTR.

[0044] The cell plugs CP may be arranged in the cell region CR along the X direction and the Y direction. Each of the cell plugs CP may extend in the Z direction. Each of the cell plugs CP may include a barrier layer BX, a charge trapping layer CTL formed along the inner wall of the barrier layer BX, a tunnel insulating layer TX formed along the inner wall of the charge trapping layer CTL, a channel layer CH formed along the inner wall of the tunnel insulating layer TX, or a core column CO inside the channel layer CH, or a combination including at least two of the above items. The barrier layer BX and the tunnel insulating layer TX may be formed of an oxide layer. For example, the barrier layer BX and the tunnel insulating layer TX may be formed of a silicon oxide layer or a silicon nitride layer, or a combination thereof. The charge trapping layer CTL may be formed of a nitride layer or a variable resistance material. The channel layer CH may be formed of a conductive layer (e.g., a doped silicon layer). The channel layer CH may be replaced with an electrode structure. The core column CO may be formed of an insulating layer or a conductive layer. Each of the blocking layer BX, the charge trapping layer CTL, the tunnel insulating layer TX, the channel layer CH, and the pillar CO may extend in the Z direction. A cap layer for improving electrical characteristics of a selection transistor included in each cell string may be further formed on the top of the pillar CO.

[0045] The contact plugs CT may be arranged in the contact region CTR along the X direction. Figure 3 Unlike the illustration of FIG. 1 , the contact plugs CT may be arranged in the contact region CTR along the Y direction. Alternatively, some of the contact plugs CT may be arranged along the X direction, while other contact plugs CT may be arranged along the Y direction. Each of the contact plugs CT may extend in the Z direction.

[0046] The spacer SP may be formed on the outer wall of the contact plug CT. The spacer SP may surround the side surface of the contact plug CT. The side wall of the contact plug CT may not be exposed by the spacer SP.

[0047] The number of cell plugs CP and contact plugs CT is not limited to Figure 3 For example, the number of contact plugs CT may vary according to the number of stacked layers included in the first memory block BLK1. In addition, the positions of the cell plugs CP and the contact plugs CT are not limited to Figure 3 , and the cell plug CP and the contact plug CT may be located at various positions as long as the cell plug CP and the contact plug CT include Figure 4A and Figure 4B Features described in .

[0048] Figure 4A and Figure 4B is a view showing a structure of a memory device according to an embodiment of the present disclosure. Figure 4A It is shown along Figure 3 A cross-sectional view of a section taken along line AA′ is shown. Figure 4B yes Figure 4A An enlarged view of A is shown.

[0049] refer to Figure 4A , the memory device 100 may include a stacked structure STK in which the conductive layers CD and the interlayer insulating layers IL are alternately stacked. The stacked structure STK may include conductive layers CD and interlayer insulating layers IL alternately stacked along the Z direction. The stacked structure STK may extend in the X direction and the Y direction. The conductive layer CD may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polycrystalline silicon (poly-Si), or may be formed of a combination of at least two of the above items. The interlayer insulating layer IL may be formed of an oxide layer (e.g., a silicon oxide layer).

[0050] Figure 4A The contact region CTR in the stacked structure STK is shown. In the present disclosure, the contact region CTR may not have any step structure. The number of stacks of the conductive layer CD and the interlayer insulating layer IL included in the stacked structure STK in the contact region CTR may be substantially the same, regardless of the position on the XY plane. The length of the conductive layer CD included in the stacked structure STK in the X direction (or the length of the conductive layer CD in the Y direction) may be substantially the same. For example, the length of any one conductive layer CDa in the X direction and the length of another conductive layer CDb in the X direction may be substantially the same.

[0051] The stacked structure STK may include an opening OP. The opening OP may be formed in the stacked structure STK. The openings OP may correspond to the conductive layers CD included in the stacked structure STK, respectively. The openings OP may be in contact with the top surfaces of the conductive layers CD, respectively. For example, any one opening OPa may be in contact with the top surface of a conductive layer CDa. Each of the openings OP may extend along the Z direction. The opening OP may extend from the conductive layer CD in the Z direction. For example, one opening OPa may extend from a conductive layer CDa in the Z direction. The cross-section of each of the openings OP may have a circular shape, an elliptical shape, or various other shapes.

[0052] The contact plugs CT may be formed in the openings OP, respectively. The contact plugs CT may be in contact with the conductive layers CD, respectively. The contact plugs CT may be electrically connected to the conductive layers CD, respectively. For example, any one contact plug CTa may be in contact with one conductive layer CDa and may be electrically connected to one conductive layer CDa. The contact plugs CT may extend in the openings OP, respectively. The contact plugs CT may extend from the top surface of the conductive layer CD in the Z direction. For example, one contact plug CTa may extend from the top surface of one conductive layer CDa in the Z direction. The contact plugs CT may penetrate at least one conductive layer CD and at least one interlayer insulating layer IL. Each of the contact plugs CT may penetrate a different number of conductive layers CD. For example, Figure 4A The contact plug CTa identified in FIG. 1 may penetrate an additional conductive layer CDb located above one conductive layer CDa, compared to an adjacent contact plug CT penetrating a conductive layer located above the conductive layer CDb. The contact plug CT may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polycrystalline silicon (poly-Si), or may be formed of a combination of at least two of the foregoing items.

[0053] The spacer SP may be formed along the inner wall of the opening OP. The spacer SP may cover the inner wall of the opening OP. The spacer SP may conformally cover the inner wall of the opening OP. For example, any spacer SPa formed in one opening OPa may have substantially the same thickness regardless of the depth of the corresponding opening OPa. The spacer SP may cover the side wall of the contact plug CT. The spacer SP may surround the side surface of the contact plug CT. The spacer SP may be filled with the contact plug CT. For example, the contact plug CT may be formed in a region surrounded by the spacer SP.

[0054] The spacer SP may be formed between the inner wall of the opening OP and the contact plug CT. The spacer SP may allow the contact plug CT to be spaced apart from at least one conductive layer CD and / or the insulating layer IL. For example, one spacer SPa may allow one contact plug CTa to be spaced apart from another conductive layer CDb disposed above one conductive layer CDa. Therefore, each of the contact plugs CT may be electrically connected to the conductive layer CD that becomes the target and electrically isolated from the other conductive layers CD by the spacer SP. The spacer SP may be formed of a material (e.g., an oxide layer, a nitride layer, an oxynitride layer, or an oxide layer doped with a metal) that can insulate the contact plug CT from the conductive layer CD.

[0055] refer to Figure 4B The stack structure STK may include a first sub-stack structure SUB1 including a first conductive layer CD1 and a first interlayer insulating layer IL1, and a second sub-stack structure SUB2 including a second conductive layer CD2 and a second interlayer insulating layer IL2. The second sub-stack structure SUB2 may be disposed on the first sub-stack structure SUB1. Figure 4B , it is shown that each of the first sub-stack structure SUB1 and the second sub-stack structure SUB2 includes a pair of conductive layers CD and interlayer insulating layers IL. However, this is merely an example, and the scope of the present disclosure is not limited thereto. For example, each of the first sub-stack structure SUB1 and the second sub-stack structure SUB2 may include two or more conductive layers and two or more interlayer insulating layers that are alternately stacked. However, the conductive layer CD may be disposed in the uppermost layer of each of the first sub-stack structure SUB1 and the second sub-stack structure SUB2, and the interlayer insulating layer IL may be disposed in the lowermost layer of each of the first sub-stack structure SUB1 and the second sub-stack structure SUB2. Reference will be made later Figure 6 An embodiment is described in which the sub-stack structure includes two or more conductive layers CD and two or more interlayer insulating layers IL.

[0056] refer to Figure 4A and Figure 4B The first sub-stack structure SUB1 and the second sub-stack structure SUB2 penetrated by the contact plug CT (eg, CTa) may contact any one of the conductive layers (eg, Figure 4A The conductive layer CDa) is shown and protrudes upward therefrom.

[0057] refer to Figure 4B, the opening OP may include a first opening OP1, and a second opening OP2 located below the first opening OP1. The first opening OP1 may be located above the second opening OP2 in the Z direction. The second opening OP2 may extend from the first opening OP1 in a downward direction. The second sub-stack structure SUB2 may include the first opening OP1, and the first sub-stack structure SUB1 may include the second opening OP2. The first opening OP1 may penetrate the second sub-stack structure SUB2, and the second opening OP2 may penetrate the first sub-stack structure SUB1. The first opening OP1 and the second opening OP2 are divided only for the convenience of description, and may be components that are not physically isolated from each other.

[0058] Each of the first opening OP1 and the second opening OP2 may have a width at its top end formed to be greater than a width at its bottom end. For example, the bottom end of the first opening OP1 may have a first width WO1, and the top end of the first opening OP1 may have a second width WO2 greater than the first width WO1. In addition, the bottom end of the second opening OP2 may have a first width WO1, and the top end of the second opening OP2 may have a second width WO2 greater than the first width WO1.

[0059] The width of the top end of the second opening OP2 may be greater than the width of the bottom end of the first opening OP1. For example, the top end of the second opening OP2 may have a second width WO2, and the bottom end of the first opening OP1 may have a first width WO1 that is smaller than the second width WO2. That is, the width of the opening OP and its relationship with the depth of the opening OP will be described. For example, when the thickness is measured from the top end to the bottom end of the first opening OP1, the width of the opening OP may decrease (e.g., from WO2 to WO1), but at a specific point (i.e., when transitioning from the first opening OP1 to a subsequent opening (the second opening OP2) located below this one opening), the width of the opening OP may increase again (e.g., from WO1 to WO2). Therefore, the sidewall of the opening OP may have an uneven surface. The inner wall of the opening may be formed to have similar unevenness.

[0060] The opening OP may include a protruding portion protruding toward a direction intersecting the Z direction (e.g., the X direction and the Y direction). The protruding portion PO may protrude into the stacking structure STK. The first opening OP1 may be formed with a protruding portion PO so that the top of the first opening OP1 may be wider than the bottom of the first opening OP1. In addition, the first opening OP1 may be formed with a protruding portion PO so that the top of the first opening OP1 protrudes into the stacking structure STK compared with the bottom of the first opening OP1. Similarly, the second opening OP2 may be formed with a protruding portion PO so that the top of the second opening OP2 may be wider than the bottom of the second opening OP2 and the bottom of the first opening OP1. In addition, the second opening OP2 may be formed with a protruding portion PO so that the top of the second opening OP2 protrudes into the stacking structure STK compared with each of the bottom of the second opening OP2 and the bottom of the first opening OP1. The protruding portion PO may include a side surface having a slope. The cross section of the protruding portion PO may include a right triangle shape. Due to the protruding portion OP, each of the first opening OP1 and the second opening OP2 may include a side wall having a slope. Each of the first opening OP1 and the second opening OP2 may include an inclined surface that becomes closer to the center of the opening OP as the depth of the opening OP increases.

[0061] exist Figure 4B , it is shown that the width of the top end of the first opening OP1 (e.g., WO2) is the same as the width of the top end of the second opening OP2 (e.g., WO2), and the width of the bottom end of the first opening OP1 (e.g., WO1) is the same as the width of the bottom end of the second opening OP2 (e.g., WO1). However, the scope of the present disclosure is not limited to this. For example, the width of the top end of the second opening OP2 may be smaller than the width of the top end of the first opening OP1, and may be larger than the width of the bottom end of the first opening OP1.

[0062] The spacer SP may be formed along the inner wall of the opening OP. The spacer SP may be conformally formed on the inner wall of the opening OP. For example, the shape of the inner wall of the spacer SP may correspond to the shape of the outer wall of the spacer SP. Since the inner wall of the opening has an uneven surface, the inner wall of the spacer SP may also have an uneven surface.

[0063] The outer wall of the spacer SP may contact the inner wall of the stack structure STK exposed by the opening OP. For example, the first surface SS1 of the spacer SP in the second opening OP2 may contact the first surface SI1 of the first interlayer insulating layer IL1. In addition, the second surface SS2 of the spacer SP in the second opening OP2 may contact the first surface SD1 of the first conductive layer CD1.

[0064] A portion of the top surface of the second opening OP2 may be in contact with the bottom surface of the second sub-stack structure SUB2. For example, the third surface SS3, which is the top surface of the spacer SP in the second opening OP2, may be in contact with the second surface SI2, which is the bottom surface of the second interlayer insulating layer IL2. Since the width of the top end of the second opening OP2 (e.g., the second width WO2) is greater than the width of the bottom end of the first opening OP1 (e.g., the first width WO1), the top end of the second opening OP2 may extend to the bottom end of the first opening OP1, and the extension is another portion of the second opening OP2 in contact with the stack structure STK.

[0065] In addition, the interface between the first and second sub-stack structures SUB1 and SUB2 may correspond to the interface between the second opening OP2 and the first opening OP1. The interface between the first and second sub-stack structures SUB1 and SUB2 and the interface between the second opening OP2 and the first opening OP1 may be formed at the same level.

[0066] The contact plug CT may be formed inside the spacer SP. The contact plug CT may fill the remaining portion of the opening OP that is not filled by the spacer SP. The outer wall of the contact plug CT may contact the inner wall of the spacer SP. Since the inner wall of the spacer SP has an uneven surface, the side wall of the contact plug CT may also have an uneven surface. Therefore, the width of the contact plug CT may vary according to the depth of the opening OP. For example, the contact plug CT may have a first width WC1 at a first position, and the contact plug CT may have a second width WC2 greater than the first width WC1 at a second position below the first position.

[0067] The contact plug CT may include a protruding portion PT protruding toward a direction intersecting the Z direction (e.g., the X direction and the Y direction). The protruding portion PT of the contact plug CT may protrude toward the stack structure STK. The protruding portion PT of the contact plug CT may include a side surface having a slope. A cross section of the protruding portion PT may have a right triangle shape. Due to the protruding portion PT, the width of the contact plug CT may vary according to the height when the contact plug CT is measured.

[0068] The inner wall of the spacer SP may contact the side wall of the contact plug CT. For example, extending in the XY plane, the fourth surface SS4 of the inner wall of the spacer SP may contact the first surface SC1 of the outer wall of the contact plug CT. In addition, the fifth surface SS5 in the inner wall of the spacer SP may contact the second surface SC2 of the contact plug CT.

[0069] The protrusion PT of the contact plug CT may be formed to be lower than the protrusion PO of the opening OP in the Z direction. Since the spacer SP is conformally formed on the inner wall of the opening OP, the position of the protrusion PT of the contact plug CT may be lower than the position of the protrusion PO of the opening OP. For example, the top surface of the protrusion PT of the contact plug CT in the second opening OP2 may be lower than the top surface of the protrusion PO included in the second opening OP2. Therefore, the interface between the fourth surface SS4 of the spacer SP and the first surface SC1 of the contact plug CT may be lower than the interface between the third surface SS3 of the spacer SP and the second surface S12 of the second interlayer insulating layer IL2.

[0070] refer to Figure 4A and Figure 4B , since the sidewall of the opening OP includes unevenness, the width of the opening OP is not constantly reduced, but can be repeatedly increased and reduced as the depth of the opening OP increases. Therefore, compared with the existing openings, the difference between the width of the top end of the opening OP and the width of the bottom end of the opening OP can be reduced. For example, compared with the case where the width of the opening decreases as the depth of the opening increases, the width of the opening OP according to the present disclosure can have a smaller difference between its top end and bottom end.

[0071] Furthermore, although the width of each opening varies based on the height at which the opening is measured, the variation can be substantially consistent between each opening. Figure 4A The openings OP shown have different depths in the Z direction, but each opening OP may have substantially the same width at a specific relative height relative to the opening itself, rather than the general Z direction. Therefore, the variation in width or thickness between the openings OP included in the memory device 100 may be small.

[0072] As described above, according to the present disclosure, since the difference between the width of the upper end and the width of the bottom end in each of the openings OP is small, the difference between the width of the upper end and the width of the bottom end in each of the contact plugs CT formed in the openings OP can also be reduced compared to the existing contact plugs. In addition, according to the present disclosure, since the width difference between the openings OP is small, the width difference between the contact plugs CT formed in the openings OP can also be reduced compared to the existing contact plugs.

[0073] When the opening OP has a constant width, the width of the gate line (e.g., the conductive layer CD) included in the memory device 100 penetrated may also be constant. When the gate line (e.g., the conductive layer CD) penetrates with a constant width, it is advantageous for the memory device 100 to control the dispersion of the resistance of the gate line. In addition, various effects obtained by the characteristics described in the present disclosure can be exhibited.

[0074] FIG. 5A to FIG. 5M 2 is a view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure. FIG. 5A to FIG. 5M It is shown along Figure 3 A cross-sectional view of a section taken along line AA′ is shown.

[0075] refer to Figure 5A , a preliminary stacked structure pSTK in which first material layers IL and second material layers SF are alternately stacked may be formed. The preliminary stacked structure pSTK may include a first material layer set MS1 and a second material layer set MS2, each material layer set including at least one first material layer IL and at least one second material layer SF. The second material layer set MS2 may be stacked on the first material layer set MS1. Figure 5A In the embodiment, each of the first material layer set MS1 and the second material layer set MS2 may include a pair of first material layers IL and second material layers SF. However, the present disclosure is not limited thereto, and each of the first material layer set MS1 and the second material layer set MS2 may include two or more pairs of first material layers IL and second material layers SF.

[0076] The first material layer IL may be formed of an insulating material. For example, the first material layer IL may be formed of an oxide layer (e.g., a silicon oxide layer). The second material layer SF may be formed of a material that can be selectively removed in a subsequent process. The second material SF may be formed of a material having an etching selectivity different from that of the first material layer IL. For example, the second material layer SF may be formed of a nitride layer.

[0077] A first hard mask HM1 may be formed on the preliminary stacked structure pSTK. The first hard mask HM1 may cover the first material layer IL at the uppermost end of the preliminary stacked structure pSTK. The first hard mask HM1 may be deposited to have a thickness greater than that of each of the first material layer IL and the second material layer SF. The first hard mask HM1 may be formed of polysilicon.

[0078] A preliminary opening OPP penetrating the first hard mask HM1 may be formed. The preliminary opening OPP may be formed to penetrate the first hard mask HM1 and at least one first material layer IL. For example, the preliminary opening OPP may be formed to expose the second material layer set MS2. Each of the preliminary openings OPP may be formed to have a top end wider than a bottom end. An anisotropic dry etching process may be performed to form the preliminary opening OPP at a designated position.

[0079] refer to Figure 5B, a second hard mask HM2 may be formed on the first hard mask HM1. The second hard mask HM2 may cover the first hard mask HM1 and the preliminary opening OPP. While forming the second hard mask HM2, an overhang (overhang) of the second hard mask HM2 extending to the inner wall of the preliminary opening OPP may appear. However, the second hard mask HM2 may not completely fill the preliminary opening OPP, but may fill a portion of the top of each of the preliminary openings OPP. The second hard mask HM2 may be deposited to have a thickness less than that of the first hard mask HM1. The second hard mask HM2 may be formed of a carbon layer.

[0080] A photoresist PR may be formed on the second hard mask HM2. The photoresist PR may cover the second hard mask HM2. The photoresist PR may be formed of a material having a chemical property changed by light.

[0081] refer to Figure 5C , a portion of the photoresist PR may be removed. For example, a partial region of the photoresist PR may be removed by a photolithography process.

[0082] A portion of the second hard mask HM2 may be exposed through the optical opening pOP, and a portion of the photoresist PR in the optical opening may be removed. The portion of the second hard mask HM2 exposed through the optical opening pOP may be removed through an etching process. As the portion of the second hard mask HM2 is removed, at least one of the preliminary openings OPP may be opened. As at least one preliminary opening OPP is opened, an area of ​​the preliminary stacked structure pSTK may be exposed. For example, a portion of the top surface of the second material layer set MS2 may be exposed through the preliminary opening OPP.

[0083] A first opening OP1 may be formed in the preliminary stack structure pSTK through the preliminary opening OPP. A portion of the second material layer set MS2 exposed through the preliminary opening OPP may be etched. The first opening OP1 may overlap with the bottom of the preliminary opening OPP and may extend from the preliminary opening OPP in a downward direction. The first opening OP1 exposing the first material layer set MS1 may be formed in the second material layer set MS2. The first opening OP1 may be formed in the second material layer set MS2. The first opening OP1 may penetrate the second material layer set MS2. The width of the top end of the first opening OP1 may be greater than the width of the bottom end of the preliminary opening OPP. In addition, the width of the top end of the first opening OP1 may be greater than the width of the bottom end of the first opening OP1. At least one process of anisotropic dry etching, isotropic wet etching, and reactive ion etching may be performed to form the first opening OP1 through the preliminary opening OPP.

[0084] refer to Figure 5D, a protective layer PL may be formed on the inner wall of the preliminary opening OPP and the inner wall of the first opening OP1. While forming the first opening OP1, the protective layer PL may be formed along the sidewall of the first opening OP1 and the sidewall of the preliminary opening OPP. The protective layer PL may cover the sidewall of the first opening OP1, but may not cover the bottom surface of the first opening OP1. The protective layer PL may be formed of a polymer. A byproduct of the etching process generated while forming the first opening OP1 by etching the second material layer set MS2 may be a protective layer PL deposited in the openings (e.g., OPP and OP1). That is, although a separate deposition process for forming the protective layer PL is not performed, a byproduct generated by the first hard mask layer HM1 in the etching process may remain on the sidewall of the first opening OP1, thereby forming the protective layer PL. During the etching process for forming the first opening OP1, the protective layer PL may be formed by controlling the discharge amount of the gas used for etching. For example, during an etching process for forming the first opening OP1 , when an exhaust amount of a source gas for etching is less than or equal to a threshold value, byproducts of the etching process may not be exhausted outside the chamber but may remain on the sidewall of the first opening OP1 .

[0085] refer to Figure 5E When a portion of the photoresist PR is removed by a photolithography process, the width of the optical opening pOP of the photoresist PR may be widened. Also, an etching process may be performed to remove a portion of the second hard mask HM2 exposed by the widened optical opening pOP. Thus, the preliminary opening OPP may be additionally opened. Figure 4A The openings OP shown having different depths from each other may be formed through a step-by-step photolithography process of the photoresist PR and a step-by-step etching process of the second hard mask HM2 .

[0086] First, we will describe FIG. 5A to FIG. 5M , and the opening OP shown on the far right in the preliminary stacked structure pSTK. A first region P1 extending from the preliminary opening OPP and the first opening OP 1 in the preliminary stacked structure pSTK may be formed. The first region P1 may be opened by etching the second material layer SF of the first material layer set MS1 exposed through the first opening OP 1. For example, the second material layer SF of the first material layer set MS1 may be exposed through the bottom surface of the first opening OP1, and the exposed second material layer SF may be etched. The width of the first region P1 may be constant. The width of the top end of the first region P1 may be equal to the width of the first material layer set MS1 exposed due to the non-formation of the protective layer PL. An anisotropic dry etching process or a reactive ion etching process may be performed to form the first region P1 through the first opening OP 1.

[0087] refer to Fig. 5F, a second opening OP2 further extending than the first region P1 may be formed in the preliminary stack structure pSTK. The depth of the first region P1 may be extended by etching the first material layer IL of the first material layer set MS1 through the first region P1. In addition, the width of the first region P1 may be extended by etching the second material layer SF of the first material layer set MS1 through the first region P1. While etching the first material layer IL through the first region P1, the second material layer SF may also be partially etched by etching selectivity. Therefore, the second opening OP2 may have a width extended compared to the first region P1, and the width of the top end of the second opening OP2 may be greater than the width of the bottom end of the first opening OP1.

[0088] The second opening OP2 may be formed in the first material layer set MS1. The second opening OP2 may penetrate the first material layer set MS1. The second opening OP2 may overlap the first opening OP1 and the preliminary opening OPP. The second opening OP2 may extend from the preliminary opening OPP and the first opening OP1 in a downward direction. An anisotropic etching process may be performed to form the second opening OP2 by extending the first region P1.

[0089] refer to FIG. 5D to FIG. 5F , while the second opening OP2 is formed through the first opening OP1, the increase in the width of the first opening OP1 may be partially suppressed by the protective layer PL. While the material layers SF and IL included in the preliminary stacked structure pSTK are etched through the first opening OP1, the protective layer PL may protect the sidewalls of the first opening OP1. For example, while the second opening OP2 is formed through the first opening OP1, the width of the first opening OP1 may be constantly maintained. Therefore, the width of the bottom end of the first opening OP1 may be smaller than the width of the top end of the second opening OP2.

[0090] refer to Figure 5G , a protective layer PL may be formed on the inner wall of the second opening OP2. While forming the second opening OP2, the protective layer PL may be formed along the sidewall of the second opening OP2. The protective layer PL may cover the sidewall of the second opening OP2, but may not cover the bottom surface of the second opening OP2. The protective layer PL may be formed of a polymer. For example, a byproduct of an etching process generated while forming the second opening OP2 by etching the first material layer set MS1 may be deposited in the second opening OP2 as a protective layer PL. In addition to the sidewall of the second opening OP2, the byproduct generated while forming the second opening OP2 may even be deposited on the sidewall of the preliminary opening OPP or the sidewall of the first opening OP1.

[0091] As reference Figure 5E The description will be located at FIG. 5A to FIG. 5MThe opening OP on the left side of the rightmost opening in the preliminary opening OPP. The first region P1′ extending from the preliminary opening OPP may be formed in the preliminary stacked structure pSTK. The first region P1′ may be opened by etching the second material layer SF of the second material layer set MS2 exposed by the preliminary opening OPP. The width of the first region P1′ extending from the preliminary opening OPP may be greater than the width of the first region P1 extending from the first opening OP1.

[0092] refer to Fig. 5F , a first opening OP1 further extending than the first region P1′ may be formed in the preliminary stacked structure pSTK. The first opening OP1 may be formed in the second material layer set MS2. The depth of the first region P1′ may be extended by etching the first material layer IL of the second material layer set MS2 through the first region P1′. In addition, the width of the first region P1′ may be extended by etching the second material layer SF of the second material layer set MS2 through the first region P1′. Since the width of the first opening OP1 is extended compared to the first region P1′, the width of the top end of the first opening OP1 may be greater than the width of the bottom end of the preliminary opening OPP.

[0093] refer to Figure 5G , a protection layer PL may be formed on the inner wall of the first opening OP1. Figure 5D The description of the protective layer PL can be equally applied to the description of the protective layer PL. FIG. 5A to FIG. 5M The rightmost opening OP.

[0094] refer to Figure 5H , a third opening OP3 may be formed in the preliminary stacked structure pSTK. The third opening OP3 may be formed by etching a portion of the preliminary stacked structure pSTK through the preliminary opening OPP, the first opening OP1, and the second opening OP2. The third opening OP3 may extend from the second opening OP2 in a downward direction. While forming the third opening OP3, the sidewalls of the preliminary opening OPP, the first opening OP1, and the second opening OP2 may be protected by the protective layer PL. It is understood that the preliminary opening OPP, the first opening OP1, the second opening OP2, and the third opening OP3 are included in the opening OP.

[0095] refer to Fig.5I When the third opening OP3 is formed, a protection layer PL may be formed along the sidewall of the third opening OP3. The protection layer PL may extend along the inner wall of the opening OP. The protection layer PL may cover the sidewall of the opening OP. The protection layer PL may not cover the bottom surface of the opening OP.

[0096] refer to Figure 5J, the photoresist PR and the second hard mask layer HM2 may be removed, and the protection layer PL in the opening OP may be removed. For example, the protection layer PL may be removed through the opening OP by an isotropic wet etching process. As the protection layer PL is removed, the sidewall of the opening OP may be exposed.

[0097] refer to Figure 5K , a spacer layer SPL may be formed along the inner wall and the bottom surface of the opening OP. For example, the spacer layer SPL may be formed along the surface of the inner wall and the bottom surface of the opening OP. The preliminary stacked structure pSTK may not be exposed to the outside. The spacer layer SPL may be formed of an insulating layer (e.g., an oxide layer, a nitride layer, an oxynitride layer, or an oxide layer doped with a metal).

[0098] A sacrificial post FP may be formed inside the spacer layer SPL. The sacrificial post FP may fill the opening OP. The spacer layer SPL may surround the sidewall and bottom surface of the sacrificial post FP. The sacrificial post FP may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si) or polycrystalline silicon (poly-Si), or may be formed of a combination of at least two of the above items.

[0099] refer to Figure 5L , the second material layer SF of the preliminary stacked structure pSTK can be replaced with the third material layer CD. While the opening OP is filled with the spacer layer SPL and the sacrificial column FP, the second material layer SF can be removed and the third material layer CD can be filled. As the third material layer CD is filled between the first material layers IL, a stacked structure STK can be formed. The stacked structure STK may include alternately stacked first material layers IL and third material layers CD. The third material layer CD may be formed of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si) or polycrystalline silicon (poly-Si), or may be formed of a combination of at least two of the above items.

[0100] After replacing the second material layer SF with the third material layer CD, the sacrificial pillar FP may be removed. As the sacrificial pillar FP is removed, a pillar opening PP may be formed in the opening OP.

[0101] refer to Figure 5M , a portion of each of the spacer layers SPL may be removed. The bottom surface of the spacer layer SPL may be etched. For example, the bottom surface of the spacer layer SPL may be etched through the pillar opening PP. As the bottom surface of the spacer layer SPL is etched, a spacer SP exposing the third material layer CD may be formed. The spacer SP may be formed along the sidewall of the opening OP. Since the spacer SP does not cover the bottom surface of the opening OP, the third material layer CD may be exposed.

[0102] Contact plugs CT may be formed in the openings OP. The contact plugs CT may respectively make contact with the third material layers CD exposed through the openings OP. The contact plugs CT may fill the spacers SP.

[0103] Figure 6 is a view showing a structure of a memory device according to another embodiment of the present disclosure.

[0104] When the general Figure 6 and Figure 4A In comparison, each of the first sub-stacked structure SUB1 and the second sub-stacked structure SUB2 may include two or more pairs of conductive layers CD and interlayer insulating layers IL. The opening OP may include a first opening OP1 located in the second sub-stacked structure SUB2 and a second opening OP2 located in the first sub-stacked structure SUB1. The width of the top end of the second opening OP2 may be greater than the width of the bottom end of the first opening OP1. Similar to Figure 6 , each of the first sub-stack structure SUB1 and the second sub-stack structure SUB2 may include three or more pairs of the conductive layer CD and the interlayer insulating layer IL.

[0105] Figure 7 is a diagram showing a memory card system to which the memory device of the present disclosure is applied.

[0106] refer to Figure 7 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0107] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control programming, reading, or erasing operations, or may control background operations of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0108] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. Exemplarily, the controller 3100 can communicate with an external device through at least one of various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a high-speed PCI (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced mini disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication protocols mentioned above.

[0109] The memory device 3200 may include a memory unit and may be configured to Figure 1 The memory devices 100 shown are identical.

[0110] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a universal flash storage (UFS).

[0111] Figure 8 is a diagram showing a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0112] refer to Figure 8 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0113] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. Exemplarily, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one interface, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0114] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be configured to Figure 1 The illustrated memory devices 100 are identical. A plurality of memory devices 4221 to 422n may communicate with a controller 4210 via channels CH1 to CHn.

[0115] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive power input from the host 4100 and may be charged. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 may provide power to the SSD 4200. Exemplarily, the auxiliary power supply 4230 may be located in the SSD 4200, or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard, and may provide auxiliary power to the SSD 4200.

[0116] The buffer memory 4240 may operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4220 to 422n. The buffer memory 4240 may include a volatile memory (such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM) or a nonvolatile memory (such as FRAM, ReRAM, STT-MRAM, and PRAM).

[0117] According to the present disclosure, the width difference between the top and bottom ends of each of the contact plugs included in the memory device is reduced so that each contact plug can have a constant width. Therefore, the operational reliability of the memory device can be improved.

[0118] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes may be made therein in form and details without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0119] In the above-described embodiments, all steps may be selectively performed, or some steps may be performed, and steps may be omitted. In each embodiment, the steps do not have to be performed in the order described, and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be clear to those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0120] Meanwhile, exemplary embodiments of the present disclosure have been described in the accompanying drawings and the specification. Although specific terms are used herein, these terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and there may be many changes within the spirit and scope of the present disclosure. It should be clear to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure.

Claims

1. A memory device, comprising: A stacked structure comprising a plurality of conductive layers and a plurality of interlayer insulating layers alternately stacked along a first direction; an opening, located in the stacked structure, extending from at least one conductive layer of the plurality of conductive layers in the first direction; as well as a contact plug located in the opening, The opening includes a protruding portion protruding in a second direction, and the second direction intersects the first direction. 2 . The memory device of claim 1 , wherein the opening comprises a first opening and a second opening, the second opening being located below the first opening. 3 . The memory device of claim 2 , wherein a width of a top end of the second opening is greater than a width of a bottom end of the first opening. 4 . The memory device of claim 2 , wherein widths of respective top ends of the first opening and the second opening are greater than widths of respective bottom ends of the first opening and the second opening.

5. The memory device according to claim 2, wherein: Due to the protruding portion, respective top ends of the first opening and the second opening protrude into the stack structure compared with respective bottom surfaces of the first opening and the second opening.

6. The memory device of claim 2 , wherein the stacked structure comprises a first sub-stacked structure and a second sub-stacked structure, the first sub-stacked structure being located on top of the at least one conductive layer, the first sub-stacked structure comprising a first conductive layer and a first interlayer insulating layer, the first conductive layer being located on top of the first interlayer insulating layer, the second sub-stacked structure being located on top of the first sub-stacked structure, the second sub-stacked structure comprising a second conductive layer and a second interlayer insulating layer, the second conductive layer being located on top of the second interlayer insulating layer, and wherein the second sub-stack structure includes the first opening, and The first sub-stack structure includes the second opening. 7 . The memory device of claim 6 , wherein an interface between the first sub-stack structure and the second sub-stack structure corresponds to an interface between the second opening and the first opening. 8 . The memory device of claim 6 , wherein a portion of a top surface of the second opening contacts a bottom surface of the second interlayer insulating layer. 9 . The memory device of claim 1 , further comprising a spacer formed along an inner wall of the opening. 10 . The memory device of claim 9 , wherein the spacer covers a sidewall of the contact plug. 11 . The memory device of claim 9 , wherein the spacer allows the contact plug to be spaced apart from a conductive layer and an interlayer insulating layer located above the at least one conductive layer among the plurality of conductive layers and the plurality of interlayer insulating layers. 12 . The memory device of claim 1 , wherein the contact plug contacts a top surface of the at least one conductive layer. 13 . The memory device of claim 1 , wherein the contact plug includes a protruding portion protruding in the second direction.

14. The memory device of claim 1, wherein a sidewall of the contact plug comprises an uneven surface. 15 . The memory device of claim 1 , wherein a width of the contact plug at a first location is smaller than a width of the contact plug at a second location, the second location being located below the first location.

16. A method of manufacturing a memory device, the method comprising: forming a preliminary stacking structure, the preliminary stacking structure comprising a first material layer set and a second material layer set, the first material layer set and the second material layer set each comprising at least one first material layer and at least one second material layer, the first material layer set and the second material layer set being stacked on each other; forming a first opening in the second material layer set exposing the first material layer set; forming a protective layer on an inner wall of the first opening while the first opening is being formed; as well as forming a second opening in the first material layer exposed by the first opening; The width of the top end of the second opening is greater than the width of the bottom end of the first opening.

17. The method according to claim 16, wherein forming the protection layer on the inner wall of the first opening comprises: The protective layer is formed by allowing byproducts generated while the second material layer set is being etched to remain on the inner wall of the first opening.

18. The method of claim 16, wherein forming the second opening comprises: opening the first region by etching the second material layer of the first material layer set exposed through the first opening; extending the depth of the first region by etching a first material layer of the first material layer set through the first region; as well as The width of the first region is extended by etching the second material layer of the first material layer set through the first region.

19. The method of claim 18, wherein a width of the first opening is maintained by the protective layer while the second opening is being formed.

20. The method of claim 16, further comprising: After forming the openings including the first opening and the second opening, forming a spacer layer along the inner wall and bottom surface of the opening; filling the spacer layer with sacrificial posts; replacing the second material layer with a third material layer; as well as A contact plug is formed in the opening, the contact plug contacting at least one of the third material layers.

21. The method according to claim 20, wherein forming the contact plug comprises: removing the sacrificial post in the opening; forming a spacer by etching a portion of the spacer layer to expose the third material layer; as well as The contact plug is formed in the spacer.

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