Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to solve the problem of charge diffusion in a channel structure. The semiconductor structure comprises isolation structures and channel structures which are alternately arranged in the second direction, and each channel structure comprises two charge storage parts arranged in the third direction at intervals and a common layer located between the two charge storage parts. The diffusion of charges in the charge storage parts of the channel structures to the adjacent channel structures in the second direction can be effectively inhibited. The charge storage part comprises a plurality of sub-charge storage parts which are arranged at intervals in the first direction, a gate dielectric layer is arranged between every two adjacent sub-charge storage parts in the first direction, and charges stored in the sub-charge storage parts are isolated from other sub-charge storage parts corresponding to different gate line layers; the diffusion of charges in the sub-charge storage unit can be suppressed. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] As the feature size of the memory cell approaches the process lower limit, the planar process and manufacturing technology become challenging and costly, which causes the storage density of 2D or planar NAND flash memory to approach the upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases the storage density by arranging the memory cells three-dimensionally on the substrate.

[0003] As the number of stacked layers of the storage stack structure in the semiconductor structure continues to increase, the thickness of the gate dielectric layer and the gate line layer also decreases, resulting in enhanced mutual influence between the various storage units and diffusion of charges in the channel structure, thereby affecting the storage performance of the semiconductor structure. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor structure and a method for preparing the same, aiming to solve the problem of charge diffusion in a channel structure.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] On the one hand, a semiconductor structure is provided. The semiconductor structure includes a storage stack structure and an isolation structure and a channel structure alternately arranged along a second direction. The storage stack structure includes a gate line layer and a gate dielectric layer alternately stacked along a first direction. The isolation structure and the channel structure both penetrate the storage stack structure; the second direction is perpendicular to the first direction. The channel structure includes two charge storage parts spaced apart in a third direction and a common layer located between the two charge storage parts; the charge storage part includes a plurality of sub-charge storage parts spaced apart in the first direction, and in the first direction, each adjacent two sub-charge storage parts are spaced apart by the gate dielectric layer; the common layer includes a tunneling layer and a channel layer, and the tunneling layer is located between the channel layer and the charge storage part; wherein the third direction is perpendicular to the first direction, and the third direction intersects with the second direction.

[0007] The semiconductor structure, gate line layer and channel structure provided in the above-mentioned embodiment of the present application can be used to form a storage cell string. Wherein, the channel structure includes two charge storage parts spaced apart in the third direction and a common layer located between the two charge storage parts. One charge storage part can be used to form a storage cell string, and one channel structure includes two charge storage parts. Therefore, one channel structure can be used to form two storage cell strings, thereby increasing the number of storage cell strings and thus improving the storage density of the semiconductor structure. The charge storage part includes a plurality of sub-charge storage parts spaced apart in the first direction, and a gate dielectric layer is spaced between each two adjacent sub-charge storage parts. Therefore, the two adjacent sub-charge storage parts in the first direction are isolated from each other, so that the charge can be diffused from one sub-charge storage part to another adjacent sub-charge storage part.

[0008] In some embodiments, the channel structure includes two first planes arranged opposite to each other in the second direction and two second planes arranged opposite to each other in the third direction, wherein both sides of the first plane in the second direction are respectively connected to the two second planes, and both sides of the second plane in the third direction are respectively connected to the two first planes.

[0009] In some embodiments, an orthographic projection of the channel structure in the first direction is a rectangle.

[0010] In some embodiments, a width of the channel structure in the third direction is greater than a width of the channel structure in the second direction.

[0011] In some embodiments, the width of the isolation structure in the third direction is smaller than the width of the channel structure in the third direction, the isolation structure is opposite to the common layer in the second direction, and the charge storage unit is staggered with the isolation structure in the second direction.

[0012] In some embodiments, the channel structure further includes: an insulating layer surrounding the charge storage portion and the common layer.

[0013] In some embodiments, the semiconductor structure further includes: a high dielectric constant layer, wherein the high dielectric constant layer is located between the channel structure and the isolation structure, and the high dielectric constant layer surrounds the channel structure.

[0014] In some other embodiments, the high dielectric constant layer is located between the gate line layer and the gate dielectric layer, and between the gate line layer and the channel structure.

[0015] In some embodiments, the common layer further includes a supporting portion, and the channel layer surrounds the supporting portion.

[0016] In another aspect, a method for preparing a semiconductor structure is provided, comprising:

[0017] forming a stacked structure on one side of the substrate, the stacked structure comprising gate replacement layers and gate dielectric layers alternately stacked along a first direction;

[0018] An isolation structure and a channel structure are formed; wherein the isolation structure and the channel structure are alternately arranged along a second direction and both penetrate the stacked structure, and the second direction is perpendicular to the first direction; the channel structure includes two charge storage parts spaced apart in a third direction and a common layer located between the two charge storage parts; the charge storage part includes a plurality of sub-charge storage parts spaced apart in the first direction, and in the first direction, each adjacent two sub-charge storage parts are spaced apart by the gate dielectric layer; the common layer includes a tunneling layer and a channel layer, and the tunneling layer is located between the channel layer and the charge storage part; wherein the third direction is perpendicular to the first direction, and the third direction intersects with the second direction.

[0019] In some embodiments, forming the isolation structure and the channel structure includes:

[0020] forming a first isolation trench, wherein the first isolation trench penetrates the stacked structure and extends along the second direction;

[0021] forming a plurality of dielectric portions spaced apart along the second direction in the first isolation groove to divide the first isolation groove into a plurality of channel holes spaced apart along the second direction;

[0022] forming an initial charge storage layer in the channel hole;

[0023] removing the initial charge storage layer on the dielectric portion to form two charge storage portions oppositely disposed along a second direction in the channel hole;

[0024] The tunnel layer and the channel layer are sequentially formed in the channel hole.

[0025] In some embodiments, before sequentially forming the tunnel layer and the channel layer in the channel hole, the method further includes:

[0026] A portion of the initial charge storage layer located on the gate dielectric layer is removed to form a plurality of sub-charge storage portions.

[0027] In some embodiments, before forming the initial charge storage layer in the channel hole, the method further includes:

[0028] Removing a portion of the gate replacement layer through the channel hole to form two recess groups that are arranged opposite to each other in the third direction and connected to the channel hole, wherein the recess group includes a plurality of recess portions that are spaced apart in the first direction;

[0029] When the initial charge storage layer is formed in the channel hole, a portion of the initial charge storage layer is located in the plurality of recessed portions.

[0030] In some embodiments, the initial charge storage layer on the gate dielectric layer and the initial charge storage layer on the dielectric portion are removed simultaneously.

[0031] In some embodiments, before forming the initial charge storage layer in the channel hole, the method further includes:

[0032] An insulating layer is formed in the channel hole.

[0033] In some embodiments, forming a plurality of dielectric portions spaced apart along the first direction in the first isolation trench to separate the first isolation trench into a plurality of channel holes spaced apart along the first direction includes:

[0034] Filling a sacrificial medium in the first isolation groove;

[0035] The sacrificial dielectric in a plurality of channel regions spaced apart along the second direction in the first isolation trench is removed to form a plurality of dielectric portions spaced apart along the second direction.

[0036] In some embodiments, the sacrificial dielectric includes one or more of polysilicon, silicon carbide, or aluminum oxide.

[0037] In some embodiments, before forming the initial charge storage layer in the channel hole, the method further includes:

[0038] A high dielectric constant layer is formed in the channel hole.

[0039] In some embodiments, after sequentially forming the tunnel layer and the channel layer in the channel hole, the method further includes:

[0040] removing the dielectric portion to form a second isolation trench;

[0041] replacing the gate replacement layer with a gate line layer via the second isolation trench;

[0042] The second isolation trench is filled with an insulating material to form an isolation structure.

[0043] In some embodiments, replacing the gate replacement layer with a gate line layer via the second isolation trench comprises:

[0044] removing the gate replacement layer to form a replacement gap;

[0045] forming the gate line layer in the replacement gap;

[0046] Before forming the gate line layer in the replacement gap, the method further includes:

[0047] A high dielectric constant layer is formed in the replacement gap.

[0048] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor structure provided in the above embodiments of the present application can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0050] Figure 1 is a schematic diagram of a three-dimensional structure of a three-dimensional memory according to some embodiments;

[0051] Figure 2 is a cross-sectional view of a three-dimensional memory according to some embodiments;

[0052] Figure 3 for Figure 1 A cross-sectional view of a memory cell string in the three-dimensional memory along the section line AA' shown;

[0053] Figure 4 is the equivalent circuit diagram of the storage unit string;

[0054] Figure 5 is a schematic cross-sectional view of a semiconductor structure according to some embodiments;

[0055] Figure 6 for Figure 5 A partial enlarged view of the middle A;

[0056] Figure 7 is a structural diagram of a semiconductor structure according to some embodiments;

[0057] Figure 8 for Figure 7 Cross-section along the BB direction;

[0058] Fig. 9is a structural diagram of a semiconductor structure according to some embodiments;

[0059] Fig.10 for Fig. 9 Cross-section view in the CC direction;

[0060] Fig.11A The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 1 ;

[0061] Fig. 11B The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 2 ;

[0062] Fig. 11C The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 3 ;

[0063] Fig.11D The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 4 ;

[0064] Fig.11E The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 5 ;

[0065] Fig.11F The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 6 ;

[0066] Fig.11G The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 7 ;

[0067] Fig.11H The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 8 ;

[0068] Fig.11I The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 9 ;

[0069] Fig.11J The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 10 ;

[0070] Figure 11K The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 10 one;

[0071] Fig.11L The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 10 two;

[0072] Fig.11M The steps of the method for preparing a semiconductor structure according to some embodiments are as follows: Figure 10 three;

[0073] Fig.12 The process of the method for preparing the semiconductor structure of some embodiments is as follows Figure 1 ;

[0074] Fig.13 The process of the method for preparing the semiconductor structure of some embodiments is as follows Figure 2 ;

[0075] Fig.14 The process of the method for preparing the semiconductor structure of some embodiments is as follows Figure 3 ;

[0076] Fig.15 The process of the method for preparing the semiconductor structure of some embodiments is as follows Figure 4 ;

[0077] Fig.16 is a block diagram of a storage system according to some embodiments;

[0078] Fig.17 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0079] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0080] In the description of the present application, it should be understood that the terms "upper", "lower", "left", "right", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0081] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0082] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0083] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments invented here are not necessarily limited to the contents of this document.

[0084] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0085] In the context of this application, the meanings of “on” and “over” should be interpreted in the broadest manner, so that “on” not only means “directly on something”, but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” not only means “over” something, but also includes the meaning of “over” something without intervening features or layers therebetween (i.e., directly on something).

[0086] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0087] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0088] The term "three-dimensional memory" refers to a semiconductor structure formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0089] Figure 1 A schematic diagram of a three-dimensional structure of a three-dimensional memory provided in some embodiments of the present application, Figure 2 is a cross-sectional view of a three-dimensional memory. Figure 3 for Figure 1 A cross-sectional view of a storage unit string of the three-dimensional memory along the section line AA', Figure 4 for Figure 3 Equivalent circuit diagram of the storage cell string in .

[0090] It should be noted that in Figure 1 and Figure 2 In the figure, the three-dimensional memory 10 extends in the YZ plane, the first direction X is perpendicular to the YZ plane, and the second direction Y and the third direction Z are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (for example, the plane where the source layer SL is located): the second direction Y is, for example, the extension direction of the word line WL, and the third direction Z is, for example, the extension direction of the bit line BL. The direction indicated by the arrow and the opposite direction thereof can be considered to be the same direction. The above definition of direction is the same in all drawings in this specification.

[0091] As used in this application, whether a component (e.g., layer, structure, or device) is "on," "above," or "below" another component (e.g., layer, structure, or device) of a semiconductor structure (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor structure in a first direction X when the substrate or source layer is located in the lowest plane of the semiconductor structure in the first direction X. The same concept is applied to describe spatial relationships throughout the content of this application.

[0092] In order to more clearly illustrate the structure of the device, Figure 2 In the figure, the view of the array area CA and the view of the step area SS are shown. The view of the array area CA is based on the left coordinate system, and the view of the step area SS is based on the right coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Z direction, and the view of the step area SS shows the cross-sectional structure along the Y direction.

[0093] See also Figure 1 and Figure 2 Some embodiments of the present application provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200, a source layer SL coupled to the semiconductor structure 200, and a peripheral device 100 coupled to the semiconductor structure 200. The peripheral device 100 may be disposed on a side of the semiconductor structure 200 away from the source layer SL.

[0094] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0095] The semiconductor structure 200 may include memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 400 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400 .

[0096] Specifically, see Figure 3 and Figure 4 , the memory cell string 400 may include a plurality of transistors T, a transistor T (eg Figure 4 The transistors T1 to T6 in the figure can be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (for example, each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor.

[0097] It should be noted that Figure 1 to Figure 4 The number of transistors is only illustrative. The storage cell string of the three-dimensional memory provided in the embodiment of the present application may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0098] Further, along the first direction X, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source end channel in the memory cell string 400. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain end channel in the memory cell string 400. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word lines WL0, word lines WL1, word lines WL2, and word lines WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (for example, transistor T) in the memory cell string 400 can be completed.

[0099] Continue to see Figure 1 and Figure 2 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., a bit line BL) of the memory cell string 400, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

[0100] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292, the contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0101] The peripheral device 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array device. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0102] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0103] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0104] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The material of the second interconnect conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0105] The peripheral interconnect layer 130 may be coupled to the array interconnect layer 290, so that the semiconductor structure 200 and the peripheral device 100 may be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the peripheral device 100 may be coupled to the memory cell string 400 in the semiconductor structure 200, so as to realize the transmission of electrical signals between the peripheral circuit and the memory cell string 400. In some possible implementations, a bonding interface 500 may be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 may be bonded and coupled to each other through the bonding interface 500.

[0106] The semiconductor structure 200 provided in the embodiment of the present application can be used as a complete three-dimensional memory 10, or as a part of the three-dimensional memory 10. Exemplarily, the three-dimensional memory 10 may include the semiconductor structure 200 and the peripheral device 100 as described above, wherein the semiconductor structure 200 is electrically connected to the peripheral device 100.

[0107] Figure 5 is a schematic cross-sectional view of a semiconductor structure according to some embodiments. Figure 5 The present application provides a semiconductor structure 200 , which includes a storage stack structure 300 , a channel structure 600 and an isolation structure 700 .

[0108] In some embodiments, the storage stack structure 300 may be disposed on the source layer SL (eg Figure 2 shown).

[0109] Figure 6 for Figure 5 A partial enlarged view of the middle A. Figure 7 is a structural diagram of a semiconductor structure according to some embodiments, Figure 8 for Figure 7 Cross-sectional view along the BB direction.

[0110] Please refer to Figure 8 The storage stack structure 300 includes gate line layers 310 and gate dielectric layers 320 alternately stacked along a first direction X. The storage stack structure 300 may include multiple gate line layers 310 and multiple gate dielectric layers 320. Figure 8 Only two gate line layers 310 and one gate dielectric layer 320 are shown.

[0111] In some examples, the first direction X may be perpendicular to the gate dielectric layer 320. “Vertical” includes absolutely perpendicular and approximately perpendicular, and the acceptable deviation range of approximately perpendicular may be, for example, within 5°.

[0112] In some embodiments, the gate line layer 310 may be made of a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide. The gate dielectric layer 320 may be made of an insulating material, such as at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0113] The channel structure 600 may penetrate the memory stack structure 300 in the first direction X. In this case, the channel structure 600 may pass through a plurality of gate line layers 310 and a plurality of gate dielectric layers 320 .

[0114] Please refer to Figures 6 to 8 The channel structure 600 may include two charge storage units 610 spaced apart in the third direction Z and a common layer 620 between the two charge storage units 610. The charge storage unit 610 is used to store electrons so that the storage unit has a corresponding threshold voltage. For example, the charge storage unit 610 may include at least one of silicon nitride, silicon oxynitride, silicon, and metal oxide.

[0115] The channel structure 600 may include two charge storage units 610 and a common layer 620. The two charge storage units 610 may share the common layer 620, thereby increasing the number of charge storage units 610 in the channel structure 600. One charge storage unit 610 may be used to form one storage cell string 400. Therefore, by providing two charge storage units 610 in the channel structure 600, the number of storage cell strings 400 in the channel structure 600 may be increased, thereby increasing the storage density of the semiconductor structure 200.

[0116] In addition, the two charge storage units 610 are respectively located on two opposite sides of the common layer 620 in the third direction Z, while no charge storage unit 610 is provided on two opposite sides of the common layer 620 in the second direction Y. This can reduce the size of the channel structure 600 in the second direction Y, thereby increasing the density of the channel structure 600, and further increasing the storage density of the semiconductor structure 200.

[0117] For example, the second direction Y and the third direction Z may be parallel to the gate dielectric layer 320. Here, “parallel” includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be within 5°. At this time, the second direction Y and the third direction Z are parallel to the gate dielectric layer 320.

[0118] For example, the second direction Y and the third direction Z are perpendicular.

[0119] Please refer again Figure 8The charge storage unit 610 includes a plurality of sub-charge storage units 611 arranged at intervals in the first direction X, wherein the plurality of sub-charge storage units 611 in one charge storage unit 610 may be arranged corresponding to the multi-layer gate line layer 310, respectively, wherein "corresponding" may be understood as: a sub-charge storage unit 611 covers at least a portion of a gate line layer 310 when projected in a direction parallel to the third direction Z. The direction parallel to the third direction Z may be a direction parallel to the gate line layer 310 and pointing to the gate line layer 310.

[0120] At this time, in the first direction X, a gate dielectric layer 320 is spaced between every two adjacent sub-charge storage parts 611 .

[0121] In which, in a channel structure 600, a sub-charge storage unit 611 in a charge storage unit 610 can be overlapped with a sub-charge storage unit 611 in another charge storage unit 610. At this time, the orthographic projection of a sub-charge storage unit 611 in one charge storage unit 610 in the third direction Z and the orthographic projection of a sub-charge storage unit 611 in another charge storage unit 610 in the third direction Z can cover the same gate line layer 310.

[0122] Among them, since the two adjacent sub-charge storage units 611 in the first direction X are arranged at intervals, the diffusion of charges in the sub-charge storage unit 611 in the first direction X can be suppressed, which is conducive to forming a uniform electric potential field at the sub-charge storage unit 611, thereby improving the storage reliability of the sub-charge storage unit 611.

[0123] In addition, a sub-charge storage unit 611 can form a transistor T with its corresponding gate line layer 310 and its corresponding common layer. In the related art, a sub-charge storage unit 611 in a transistor T can store at most 3 bytes. Since the two adjacent sub-charge storage units 611 in the first direction X are isolated from each other, the diffusion of charges is suppressed. Therefore, in the present application, more bytes can be stored in a sub-charge storage unit 611. For example, 4 or 5 bytes can be stored in a sub-charge storage unit 611, and thus the number of bytes that can be stored in a channel structure 600 is more, thereby improving the storage density of a semiconductor structure.

[0124] Among them, when one sub-charge storage unit 611 can store 5 bytes, the above-mentioned semiconductor structure 200 can be applied to a PLC (Penta-level cell, five-layer storage) memory. When one sub-charge storage unit 611 can store 4 sub-nodes, the above-mentioned semiconductor structure 200 can be applied to a QLC (Quad-Level Cel, four-layer storage) memory.

[0125] For example, the sub-charge storage unit 611 may include at least one of silicon nitride, silicon oxynitride, silicon, and metal oxide.

[0126] Please refer again Figure 5 The semiconductor structure 200 may further include an isolation structure 700, which penetrates the memory stack structure 300 in the first direction X. The isolation structure 700 is located between two adjacent channel structures 600 in the second direction Y, that is, along the second direction Y, the isolation structure 700 and the channel structure 600 are alternately arranged.

[0127] The isolation structure 700 is made of insulating material, so that the two channel structures 600 adjacent to each other in the second direction Y can be electrically insulated, thereby reducing the influence between the two channel structures 600 adjacent to each other in the second direction Y.

[0128] As an example, the isolation structure 700 may include at least one of an oxide and a high dielectric constant insulating material.

[0129] Reference Figure 6 In the above implementation, the width H1 of the isolation structure 700 in the third direction Z is smaller than the width H2 of the channel structure 600 in the third direction Z.

[0130] For example, the isolation structure 700 is opposite to the common layer 620 in the second direction Y, and the charge storage unit 610 can be staggered with the isolation structure 700 in the second direction Y, so that the width H1 of the isolation structure 700 in the third direction Z is smaller than the width H2 of the channel structure 600 in the third direction Z.

[0131] The isolation structure 700 is opposite to the common layer 620 in the second direction Y. At this time, the orthographic projection of the isolation structure 700 in the second direction Y can cover at least a portion of the common layer 620. At this time, the width of the isolation structure 700 in the third direction Z can be less than or equal to the width of the common layer 620 in the third direction Z.

[0132] The charge storage unit 610 may be staggered with the isolation structure 700 in the second direction Y. At this time, the orthographic projection of the charge storage unit 610 in the second direction Y does not overlap with the orthographic projection of the isolation structure 700 in the second direction Y. The charge storage unit 610 corresponds to the gate line layer 310 in the second direction Y, and the charge storage unit 610 also corresponds to the gate line layer 310 in the third direction Z, thereby increasing the detection area of ​​the charge storage unit 610 and the gate line layer 310 and improving the storage speed of the charge storage unit 610.

[0133] Continue to refer to Figure 6 In the above implementation, the common layer 620 may include a tunnel layer 621 and a channel layer 622 .

[0134] In some examples, the channel layer 622 may be columnar, and the channel layer 622 extends through the storage stack structure 300 along the first direction X, and the tunnel layer 621 covers the outer wall of the channel layer 622, that is, in the second direction Y, the tunnel layer 621 is located between the channel layer 622 and the isolation structure 700, and in the second direction Y, the tunnel layer 621 is located between the channel layer 622 and the charge storage unit 610 or between the channel layer 622 and the gate dielectric layer 320. For example, the tunnel layer 621 may include at least one of silicon oxide or metal oxide. For example, the channel layer 622 may include at least one of polycrystalline silicon or single crystal silicon. See Figure 6 In some examples, the channel layer 622 may be a solid pillar.

[0135] Please refer to Figure 7 In some other examples, the channel layer 622 may also be a hollow cylinder. When the columnar structure of the channel layer 622 is a hollow cylinder, the common layer 620 may further include a support portion 623, and the support portion 623 may be located inside the channel layer 622. At this time, the channel layer 622 may surround the support portion 623, and the support portion 623 may provide support for the channel structure 600.

[0136] For example, the support portion 623 may include an insulating material, such as silicon oxide.

[0137] Please refer again Figure 6 In the embodiment of the present application, the channel structure 600 may further include an insulating layer 630, and the insulating layer 630 surrounds the charge storage unit 610 and the common layer 620. The insulating layer 630 may include an oxide, a high insulation constant insulating material, or a combination thereof. The material forming the insulating layer 630 may be the same as the material forming the isolation structure 700.

[0138] Continue to refer to Figure 6 and Figure 7 In the embodiment of the present application, the channel structure 600 includes two first planes 640 arranged opposite to each other in the second direction Y and two second planes 650 arranged opposite to each other in the third direction Z, wherein the first plane 640 is respectively connected to the two second planes 650 on both sides in the second direction Y, and the second plane 650 is respectively connected to the two first planes 640 on both sides in the third direction Z.

[0139] In some examples, the first plane 640 and the second plane 650 are both located on a side of the insulating layer 630 facing away from the common layer 620. The two charge storage portions 610 are disposed close to the two first planes 640, respectively.

[0140] Continue to refer to Figure 6 and Figure 7In the above implementation, the positive projection of the channel structure 600 in the first direction X is a rectangle, that is, it can be a square or a rectangle.

[0141] The rectangle may be a standard rectangle, that is, the angle formed by two adjacent sides of the rectangle is a right angle.

[0142] In addition, the rectangle may also be an approximate rectangle, that is, two adjacent straight sides in the rectangle are perpendicular to each other, and the intersection of the two straight sides is in an arc shape.

[0143] Please refer to Figure 6 In some embodiments, the width H2 of the channel structure 600 in the third direction Z is greater than the width H3 of the channel structure 600 in the second direction Y, thereby reducing the width of the channel structure 600 in the second direction Y, thereby increasing the density of the channel structure 600 and further improving the storage density of the semiconductor structure 200.

[0144] Continue to refer to Figure 8 In some embodiments of the invention, the semiconductor structure 200 may further include a high dielectric constant layer 800. The high dielectric constant layer 800 may also be located between the gate line layer 310 and the gate dielectric layer 320, and between the gate line layer 310 and the channel structure 600. The high dielectric constant layer 800 may be formed of a high dielectric constant material. In the semiconductor industry, a high dielectric constant generally means that the dielectric constant k of the material is higher than the dielectric constant k of silicon dioxide, i.e., 3.9. The dielectric constant of the high dielectric constant layer 800 may be 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, and the like. The material of the high dielectric constant layer 800 includes, but is not limited to, any one or more of aluminum oxide (Al2O3), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), and silicon oxynitride (SiOxNy).

[0145] At this time, part of the high dielectric constant layer 800 may be located on two opposite surfaces of the gate line layer 310 in the first direction X. The high dielectric constant layer 800 may protect the gate line layer 310 to prevent the gate line layer 310 from being oxidized and affecting the conductive performance of the gate line layer 310 .

[0146] Reference Figure 8 In some embodiments, the semiconductor structure may further include a TiN (titanium nitride) layer 900 , wherein the high dielectric constant layer 800 is located between the TiN layer 900 and the gate line layer 310 .

[0147] Fig. 9 is a structural diagram of a semiconductor structure according to some embodiments, Fig.10 for Fig. 9 Cross-sectional view along CC direction.

[0148] Reference Fig. 9 and Fig.10 In other embodiments, the high dielectric constant layer 800 may surround the channel structure 600. In this case, the high dielectric constant layer 800 may store the stacked structure 300 in the first direction X. This arrangement may reduce the area of ​​the high dielectric constant layer 800, thereby making the thickness of the high dielectric constant layer 800 more uniform.

[0149] The high dielectric constant layer 800 may be located between the gate line layer 310 and the channel structure 600 , between the gate dielectric layer 320 and the channel structure 600 , and between the isolation structure 700 and the channel structure 600 .

[0150] In this embodiment, the orthographic projection of the high dielectric constant layer 800 in the third direction Z may cover the gate dielectric layer 320 and the gate line layer 310 .

[0151] In some other embodiments, the orthographic projection of the high dielectric constant layer 800 in the third direction Z may only cover the gate line layer 310 .

[0152] Based on the semiconductor structure 200 provided in some of the above embodiments, the present application also provides a method for preparing the semiconductor structure.

[0153] Please refer to Figure 11A to Figure 11M , Figure 11A to Figure 11M FIG. 4 is a diagram showing steps of a method for preparing a semiconductor structure according to some embodiments. Fig.12 The process of the method for preparing a semiconductor structure according to some embodiments is as follows Figure 1 .

[0154] See also Fig.12 The method for preparing the semiconductor structure may include the following steps: S100 and S200.

[0155] S100: forming a stacked structure on one side of a substrate, wherein the stacked structure includes gate replacement layers and gate dielectric layers alternately stacked along a first direction.

[0156] In step S100 , alternately stacked gate replacement layers 95 and gate dielectric layers 320 may be formed on a substrate by a thin film deposition process, that is, the gate replacement layers 95 and the gate dielectric layers 320 are alternately stacked in the first direction X.

[0157] The “alternating stacking” means that after forming a gate dielectric layer 320 on the substrate, a gate replacement layer 95 is formed on the gate dielectric layer 320, and then a gate dielectric layer 320 is formed on the gate replacement layer 95, and then the above steps are repeated.

[0158] Exemplarily, the thin film deposition process may include a combination of one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and electroplating processes.

[0159] S200: forming an isolation structure and a channel structure.

[0160] Please refer to Figure 5 and Figure 6 , wherein the isolation structure 700 and the channel structure 600 are alternately arranged along the second direction and both penetrate the stacked structure, and the second direction is perpendicular to the first direction; the channel structure 600 includes two charge storage parts 610 arranged at intervals in the third direction and a common layer 620 located between the two charge storage parts 610; the charge storage part 610 includes a plurality of sub-charge storage parts 611 arranged at intervals in the first direction, and in the first direction, each two adjacent sub-charge storage parts 611 are separated by a gate dielectric layer 320; the common layer 620 includes a tunneling layer 621 and a channel layer 622, and the tunneling layer 621 is located between the channel layer 622 and the charge storage part 610; wherein the third direction is perpendicular to the first direction and intersects with the second direction.

[0161] The channel structure 600 may include two charge storage units 610 and a common layer 620. The two charge storage units 610 may share the common layer 620, thereby increasing the number of charge storage units 610 in the channel structure 600. One charge storage unit 610 may be used to form one storage cell string 400. Therefore, by providing two charge storage units 610 in the channel structure 600, the number of storage cell strings 400 in the channel structure 600 may be increased, thereby increasing the storage density of the semiconductor structure 200.

[0162] Next, step S200 will be introduced.

[0163] Fig.13 The process of the method for preparing the semiconductor structure of some embodiments is as follows Figure 2 .

[0164] Please refer to Fig.13 In some embodiments, step S200 may include: the following steps S210 to S280.

[0165] Please refer to Fig.11A , S210: forming a first isolation trench, the first isolation trench penetrates the stacked structure and extends along the second direction.

[0166] In the above step S210 , the first isolation trench 91 may be etched on the stacked structure 810 by means of a dry etching process or a wet etching process, wherein the number of the first isolation trench 91 may be multiple.

[0167] In some examples, the plurality of first isolation trenches 91 may be sequentially arranged along the third direction and disposed at intervals. Furthermore, the plurality of first isolation trenches 91 may be parallel to each other.

[0168] Continue to refer to Fig.11A In some examples, the intervals between two adjacent first isolation trenches 91 are the same.

[0169] See also FIG. 11B to FIG. 11D , S220: forming a plurality of dielectric portions spaced apart along the second direction in the first isolation trench to separate the first isolation trench into a plurality of channel holes spaced apart along the second direction.

[0170] Two adjacent channel holes 93 in the second direction Y may be separated by the dielectric portion 94 . In this case, a portion of the surface of the dielectric portion 94 may be used to form the hole wall of the channel hole 93 .

[0171] For example, the orthographic projection of the channel hole 93 on the substrate can be a rectangle, wherein the rectangle can be a standard rectangle, that is, the angle formed by two adjacent sides of the rectangle is a right angle. In addition, the rectangle can also be an approximate rectangle, that is, two adjacent straight sides of the rectangle are perpendicular to each other, and the intersection of the two straight sides is in an arc shape.

[0172] For example, the rectangle may include a square or a rectangle, wherein the square may include a standard square or an approximate square, and the rectangle may include a standard rectangle or an approximate rectangle.

[0173] In some examples, in the stacked structure 810 , the plurality of channel holes 93 may be arranged in multiple rows and columns, wherein the plurality of channel holes 93 in a row of channel holes 93 may be sequentially arranged along the second direction Y. And the plurality of channel holes 93 in a column may be sequentially arranged along the third direction Z.

[0174] The plurality of channel holes 93 in a row of channel holes 93 are located in the first isolation trench 91 , and the plurality of channel holes 93 located in one first isolation trench 91 may be arranged at equal intervals.

[0175] Fig.14 The process of the method for preparing the semiconductor structure of some embodiments is as follows Figure 3 .

[0176] Please refer to Fig.14 , step S220 may include: the following steps S221 and S222.

[0177] Please refer to Fig. 11B, S221: Filling a sacrificial medium in the first isolation groove.

[0178] In the above step S221 , the sacrificial medium 92 may include one or more of polysilicon, silicon carbide or aluminum oxide.

[0179] In the implementation mode where the sacrificial medium 92 is polysilicon, the polysilicon may be doped with P (phosphorus) element or B (boron) element. The etching speed of the sacrificial medium 92 may be increased by doping the boron element or the phosphorus element after etching the sacrificial medium 92.

[0180] See also Fig. 11C and Fig.11D S222: removing the sacrificial dielectric in the plurality of channel regions spaced apart along the second direction in the first isolation trench to form a plurality of dielectric portions spaced apart along the second direction.

[0181] In the above step S222, a mask plate may be disposed on the top of the stacked structure 810. Fig. 11C The dotted line frame in the figure is the frame of the mask plate, wherein the dotted line only roughly indicates the position of the mask plate, and does not limit the specific size of the mask plate. The mask plate is provided with a plurality of mask holes 98, and the mask holes 98 are in the shape of long strips. When the mask plate is arranged on the top of the stacked structure, the length direction of the mask holes 98 can intersect with the extension direction of the first isolation groove 91, so that part of the sacrificial dielectric 92 can be exposed to the mask holes 98. Then, the sacrificial dielectric 92 exposed by the mask holes 98 is etched to form a plurality of dielectric portions 94 arranged at intervals.

[0182] When the mask plate is arranged on the top of the stacked structure 810, the mask hole 98 can be extended along the third direction Z on the stacked structure 810, so that the extension direction of the mask hole 98 is perpendicular to the extension direction of the first isolation groove 91, and a rectangular channel hole 93 can be formed in this arrangement. The rectangular channel hole 93 is a channel hole 93 whose orthographic projection on the substrate is a rectangle.

[0183] For example, the plurality of mask holes 98 are arranged at equal intervals, so that a plurality of dielectric portions 94 having equal widths in the second direction Y can be formed. In addition, the plurality of mask holes 98 have equal widths in the second direction Y, so that the plurality of dielectric portions 94 can separate the first isolation trench 91 into a plurality of channel holes 93 arranged at equal intervals. At this time, two surfaces of the dielectric portion 94 arranged opposite to each other in the second direction Y, a surface of a portion of the gate dielectric layer 320, and a surface of a portion of the gate replacement layer 95 can be used to form the hole walls of the channel holes 93.

[0184] The dielectric portion 94 includes two surfaces disposed opposite to each other in the third direction Z and two surfaces disposed opposite to each other in the second direction Y, wherein the two surfaces disposed opposite to each other in the second direction Y of the dielectric portion 94 are respectively used to form hole walls of two channel holes 93. At this time, the two hole walls disposed opposite to each other in the second direction Y of the channel hole 93 may be located on the two dielectric portions 94, respectively.

[0185] Please refer to Fig.11D After completing step S222, a plurality of channel holes 93 can be formed.

[0186] Please refer to Fig.13 , after step S222, the following steps S220.1 may also be included.

[0187] S220.1: removing a portion of the gate replacement layer through the channel hole to form two recess groups that are arranged opposite to each other in the third direction and connected to the channel hole, wherein the recess group includes a plurality of recess portions that are spaced apart in the first direction.

[0188] Please refer to Fig.11E In the above step S220.1, gate replacement layers 95 are provided on both sides of the channel hole 93 in the third direction Z. In the process of removing part of the gate replacement layer 95 through the channel hole 93, the gate replacement layer 95 located on both sides of the channel hole 93 can be removed, thereby forming a plurality of recessed portions 961, and the recessed portions 961 located on the same side of the channel hole 93 in the third direction Z can form a recess group 96.

[0189] The recessed portion 961 may be surrounded by the gate dielectric layer 320 and the gate replacement layer 95. The recessed portion 961 may include two surfaces arranged opposite to each other in the first direction X, and a recessed bottom and a recessed opening arranged opposite to each other in the third direction Z. The surface of the recessed portion 961 in the first direction X may be formed by two adjacent gate dielectric layers 320, and the recessed bottom of the recessed portion 961 may be formed by the gate replacement layer 95, and the recessed opening may be located on the sidewall of the channel hole 93, so that the recessed portion 961 can be connected to the channel hole 93.

[0190] In two recess groups 96 corresponding to a channel hole 93 , a recess portion 961 in one recess group 96 may correspond to another recess portion 961 in another recess group 96 . At this time, the orthographic projections of the two corresponding recess portions 961 in the third direction Z may cover the same gate replacement layer 95 .

[0191] The two recess groups 96 corresponding to one channel hole 93 refer to that the multiple recess portions 961 in the two recess groups 96 are all connected to the same channel hole 93 .

[0192] In addition, since the gate replacement layers 95 and the gate dielectric layers 320 are alternately stacked along the first direction X, a gate dielectric layer 320 may be disposed between two adjacent recesses 961 in one recess group 96 in the first direction X.

[0193] Please refer to Fig.11F In step S220, that is, after step S222, the process may further include S220.2: forming an insulating layer 630 in the channel hole 93. The insulating layer 630 may be formed by a deposition process.

[0194] At this time, the insulating layer 630 can cover the hole wall of the channel hole 93, that is, the insulating layer 630 can cover two surfaces of the dielectric portion 94 opposite to each other in the second direction Y, a surface of part of the gate dielectric layer 320 and a surface of part of the gate replacement layer 95.

[0195] In which, when the preparation method further includes the above-mentioned step S220.1, when the insulating layer 630 is formed in the channel hole 93, the insulating layer 630 can also be formed in the multiple recessed portions 961 of the recess group 96.

[0196] S230: forming an initial charge storage layer in the channel hole.

[0197] Please refer to Fig.11G In step S230 , a deposition process may be used to form an initial charge storage layer 612 in the channel hole 93 . At this time, the initial charge storage layer 612 may cover the hole wall of the channel hole 93 .

[0198] In step S230 , the initial charge storage layer 612 may cover two surfaces of the dielectric portion 94 that are opposite to each other in the second direction Y, a portion of the surface of the gate dielectric layer, and a portion of the surface of the gate replacement layer 95 .

[0199] Wherein, when the preparation method further includes the above step S220.1, when the initial charge storage layer 612 is formed in the channel hole 93, the initial charge storage layer 612 is partially located in the plurality of recessed portions 961 (such as Fig.11E shown).

[0200] In which, an initial charge storage layer 612 is formed in the channel hole 93, and part of the initial charge storage layer 612 can fill the recess 961 or only fill part of the recess 961. Part of the initial charge storage layer 612 is located on part of the gate dielectric layer 320 and the dielectric part 94 which serve as the inner wall of the channel hole 93.

[0201] The above “forming an insulating layer 630 in the channel hole 93 ” may be performed before step S230 . It is understood that the initial charge storage layer 612 may be formed on the surface of the insulating layer 630 away from the wall of the channel hole 93 .

[0202] S240: removing a portion of the initial charge storage layer located on the dielectric portion to form two charge storage portions oppositely disposed along the second direction in the channel hole.

[0203] Please refer to Fig.11G and Fig.11H In step S240, the initial charge storage layer 612 on the portion of the dielectric portion 94 used to form the hole wall of the channel hole 93 is removed, that is, the initial charge storage layer 612 on the two surfaces of the dielectric portion 94 opposite to each other in the second direction Y is removed. At this time, the initial charge storage layer 612 located on the gate dielectric layer 320 and the gate replacement layer 95 is retained, so that the initial charge storage layer 612 covering the inner wall of the channel hole 93 can be divided into two charge storage portions 610 opposite to each other in the second direction Y.

[0204] When the preparation method further includes the above step S220.1, the initial charge storage layer 612 located on the gate dielectric layer 320 and the gate replacement layer 95 may further include the initial charge storage layer 612 located in the recessed portion 961. That is, after step S240, i.e., after removing part of the initial charge storage layer 612 located on the dielectric portion 94, the initial charge storage layer 612 located in the plurality of recessed portions 961 may be retained.

[0205] Among them, by removing the initial charge storage layer 612 located on the dielectric part 94, two charge storage parts 610 can be formed, and one charge storage part 610 can be used to form a storage cell string. Therefore, by setting two charge storage parts 610 in the channel structure 600, the number of storage cell strings in the channel structure can be increased, thereby increasing the storage density of the semiconductor structure 200.

[0206] After step S230, the method may further include step S240.1: removing a portion of the initial charge storage layer located on the gate dielectric layer to form a plurality of sub-charge storage portions.

[0207] Wherein, the gate dielectric layer 320 (such as Fig.10 Part of the surface of the gate dielectric layer 320 (as shown) can be used to form the inner wall of the channel hole 93, and part of the initial charge storage layer 612 located on the gate dielectric layer 320 is removed, that is, the initial charge storage layer 612 on the surface of the gate dielectric layer 320 used to form the inner wall of the channel hole 93 is removed.

[0208] After step S240.1, ie after removing part of the initial charge storage layer 612 on the gate dielectric layer 320, the charge storage portion 610 covering the inner wall of the channel hole 93 can be divided into a plurality of sub-charge storage portions 611 spaced apart in the first direction X.

[0209] In the case where the preparation method also includes the above-mentioned step S220.1, after step S240.1, that is, after part of the initial charge storage layer 612 on the gate dielectric layer 320 is removed, the initial charge storage layer 612 located in the recess 961 can be retained, wherein the initial charge storage layer 612 retained in the recess 961 can serve as the sub-charge storage portion 611.

[0210] The sub-charge storage unit 611 may fill up the recess 961 , or the sub-charge storage unit 611 may fill part of the recess 961 . In this case, the sub-charge storage unit 611 does not fill up the recess 961 .

[0211] Among them, a gate dielectric layer 320 is separated between two adjacent sub-charge storage units 611 in the first direction X. Therefore, the two adjacent sub-charge storage units 611 in the first direction X are isolated from each other, thereby preventing charges from diffusing from one sub-charge storage unit 611 to the adjacent sub-charge storage unit 611 in the first direction X.

[0212] In some embodiments, the initial charge storage layer 612 on the gate dielectric layer 320 and the initial charge storage layer 612 on the dielectric portion 94 may be removed simultaneously.

[0213] By simultaneously removing the initial charge storage layer 612 located on the gate dielectric layer 320 and the initial charge storage layer 612 located on the dielectric portion 94 , step S240 . 1 can be performed in one process.

[0214] After forming the sub-charge storage part 611, a common layer 620 may be formed in the channel hole 93. In some examples, the common layer 620 may include a tunneling layer 621 and a channel layer 622, and in this case, the channel layer 622 may be a solid column.

[0215] S250: forming a tunnel layer and a channel layer in sequence in the channel hole to form a channel structure.

[0216] Please refer to Fig.11I In step S250 , after the tunneling layer 621 is formed in the channel hole 93 , the tunneling layer 621 may be located on the surface of the sub-charge storage portion 611 and the surface of the insulating layer 630 .

[0217] See also Fig.11J After forming the tunnel layer 621 , the channel layer 622 may be formed.

[0218] In some other examples, the common layer 620 may further include a support portion 623, and the support portion 623 may be located inside the channel layer 622. In this case, the channel layer 622 may surround the support portion 623, and the support portion 623 may provide support for the channel structure 600.

[0219] At this time, the step of forming the common layer 620 in the channel hole 93 may include sequentially forming a tunneling layer 621 , a channel layer 622 , and a supporting portion 623 in the channel hole.

[0220] When the sub-charge storage portion 610 does not completely fill the recess 961 , the charge storage portion 610 and a portion of the tunneling layer 621 are both located in the recess 961 .

[0221] After forming the common layer 620 , the channel structure 600 is completed.

[0222] The above describes the method for preparing the channel structure 600 . Next, the method for preparing the isolation structure 700 will be described.

[0223] In step S250 : after the tunnel layer 621 and the channel layer 622 are sequentially formed in the channel hole 93 , the following steps S260 to S280 may also be included.

[0224] S260: removing the dielectric portion to form a second isolation trench.

[0225] Please refer to Figure 11K and Fig.11L In step S260, the dielectric portion 94 may be removed by a wet etching process. After the dielectric portion 94 is removed, a second isolation trench 97 may be formed, wherein the second isolation trench 97 penetrates the stacked structure.

[0226] The number of second isolation trenches 97 can be the same as the number of second isolation trenches 97 , and multiple second isolation trenches 97 are spaced apart in the second direction Y, and a channel structure 600 exists between two adjacent second isolation trenches 97 in the second direction Y; multiple second isolation trenches 97 can also be spaced apart in the third direction Z, and a stacked structure 810 exists between two adjacent second isolation trenches 97 .

[0227] In some embodiments, the dielectric portion 94 can be formed by a sacrificial dielectric. Therefore, the material of the dielectric portion 94 can be the same as the material of the sacrificial dielectric. When the sacrificial dielectric is polysilicon, the sacrificial dielectric is doped with B element or P element. At this time, the etching selectivity of the material forming the dielectric portion 94 is greater than the etching selectivity of the material forming the channel layer 622, thereby preventing damage to the channel layer 622 during the removal of the dielectric portion 94, which is beneficial to improving the stability of the channel structure 600.

[0228] Please continue reading Figure 11K After the second isolation trench 97 is formed, the gate replacement layer 95 may be exposed through the second isolation trench 97 .

[0229] S270: replacing the gate replacement layer with a gate line layer via the second isolation trench.

[0230] Next, the formation process of the gate line layer 310 is introduced.

[0231] Please refer to Fig.15 , Fig.15 The process of the method for preparing the semiconductor structure of some embodiments is as follows Figure 4 .

[0232] The above step S270 may include: the following steps S271 and S272.

[0233] S271: forming a replacement gap by removing the gate replacement layer.

[0234] S272: forming a gate line layer in the replacement gap.

[0235] In step S271, the gate replacement layer 95 in the stacked structure 810 can be removed by isotropic etching through the second isolation trench 97, thereby forming a replacement gap 820. At this time, the channel structure 600 can support the multi-layer gate dielectric layer 320. The isotropic etching can be selective wet etching or vapor etching.

[0236] Among them, the replacement gap 820 can be seen back Fig.10 , it should be noted that in Fig.10 In the figure, the dotted frame indicated by the reference numeral 820 is only for illustrating the location of the replacement gap 820 and does not represent the boundary of the replacement gap 820.

[0237] In addition, the gate dielectric layer 320 (eg Figure 8 The etching rate of the gate replacement layer 95 is different from that of the gate replacement layer 95 under the same process conditions, so that when the gate replacement layer 95 is removed, the gate dielectric layer 320 will not be damaged.

[0238] In the process of replacing the gate replacement layer 95 with the gate line layer 310 , the plurality of second isolation trenches 97 can increase the channels for removing the gate replacement layer 95 and forming the gate line layer 310 , thereby improving the replacement efficiency.

[0239] In some embodiments, before step S272 : forming a gate line layer in the replacement slit 820 , the method may further include: forming a high dielectric constant layer 800 in the replacement slit 820 .

[0240] The high dielectric constant layer 800 is formed before the gate line layer 310 and is located between two adjacent gate dielectric layers 320 . At this time, a portion of the high dielectric constant layer 800 and another portion are located between the gate line layer 310 and the gate dielectric layer 320 .

[0241] In addition, the semiconductor structure 200 may further include a TiN layer 900 (eg Figure 8 As shown in FIG. 1 , the TiN layer 900 may be formed before the gate line layer 310 . At this time, the TiN layer 900 is located between the high dielectric constant layer 800 and the gate line layer 310 .

[0242] In another embodiment, the high dielectric constant layer 800 may also be formed before the initial charge storage layer 612 is formed in the channel hole 93 in step S230. At this time, the high dielectric constant layer 800 is formed in the channel hole 93, so that the high dielectric constant layer 800 covers the surface of the gate dielectric layer 320 exposed in the channel hole 93 and the surfaces of the gate replacement layer 95 and the gate dielectric layer 320 exposed in the recess group 96. In this example, the area of ​​the high dielectric constant layer 800 is small, which is conducive to a more uniform thickness of the high dielectric constant layer 800. At this time, the structure of the formed semiconductor structure 200 can be referred to. Fig. 9 and Fig.10 At this time, the orthographic projection of the high dielectric constant layer 800 in the third direction Z can cover the gate dielectric layer 320 and the gate line layer 310 , and the orthographic projection in the second direction Y can cover the entire isolation structure 700 .

[0243] However, in some other embodiments, after the high dielectric constant layer 800 is formed in the channel hole 93, the high dielectric constant layer 800 can cover the hole wall of the channel hole 93 and the recessed portion 961, and then the high dielectric constant layer 800 located on the dielectric portion 94 and on the gate dielectric layer 320 can be removed. At this time, the orthographic projection of the high dielectric constant layer 800 in the third direction Z can only cover the gate line layer 310.

[0244] S280: Filling the second isolation trench with an insulating material to form an isolation structure.

[0245] See also Fig.11M , a deposition process may be used to fill the second isolation trench 97 with insulating material. In the process of depositing the insulating material, the insulating material may not only be filled in the second isolation trench 97, but also cover the top of the stacked structure 810. At this time, an oxide layer is also formed on the top of the stacked structure 810, wherein the top of the stacked structure 810 refers to a surface of the stacked structure 810 that is away from the substrate.

[0246] In some embodiments, after step S280 , the oxide layer may be chemically mechanically polished so that the stacked structure 810 has a flat surface, which facilitates the formation of a peripheral circuit on the top of the stacked structure 810 .

[0247] At this point, the semiconductor structure 200 is completed. That is, after step S280 , the stacked structure 810 may also be referred to as a storage stacked structure 300 .

[0248] Fig.16 is a block diagram of a storage system according to some embodiments. Fig.17 is a block diagram of a storage system according to some other embodiments.

[0249] See also Fig.16 and Fig.17 Some embodiments of the present application further provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10 of some embodiments described above. The controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0250] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0251] In some embodiments, see Fig.16 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0252] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0253] In other embodiments, see Fig.17 The storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0254] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0255] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0256] In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 10.

[0257] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0258] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0259] Some embodiments of the present application also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0260] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0261] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A storage stack structure, comprising gate line layers and gate dielectric layers alternately stacked along a first direction; Isolation structures and channel structures are alternately arranged along a second direction; wherein the isolation structures and the channel structures both penetrate the storage stack structure; and the second direction is perpendicular to the first direction; The channel structure includes two charge storage parts spaced apart in a third direction and a common layer located between the two charge storage parts; the charge storage part includes a plurality of sub-charge storage parts spaced apart in a first direction, and in the first direction, each two adjacent sub-charge storage parts are spaced apart by the gate dielectric layer; the common layer includes a tunneling layer and a channel layer, and the tunneling layer is located between the channel layer and the charge storage part; wherein the third direction is perpendicular to the first direction, and the third direction intersects with the second direction.

2. The semiconductor structure according to claim 1, characterized in that: The channel structure includes two first planes arranged opposite to each other in the second direction and two second planes arranged opposite to each other in the third direction, wherein both sides of the first plane in the second direction are respectively connected to the two second planes, and both sides of the second plane in the third direction are respectively connected to the two first planes.

3. The semiconductor structure according to claim 2, characterized in that: The orthographic projection of the channel structure in the first direction is a rectangle.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The width of the channel structure in the third direction is greater than the width of the channel structure in the second direction.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The width of the isolation structure in the third direction is smaller than the width of the channel structure in the third direction, the isolation structure is opposite to the common layer in the second direction, and the charge storage part is staggered with the isolation structure in the second direction.

6. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The channel structure further includes an insulating layer surrounding the charge storage portion and the common layer.

7. The semiconductor structure according to any one of claims 1 to 3, characterized in that: Also includes: A high dielectric constant layer is located between the channel structure and the isolation structure, and the high dielectric constant layer surrounds the channel structure.

8. The semiconductor structure according to any one of claims 1 to 3, characterized in that: Also includes: A high dielectric constant layer is located between the gate line layer and the gate dielectric layer, and between the gate line layer and the channel structure.

9. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The common layer further includes a support portion, and the channel layer surrounds the support portion.

10. A method for preparing a semiconductor structure, characterized in that: include: forming a stacked structure on one side of the substrate, the stacked structure comprising gate replacement layers and gate dielectric layers alternately stacked along a first direction; An isolation structure and a channel structure are formed; wherein the isolation structure and the channel structure are alternately arranged along a second direction and both penetrate the stacked structure, and the second direction is perpendicular to the first direction; the channel structure includes two charge storage parts spaced apart in a third direction and a common layer located between the two charge storage parts; the charge storage part includes a plurality of sub-charge storage parts spaced apart in the first direction, and in the first direction, each adjacent two sub-charge storage parts are spaced apart by the gate dielectric layer; the common layer includes a tunneling layer and a channel layer, and the tunneling layer is located between the channel layer and the charge storage part; wherein the third direction is perpendicular to the first direction, and the third direction intersects with the second direction.

11. The preparation method according to claim 10, characterized in that: The forming of the isolation structure and the channel structure comprises: forming a first isolation trench, wherein the first isolation trench penetrates the stacked structure and extends along the second direction; forming a plurality of dielectric portions spaced apart along the second direction in the first isolation groove to divide the first isolation groove into a plurality of channel holes spaced apart along the second direction; forming an initial charge storage layer in the channel hole; removing a portion of the initial charge storage layer located on the dielectric portion to form two charge storage portions oppositely disposed along a second direction in the channel hole; The tunnel layer and the channel layer are sequentially formed in the channel hole.

12. The preparation method according to claim 11, characterized in that: Before sequentially forming the tunnel layer and the channel layer in the channel hole, the method further includes: A portion of the initial charge storage layer located on the gate dielectric layer is removed to form a plurality of sub-charge storage portions.

13. The preparation method according to claim 12, characterized in that: Before forming the initial charge storage layer in the channel hole, the method further includes: Removing a portion of the gate replacement layer through the channel hole to form two recess groups that are arranged opposite to each other in the third direction and connected to the channel hole, wherein the recess group includes a plurality of recess portions that are spaced apart in the first direction; When the initial charge storage layer is formed in the channel hole, a portion of the initial charge storage layer is located in the plurality of recessed portions.

14. The preparation method according to claim 13, characterized in that: The initial charge storage layer on the gate dielectric layer and the initial charge storage layer on the dielectric portion are removed simultaneously.

15. The preparation method according to claim 11, characterized in that: Before forming the initial charge storage layer in the channel hole, the method further includes: An insulating layer is formed in the channel hole.

16. The preparation method according to claim 11, characterized in that: The method of forming a plurality of dielectric portions spaced apart along the first direction in the first isolation trench to separate the first isolation trench into a plurality of channel holes spaced apart along the first direction comprises: Filling a sacrificial medium in the first isolation groove; The sacrificial dielectric in a plurality of channel regions spaced apart along the second direction in the first isolation trench is removed to form a plurality of dielectric portions spaced apart along the second direction.

17. The preparation method according to claim 16, characterized in that: The sacrificial medium includes one or more of polysilicon, silicon carbide or aluminum oxide.

18. The preparation method according to claim 11, characterized in that: Before forming the initial charge storage layer in the channel hole, the method further comprises: A high dielectric constant layer is formed in the channel hole.

19. The preparation method according to claim 11, characterized in that: After the tunnel layer and the channel layer are sequentially formed in the channel hole, the method further includes: removing the dielectric portion to form a second isolation trench; replacing the gate replacement layer with a gate line layer via the second isolation trench; The second isolation trench is filled with an insulating material to form an isolation structure.

20. The preparation method according to claim 19, characterized in that: The replacing the gate replacement layer with a gate line layer via the second isolation trench comprises: removing the gate replacement layer to form a replacement gap; forming the gate line layer in the replacement gap; Before forming the gate line layer in the replacement gap, the method further includes: A high dielectric constant layer is formed in the replacement gap.

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