Semiconductor device and data storage system including the same

Abstract

The invention discloses a semiconductor device and a data storage system including the same. The semiconductor device includes a first semiconductor structure including a substrate, a circuit element, and a circuit interconnect line, and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure comprises a plate layer; first gate electrodes stacked on the plate layer in the first direction and spaced apart from each other; a separation region penetrating the first gate electrode and extending in the second direction; a first channel structure spaced apart from the partition section in the third direction, penetrating the first gate electrode, and extending in the first direction; and a dummy structure contacting the separation region, penetrating the first gate electrode, and extending in the first direction. The first channel structure and the dummy structure each have a circular shape in a plan view, and the partition region is in contact with at least a portion of a corresponding side surface of the dummy structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0100461 filed in the Korean Intellectual Property Office on August 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure is directed to a semiconductor device and a data storage system including the semiconductor device. Background Art

[0004] In data storage systems, semiconductor devices can be used to store high-capacity data. Therefore, it is desirable to increase the data storage capacity of semiconductor devices. Methods for increasing the data storage capacity of semiconductor devices include three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells. Summary of the invention

[0005] In general, in some aspects, the present disclosure is directed to a semiconductor device with improved design freedom and reduced process difficulty. In some aspects, the present disclosure is directed to a data storage system including a semiconductor device with improved design freedom and reduced process difficulty.

[0006] According to some aspects of the present disclosure, a semiconductor device includes a first semiconductor structure and a second semiconductor structure on the first semiconductor structure, the first semiconductor structure including a substrate, a circuit element on the substrate, and a circuit interconnection line on the circuit element. The second semiconductor structure includes: a board layer; a first gate electrode, stacked on the board layer in a first direction perpendicular to the upper surface of the board layer and spaced apart from each other; a separation region, penetrating the first gate electrode and extending in a second direction perpendicular to the first direction; a first channel structure, spaced apart from the separation region in a third direction perpendicular to the first direction and the second direction, penetrating the first gate electrode, and extending in the first direction; and a dummy structure, contacting the separation region, penetrating the first gate electrode, and extending in the first direction. The first channel structure and the dummy structure have circular shapes in a plan view, respectively, and the separation region contacts at least a portion of the corresponding side surface of the dummy structure.

[0007] According to some aspects of the present disclosure, a semiconductor device includes: a plate layer; a gate electrode stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and spaced apart from each other; a channel structure penetrating the gate electrode, extending in the first direction, and arranged in a row along a second direction perpendicular to the first direction; a dummy structure extending in the first direction outside the channel structure, penetrating the gate electrode, and arranged in a row along the second direction; and a separation region penetrating the gate electrode between the rows of the dummy structure and extending in the second direction. The channel structure is arranged at a first pitch in a third direction perpendicular to the first direction and the second direction, and the width of the separation region is greater than the first pitch.

[0008] According to some aspects of the present disclosure, a data storage system includes: a semiconductor memory device including a first semiconductor structure including a circuit element, a second semiconductor structure on a surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element; and a controller electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device. The second semiconductor structure includes: a plate layer; a gate electrode stacked on the plate layer in a first direction perpendicular to the upper surface of the plate layer and spaced apart from each other; a channel structure extending in a first direction, penetrating the gate electrode, and arranged in a row along a second direction perpendicular to the first direction; a dummy structure, outside the channel structure, penetrating the gate electrode, extending in the first direction, and arranged in a row along the second direction; and a separation region, between the rows of the dummy structures, penetrating the gate electrode, and extending in the second direction. The separation region surrounds at least a portion of each dummy structure and contacts the dummy structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary implementations will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a schematic plan view of an exemplary semiconductor device according to some implementations.

[0011] Figure 2 is a schematic cross-sectional view of an exemplary semiconductor device according to some implementations.

[0012] Figure 3A and Figure 3B is a schematic, partially enlarged view of an exemplary semiconductor device according to some implementations.

[0013] Figure 4A and Figure 4B is a schematic plan view of an exemplary semiconductor device according to some implementations.

[0014] Figure 5 is a schematic plan view of an exemplary semiconductor device according to some implementations.

[0015] FIG. 6A to FIG. 6C is a schematic cross-sectional view of an exemplary semiconductor device according to some implementations.

[0016] Figure 7 is a schematic cross-sectional view of an exemplary semiconductor device according to some implementations.

[0017] Figures 8 to 17 is a schematic diagram illustrating an exemplary method of manufacturing a semiconductor device according to some implementations.

[0018] Fig.18 is a diagram schematically illustrating an exemplary data storage system including a semiconductor device according to some implementations.

[0019] Fig.19 is a perspective view schematically illustrating an exemplary data storage system including a semiconductor device according to some implementations.

[0020] Fig. 20 is a cross-sectional view schematically illustrating an exemplary semiconductor package according to some implementations. DETAILED DESCRIPTION

[0021] Hereinafter, exemplary implementations will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a schematic plan view of an exemplary semiconductor device according to some implementations, including an arrangement of components below the level of an upper surface of a first channel structure CH. Figure 2 is an exemplary semiconductor device according to some implementations along Figure 1 Schematic cross-sectional view along line II' in FIG. Figure 3A and Figure 3B is a schematic partial enlarged view of an exemplary semiconductor device according to some implementations, wherein Figure 3A Shows Figure 2 A magnified view of the "A" area, Figure 3B Shows Figure 2 A magnified view of the "B" area

[0023] exist Figure 1 , Figure 2 , Figure 3A and Figure 3B , the semiconductor device 100 may include a peripheral circuit region PERI and a memory cell region CELL, the peripheral circuit region PERI is a first semiconductor structure including a substrate 201, and the memory cell region CELL is a second semiconductor structure including a board layer 101. In some implementations, the memory cell region CELL may be disposed on the peripheral circuit region PERI. In some implementations, the memory cell region CELL may be disposed below the peripheral circuit region PERI.

[0024] The peripheral circuit region PERI may include a substrate 201, an impurity region 205 and a device isolation layer 210 in the substrate 201, a circuit element 220 disposed on the substrate 201, and a peripheral region insulating layer 290. The peripheral circuit region PERI further includes a circuit contact plug 270 and a circuit interconnection line 280.

[0025] The substrate 201 may have an upper surface extending in the X direction and in the Y direction perpendicular to the X direction. The active region may be defined in the substrate 201 by the device isolation layer 210, and the impurity region 205 containing impurities may be disposed in a portion of the active region. The substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. In some implementations, the substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0026] The circuit elements 220 may include planar transistors, wherein each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Impurity regions 205 may be disposed in the substrate 201 on both sides of the circuit gate electrode 225 as source / drain regions.

[0027] The peripheral region insulating layer 290 may be disposed on the circuit element 220 on the substrate 201 and may include a plurality of insulating layers formed in different process steps. The peripheral region insulating layer 290 may be formed of an insulating material.

[0028] The circuit contact plug 270 and the circuit interconnection line 280 may form a circuit interconnection structure electrically connected to the circuit element 220 and the impurity region 205. In some implementations, the circuit contact plug 270 may have a cylindrical shape, and the circuit interconnection line 280 may have a linear shape. An electrical signal may be applied to the circuit element 220 through the circuit contact plug 270 and the circuit interconnection line 280. Although not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit interconnection line 280 may have a linear shape, may be connected to the circuit contact plug 270, and may be arranged in multiple layers. The circuit contact plug 270 and the circuit interconnection line 280 may include a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), etc. Each of the circuit contact plug 270 and the circuit interconnection line 280 may further include a diffusion barrier. In some implementations, the number of layers of the circuit contact plug 270 and the circuit interconnection line 280 may vary.

[0029] The memory cell region CELL may include a source structure SS, a gate electrode 130 stacked on the source structure SS, and an interlayer insulating layer 120 alternately stacked with the gate electrode 130. The memory cell region CELL may further include a first channel structure CH and a second channel structure SCH disposed to penetrate the gate electrode 130, a first separation region MS extending through a portion of the gate electrode 130, a dummy structure DH disposed to contact the first separation region MS and penetrate the gate electrode 130, a second separation region US penetrating a first upper gate electrode 130U1 among the gate electrodes 130, a horizontal insulating layer 150 disposed between the first channel structure CH and the second channel structure SCH, a pillar 180 on the second channel structure SCH, and a bit line 185 on the pillar 180. The memory cell region CELL may further include first to third cell region insulating layers 192, 194, and 196 on the gate electrode 130.

[0030] The source structure SS may include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 stacked sequentially. In some implementations, the number of conductive layers forming the source structure SS may vary.

[0031] The plate layer 101 has a plate shape and may be used as at least part of a common source line of the semiconductor device 100. The plate layer 101 may have an upper surface extending in the X direction and the Y direction and may include a conductive material. For example, the plate layer 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The plate layer 101 may further include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer (such as a polycrystalline silicon layer) or an epitaxial layer.

[0032] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be sequentially stacked and disposed on the upper surface of the plate layer 101. The first horizontal conductive layer 102 may be used as part of a common source line of the semiconductor device 100, and may be used as a common source line together with the plate layer 101, for example. Figure 3B In the embodiment, the first horizontal conductive layer 102 may be directly connected to the first channel layer 140 around the first channel layer 140 of each first channel structure CH.

[0033] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material, such as polysilicon. In addition, at least the first horizontal conductive layer 102 may be a layer doped with impurities of the same conductivity type as the plate layer 101, and the second horizontal conductive layer 104 may be a doped layer or a layer containing impurities diffused from the first horizontal conductive layer 102. However, the material of the second horizontal conductive layer 104 is not limited to a semiconductor material.

[0034] Part of the gate electrode 130 other than the first upper gate electrode 130U1 may be stacked on the plate layer 101 to be vertically spaced apart to form a stacked structure together with the interlayer insulating layer 120. The stacked structure may include a lower stacked structure and an upper stacked structure stacked vertically. However, in some implementations, the stacked structure may consist of a single stacked structure.

[0035] The gate electrode 130 may include a first upper gate electrode 130U1 forming a string selection transistor, a second upper gate electrode 130U2 forming an erase transistor, a memory gate electrode 130M forming a plurality of memory cells, a first lower gate electrode 130L1 constituting an erase transistor, and a second lower gate electrode 130L2 constituting a ground selection transistor. The number of memory gate electrodes 130M constituting a memory cell may be determined according to the capacity of the semiconductor device 100. In some implementations, the second upper gate electrode 130U2, the first lower gate electrode 130L1, and the second lower gate electrode 130L2 may each be 1 to 4 or more. In some implementations, the positions of the first lower gate electrode 130L1 and the second lower gate electrode 130L2 may be interchanged. In some implementations, the second upper gate electrode 130U2 and / or the first lower gate electrode 130L1 may be omitted. In some implementations, a portion of the memory gate electrode 130M may be a dummy gate electrode.

[0036] The second lower gate electrode 130L2, the first lower gate electrode 130L1, the memory gate electrode 130M, and the second upper gate electrode 130U2 sequentially arranged from the bottom may be referred to as a first gate electrode, and the first upper gate electrode 130U1 may be referred to as a second gate electrode. In some implementations, the thickness of the first upper gate electrode 130U1 (e.g., the second gate electrode) may be greater than the thickness of each first gate electrode.

[0037] The gate electrode 130 may include a conductive material, such as at least one metal substance among tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re) and titanium (Ti), or a semiconductor material such as polysilicon. For example, the first upper gate electrode 130U1 may include polysilicon, and the other gate electrodes 130 may include a metal material.

[0038] The interlayer insulating layer 120 may be disposed between the gate electrodes 130 other than the first upper gate electrode 130U1. Like the gate electrodes 130, the interlayer insulating layers 120 may also be disposed to be spaced apart from each other in a direction perpendicular to the upper surface of the plate layer 101. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride. In some implementations, the thickness of each interlayer insulating layer 120 may vary.

[0039] The first channel structure CH extends through the gate electrode 130 except the first upper gate electrode 130U1 in the Z direction perpendicular to the X direction and the Y direction, and may be connected to the plate layer 101. Each first channel structure CH forms a memory cell string together with a corresponding one of the second channel structures SCH, and the first channel structures CH together with the second channel structures SCH may be arranged to be spaced apart from each other in rows and columns on the plate layer 101. Figure 1 In the embodiment, the first channel structures CH may be arranged to form a grid pattern in the XY plane together with the dummy structures DH, or may be arranged in a zigzag shape in one direction. The first channel structures CH may be regularly arranged together with the dummy structures DH, each of the first channel structures CH may have a pillar shape, and may have an inclined side surface so that as the distance to the board layer 101 decreases, the cross-section of the first channel structure CH in the XY plane becomes smaller.

[0040] The first channel structures CH may be arranged at a first pitch P1 in the X direction, at a second pitch P2 in the Y direction, and at a third pitch P3 in the W direction inclined relative to the X direction and the Y direction. In some implementations, the first pitch P1 may be greater than the second pitch P2 and the third pitch P3. However, at least portions of the first pitch P1, the second pitch P2, and the third pitch P3 may be the same or different from each other, and their relative sizes may vary in some implementations.

[0041] exist Figure 3A and Figure 3B , each first channel structure CH may include a first channel layer 140 disposed in a first channel hole, a first gate dielectric layer 145, a first channel buried insulating layer 147, and a first channel pad 149. The first channel layer 140 may be formed in a ring shape surrounding the first channel buried insulating layer 147 inside, and may have a pillar shape (such as a cylinder or a prism) without the first channel buried insulating layer 147 depending on some implementations. The lower portion of the first channel layer 140 may be connected to the first horizontal conductive layer 102. The first channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon.

[0042] The first gate dielectric layer 145 may be disposed between the gate electrode 130 and the first channel layer 140. Although not shown, the first gate dielectric layer 145 may include a tunneling layer, a data storage layer, and a blocking layer sequentially stacked from the first channel layer 140. The tunneling layer may tunnel charges into the data storage layer, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4), silicon oxynitride (SiON), or a combination thereof. The data storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. In some implementations, at least a portion of the first gate dielectric layer 145 may extend along the gate electrode 130 in a horizontal direction.

[0043] The first channel buried insulating layer 147 may include an insulating material, for example, silicon oxide, silicon nitride, or silicon oxynitride. The first channel pad 149 may be disposed only on an upper end of the upper channel structure CH2 provided at an upper portion of the first channel structure CH. The first channel pad 149 may include, for example, doped polysilicon.

[0044] The first channel structure CH may include a lower channel structure CH1 and an upper channel structure CH2 stacked vertically. The first channel structure CH may have a shape in which the lower channel structure CH1 and the upper channel structure CH2 are connected, and the connection area may have a curved portion due to a difference in width. However, in some implementations, the number of channel structures stacked in the Z direction may vary. The first channel layer 140, the first gate dielectric layer 145, and the first channel buried insulating layer 147 may extend continuously between the lower channel structure CH1 and the upper channel structure CH2.

[0045] The dummy structure DH extends through the gate electrode 130 other than the first upper gate electrode 130U1 in the Z direction and may be connected to the board layer 101. The dummy structure DH may be arranged in a specific pattern together with the first channel structure CH. The dummy structure DH may be arranged in a row outside the outermost row of the first channel structure CH in the X direction. The dummy structure DH may be arranged in rows on both sides of each first separation region MS in the X direction. The dummy structure DH may be arranged between the first channel structure CH and the first separation region MS. A portion of the side surface of each dummy structure DH may contact the first separation region MS.

[0046] Each dummy structure DH can be Figure 1 In the plan view, each first channel structure CH may have a circular shape, and each first channel structure CH may also have the same circular shape in the plan view. In some implementations, the dummy structure DH and the first channel structure CH may have a cylindrical shape of substantially the same size. In the plan view, the first separation region MS may contact a portion of the circular side surface of each dummy structure DH.

[0047] The dummy structure DH may have the same internal structure as the first channel structure CH. Each dummy structure DH may include a first channel layer 140 disposed in a first channel hole, a first gate dielectric layer 145, a first channel buried insulating layer 147, and a first channel pad 149. In each dummy structure DH, the shape of the layer may be substantially the same as the shape of the layer in each first channel structure CH.

[0048] However, unlike the first channel structure CH, the dummy structure DH may not form a memory cell string within the semiconductor device 100. The dummy structure DH may not be electrically connected to the cell interconnect structure. Therefore, the second channel structure SCH may not be connected to the dummy structure DH, and all upper surfaces of the dummy structure DH may be covered by the horizontal insulating layer 150. In the lower region of the dummy structure DH, the first channel layer 140 may be connected to the first horizontal conductive layer 102. However, the detailed shape of the first horizontal conductive layer 102 in the region where the dummy structure DH contacts the first separation region MS is not limited to Figure 3B Shape shown.

[0049] The second channel structure SCH extends through the first upper gate electrode 130U1 in the Z direction and may be physically and electrically connected to the first channel structure CH, respectively. The second channel structures SCH may be disposed on the first channel structures CH, respectively. In some implementations, at least a portion of the second channel structure SCH is not aligned with the first channel structure CH and may be shifted or placed misaligned in the X direction. In some implementations, a portion of the second channel structure SCH may have a misalignment length different from the misalignment length of the first channel structure CH. The diameter of the second channel structure SCH may be smaller than the diameter of the first channel structure CH, but is not limited thereto.

[0050] exist Figure 3A In the embodiment, each second channel structure SCH may include a second channel layer 160 disposed in the second channel hole, a second gate dielectric layer 165, a second channel buried insulating layer 167, and a second channel pad 169. The second channel layer 160 may be formed in a ring shape surrounding the inner second channel buried insulating layer 167. A lower portion of the second channel layer 160 may be connected to a connection pad 151, and may be electrically connected to the first channel layer 140 of the first channel structure CH through the connection pad 151.

[0051] The second gate dielectric layer 165 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. With respect to the materials of the second channel layer 160, the second channel buried insulating layer 167, and the second channel pad 169, the above description of the first channel layer 140, the first channel buried insulating layer 147, and the first channel pad 149 may be applied respectively.

[0052] The horizontal insulating layer 150 may be disposed between the first channel structure CH and the second channel structure SCH and extend horizontally. The horizontal insulating layer 150 may be disposed between the first upper gate electrode 130U1 and the second upper gate electrode 130U2. The horizontal insulating layer 150 serves as an etching stop layer when forming the second channel structure SCH, and may also be a layer used when forming the connection pad 151.

[0053] The horizontal insulating layer 150 includes an insulating material, and may include a different material from the second cell area insulating layer 194 and the third cell area insulating layer 196. The horizontal insulating layer 150 may include a nitride, for example, at least one of SiN, SiON, SiCN, and SiOCN.

[0054] The connection pad 151 may penetrate the horizontal insulating layer 150 between the first channel structure CH and the second channel structure SCH to electrically connect the first channel layer 140 and the second channel layer 160. The connection pad 151 is formed by partially removing the horizontal insulating layer 150 and may have an upper surface coplanar with the upper surface of the horizontal insulating layer 150. The connection pad 151 may be arranged in a form that partially recesses the first channel pad 149. However, the detailed arrangement of the connection pad 151 may vary in various implementations. The connection pad 151 may include a conductive material, such as polysilicon. In some embodiments, the connection pad 151 may be integrated with the second channel layer 160.

[0055] The first separation region MS may be disposed to extend in the Y direction through the gate electrodes 130 except for the first upper gate electrode 130U1. Figure 1 In the embodiment, the first separation regions MS may be arranged in parallel with each other. The gate electrodes 130 separated by the first separation regions MS may form a memory block. The scope of the memory block is not limited thereto. Figure 2 In the embodiment, the first separation region MS penetrates the gate electrode 130 stacked on the plate layer 101 , and may further penetrate the underlying first horizontal conductive layer 102 and second horizontal conductive layer 104 and be connected to the plate layer 101 .

[0056] The first separation region MS may contact the dummy structure DH. For example, in some implementations, the first separation region MS may be located between rows of dummy structures DH and may contact a portion of each of the dummy structures DH forming the rows. Figure 1In the embodiment, the first separation region MS may surround a portion of the side surface of each dummy structure DH. In a plan view, a portion of the side surface of the first separation region MS contacts the dummy structure DH, and the other portion thereof may be located between the dummy structures DH. The side surface of the first separation region MS may have a tortuosity corresponding to the side surface of the dummy structure DH. Even in an area where the first separation region MS does not contact the dummy structure DH, the side surface of the first separation region MS may have a tortuosity corresponding to the first channel structure CH and the dummy structure DH. Figure 2 In the embodiment, the entire side surface of each of the dummy structures DH from top to bottom may be in contact with the first separation region MS in some areas.

[0057] The width L1 of the first separation region MS in the X direction may be greater than the first pitch P1 of the first channel structure CH in the X direction. For example, the width L1 may be greater than the first pitch P1 and less than twice the first pitch P1. For example, the width L1 may be in a range from about 400 nm to about 700 nm. In some implementations, the length L2 between adjacent first separation regions MS in the X direction may be the same. The length L2 may correspond to the length of the memory block. The first separation region MS may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0058] exist Figure 2 In the embodiment of the present invention, the second separation region US may penetrate the first upper gate electrode 130U1 disposed at the top among the gate electrodes 130. The second separation region US may extend in the Y direction, and a plurality of second separation regions US may be disposed between adjacent first separation regions MS. The second separation region US may divide the first upper gate electrode 130U1 into a plurality of parts between the first separation regions MS. The upper surface of the second separation region US may be located at substantially the same level as the upper surface of the second channel structure SCH. The second separation region US may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0059] The column 180 may form a cell interconnect structure electrically connected to the memory cells in the memory cell region CELL. The column 180 is connected to the second channel structure SCH and may be electrically connected to the first channel structure CH and the second channel structure SCH. The column 180 has a column shape and may be connected to the second channel pad 169 of the second channel structure SCH. The column 180 may electrically connect the first channel structure CH and the second channel structure SCH to the bit line 185. The bit line 185 may be connected to the column 180 and electrically connected to the first channel structure CH and the second channel structure SCH. The column 180 and the bit line 185 may include a metal, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0060] The first to third cell region insulating layers 192, 194, and 196 may be disposed on the gate electrode 130. The first cell region insulating layer 192 covers the second upper gate electrode 130U2, the second cell region insulating layer 194 covers the horizontal insulating layer 150, and the third cell region insulating layer 196 may cover the first upper gate electrode 130U1. The first to third cell region insulating layers 192, 194, and 196 may be formed of an insulating material, and each may be formed of a plurality of insulating layers.

[0061] Figure 4A and Figure 4B is a schematic plan view of an exemplary semiconductor device according to some implementations and shows a circuit corresponding to Figure 1 In the area. Figure 4A In the semiconductor device 100a, two rows of dummy structures DH may be disposed on one side of each first separation region MSa in the X direction. The first separation region MSa completely surrounds the side surface of the dummy structure DH in the first row closest to the first separation region MSa, and may surround a portion of the side surface of each dummy structure DH in the second row. Therefore, the first separation region MSa may have a relatively increased width L1a. In some implementations, three or more rows of dummy structures DH may be disposed on one side of each first separation region MSa in the X direction.

[0062] exist Figure 4B In the semiconductor device 100b, the side surface of the first separation region MSb may have a relatively more curved shape in the region extending between the dummy structures DH. Figure 1 In contrast, the second pitch P2b of the first channel structure CH in the Y direction and the third pitch P3b in the W direction may be relatively large. Therefore, the degree of curvature of the side surface of the first separation region MSb may vary depending on the pitch at which the first channel structure CH and the dummy structure DH are arranged.

[0063] Figure 5 is a schematic plan view of an exemplary semiconductor device according to some implementations. Figure 5 In the semiconductor device 100c, the first memory block BLK1 and the second memory block BLK2 defined by the first partition region MS may have different lengths. The first memory block BLK1 and the second memory block BLK2 may be adjacent to or spaced apart from each other. For example, the first memory block BLK1 may be a main memory block, and the second memory block BLK2 may be a spare memory block. Therefore, the first channel structure CH in the second memory block BLK2 may also be electrically connected to the above reference Figure 1 , Figure 3A and Figure 3B The second channel structure SCH, the pillar 180 and the bit line 185 are described.

[0064] The length L3 of the second memory block BLK2 may be smaller than the length L2 of the first memory block BLK1. The length L2 of the first memory block BLK1 corresponds to the length between the first separation regions MS on both sides of the first memory block BLK1, and the length L3 of the second memory block BLK2 may correspond to the length between the first separation regions MS on both sides of the second memory block BLK2. Therefore, the pitch between the first separation regions MS forming the second memory block BLK2 may be smaller than the pitch between the first separation regions MS forming the first memory block BLK1. The number of rows of the first channel structure CH constituting the second memory block BLK2 along the Y direction may be less than the number of rows of the first channel structure CH constituting the first memory block BLK1 along the Y direction.

[0065] In some implementations, the width L1 of the first separation regions MS is constant, and the distances L2 and L3 between the first separation regions MS may be different in a plurality of regions. Fig.11A and Fig. 11B ) to form the first separation region MS, so the position where the first separation region MS is formed can be easily adjusted, as shown below with reference to 9A to 15B described.

[0066] FIG. 6A to FIG. 6C is a schematic cross-sectional view of an exemplary semiconductor device according to some implementations and shows a circuit corresponding to Figure 2 In the area. Fig. 6A In the semiconductor device 100d, the second channel structure SCH may be further disposed on the dummy structure DH. However, the second channel structure SCH on the dummy structure DH may not be connected to the pillar 180. Therefore, the second channel structure SCH on the dummy structure DH may also be a dummy structure.

[0067] exist Figure 6B In the semiconductor device 100e, the dummy structure DHe may have a structure different from that of the first channel structure CH. In the region where the dummy structure DHe contacts the first separation region MS, the first gate dielectric layer 145 disposed at the outermost portion may be removed. Therefore, the first gate dielectric layer 145 of the dummy structure DHe may have a shape corresponding to a portion of the first gate dielectric layer 145 of the first channel structure CH. However, the first channel layer 140 of the dummy structure DHe may have a shape corresponding to the first channel layer 140 of the first channel structure CH. In some implementations, the dummy structure DHe may have a cylindrical shape smaller than that of the first channel structure CH.

[0068] In some implementations, in the dummy structure DHe, only a portion of the layers forming the first gate dielectric layer 145 (eg, the barrier layer described above) may be removed.

[0069] exist Figure 6C In the semiconductor device 100f, the dummy structure DHf may have a structure different from the first channel structure CH. In the lower region of the region where the first separation region MS contacts the dummy structure DHf, the first gate dielectric layer 145 disposed at the outermost portion may be partially removed. For example, the first gate dielectric layer 145 may be partially removed at a level lower than the lowermost second lower gate electrode 130L2 (e.g., at a level lower than the upper surface of the second horizontal conductive layer 104). However, the first channel layer 140 of the dummy structure DHf may have a shape corresponding to the first channel layer 140 of the first channel structure CH. In some implementations, the region from which the first gate dielectric layer 145 of the dummy structure DHf is removed may be changed in various ways, and the thickness of the removal may also vary.

[0070] Figure 7 is a schematic cross-sectional view of an exemplary semiconductor device according to some implementations. Figure 7 In the embodiment, the semiconductor device 100g may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded using a wafer bonding method.

[0071] Refer to the above Figure 1 and Figure 2 The description of the peripheral circuit region PERI described may be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 may further include a first bonding via 295, a first bonding metal layer 298, and a first bonding insulating layer 299 as a bonding structure. The first bonding via 295 may be disposed on an upper portion of the uppermost circuit interconnection line 280 and connected to the circuit interconnection line 280. At least a portion of the first bonding metal layer 298 may be connected to the first bonding via 295 on the first bonding via 295. The first bonding metal layer 298 may be connected to the second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298 together with the second bonding metal layer 198 may provide an electrical connection path for bonding the first semiconductor structure S1 and the second semiconductor structure S2.

[0072] The first bonding metal layer 298 may not be connected to the circuit interconnection line 280 at the bottom, and may be provided only for bonding. The first bonding via 295 and the first bonding metal layer 298 may include a conductive material, such as copper (Cu). The first bonding insulating layer 299 may be provided around the first bonding metal layer 298. The first bonding insulating layer 299 may also be used as a diffusion barrier for the first bonding metal layer 298, and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0073] For the second semiconductor structure S2, unless otherwise specified, the above references may be applied. Figures 1 to 3B The second semiconductor structure S2 may further include a lower contact plug 182 and a cell interconnection line 184 as a cell interconnection structure, and may further include a second bonding via 195, a second bonding metal layer 198, and a second bonding insulating layer 199 as a bonding structure. The second semiconductor structure S2 may further include a passivation layer 106 covering the upper surface of the plate layer 101.

[0074] The lower contact plug 182 may be connected to the bit line 185, and the cell interconnection line 184 may be connected to the lower contact plug 182. However, in example embodiments, the number of layers and arrangement of the contact plugs and interconnection lines forming the cell interconnection structure may vary. The lower contact plug 182 and the cell interconnection line 184 may be formed of a conductive material, and may include, for example, at least one of tungsten (W), aluminum (Al), and copper (Cu).

[0075] The second bonding via 195 and the second bonding metal layer 198 may be disposed below the lowermost cell interconnection line 184. The second bonding via 195 connects the cell interconnection line 184 and the second bonding metal layer 198, and the second bonding metal layer 198 may be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 may be connected to the first bonding insulating layer 299 of the first semiconductor structure S1 by bonding. The second bonding via 195 and the second bonding metal layer 198 may include a conductive material, such as copper (Cu). The second bonding insulating layer 199 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0076] The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded by bonding the first bonding metal layer 298 and the second bonding metal layer 198 and bonding the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding of the first bonding metal layer 298 and the second bonding metal layer 198 may be, for example, copper (Cu) to copper (Cu) bonding, and the bonding of the first bonding insulating layer 299 and the second bonding insulating layer 199 may be, for example, dielectric to dielectric bonding, such as SiCN to SiCN bonding. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded by hybrid bonding, which includes copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0077] The passivation layer 106 may be disposed on the upper surface of the board layer 101 and may protect the semiconductor device 100g. The passivation layer 106 may include at least one of insulating materials such as silicon oxide, silicon nitride, and silicon carbide, and may be formed of a plurality of insulating layers in some implementations.

[0078] In some implementations, the second semiconductor structure S2 may not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (see Figure 2 In the first channel layer 140 (see Figure 3B ) in a state where the upper end thereof is exposed, the first channel structure CH may be directly connected to the plate layer 101. However, the electrical connection form of the first channel structure CH and the common source line may be changed in some implementations, and the first channel structure CH and the source structure SS may also have the same Figure 2 The same structure as the example implementation is shown.

[0079] Figures 8 to 17 is a schematic diagram illustrating an exemplary method of manufacturing a semiconductor device according to some implementations. Figure 8 , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig.16 and Fig.17 The corresponding Figure 2 area, Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A The corresponding Figure 1 area.

[0080] exist Figure 8In the embodiment, the circuit element 220, the circuit interconnect structure and the peripheral region insulating layer 290 forming the peripheral circuit region PERI can be formed on the substrate 201. First, the device isolation layer 210 is formed in the substrate 201, and the circuit gate dielectric layer 222 and the circuit gate electrode 225 can be sequentially formed on the substrate 201. The device isolation layer 210 can be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 can be formed of silicon oxide, and the circuit gate electrode 225 can be formed of at least one of polysilicon and a metal silicide layer, but is not limited thereto. Next, the impurity region 205 and the spacer layer 224 on both sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed. In some implementations, the spacer layer 224 can be composed of multiple layers. The impurity region 205 can be formed by performing an ion implantation process.

[0081] In the circuit interconnection structure, the circuit contact plug 270 may be formed by forming a portion of the peripheral region insulating layer 290, then partially etching and removing it and filling it with a conductive material. The circuit interconnection line 280 may be formed, for example, by depositing a conductive material and then patterning the conductive material.

[0082] The peripheral region insulating layer 290 may be composed of a plurality of insulating layers. The peripheral region insulating layer 290 may be formed by a plurality of steps of forming a circuit interconnection structure. As a result, a peripheral circuit region PERI may be formed.

[0083] exist Fig.9A and Fig. 9B In the embodiment, on the peripheral circuit region PERI, a plate layer 101, a horizontal sacrificial layer 110, and a second horizontal conductive layer 104 providing a memory cell region CELL may be formed, sacrificial insulating layers 118 and interlayer insulating layers 120 may be alternately stacked to form a lower mold structure, and after forming a lower vertical sacrificial layer 119L, an upper mold structure may be formed. The plate layer 101 may be formed on the peripheral region insulating layer 290. The plate layer 101 may be made of, for example, polysilicon and may be formed by a CVD process. The polysilicon forming the plate layer 101 may contain impurities.

[0084] The first horizontal insulating layer 111 and the second horizontal insulating layer 112 forming the horizontal sacrificial layer 110 may be alternately stacked on the board layer 101. The horizontal sacrificial layer 110 may be Figure 2In some implementations, the first horizontal insulating layer 111 may include a material different from that of the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 is formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 is formed of the same material as the sacrificial insulating layer 118. The second horizontal conductive layer 104 may be formed on the horizontal sacrificial layer 110. In addition, a lower mold structure may be formed on the second horizontal conductive layer 104 in the first channel structure CH (see Figure 2 ) of the lower channel structure CH1 (see Figure 2 ) at the height set by the .

[0085] The sacrificial insulating layer 118 may be replaced by the gate electrode 130 through a subsequent process (see Figure 2 ). The sacrificial insulating layer 118 may be formed of a material different from the interlayer insulating layer 120, and may be formed of a material that can be etched with an etching selectivity relative to the interlayer insulating layer 120 under specific etching conditions. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from the interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some implementations, the thickness of the interlayer insulating layer 120 may not all be the same. The thickness of the interlayer insulating layer 120 and the sacrificial insulating layer 118 and the number of layers may vary from the thickness and number shown.

[0086] The lower vertical sacrificial layer 119L may be formed at a position corresponding to the lower channel structure CH1. The lower vertical sacrificial layer 119L may be further formed at a position corresponding to the lower channel structure CH1. Figure 2 The lower region of the dummy structure DH and the region corresponding to a portion of the first separation region MS. Fig.9A In the embodiment of the present invention, the lower vertical sacrificial layer 119L may be regularly arranged in the entire region where the first channel structure CH, the dummy structure DH, and the first separation region MS are to be disposed. The lower vertical sacrificial layer 119L may be formed after forming a hole penetrating the lower mold structure, depositing a material forming the lower vertical sacrificial layer 119L in the hole, and performing a planarization process. The lower vertical sacrificial layer 119L may include, for example, carbon (C), but is not limited thereto.

[0087] The upper mold structure may form an upper channel structure CH2 (see FIG. Figure 2 ) is set at a height. The upper mold structure can be formed by alternately stacking sacrificial insulating layers 118 and interlayer insulating layers 120 in the same manner as the lower mold structure. A first cell region insulating layer 192 can be formed on the uppermost sacrificial insulating layer 118.

[0088] exist Fig. 10A and Fig. 10BIn the embodiment, the upper vertical sacrificial layer 119U may be formed by penetrating the upper mold structure. The upper vertical sacrificial layers 119U may be formed on the lower vertical sacrificial layers 119L, respectively. The upper vertical sacrificial layers 119U may be connected to the lower vertical sacrificial layers 119L, respectively. The upper vertical sacrificial layer 119U may include the same material as the lower vertical sacrificial layer 119L. The upper vertical sacrificial layer 119U may include, for example, carbon (C), but is not limited thereto.

[0089] exist Fig.11A and Fig. 11B In the embodiment of the present invention, a first channel structure CH may be formed. First, a first channel hole may be formed by removing portions of the lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U. For example, when the lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U include carbon (C), portions of the lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U may be removed by an ashing process.

[0090] In with Figure 2 In the area corresponding to the position of the first separation region MS, the lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U may be retained without being removed. Fig.11A As shown, two rows of lower vertical sacrificial layers 119L and upper vertical sacrificial layers 119U may remain at a predetermined interval in the Y direction. However, in some implementations, the number and interval of the rows of the remaining lower vertical sacrificial layers 119L and upper vertical sacrificial layers 119U may be selected in various ways.

[0091] The first channel structure CH may be formed by sequentially depositing at least a portion of the first gate dielectric layer 145, the first channel layer 140, the first channel buried insulating layer 147, and the first channel pad 149 in the first channel hole. The first gate dielectric layer 145 may be formed to have a uniform thickness using an ALD or CVD process. In some implementations, the first gate dielectric layer 145 may be formed in whole or in part, and a portion extending perpendicularly to the plate layer 101 along the first channel structure CH may be formed in this operation. The first channel layer 140 may be formed on the first gate dielectric layer 145 within the first channel hole. The first channel buried insulating layer 147 is formed to fill the first channel hole and may be formed of an insulating material. The first channel pad 149 may be formed after partially removing the first channel buried insulating layer 147. The first channel pad 149 may be formed of a conductive material (e.g., polysilicon). In some implementations, the first channel structure CH is formed using portions of the lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U regularly arranged over the entire area, and may be formed in a uniform size.

[0092] exist Fig. 12A and Fig. 12BIn the embodiment, the lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U may be removed to form a first opening OP1. The first opening OP1 may be formed by removing the remaining lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U. The lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U may be removed by, for example, an ashing process.

[0093] exist Fig.13A and Fig. 13B In the embodiment of the present invention, the first opening OP1 can be enlarged to form the second opening OP2. The second opening OP2 can be formed by connecting adjacent first openings OP1 to each other by enlarging the size of the first opening OP1. The second opening OP2 can be formed, for example, by partially removing the stacked structure of the interlayer insulating layer 120 and the sacrificial insulating layer 118 exposed by the first opening OP1 using a wet etching process. Each first opening OP1 can be enlarged by a length or more, and adjacent first openings OP1 can be connected to each other by the length. For example, each first opening OP1 can be enlarged in the range of about 30nm to about 60nm on one side.

[0094] At least a portion of the first channel structure CH may be exposed through the second opening OP2, and a dummy structure DH may be generated. A portion of a side surface of each dummy structure DH is exposed through the second opening OP2, and the other portion may contact the stacked structure of the interlayer insulating layer 120 and the sacrificial insulating layer 118. Figure 6B and Figure 6C , the dummy structure DH can be used in this operation and / or in reference to Fig.14A and Fig. 14B A portion of the first gate dielectric layer 145 is removed to form a subsequent process step as described.

[0095] exist Fig.14A and Fig. 14B In the embodiment, the first horizontal conductive layer 102 may be formed, and the sacrificial insulating layer 118 may be removed. First, while forming a separate sacrificial spacer layer in the second opening OP2, an etch-back process is performed to selectively remove the horizontal sacrificial layer 110, and the exposed first gate dielectric layer 145 may also be removed (see FIG. Figure 3B After forming the first horizontal conductive layer 102 by depositing a conductive material in a region where the horizontal sacrificial layer 110 is removed, the sacrificial spacer layer may be removed within the second opening OP2.

[0096] The sacrificial insulating layer 118 may be removed selectively with respect to the interlayer insulating layer 120, the second horizontal conductive layer 104, and the first channel structure CH using, for example, wet etching. The tunnel portion TL may be formed in a region where the sacrificial insulating layer 118 has been removed.

[0097] exist Fig.15A and Fig. 15B In the embodiment of the present invention, a second lower gate electrode 130L2, a first lower gate electrode 130L1, a memory gate electrode 130M, and a second upper gate electrode 130U2 are formed, and a first separation region MS may be formed. Among the gate electrodes 130, a first gate electrode surrounding the first channel structure CH may be formed, such as the second lower gate electrode 130L2, the first lower gate electrode 130L1, the memory gate electrode 130M, and the second upper gate electrode 130U2. The first gate electrode may be formed by depositing a conductive material on the tunnel portion TL. In some implementations, a portion of the first gate dielectric layer 145 may be first formed before forming the first gate electrode. After forming the first gate electrode, the first separation region MS may be formed by depositing an insulating material in the second opening OP2.

[0098] Since the first separation region MS is formed using portions of the lower vertical sacrificial layer 119L and the upper vertical sacrificial layer 119U, the formation position of the first separation region MS in the semiconductor device can be easily adjusted. In addition, since the first separation region MS does not affect the shape of the first channel structure CH, the difficulty of designing the semiconductor device can be reduced.

[0099] exist Fig.16 In the embodiment of the present invention, a horizontal insulating layer 150 and a second cell region insulating layer 194 may be formed, and a first upper gate electrode 130U1 may be formed. The horizontal insulating layer 150 may be formed to cover the upper surface of the first channel structure CH, the upper surface of the dummy structure DH, and the upper surface of the first separation region MS. Next, the second cell region insulating layer 194 and the first upper gate electrode 130U1 may be sequentially formed. The first upper gate electrode 130U1 may be formed by a deposition process and a patterning process. For example, the first upper gate electrode 130U1 may include polysilicon.

[0100] exist Fig.17 In the process, a second channel structure SCH penetrating the first upper gate electrode 130U1 may be formed, and a pillar 180 may be formed. First, a third cell area insulating layer 196 may be formed on the first upper gate electrode 130U1.

[0101] The second channel structures SCH may be formed to correspond to the first channel structures CH, respectively. First, after forming the second channel hole penetrating the first upper gate electrode 130U1, the second gate dielectric layer 165 (see Figure 3A Then, a lower hole is formed in the bottom surface of the second channel hole and extends through the second gate dielectric layer 165 and the sacrificial layer to the horizontal insulating layer 150, the first channel pad 149 (see Figure 3A) can be exposed by partially removing the horizontal insulating layer 150 exposed through the lower hole. After forming the connection pad 151 in the region where the horizontal insulating layer 150 is removed and removing the sacrificial layer, in each second channel hole, as shown in FIG. Figure 3A As shown, a second channel layer 160, a second channel buried insulating layer 167, and a second channel pad 169 are sequentially formed, and thus, a second channel structure SCH can be formed. Each layer in the second channel structure SCH can be formed in the same manner as in the first channel structure CH. The lower portion of the second channel layer 160 can be connected to the connection pad 151.

[0102] The pillars 180 may each be formed on the second channel structure SCH. Figure 2 , the semiconductor device 100 may be manufactured by forming the bit line 185 on the pillar 180 .

[0103] Fig.18 is a diagram schematically illustrating an exemplary data storage system including a semiconductor device according to some implementations. Fig.18 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0104] The semiconductor device 1100 may be a non-volatile memory device, such as the one described above with reference to Figures 1 to 7 The NAND flash memory device described herein. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some implementations, the first structure 1100F may be placed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second upper gate lines UL1 and UL2, first and second lower gate lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0105] In the second structure 1100S, each memory cell string CSTR includes lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the upper transistors UT1 and UT2 and the lower transistors LT1 and LT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary depending on the implementation.

[0106] In some implementations, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0107] In some implementations, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation to erase data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0108] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word line WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0109] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection interconnect 1135 extending from the first structure 1100F to the second structure 1100S.

[0110] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some implementations, the data storage system 1000 may include a plurality of semiconductor devices 1100 , in which case the controller 1200 may control the plurality of semiconductor devices 1100 .

[0111] The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a controller interface 1221 that processes communication with the semiconductor device 1100. Through the controller interface 1221, a control command for controlling the semiconductor device 1100, data to be written to the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100, etc. may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0112] Fig.19 is a perspective view schematically illustrating an exemplary data storage system including a semiconductor device according to some implementations. Fig.19 In the embodiment, the data storage system 2000 includes a mainboard 2001, a controller 2002 mounted on the mainboard 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 can be connected to the controller 2002 by an interconnection pattern 2005 formed on the mainboard 2001. The mainboard 2001 may include a connector 2006, and the connector 2006 includes a plurality of pins connected to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some implementations, the data storage system 2000 may communicate with the external host through any one of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In some implementations, the data storage system 2000 may operate with power supplied from an external host through the connector 2006. The data storage system 2000 may further include a power management integrated circuit (PMIC) that distributes power supplied from an external host to the controller 2002 and the semiconductor package 2003 .

[0113] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operation speed of the data storage system 2000. The DRAM 2004 can be a buffer memory to alleviate the speed difference between the external host and the semiconductor package 2003 as a data storage space. The DRAM 2004 included in the data storage system 2000 can also operate as a high-speed cache memory. During the control operation of the semiconductor package 2003, a space for temporarily storing data can be provided. When the data storage system 2000 includes the DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 can further include a DRAM controller for controlling the DRAM 2004.

[0114] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0115] The package substrate 2100 may be a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.18 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the above reference Figures 1 to 7 A semiconductor device is described.

[0116] In some implementations, the connection structure 2400 may be a bonding wire electrically connecting the input / output pad 2210 and the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to some implementations, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through electrode (through silicon via, TSV) instead of a bonding wire type connection structure 2400.

[0117] In some implementations, the controller 2002 and the semiconductor chip 2200 may be included in one package. For example, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer different from the mainboard 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through wiring formed on the interposer.

[0118] Fig. 20 is a schematic diagram illustrating an exemplary semiconductor package according to some implementations. Fig.19 A cross-sectional view of the line II-II'. Fig. 20 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, a package upper pad 2130 disposed on the upper surface of the package substrate body 2120, a lower pad 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface of the package substrate body 2120, and an internal interconnect 2135 electrically connecting the package upper pad 2130 and the lower pad 2125 inside the package substrate body 2120. The lower pad 2125 may be connected to a conductive connector 2800 such as Fig.19 An interconnection pattern 2005 of a main board 2001 of a data storage system 2000 is shown.

[0119] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral interconnect 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and a separation region 3230 penetrating the gate stack structure 3210, and a bit line 3240 electrically connected to the channel structure 3220. As described above with reference to Figures 1 to 7As described above, the first separation region MS in each semiconductor chip 2200 may be in contact with the dummy structure DH having the same or similar structure as the first channel structure CH.

[0120] Each semiconductor chip 2200 may include a through wiring 3245 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may penetrate the gate stack structure 3210 and may be further disposed outside the gate stack structure 3210. Each semiconductor chip 2200 may further include an input / output connection 3265 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending to the second structure 3200, and the input / output pad 2210 is electrically connected to the input / output connection 3265.

[0121] As described above, by including the first separation region formed using the channel hole, a semiconductor device having improved design freedom and reduced process difficulty and a data storage system including the semiconductor device can be provided.

[0122] Although the present disclosure includes many specific implementation details, these details should not be interpreted as limiting the scope of possible protection. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. On the contrary, various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. In addition, although features may be described above as working in certain combinations, and even initially claimed as such, one or more features from a combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variant of a sub-combination.

Claims

1. A semiconductor device, comprising: a first semiconductor structure; as well as a second semiconductor structure on the first semiconductor structure, Wherein, the second semiconductor structure comprises: Lamellar; a plurality of first gate electrodes stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and spaced apart from each other; a plurality of separation regions, each of the plurality of separation regions extending into at least one first gate electrode of the plurality of first gate electrodes and extending in a second direction perpendicular to the first direction; a plurality of first channel structures, each of the plurality of first channel structures being spaced apart from the plurality of separation regions in a third direction perpendicular to the first direction and the second direction, extending into at least one of the plurality of first gate electrodes, and extending in the first direction; and a plurality of dummy structures contacting the plurality of separation regions, extending into at least one of the plurality of first gate electrodes, and extending in the first direction, wherein each of the plurality of first channel structures and each of the plurality of dummy structures respectively has a circular shape in a plan view, and Each of the plurality of separation regions is in contact with at least a portion of a corresponding side surface of at least one dummy structure of the plurality of dummy structures.

2. The semiconductor device according to claim 1, wherein Each of the plurality of first channel structures and each of the plurality of dummy structures includes a gate dielectric layer and a channel layer sequentially disposed from each of the plurality of first gate electrodes, the gate dielectric layer including a data storage layer.

3. The semiconductor device according to claim 2, wherein: A shape of the channel layer of each of the plurality of first channel structures is substantially the same as a shape of the channel layer of each of the plurality of dummy structures.

4. The semiconductor device according to claim 2, wherein: The gate dielectric layer of each of the plurality of dummy structures has a shape corresponding to a portion of the gate dielectric layer of each of the plurality of first channel structures.

5. The semiconductor device according to claim 1, in, The plurality of first channel structures and the plurality of dummy structures are arranged in a plurality of rows along the second direction, and The plurality of dummy structures are arranged in at least one of the plurality of rows on both sides of each of the plurality of separation regions in the third direction.

6. The semiconductor device according to claim 5, wherein: A portion of each side surface of each of the plurality of separation regions in the third direction is located between adjacent dummy structures of the dummy structures of the at least one row of the plurality of rows.

7. The semiconductor device according to claim 1, in, A first portion of the plurality of partitions are spaced apart by a first length in the third direction, and The second parts of the plurality of partitions are spaced apart in the third direction by a second length that is smaller than the first length.

8. The semiconductor device according to claim 1, wherein The second semiconductor structure further comprises: a second gate electrode on the plurality of first gate electrodes; and A plurality of second channel structures extend into the second gate electrode and are respectively connected to the plurality of first channel structures.

9. The semiconductor device according to claim 8, in, The second semiconductor structure further includes a horizontal insulating layer between each of the plurality of first channel structures and the second gate electrode, and wherein each of the plurality of dummy structures is separated from each of the plurality of second channel structures, and Each of the plurality of dummy structures has an upper surface completely covered by the horizontal insulating layer.

10. The semiconductor device according to claim 1, in, The second semiconductor structure further includes a cell interconnect structure on each of the plurality of first channel structures, the cell interconnect structure being electrically connected to at least one of the plurality of first channel structures, and Each of the plurality of dummy structures is not electrically connected to the cell interconnection structure.

11. The semiconductor device according to claim 1, wherein A width of each of the plurality of separation regions in the third direction is greater than a pitch of the plurality of first channel structures in the third direction.

12. The semiconductor device according to claim 11, wherein The width is in the range from about 400 nm to about 700 nm.

13. A semiconductor device comprising: Lamellar; a plurality of gate electrodes stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and spaced apart from each other; a plurality of channel structures extending into at least one gate electrode of the plurality of gate electrodes, extending in the first direction, and arranged in rows along a second direction perpendicular to the first direction; a plurality of dummy structures, each of the plurality of dummy structures extending outside at least one of the plurality of channel structures and in the first direction, the plurality of dummy structures extending into at least one of the plurality of gate electrodes and arranged in a plurality of rows along the second direction; as well as a plurality of partition regions, each of the plurality of partition regions being between rows of the plurality of rows of the plurality of dummy structures and extending into at least one gate electrode of the plurality of gate electrodes, each of the plurality of partition regions extending in the second direction, wherein each of the plurality of channel structures is arranged at a first pitch in a third direction perpendicular to the first direction and the second direction, and Wherein, a width of each of the plurality of separation regions is greater than the first pitch.

14. The semiconductor device according to claim 13, wherein: The plurality of separation regions are arranged at a second pitch in the first region, and are arranged at a third pitch smaller than the second pitch in the second region.

15. The semiconductor device according to claim 14, wherein: The second area includes spare memory blocks.

16. The semiconductor device according to claim 14, further comprising: A plurality of pillars are on and electrically connected to the plurality of channel structures in both the first region and the second region.

17. The semiconductor device according to claim 13, wherein: Each of the plurality of separation regions contacts at least one dummy structure of the plurality of dummy structures.

18. The semiconductor device according to claim 13, wherein: Each of the plurality of separation regions has a curved side surface corresponding to a portion of a side surface of each of the plurality of dummy structures.

19. A data storage system comprising: A semiconductor memory device comprising a first semiconductor structure including a circuit element, a second semiconductor structure on a surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element; as well as a controller electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device, Wherein, the second semiconductor structure comprises: Lamellar; a plurality of gate electrodes stacked on the plate layer in a first direction perpendicular to an upper surface of the plate layer and spaced apart from each other; a plurality of channel structures, each of the plurality of channel structures extending in the first direction and extending into at least one gate electrode of the plurality of gate electrodes, the plurality of channel structures being arranged in a plurality of rows along a second direction perpendicular to the first direction; a plurality of dummy structures, each of the plurality of dummy structures being outside at least one of the plurality of channel structures and extending into at least one of the plurality of gate electrodes, the plurality of dummy structures extending in the first direction and arranged in a plurality of rows along the second direction; and a plurality of partition regions, each of the plurality of partition regions being between rows of the plurality of rows of the plurality of dummy structures and extending into at least one gate electrode of the plurality of gate electrodes, each of the plurality of partition regions extending in the second direction, The plurality of separation regions surround at least a portion of each of the plurality of dummy structures and are in contact with the plurality of dummy structures.

20. The data storage system according to claim 19, wherein: Each of the plurality of channel structures and each of the plurality of dummy structures have a cylindrical shape, respectively.

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