Semiconductor memory device and electronic system including the same

Abstract

A semiconductor memory device includes: a substrate; a mold structure including a plurality of gate electrodes and a plurality of mold insulating films alternately stacked on the substrate; a channel structure extending in a first direction and penetrating the molding structure, the channel structure including a semiconductor pattern and a ferroelectric film between the semiconductor pattern and the plurality of gate electrodes; a channel pad on the channel structure; and a bit line contact portion connected to the channel pad, in which an uppermost portion of the ferroelectric film protrudes beyond an uppermost gate electrode among the plurality of gate electrodes, the channel pad includes a first portion in contact with the semiconductor pattern, and a second portion in contact with the first portion and the bit line contact portion, the first portion having a first width, and the second portion having a second width. And the second portion has a second width greater than the first width.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits obtained from Korean Patent Application No. 10-2023-0101929 filed in the Korean Intellectual Property Office on August 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor memory device and / or an electronic system including the semiconductor memory device. For example, the present disclosure relates to a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells and / or an electronic system including the three-dimensional semiconductor memory device. Background Art

[0004] There is a need to increase the integration level of semiconductor memory devices to meet the excellent performance and low prices required by consumers. In the case of semiconductor memory devices, since the integration level is an important factor in determining the price of the product, the increased integration level is particularly desired.

[0005] In the case of two-dimensional or planar semiconductor memory devices, the integration level is mainly determined by the area occupied by the unit memory cell, and is therefore greatly affected by the level of fine pattern forming technology. However, since ultra-expensive devices are required to minimize the pattern, the integration level of two-dimensional semiconductor devices is increasing, but is still limited. Therefore, three-dimensional semiconductor devices including three-dimensionally arranged memory cells have been proposed. Summary of the invention

[0006] Some example embodiments of the present disclosure provide a semiconductor memory device having improved durability and reliability.

[0007] Some example embodiments of the present disclosure also provide electronic systems including semiconductor memory devices having improved durability and reliability.

[0008] However, example embodiments of the present disclosure are not limited to the example embodiments set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an example embodiment of the present disclosure, a semiconductor memory device may include: a substrate; a molded structure including a plurality of gate electrodes and a plurality of molded insulating films alternately stacked on the substrate; a channel structure extending in a first direction and penetrating the molded structure, the channel structure including a semiconductor pattern, and a ferroelectric film between the semiconductor pattern and the plurality of gate electrodes; a channel pad on the channel structure; and a bit line contact connected to the channel pad, wherein an uppermost portion of the ferroelectric film protrudes beyond an uppermost gate electrode among the plurality of gate electrodes, the channel pad including a first portion contacting the semiconductor pattern, and a second portion contacting the first portion and the bit line contact, the first portion having a first width, and the second portion having a second width greater than the first width.

[0010] According to an example embodiment of the present disclosure, a semiconductor memory device may include: a substrate; a molded structure including a plurality of gate electrodes and a plurality of molded insulating films alternately stacked on the substrate; a channel structure extending in a first direction and penetrating the molded structure; and a channel pad, on the channel structure, the channel pad including a first portion having a first width, and a second portion having a second width greater than the first width, wherein the channel structure includes: a semiconductor pattern; a first interface film on the semiconductor pattern; a first ferroelectric film on the first interface film; a second interface film on the first ferroelectric film; and a second ferroelectric film on the second interface film.

[0011] According to an example embodiment of the present disclosure, an electronic system may include: a mainboard; a semiconductor memory device on the mainboard; and a controller on the mainboard and electrically connected to the semiconductor memory device, wherein the semiconductor memory device includes: a substrate; a molded structure including a plurality of gate electrodes and a plurality of molded insulating films alternately stacked on the substrate; a channel structure extending in a first direction and penetrating the molded structure, the channel structure including a semiconductor pattern, and a ferroelectric film between the semiconductor pattern and the plurality of gate electrodes; a channel pad on the channel structure; and a bit line contact connected to the channel pad, wherein an uppermost portion of the ferroelectric film protrudes beyond an uppermost gate electrode among the plurality of gate electrodes, and wherein the channel pad includes a first portion in contact with the semiconductor pattern, and a second portion in contact with the first portion and the bit line contact, the first portion having a first width, and the second portion having a second width greater than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail some illustrative example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0013] Figure 1 is an example block diagram for explaining a semiconductor memory device according to an example embodiment;

[0014] Figure 2 is an example circuit diagram for explaining a semiconductor memory device according to an example embodiment;

[0015] Figure 3 is an example layout diagram for explaining a semiconductor memory device according to an example embodiment;

[0016] Figure 4 is along Figure 3 A cross-sectional view taken along line AA;

[0017] Figure 5 It is used to illustrate Figure 4 An enlarged view of region R1;

[0018] Figure 6 It is used to illustrate Figure 4 An enlarged view of region R2;

[0019] Figure 7 is along Figure 3 A cross-sectional view taken along line BB;

[0020] Figure 8 is a diagram for explaining a semiconductor memory device according to an example embodiment;

[0021] Fig. 9 and Fig.10 is a diagram for explaining a semiconductor memory device according to an example embodiment;

[0022] Fig.11 is a diagram for explaining a semiconductor memory device according to an example embodiment;

[0023] Fig.12 is a diagram for explaining a semiconductor memory device according to an example embodiment;

[0024] Fig.13 is a diagram for explaining a semiconductor memory device according to an example embodiment;

[0025] Figures 14 to 17 is a diagram for explaining intermediate steps of a method for manufacturing a semiconductor memory device according to an example embodiment;

[0026] Fig.18 is an example block diagram for illustrating an electronic system according to an example embodiment;

[0027] Fig.19 is an example perspective view for explaining an electronic system according to an example embodiment; and

[0028] Fig. 20 is along Fig.19 Schematic cross-sectional view taken along line II. DETAILED DESCRIPTION

[0029] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than modifying the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Likewise, A and / or B means A, B, or A and B.

[0030] Although the terms "same", "equal" or "identical" are used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0031] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, the associated numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "about" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0032] The following will refer to Figures 1 to 7 A semiconductor memory device according to example embodiments is described.

[0033] Figure 1 is an example block diagram for explaining a semiconductor memory device according to example embodiments.

[0034] refer to Figure 1 , a semiconductor memory device 10 according to example embodiments includes a memory cell array 20 and a peripheral circuit 30 .

[0035] The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell array 20 may be connected to the peripheral circuit 30 through the bit lines BL, the word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. For example, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL. In addition, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit lines BL.

[0036] The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from outside the semiconductor memory device 10, and may transmit and receive data DATA to and from an external device of the semiconductor memory device 10. The peripheral circuit 30 may include a control logic 37, a row decoder 33, and a page buffer 35. Although not shown, the peripheral circuit 30 may further include various sub-circuits, for example, an input / output circuit, a voltage generating circuit that generates various voltages desired for the operation of the semiconductor memory device 10, and an error correction circuit for correcting errors of the data DATA read from the memory cell array 20.

[0037] The control logic 37 may be connected to the row decoder 33, the input / output circuit, and the voltage generating circuit. The control logic 37 may control the overall operation of the semiconductor memory device 10. The control logic 37 may generate various internal control signals used inside the semiconductor memory device 10 in response to the control signal CTRL. For example, when performing a storage operation such as a program operation or an erase operation, the control logic 37 may adjust the voltage levels supplied to the word lines WL and the bit lines BL.

[0038] The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and may select at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL of the selected memory cell block BLK1 to BLKn. The row decoder 33 may transmit a voltage for performing a storage operation to the word line WL of the selected memory cell block BLK1 to BLKn.

[0039] The page buffer 35 may be connected to the memory cell array 20 through the bit line BL. The page buffer 35 may operate as a write driver or a sense amplifier. For example, at the time of a programming operation, the page buffer 35 may operate as a write driver to apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit line BL. On the other hand, at the time of a read operation, the page buffer 35 may operate as a sense amplifier to read out the data DATA stored in the memory cell array 20.

[0040] Figure 2 is an example circuit diagram for explaining a semiconductor memory device according to example embodiments.

[0041] refer to Figure 2 , a memory cell array (eg, Figure 1 20) may include a common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR.

[0042] The common source line CSL may extend in a first direction (e.g., X direction). In some example embodiments, a plurality of common source lines CSL may be arranged two-dimensionally. For example, a plurality of common source lines CSL may extend in the first direction X while being spaced apart from each other. The common source lines CSL may be electrically applied with the same voltage, or may be applied with different voltages and controlled separately.

[0043] A plurality of bit lines BL may be arranged two-dimensionally. For example, the bit lines BL may each extend in a second direction (e.g., a Y direction) intersecting the first direction X while being spaced apart from each other. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the bit lines BL and the common source line CSL.

[0044] Each cell string CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT disposed between the ground selection transistor GST and the string selection transistor SST. Each memory cell transistor MCT may include a data storage element. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistor MCT may be connected in series.

[0045] The common source line CSL may be commonly connected to the source of the ground selection transistor GST. In addition, the ground selection line GSL, a plurality of word lines WL11 to WL1n and WL21 to WL2n, and a string selection line SSL may be provided between the common source line CSL and the bit line BL. The ground selection line GSL may be used as a gate electrode of the ground selection transistor GST, the word lines WL11 to WL1n and WL21 to WL2n may be used as gate electrodes of the memory cell transistors MCT, and the string selection line SSL may be used as a gate electrode of the string selection transistor SST.

[0046] In some example embodiments, the erase control transistor ECT may be disposed between a common source line CSL and a ground selection transistor GST. The common source line CSL may be commonly connected to a source of the erase control transistor ECT. In addition, an erase control line ECL may be disposed between the common source line CSL and the ground selection line GSL. The erase control line ECL may be used as a gate electrode of the erase control transistor ECT. The erase control transistor ECT may generate a gate induced drain leakage (GIDL) to perform an erase operation of the memory cell array.

[0047] Figure 3 is an example layout diagram for explaining a semiconductor memory device according to example embodiments. Figure 4 is along Figure 3 A cross-sectional view taken along line AA. Figure 5 It is used to illustrate Figure 4 Magnified view of region R1. Figure 6 It is used to illustrate Figure 4 An enlarged view of region R2. Figure 7 is along Figure 3 A cross-sectional view taken along line BB.

[0048] refer to Figures 3 to 7 , a semiconductor memory device according to example embodiments includes a memory cell region CELL and a peripheral circuit region PERI.

[0049] The memory cell region CELL may include a cell substrate 100 , an insulating substrate 101 , mold structures MS1 and MS2 , interlayer insulating films 140 a and 140 b , a channel structure CH, a channel pad 136 , a block isolation region WCf, a bit line BL, a cell contact 162 , a source contact 164 , a through hole 166 , and a first wiring structure 180 .

[0050] The unit substrate 100 may include, for example, a semiconductor substrate, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate. In some example embodiments, the unit substrate 100 may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, etc. In some example embodiments, the unit substrate 100 may include impurities. For example, the unit substrate 100 may include n-type impurities (e.g., phosphorus (P), arsenic (As), etc.).

[0051] The unit substrate 100 may include a cell array region CAR and an extension region EXT.

[0052] A memory cell array including a plurality of memory cells (eg, Figure 1 20) may be disposed on the cell array region CAR. For example, the channel structure CH, the bit line BL, and the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2, etc., which will be described later, may be disposed on the cell array region CAR. In the following description, the surface of the unit substrate 100 on which the memory cell array is disposed may be referred to as the front side of the unit substrate 100. Conversely, the surface of the unit substrate 100 opposite to the front side of the unit substrate 100 may be referred to as the back side of the unit substrate 100.

[0053] The extension region EXT may be disposed around the cell array region CAR. The gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 may be stacked in a step-like manner in the extension region EXT.

[0054] In some example embodiments, the unit substrate 100 may further include a through region THR. The through region THR may be disposed inside the cell array region CAR and the extension region EXT, or may be disposed outside the cell array region CAR and the extension region EXT. A through hole 166 to be described below may be disposed inside the through region THR.

[0055] The insulating substrate 101 may be formed inside the unit substrate 100 of the extension region EXT. The insulating substrate 101 may form an insulating region inside the unit substrate 100 of the extension region EXT. For example, the insulating substrate 101 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide. In some example embodiments, the insulating substrate 101 may be formed inside the unit substrate 100 of the through region THR.

[0056] Although the lower surface of the insulating substrate 101 is merely shown to be coplanar with the lower side of the unit substrate 100 , this is merely an example. As another example, the lower side of the insulating substrate 101 may be lower than the lower side of the unit substrate 100 .

[0057] The mold structures MS1 and MS2 may be formed on the front side of the unit substrate 100. The mold structures MS1 and MS2 include a plurality of gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2, and a plurality of mold insulating films 110 and 115 stacked on the unit substrate 100. Each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 and each of the mold insulating films 110 and 115 may be a layered structure extending parallel to the front side of the unit substrate 100. The gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2 are spaced apart from each other by the mold insulating films 110 and 115 and may be sequentially stacked on the unit substrate 100.

[0058] In some example embodiments, the mold structures MS1 and MS2 may include a first mold structure MS1 and a second mold structure MS2 sequentially stacked on the unit substrate 100 .

[0059] The first mold structure MS1 may include first gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n alternately stacked on the unit substrate 100, and a first mold insulating film 110. In some example embodiments, the first gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n may include an erase control line ECL, ground selection lines GSL1 and GSL2, and a plurality of first word lines WL11 to WL1n sequentially stacked on the unit substrate 100. The ground selection lines GSL1 and GSL2 may include a first ground selection line GSL1 and a second ground selection line GSL2 stacked in sequence. Although the first gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n are shown as including only two ground selection lines GSL1 and GSL2, this is only an example, and of course, the first gate electrodes ECL, GSL1, GSL2, and WL11 to WL1n may include three or more ground selection lines. In some other example embodiments, the erase control line ECL may be omitted.

[0060] The second mold structure MS2 may include second gate electrodes WL21 to WL2n, SSL1, and SSL2 alternately stacked on the first mold structure MS1, and a second mold insulating film 115. In some example embodiments, the second gate electrodes WL21 to WL2n, SSL1, and SSL2 may include a plurality of second word lines WL21 to WL2n, and string selection lines SSL1 and SSL2 sequentially stacked on the first mold structure MS1. The string selection lines SSL1 and SSL2 may include a first string selection line SSL1 and a second string selection line SSL2 stacked in sequence. Although the second gate electrodes WL21 to WL2n, SSL1, and SSL2 are shown as including only two string selection lines SSL1 and SSL2, this is only an example, and of course, the second gate electrodes WL21 to WL2n, SSL1, and SSL2 may include three or more string selection lines.

[0061] The gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2 may each include, but are not limited to, a conductive material such as metal (eg, tungsten (W), cobalt (Co), and nickel (Ni)) or a semiconductor material (eg, silicon).

[0062] Each of the mold insulating films 110 and 115 may include, but is not limited to, an insulating material, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0063] In some example embodiments, the mold structures MS1 and MS2 of the through region THR may include a plurality of mold sacrificial films 112 and 117 and a plurality of mold insulating films 110 and 115 alternately stacked on the unit substrate 100 and / or the insulating substrate 101. Each of the mold sacrificial films 112 and 117 and each of the mold insulating films 110 and 115 may be a layered structure extending parallel to the upper side of the unit substrate 100. The mold sacrificial films 112 and 117 are sequentially stacked on the unit substrate 100 while being spaced apart from each other by the mold insulating films 110 and 115.

[0064] In some example embodiments, the first mold structure MS1 of the through region THR may include a first mold sacrificial film 112 and a first mold insulating film 110 alternately stacked on the unit substrate 100, and the second mold structure MS2 of the through region THR may include a second mold sacrificial film 117 and a second mold insulating film 115 alternately stacked on the first mold structure MS1.

[0065] The mold sacrificial films 112 and 117 may each include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, or silicon oxynitride. In some example embodiments, the mold sacrificial films 112 and 117 may include a material having an etching selectivity relative to the mold insulating films 110 and 115. As an example, the mold insulating films 110 and 115 may include silicon oxide, and the mold sacrificial films 112 and 117 may include silicon nitride.

[0066] Interlayer insulating films 140a and 140b may be formed on the unit substrate 100 to cover the mold structures MS1 and MS2. In some example embodiments, the interlayer insulating films 140a and 140b may include a first interlayer insulating film 140a and a second interlayer insulating film 140b sequentially stacked on the unit substrate 100. The first interlayer insulating film 140a may cover the first mold structure MS1, and the second interlayer insulating film 140b may cover the second mold structure MS2. The interlayer insulating films 140a and 140b may include, for example, but not limited to, at least one of silicon oxide, silicon oxynitride, or a low-k material having a lower dielectric constant than silicon oxide.

[0067] The channel structure CH may be formed inside the mold structures MS1 and MS2 of the cell array region CAR. The channel structure CH may extend in a vertical direction (hereinafter referred to as a third direction Z) intersecting the upper side of the cell substrate 100 and penetrate the mold structures MS1 and MS2. For example, the channel structure CH may have a column shape (e.g., a cylindrical shape) extending in the third direction Z. Therefore, the channel structure CH may intersect each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2.

[0068] like Figure 5 and Figure 6 As shown, the channel structure CH may include a semiconductor pattern 130 , an interface film 133 , and a ferroelectric film 150 .

[0069] The semiconductor pattern 130 may extend in the third direction Z and penetrate the mold structures MS1 and MS2. Although the semiconductor pattern 130 is shown as having a cup shape, this is only an example. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a rectangular barrel shape, and a solid filler shape. The semiconductor pattern 130 may include, for example, (but not limited to) semiconductor materials, such as single crystal silicon, polycrystalline silicon, organic semiconductor substances, and carbon nanostructures.

[0070] The interface film 133 may be disposed on the semiconductor pattern 130. The interface film 133 may be interposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the interface film 133 may extend along the outer side of the semiconductor pattern 130. The interface film 133 may include, for example, silicon oxide, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide (e.g., aluminum oxide (Al2O3)). 2 O 3 )) and at least one of silicon oxide or silicon nitride.

[0071] The ferroelectric film 150 may be disposed on the interface film 133. The ferroelectric film 150 may be in contact with each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. The ferroelectric film 150 may be disposed on the outermost portion of the channel structure CH. The ferroelectric film 150 may be disposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. The ferroelectric film 150 may extend along the outer side of the interface film 133.

[0072] The ferroelectric film 150 may include a ferroelectric material. For example, the ferroelectric film 150 may include a hafnium-based compound having ferroelectric properties. As an example, the ferroelectric film 150 may include HfO 2 , HfZnO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or a combination thereof. In addition, the ferroelectric film 150 may include a ferroelectric material of a perovskite structure, for example, PZT (PbZrxTi1-xO3), BaTiO 3 and PbTiO 3The ferroelectric film 150 may include at least one dopant selected from carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), or lanthanum (La). The ferroelectric film 150 may be made of a crystal structure. For example, the ferroelectric film 150 may have a crystal structure of an orthorhombic system.

[0073] The channel pad 136 may be disposed on the channel structure CH. The channel pad 136 may cover an upper portion of the channel structure CH. For example, the channel pad 136 may cover an upper side of the filling pattern 134, an upper side of the semiconductor pattern 130, and an upper side of the interface film 133. The channel pad 136 may include, for example, but not limited to, doped polysilicon.

[0074] The following will refer to Figure 6 Example shapes of channel pad 136 are described.

[0075] The channel pad 136 may include a first portion 136_1 and a second portion 136_2. The first portion 136_1 of the channel pad 136 may have a first width W1. Here, the first width W1 may be a width of the first portion 136_1 in the first direction X or the second direction Y. The second portion 136_2 of the channel pad 136 may have a second width W2. The second width W2 is greater than the first width W1. Here, the second width W2 may be a width of the second portion 136_2 in the first direction X or the second direction Y.

[0076] The first portion 136_1 of the channel pad 136 may be disposed on an upper side of the semiconductor pattern 130 and an upper side of the filling pattern 134. The first portion 136_1 may cover an upper side of the semiconductor pattern 130 and an upper side of the filling pattern 134. A portion of the interface film 133 may be disposed between the first portion 136_1 and the ferroelectric film 150. In other words, a portion of the interface film 133 may overlap the first portion 136_1 in the first direction X and the second direction Y. The first width W1 of the first portion 136_1 may be the same as the width of the semiconductor pattern 130.

[0077] The second portion 136_2 of the channel pad 136 may be disposed on the first portion 136_1. The second portion 136_2 may be in contact with the bit line contact 182. The second portion 136_2 may be electrically connected to the bit line contact 182. The second portion 136_2 may be disposed between the first portion 136_1 and the bit line contact 182. The second portion 136_2 may cover the upper side of the ferroelectric film 150. The second portion 136_2 may be in contact with the upper side of the interface film 133.

[0078] The uppermost portion of the ferroelectric film 150 may protrude beyond the upper side of the second mold structure MS2. For example, the uppermost portion of the ferroelectric film 150 may protrude in the third direction Z beyond the upper side of the second mold insulating film 115 disposed on the uppermost portion of the second mold structure MS2. The second interlayer insulating film 140b may be disposed on the second mold insulating film 115 disposed on the uppermost portion of the second mold structure MS2. The boundary between the uppermost second mold insulating film 115 and the second interlayer insulating film 140b may not be distinguished. The uppermost portion of the ferroelectric film 150 protrudes in the third direction Z beyond the upper side of the gate electrode SSL2 disposed on the uppermost portion of the second mold structure MS2.

[0079] A portion of the interface film 133 may cover the upper side of the ferroelectric film 150. A portion of the interface film 133 may be disposed between the upper side of the ferroelectric film 150 and the second portion 136_2 of the channel pad 136. An upper portion of the interface film 133 may have an L shape rotated 180 degrees.

[0080] The channel pad 136 may have a T shape. The second width W2 of the second portion 136_2 may be the same as the width W3 of the uppermost portion of the channel structure CH. However, example embodiments are not limited thereto. For example, the second width W2 of the second portion 136_2 may be different from the width W3 of the uppermost portion of the channel structure CH. The width of the uppermost portion of the channel structure CH may refer to the width of the uppermost portion of the ferroelectric film 150.

[0081] In some example embodiments, the channel structure CH may further include a filling pattern 134. The filling pattern 134 may be formed to fill the inside of the cup-shaped semiconductor pattern 130. The filling pattern 134 may include an insulating material, such as, but not limited to, silicon oxide.

[0082] In some example embodiments, the plurality of channel structures CH may be arranged in a zigzag form. Figure 3 As shown, the plurality of channel structures CH may be alternately arranged in a first direction X and a second direction Y parallel to the upper side of the unit substrate 100. The plurality of channel structures CH arranged in a zigzag form may further improve the integration of the semiconductor memory device. In some example embodiments, the plurality of channel structures CH may be arranged in a honeycomb form.

[0083] In some example embodiments, the dummy channel structure DCH may be formed inside the mold structures MS1 and MS2 of the extension region EXT. The dummy channel structure DCH may be formed in, for example, a similar shape to the channel structure CH to reduce stress applied to the mold structures MS1 and MS2 of the extension region EXT.

[0084] In some example embodiments, the first source structures 102 and 104 may be formed on the unit substrate 100. The first source structures 102 and 104 may be interposed between the unit substrate 100 and the mold structures MS1 and MS2. For example, the first source structures 102 and 104 may extend along the upper side of the unit substrate 100. The first source structures 102 and 104 may be connected to the semiconductor pattern 130 of the channel structure CH. For example, Figure 5 As shown, the first source structures 102 and 104 can penetrate the ferroelectric film 150 and the interface film 133 (collectively referred to as an information storage film) and be connected to the semiconductor pattern 130. Such first source structures 102 and 104 can be set as a common source line of a semiconductor memory device (e.g., Figure 2 The first source structures 102 and 104 may include, for example (but not limited to), doped polysilicon or metal.

[0085] In some example embodiments, the channel structure CH may penetrate the first source structures 102 and 104. For example, a lower portion of the channel structure CH may penetrate the first source structures 102 and 104 and be disposed inside the unit substrate 100.

[0086] In some example embodiments, the first source structures 102 and 104 may be formed of a plurality of films. For example, the first source structures 102 and 104 may include a first source layer 102 and a second source layer 104 sequentially stacked on the unit substrate 100. The first source layer 102 and the second source layer 104 may each include, but are not limited to, doped polysilicon or undoped polysilicon. The first source layer 102 may contact the semiconductor pattern 130 and be provided as a common source line (e.g., Figure 2 The second source layer 104 may be used as a support layer to mitigate or prevent the mold stack from collapsing or falling in an alternative process for forming the first source layer 102.

[0087] Although not shown, a base insulating film may be interposed between the unit substrate 100 and the first source structures 102 and 104. The base insulating film may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0088] In some example embodiments, the first source structures 102 and 104 may not be formed inside the extension region EXT formed with the insulating substrate 101. Although the upper side of the insulating substrate 101 is only shown as being coplanar with the upper sides of the first source structures 102 and 104, this is only an example. As another example, the upper side of the insulating substrate 101 may be higher than the upper sides of the first source structures 102 and 104.

[0089] In some example embodiments, the source sacrificial film 103 may be formed on a portion of the unit substrate 100. For example, the source sacrificial film 103 may be formed on a portion of the unit substrate 100 of the extension region EXT. The source sacrificial film 103 may include a material having an etching selectivity relative to the mold insulating films 110 and 115. As an example, the mold insulating films 110 and 115 may include silicon oxide, and the source sacrificial film 103 may include silicon nitride. The source sacrificial film 103 may be a layer remaining after replacing a portion of the source sacrificial film 103 with the first source layer 102 in the manufacturing process of the first source structures 102 and 104.

[0090] The block isolation region WCf, the first partial isolation region WC1, and the second partial isolation region WC2 may each extend in the first direction X to cut the mold structures MS1 and MS2. The block isolation region WCf may completely cut the mold structures MS1 and MS2. For example, the block isolation region WCf may extend continuously in the first direction X. The first partial isolation region WC1 and the second partial isolation region WC2 may partially cut the mold structures MS1 and MS2, respectively. For example, the first partial isolation regions WC1 of the first row arranged along the first direction X may be spaced apart from each other to partially cut the mold structures MS1 and MS2, and the second partial isolation regions WC2 of the first row arranged along the first direction X may be spaced apart from each other to partially cut the mold structures MS1 and MS2.

[0091] The string isolation structure SC may extend in the first direction X to cut the string selection lines SSL1 and SSL2. For example, the string isolation structure SC formed in the first cell block BLK1 may divide the string selection lines SSL1 and SSL2 into a first region I and a second region II, respectively. Therefore, a first string selection line SSL1 of the first region I and a first string selection line SSL1 of the second region II may be separated and separately controlled, and a second string selection line SSL2 of the first region I and a second string selection line SSL2 of the second region II may be separated and separately controlled.

[0092] The string isolation structure SC may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0093] The bit line BL may be formed on the mold structures MS1 and MS2. The bit line BL may extend in the second direction Y and intersect the block isolation region WCf. In addition, the bit line BL may extend in the second direction Y and be connected to a plurality of channel structures CH arranged along the second direction Y. For example, a bit line contact 182 connected to the uppermost portion of each channel structure CH may be formed inside the second interlayer insulating film 140b. The bit line BL may be electrically connected to the channel structure CH through the bit line contact 182.

[0094] The cell contact 162 may be connected to each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the cell contact 162 may extend in the third direction Z inside the interlayer insulating films 140a and 140b and be connected to each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. In some example embodiments, the cell contact 162 may have a bent portion between the first mold structure MS1 and the second mold structure MS2.

[0095] The source contact 164 may be connected to the first source structures 102 and 104. For example, the source contact 164 may extend in the third direction Z inside the interlayer insulating films 140a and 140b and be connected to the unit substrate 100. In some example embodiments, the source contact 164 may have a bent portion between the first and second mold structures MS1 and MS2.

[0096] The through hole 166 may be disposed inside the through region THR. For example, the through hole 166 may extend along the third direction Z inside the mold structures MS1 and MS2 of the through region THR. In some example embodiments, the through hole 166 may have a curved portion between the first mold structure MS1 and the second mold structure MS2. Although the through hole 166 is only shown as penetrating the mold structures MS1 and MS2, this is only an example. As another example, the through hole 166 may be disposed outside the mold structures MS1 and MS2 and may not penetrate the mold structures MS1 and MS2.

[0097] The cell contact 162, the source contact 164, and the through hole 166 may be connected to the first wiring structure 180 on the interlayer insulating films 140a and 140b, respectively. For example, the first inter-wiring insulating film 142 may be formed on the second inter-layer insulating film 140b. The first wiring structure 180 may be formed inside the first inter-wiring insulating film 142. The cell contact 162, the source contact 164, and the through hole 166 may each be connected to the first wiring structure 180 through the contact via 184. For example, although not shown, the first wiring structure 180 may be connected to the bit line BL.

[0098] The peripheral circuit region PERI may include a peripheral circuit board 200 , a peripheral circuit element PT, and a second wiring structure 260 .

[0099] The peripheral circuit board 200 may be disposed below the unit substrate 100. For example, the upper side of the peripheral circuit board 200 may be opposite to the lower side of the unit substrate 100. The peripheral circuit board 200 may include, for example, a semiconductor substrate, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate. In some example embodiments, the peripheral circuit board 200 may include a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate.

[0100] The peripheral circuit element PT may be formed on the peripheral circuit board 200. The peripheral circuit element PT may constitute a peripheral circuit (eg, Figure 1 30). For example, the peripheral circuit element PT may include control logic (e.g., Figure 1 37), a row decoder (e.g., Figure 1 33), page buffer (e.g., Figure 1 In the following description, the surface of the peripheral circuit board 200 on which the peripheral circuit element PT is provided may be referred to as the front surface of the peripheral circuit board 200. Conversely, the surface of the peripheral circuit board 200 opposite to the front surface of the peripheral circuit board 200 may be referred to as the back surface of the peripheral circuit board 200.

[0101] The peripheral circuit element PT may include, for example, but not limited to, a transistor. For example, the peripheral circuit element PT may include not only various active elements such as a transistor, but also various passive elements such as a capacitor, a resistor, and an inductor.

[0102] In some example embodiments, the back surface of the unit substrate 100 may be opposite to the front surface of the peripheral circuit board 200. For example, the second inter-wiring insulating film 240 covering the peripheral circuit element PT may be formed on the front surface of the peripheral circuit board 200. The unit substrate 100 and / or the insulating substrate 101 may be stacked on the upper surface of the second inter-wiring insulating film 240.

[0103] The first wiring structure 180 may be connected to the peripheral circuit element PT through the via 166. For example, the second wiring structure 260 connected to the peripheral circuit element PT may be formed inside the second inter-wiring insulating film 240. The via 166 may extend in the third direction Z to connect the first wiring structure 180 and the second wiring structure 260. Therefore, each of the bit line BL, the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1 and SSL2, and / or the first source structures 102 and 104 may be electrically connected to the peripheral circuit element PT.

[0104] In some example embodiments, the via 166 may penetrate the insulating substrate 101 to connect the first wiring structure 180 and the second wiring structure 260. Thus, the via 166 may be electrically separated from the unit substrate 100.

[0105] Figure 8 is a diagram for explaining a semiconductor memory device according to an example embodiment. Figures 1 to 7 The points described in the article are different from those in the previous article.

[0106] refer to Figure 8 , the channel structure CH may include a semiconductor pattern 130 , a charging pattern 134 , a first interface film 133 a , a second interface film 133 b , a first ferroelectric film 150 a , and a second ferroelectric film 150 b .

[0107] The semiconductor pattern 130 may extend in the third direction Z and penetrate the mold structures MS1 and MS2. Although the semiconductor pattern 130 is shown as having a cup shape, this is only an example. For example, the semiconductor pattern 130 may have various shapes, such as a cylindrical shape, a rectangular barrel shape, and a solid filler shape. The semiconductor pattern 130 may include, for example, (but not limited to) semiconductor materials, such as single crystal silicon, polycrystalline silicon, organic semiconductor substances, and carbon nanostructures.

[0108] The first interface film 133a may be disposed on the semiconductor pattern 130. The first interface film 133a may be interposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. For example, the first interface film 133a may extend along an outer side of the semiconductor pattern 130. The first interface film 133a may contact the channel pad 136. The channel pad 136 may be disposed on the first interface film 133a.

[0109] The first ferroelectric film 150a may be disposed on the first interface film 133a. The first ferroelectric film 150a may be formed along the first interface film 133a. The first ferroelectric film 150a may be disposed between the semiconductor pattern 130 and each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2.

[0110] The upper side of the first ferroelectric film 150a may protrude beyond the upper side of the second mold structure MS2. The upper side of the first ferroelectric film 150a may protrude beyond the second mold insulating film 115 and the gate electrode SSL2 disposed at the uppermost portion of the second mold structure MS2 in the third direction Z. The uppermost portion of the first interface film 133a may cover the upper side of the first ferroelectric film 150a. The uppermost portion of the first ferroelectric film 150a may have an L-shape rotated 180 degrees. The first interface film 133a may have an L-shape rotated 180 degrees.

[0111] The second interface film 133b may be disposed on the first interface film 133a. The second interface film 133b may be formed along the first interface film 133a. The second interface film 133b may be disposed between the first interface film 133a and each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2.

[0112] The second ferroelectric film 150b may be disposed on the second interface film 133b. The second ferroelectric film 150b may be formed along the second interface film 133b. The second ferroelectric film 150b may be disposed between the first ferroelectric film 150a and each of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2.

[0113] The upper side of the second ferroelectric film 150b may protrude beyond the upper side of the second mold structure MS2. The upper side of the second ferroelectric film 150b may protrude beyond the second mold insulating film 115 and the gate electrode SSL2 disposed at the uppermost portion of the second mold structure MS2 in the third direction Z. The uppermost portion of the second interface film 133b may cover the upper side of the second ferroelectric film 150b. The second interface film 133b may have an L shape rotated 180 degrees.

[0114] Each of the first interface film 133a and the second interface film 133b may include, for example, silicon oxide, or a high dielectric constant material (eg, aluminum oxide (Al2O3)) having a dielectric constant higher than that of silicon oxide. 2 O 3 )) and at least one of silicon oxide or silicon nitride.

[0115] The description of the materials of the first ferroelectric film 150a and the second ferroelectric film 150b can be the same as Figures 1 to 7 The materials of the ferroelectric film 150 are the same as those described in .

[0116] In a semiconductor device according to some example embodiments, when a plurality of ferroelectric films and interface films are included, characteristics of a semiconductor memory device may be improved. For example, a memory window of a nonvolatile memory device may be increased.

[0117] As the size of the semiconductor memory device decreases, the size of the channel pad 136 decreases. This may cause misalignment between the channel pad 136 and the bit line contact 182. In the semiconductor memory device according to the present disclosure, since the width of the second portion 136_2 of the channel pad 136 is greater than the width of the first portion 136_1, the misalignment between the channel pad 136 and the bit line contact 182 can be reduced.

[0118] For example, when a ferroelectric material is used and a plurality of ferroelectric films are included, the width of the semiconductor pattern may be excessively reduced. If the width of the channel pad is the same as the semiconductor pattern, misalignment between the channel pad and the bit line contact may occur. Since the semiconductor device according to some example embodiments of the present disclosure can increase the width of the channel pad 136 regardless of the width of the semiconductor pattern 130, the reliability of the semiconductor memory device can be improved.

[0119] Fig. 9 and Fig.10 is a diagram for explaining a semiconductor memory device according to an example embodiment. For reference, Fig.10 It is used to illustrate Fig. 9 For the sake of convenience, the following will mainly describe Figures 1 to 7 The points described in the article are different from those in the previous article.

[0120] refer to Fig. 9 and Fig.10 , the semiconductor memory device according to example embodiments includes a second source structure 106 .

[0121] The second source structure 106 may be formed on the unit substrate 100. Although the lower portion of the second source structure 106 is only shown as being disposed inside the unit substrate 100, this is only an example. The second source structure 106 may be connected to the semiconductor pattern 130 of the channel structure CH. For example, the semiconductor pattern 130 may penetrate the ferroelectric film 150 and contact the upper side of the second source structure 106. The second source structure 106 may be formed from the unit substrate 100 by, for example, (but not limited to) a selective epitaxial growth process.

[0122] In some example embodiments, the upper side of the second source structure 106 may intersect some of the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2. As an example, the upper side of the second source structure 106 may be formed to be higher than the upper side of the erase control line ECL. In this case, the gate insulating film 110S may be interposed between the gate electrode (e.g., the erase control line ECL) intersecting the second source structure 106 and the second source structure 106.

[0123] Fig.11is a diagram for explaining a semiconductor memory device according to an example embodiment. Figures 1 to 7 The points described in the article are different from those in the previous article.

[0124] The ferroelectric film 150 may include a protrusion 150PR. The protrusion 150PR may be disposed on the second mold structure MS2. The protrusion 150PR may be disposed on the upper side of the second mold structure MS2. For example, the protrusion 150PR may be disposed on the second mold insulating film 115 disposed at the uppermost portion of the second mold structure MS2. The protrusion 150PR may overlap the second mold structure MS2 in the third direction Z.

[0125] The interface film 133 may be disposed on the ferroelectric film 150. The interface film 133 may cover an upper side of the ferroelectric film 150. The interface film 133 may be disposed on the protrusion 150PR of the ferroelectric film 150.

[0126] The second portion 136_2 of the channel pad 136 may have a fourth width W4. The channel structure CH may have a third width W3. The fourth width W4 is greater than the third width W3. The third width W3 may refer to a maximum width among widths of a portion of the channel structure CH disposed inside the second molding structure MS2.

[0127] Fig.12 is a diagram for explaining a semiconductor memory device according to an example embodiment. Figures 1 to 7 The points described in the article are different from those in the previous article.

[0128] refer to Fig.12 , the semiconductor memory device according to example embodiments may include only the first mold structure MS1. That is, the semiconductor memory device according to example embodiments may have a single stack structure. The channel structure CH, the cell contact 162, the source contact 164, and the through hole 166 do not have a bent portion.

[0129] Fig.13 is a diagram for explaining a semiconductor memory device according to example embodiments.

[0130] refer to Fig.13 , in the semiconductor memory device according to example embodiments, a front surface of the unit substrate 100 is opposite to a front surface of the peripheral circuit board 200 .

[0131] For example, the semiconductor memory device according to some example embodiments may be a C2C (chip-to-chip) structure. The C2C structure may refer to a structure in which an upper chip including a memory cell region CELL is manufactured on a first wafer (e.g., a unit substrate 100), and a lower chip including a peripheral circuit region PERI is manufactured on a second wafer (e.g., a peripheral circuit board 200) different from the first wafer, and then the upper chip and the lower chip are connected to each other by bonding.

[0132] As an example, the bonding method may refer to a method of electrically connecting the first bonding metal 190 formed on the uppermost metal layer of the upper chip and the second bonding metal 290 formed on the uppermost metal layer of the lower chip. For example, when the first bonding metal 190 and the second bonding metal 290 are formed of copper (Cu), the bonding type may be a Cu-Cu bonding type. However, this is only an example, and of course, the first bonding metal 190 and the second bonding metal 290 may be formed of various other metals such as aluminum (Al) or tungsten (W).

[0133] As the first bonding metal 190 and the second bonding metal 290 are bonded, the first wiring structure 180 may be connected to the second wiring structure 260. Therefore, each of the bit lines BL, the gate electrodes ECL, GSL1, GSL2, WL11 to WL1n, WL21 to WL2n, SSL1, and SSL2, and / or the first source structures 102 and 104 may be electrically connected to the peripheral circuit element PT.

[0134] Figures 14 to 17 is an intermediate step diagram for explaining a method for manufacturing a semiconductor memory device according to an example embodiment. For reference, Fig.15 It is used to illustrate Fig.14 For convenience of description, the portion where the channel structure CH of the cell array region CAR is formed will be mainly described.

[0135] refer to Fig.14 and Fig.15 , a pre-ferroelectric film 150P may be formed on the first and second mold structures MS1 and MS2.

[0136] For example, first and second mold structures MS1 and MS2 may be formed on the peripheral circuit board 200 and the second inter-wiring insulating film 240. Unlike the illustrated example, first and second mold structures MS1 and MS2 may be formed, and the second inter-wiring insulating film 240 and the peripheral circuit board 200 may be formed.

[0137] A channel hole penetrating the first mold structure MS1 and the second mold structure MS2 may be formed. A pre-ferroelectric film 150P may be formed along the inner sidewall of the channel hole. The pre-ferroelectric film 150P may cover the upper side of the second mold structure MS2. For example, the pre-ferroelectric film 150P may cover the upper side of the second mold insulating film 115 disposed at the uppermost portion of the second mold structure MS2.

[0138] Subsequently, the pre-interface film 133P may be formed along the pre-ferroelectric film 150P. The pre-interface film 133P may be formed along the contour of the pre-ferroelectric film 150P.

[0139] The semiconductor pattern 130 may be formed on the pre-interface film 133P. The filling pattern 134 may be formed on the semiconductor pattern 130. The semiconductor pattern 130 and the filling pattern 134 may fill a portion remaining after the channel hole is filled by the pre-ferroelectric film 150P and the pre-interface film 133P.

[0140] refer to Fig.16 , a pre-channel pad 136P may be formed on the pre-interface film 133P, the semiconductor pattern 130 , and the filling pattern 134 .

[0141] The pre-channel pad 136P may cover the second mold structure MS2 . The pre-channel pad 136P may be disposed on the pre-ferroelectric film 150P and the pre-interface film 133P. The pre-channel pad 136P may contact the semiconductor pattern 130 .

[0142] refer to Fig.17 , a channel pad 136 and a channel structure CH may be formed on the second mold structure MS2.

[0143] Can be etched by etching process Fig.16 The pre-channel pad 136P is used to form the channel pad 136. The etching process can use, for example, an etching mask for forming the channel hole. In this case, since the etching mask for forming the channel pad 136 is the same as the etching mask for forming the channel hole, the number of process steps can be reduced.

[0144] The channel structure CH may be formed by an etching process. For example, when the channel pad 136 is formed, the pre-interface film 133P and the pre-ferroelectric film 150P may be etched to form the interface film 133 and the ferroelectric film 150 .

[0145] Subsequently, a second interlayer insulating film 140 b , a bit line contact 182 , a bit line BL, etc. may be formed on the second mold structure MS2 .

[0146] The following will refer to Figures 18 to 20 An electronic system including a semiconductor memory device according to some example embodiments is described.

[0147] Fig.18 is an example block diagram for explaining an electronic system according to an example embodiment. Fig.19 is an example perspective view for explaining an electronic system according to an example embodiment. Fig. 20 is along Fig.19 Schematic cross-sectional view taken along line II.

[0148] refer to Fig.18 , an electronic system 1000 according to an example embodiment may include a semiconductor memory device 1100, and a controller 1200 electrically connected to the semiconductor memory device 1100. The electronic system 1000 may be a storage device including one or more semiconductor memory devices 1100, or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive device (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor memory devices 1100.

[0149] The semiconductor memory device 1100 may be a nonvolatile memory device (eg, a NAND flash memory device), and may be, for example, the device described above using Figures 1 to 13 The semiconductor memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0150] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110 (eg, Figure 1 , a row decoder 33), a page buffer 1120 (eg, Figure 1 110 and logic circuit 1130 (eg, Figure 1 control logic 37).

[0151] The second structure 1100S may include the above using Figure 2 The common source line CSL, a plurality of bit lines BL, and a plurality of cell strings CSTR are illustrated. The cell strings CSTR may be connected to the decoder circuit 1110 through word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. In addition, the cell strings CSTR may be connected to the page buffer 1120 through the bit lines BL.

[0152] In some example embodiments, the common source line CSL and the cell string CSTR may be electrically connected to the decoder circuit 1110 through a first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The first connection wiring 1115 may correspond to the first connection wiring 1115 used above. Figures 1 to 12 That is, the through hole 166 can connect each of the gate electrodes ECL, GSL, WL, and SSL to the decoder circuit 1110 (eg, Figure 1 The row decoder 33) is electrically connected.

[0153] In some example embodiments, the bit line BL may be electrically connected to the page buffer 1120 through a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S. The second connection wiring 1125 may correspond to the first structure 1100F and the second structure 1100S. Figures 1 to 12 That is, the through hole 166 can connect the bit line BL and the page buffer 1120 (eg, Figure 1 The page buffer 35 is electrically connected.

[0154] The semiconductor memory device 1100 can be connected to the logic circuit 1130 (eg, Figure 1 The I / O pads 1101 electrically connected to the control logic 37 of the first structure 1100F can communicate with the controller 1200. The I / O pads 1101 can be electrically connected to the logic circuit 1130 through the I / O connection wiring 1135 extending from the inside of the first structure 1100F to the second structure 1100S.

[0155] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some example embodiments, the electronic system 1000 may include a plurality of semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor memory devices 1100.

[0156] The processor 1210 may control the operation of the entire electronic system 1000 including the controller 1200. The processor 1210 may operate according to a desired (or alternatively, predetermined) firmware, and may control the NAND controller 1220 to access the semiconductor memory device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor memory device 1100. A control command for controlling the semiconductor memory device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor memory device 1100, data to be read from the memory cell transistor MCT of the semiconductor memory device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor memory device 1100 in response to the control command.

[0157] refer to Fig.19 and Fig. 20, an electronic system according to an example embodiment may include a main board 2001, a main controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the main controller 2002 through a wiring pattern 2005 formed on the main board 2001.

[0158] The mainboard 2001 may include a connector 2006 including a plurality of pins configured to be coupled to an external host. In the connector 2006, the number and placement of the plurality of pins may vary according to the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host according to any of the interfaces such as M-Phy for USB (Universal Serial Bus), PCI Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), or UFS (Universal Flash Memory). In some example embodiments, the electronic system 2000 may be operated by power supplied from an external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from an external host to the main controller 2002 and the semiconductor package 2003.

[0159] The main controller 2002 may record data in the semiconductor package 2003 or read data from the semiconductor package 2003 , and may improve the operation speed of the electronic system 2000 .

[0160] The DRAM 2004 may be a buffer memory for alleviating the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a high-speed cache memory, and may also provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the main controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0161] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower side of each semiconductor chip 2200, a connection structure 2400 for electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a mold layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0162] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an I / O pad 2210. The I / O pad 2210 may correspond to Fig.18 I / O pad 1101.

[0163] In some example embodiments, the connection structure 2400 may be a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire type, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through electrode (through silicon via TSV) instead of a connection structure 2400 of a bonding wire type.

[0164] In some example embodiments, the main controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the main controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate different from the main board 2001, and the main controller 2002 and the semiconductor chip 2200 may be connected to each other through wiring formed on the interposer substrate.

[0165] In some example embodiments, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, an upper pad 2130 disposed on an upper surface of the package substrate body 2120, a lower pad 2125 disposed on a lower surface of the package substrate body 2120 or exposed through the lower surface, and an internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 inside the package substrate body 2120. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to a wiring pattern 2005 of a main board 2001 of the electronic system 2000 through a conductive connection 2800, such as Fig.19 as shown in .

[0166] In the electronic system according to some example embodiments, each of the semiconductor chips 2200 may include the above-mentioned Figures 1 to 13 For example, each semiconductor chip 2200 may include a peripheral circuit region PERI and a memory cell region CELL stacked on the peripheral circuit region PERI. As an example, the peripheral circuit region PERI may include the memory cell region CELL stacked on the peripheral circuit region PERI. Figures 3 to 7 The peripheral circuit board 200 and the second wiring structure 260 are shown. In addition, as an example, the memory cell region CELL may include the above-mentioned Figures 3 to 7 The illustrated unit substrate 100, the mold structures MS1 and MS2, and the channel structure CH.

[0167] Any functional blocks shown in the figures and described above may be implemented in a processing circuit (e.g., hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof). For example, the processing circuit may also include (but not limited to) a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0168] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the disclosed exemplary embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the inventive concept are intended only for general and descriptive purposes and not for purposes of limitation.

Claims

1. A semiconductor memory device, comprising: substrate; a mold structure including a plurality of gate electrodes and a plurality of mold insulating films alternately stacked on the substrate; a channel structure extending in a first direction and penetrating the mold structure, the channel structure comprising a semiconductor pattern, and a ferroelectric film between the semiconductor pattern and the plurality of gate electrodes; A channel pad, on the channel structure; as well as a bit line contact portion connected to the channel pad, wherein the uppermost portion of the ferroelectric film protrudes beyond the uppermost gate electrode among the plurality of gate electrodes, The channel pad includes a first portion contacting the semiconductor pattern and a second portion contacting the first portion and the bit line contact portion, The first portion has a first width, and The second portion has a second width greater than the first width.

2. The semiconductor memory device according to claim 1, in, The uppermost portion of the ferroelectric film protrudes beyond an upper side of the mold structure.

3. The semiconductor memory device according to claim 1, in, The channel structure includes an interface film between the ferroelectric film and the semiconductor pattern.

4. The semiconductor memory device according to claim 3, in, A portion of the interface film covers an upper side of the ferroelectric film.

5. The semiconductor memory device according to claim 3, in, A portion of the interface film is between the ferroelectric film and the second portion of the channel pad.

6. The semiconductor memory device according to claim 1, in, The ferroelectric film includes a protrusion, and The protrusion overlaps a portion of the gate electrode in the first direction.

7. The semiconductor memory device according to claim 1, further comprising: The source layer is in contact with the semiconductor pattern.

8. The semiconductor memory device according to claim 1, in, The ferroelectric film is in direct contact with the plurality of gate electrodes.

9. The semiconductor memory device according to claim 1, in, The uppermost portion of the channel structure has a third width, and The third width is the same as the second width of the second portion.

10. The semiconductor memory device according to claim 1, in, The uppermost portion of the channel structure has a third width, and The third width is smaller than the second width of the second portion.

11. A semiconductor memory device comprising: substrate; a mold structure including a plurality of gate electrodes and a plurality of mold insulating films alternately stacked on the substrate; a channel structure extending in a first direction and penetrating the mold structure; and a trench pad, on the trench structure, the trench pad including a first portion having a first width and a second portion having a second width greater than the first width, Wherein, the channel structure comprises: Semiconductor patterning; a first interface film on the semiconductor pattern; a first ferroelectric film, on the first interface film; a second interface film on the first ferroelectric film; and The second ferroelectric film is on the second interface film.

12. The semiconductor memory device according to claim 11, in, The second ferroelectric film is in contact with the plurality of gate electrodes.

13. The semiconductor memory device according to claim 11, in, The first interface film covers an upper side of the first ferroelectric film.

14. The semiconductor memory device according to claim 11, in, The second interface film covers an upper side of the second ferroelectric film.

15. The semiconductor memory device according to claim 11, in, The semiconductor pattern contacts the first portion of the channel pad.

16. The semiconductor memory device according to claim 11, in, An uppermost portion of the second ferroelectric film protrudes beyond an upper side of the mold structure.

17. The semiconductor memory device according to claim 11, in, The uppermost portion of the channel structure has a third width, and The third width is the same as the second width of the second portion.

18. The semiconductor memory device according to claim 11, in, An uppermost portion of the second ferroelectric film protrudes beyond an uppermost gate electrode among the plurality of gate electrodes.

19. An electronic system comprising: Motherboard; A semiconductor memory device, on the main board; as well as a controller, on the main board and electrically connected to the semiconductor memory device, Wherein, the semiconductor memory device comprises: substrate; a mold structure including a plurality of gate electrodes and a plurality of mold insulating films alternately stacked on the substrate; a channel structure extending in a first direction and penetrating the mold structure, the channel structure comprising a semiconductor pattern, and a ferroelectric film between the semiconductor pattern and the plurality of gate electrodes; a channel pad on the channel structure; and a bit line contact portion connected to the channel pad, wherein the uppermost portion of the ferroelectric film protrudes beyond the uppermost gate electrode among the plurality of gate electrodes, and wherein the channel pad includes a first portion contacting the semiconductor pattern and a second portion contacting the first portion and the bit line contact portion, The first portion has a first width, and The second portion has a second width greater than the first width.

20. The electronic system according to claim 19, in, The channel structure includes an interface film between the ferroelectric film and the semiconductor pattern, and A portion of the interface film covers an upper side of the ferroelectric film.

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